AVAGO MGA-13116-BLKG High gain, high linearity, very low noise amplifier Datasheet

MGA-13116
High Gain, High Linearity, Very Low Noise Amplifier
Data Sheet
Description
Features
Avago Technologies’ MGA-13116 is a two stage, easy-touse GaAs MMIC Low Noise Amplifier (LNA). The LNA has
low noise with good input return loss and high linearity
achieved through the use of Avago Technologies’ proprietary 0.25 Pm GaAs Enhancement-mode pHEMT process.
Minimum matching needed for input, output and the
inter-stage between the two LNA.
x
x
x
x
x
x
It is designed for optimum use between 400 MHz to 1.5
GHz. For optimum performance at higher frequency from
1.5 GHz to 2.5 GHz, the MGA-13216 is recommended. Both
MGA-13116 & MGA-13216 share the same package and
pinout configuration.
x Low cost small package size: 4.0 x 4.0 x 0.85 mm3
Pin Configuration and Package Marking
TOP VIEW
16
15
12
1
11
2
GND
Pin 2
Pin 3
Pin 10
Pin 11
Pin 13
Pin 16
Vbias
RFinQ1
RFoutQ2
RFoutQ2
RFinQ2
RFoutQ1
All other pics NC
– Not Connected
5
4
6
3
9
7
10
8
AVAGO
13116
YYWW
XXXX
14
13
4.0 x 4.0 x 0.85 mm3 16-lead QFN
BOTTOM VIEW
Optimum frequency of operation 400 MHz – 1.5 GHz
Very low noise figure
High gain
High linearity performance
Excellent isolation
GaAs E-pHEMT Technology[1]
Specifications
900 MHz; Q1: 5 V, 55 mA (typ) Q2: 5 V, 112 mA (typ)
x
x
x
x
x
0.51 dB Noise Figure
38 dB Gain
52 dB RFoutQ1 to RFinQ2 Isolation
41.4 dBm Output IP3
23.3 dBm Output Power at 1dB gain compression
Applications
x Low noise amplifier for cellular infrastructure including
GSM, CDMA, and W-CDMA.
x Other very low noise applications.
Simplified Schematic
Note:
Package marking provides orientation and identification
“13116” = Device Part Number
“YYWW” = Work Week and Year of Manufacture
“XXXX” = Lot Number
C10
C9
R4
R2
C7
R3
C8
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 90 V
ESD Human Body Model = 300 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Vdd2
Vdd1
L3
C6
16
L1
RFIN C1
C5
15
C4
R1
C3
14 13
1
12
2 Q1bias
11
3
Q1
L2
C2
Q2
RFOUT
10
4
9
5
6
7
8
Notes: Enhancement mode technology employs positive gate bias,
thereby eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
MGA-13116 Absolute Maximum Rating [1] TA = 25° C
Thermal Resistance [3]
Symbol
Parameter
Units
Absolute Maximum
Vdd1
Device Voltage
V
5.5
Vdd2
Device Voltage
V
5.5
Idd1
Q1 Drain Current
mA
90
Pd
Power Dissipation (2)
W
1.02
Pin,max
CW RF Input Power
dBm
20
Tj,max
Junction Temperature
°C
150
Tstg
Storage Temperature
°C
-65 to 150
(Vdd1 =5.0V, Idd1 =55mA, Vdd2 =5.0V,
Idd2 =112mA) Tjc = 41.9°C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Board temperature (Tc) is 25° C. For Tc >100° C,
derate the device power at 23.9 mW per
°C rise in board temperature adjacent to
package bottom.
3. Thermal resistance measured using Infrared
Measurement Technique.
Electrical Specifications [1]
RF performance at Vdd1 = 5 V, Vdd2 = 5 V, 900 MHz, TA = 25° C, measured on the demo board.
Symbol
Parameter and Test Condition
Units
Min.
Typ.
Max.
Idd1
Current at Q1
mA
42
55
69
Idd2
Current at Q2
mA
92
112
131
NF
Noise Figure
dB
–
0.51
0.85
Gain
Gain
dB
36.5
38
39.5
OIP3[2]
Output Third Order Intercept Point
dBm
37.5
41.4
–
OP1dB
Output Power at 1 dB Gain Compression
dBm
22
23.3
–
IRL
Input Return Loss, 50 : source
dB
–
-19
–
ORL
Output Return Loss, 50 : load
dB
–
-12
–
|S12|
Reverse Isolation
dB
–
48
–
|ISOL1-2|
Isolation between Q1’s Output pin & Q2’s Input pin
dB
–
52
–
Notes:
1. Measurements obtained using demo board described in Figure 7 with component list in Table 1. Input and Output trace loss is not de-embedded
from the measurement.
2. OIP3 test condition: ftone1 = 900 MHz, ftone2 = 901 MHz with input power of -29 dBm per tone.
3. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note for more details.
2
Product consistency Distribution Charts [1,2]
LSL
USL
45
50
55
60
LSL
65
100
Figure 1. Idd1 @ 900 MHz, Vdd1 = 5 V, LSL = 42 mA, Nominal = 55 mA,
USL = 69 mA
USL
0.2
0.3
0.4
0.5
0.6
0.7
110
120
130
Figure 2. Idd2 @ 900 MHz, Vdd2 = 5 V, LSL = 92 mA, Nominal = 112 mA,
USL = 131 mA
LSL
0.8
USL
37
Figure 3. Noise Figure @ 900 MHz, Vdd1 = 5 V, Vdd2 = 5 V, Nominal = 0.51 dB,
USL = 0.85 dB
38
39
Figure 4. Gain @ 900 MHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 36.5 dB,
Nominal = 38 dB, USL = 39.5 dB
LSL
LSL
38
USL
39
40
41
42
Figure 5. OIP3 @ 900 MHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 37.5 dBm,
Nominal = 41.4 dBm
43
22
22.5
23
23.5
Figure 6. OP1dB @ 900 MHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 22 dBm,
Nominal = 23.3 dBm
Notes:
1. Data sample size is 10026 samples taken from 3 different wafers. Future wafers allocated to this product may have nominal values anywhere
between the upper and lower limits.
2. Measurements are made on production test board which represents a trade-off between optimal Gain, NF, OIP3 and OP1dB. Circuit losses have
been de-embedded from actual measurements.
3
C9b
C9a
R3
C8
C11
IN
Vdd2
GND
Vdd1
VDD2
R4b
R4a
Demo Board Schematic
GND
VDD1
GND
VBias
Demo Board Layout
C5b
C7 L3
C5a
C4
C6 R1
C3
OUT
L2
C1 L1
C10
C9
R5
C10 C12
R2
R4
R2
C7
R3
C8
C5
L3
C6
C4
R1
C3
C2
L4
L5
16
C13
JAN 2011
AVAGO
Technologies
L1
RFIN C1
14 13
12
2 Q1bias
11
3
MANGROVE
15
1
Q1
C2
Q2
10
4
9
5
Figure 7. Demo Board layout diagram.
L2
6
7
8
Figure 8. Demo Board schematic diagram.
– Recommended PCB material is 10 mils Rogers R04350.
– Suggested component values may vary according to layout and PCB material.
Table 1. Component list for 900MHz matching
Part
Size
Value
Detail Part Number
Notes
C1, C6
0402
100pF (Murata)
GRM1555C1H101JD01E
DC Blocking Capacitors
C2
0402
12pF (Murata)
MCH155A120JK
DC Blocking Capacitor
C3
0402
10pF (Murata)
GRM1555C1H100JZ01E
Bypass Capacitor
C4
0402
0.1uF (Murata)
GRM155R61A104KA01D
Bypass Capacitor
C5a
0603
2.2uF (Murata)
GRM188R61A225KE34D
Bypass Capacitor
C7
0402
33pF (Murata)
GRM1555C1H330JZ01E
Bypass Capacitor
C9a, C9b
N/A
Not used
Not used
Bypass Capacitor
C8, C10
0402
4.7uF (Murata)
GRM155R60E475ME760
Bypass Capacitors
L1
0402
18nH (Toko)
LL1005-FHL18NJ
Input Match for NF
L2
0402
39nH (Toko)
LL1005-FHL39NJ
Output match for Q2
L3
0402
39nH (Toko)
LL1005-FHL39NJ
Output match for Q1
R3, R1
0402
0 ohm (Koa)
RK73Z1ELTP
Bridging Resistors
R2
0402
10 ohm (Rohm)
MCR01J100
Stabilizing Resistor for Q1
R4b
0402
6.8K ohm (Koa)
RM73B1E682J
Biasing Resistor for Q1
4
RFOUT
MGA-13116 Typical Performance in Demoboard for 900 MHz
TA = 25° C, Vdd1 = 5.0 V, Vdd2 = 5.0 V, Idd1 = 55 mA, Idd2 = 112 mA
45
1.2
85° C
25° C
-40° C
1.0
85° C
25° C
-40° C
40
Gain (dB)
NF (dB)
0.8
0.6
35
0.4
30
0.2
0.0
300
500
700
900
1100
Frequency (MHz)
1300
50
28
45
26
40
35
500
700
900
1100
Frequency (MHz)
1300
1300
1500
22
20
85° C
25° C
-40° C
16
300
1500
500
700
900
1100
Frequency (MHz)
1300
1500
Figure 12. OP1dB vs Frequency and Temperature
60
S11
S22
S21
S12
40
20
10
9
8
7
6
5
4
3
2
1
0
85° C
25° C
-40° C
K - factor
IRL, ORL, Gain, Rev Isol (dB)
900
1100
Frequency (MHz)
18
Figure 11. OIP3 vs Frequency and Temperature
0
-20
-40
-60
700
24
85° C
25° C
-40° C
30
25
300
500
Figure 10. Gain vs Frequency and Temperature
OP1dB (dBm)
OIP3 (dBm)
Figure 9. NF vs Frequency and Temperature
0
1
2
3
Frequency (GHz)
4
5
Figure 13. Input Return Loss, Output Return Loss, Gain, & Reverse Isolation
vs Frequency
5
25
300
1500
0
2
4
6
8
10 12
Frequency (GHz)
Figure 14. K-factor vs Frequency and Temperature
14
16
18
20
MGA-13116 Typical Performance in Demoboard for 900 MHz
TA = 25° C, Vdd1 = 5.0 V, Vdd2 = 5.0 V, Idd1 = 55 mA, Idd2 = 112 mA
0
0
85° C
25° C
-40° C
-5
-10
ORL (dB)
IRL (dB)
-5
-15
-20
0.5
0.7
Frequency (GHz)
0.9
0.7
Frequency (GHz)
0.9
1.1
140
85° C
25° C
-40° C
60
85° C
25° C
-40° C
120
100
Idd2 (mA)
50
Idd1 (mA)
0.5
Figure 16. ORL vs Frequency and Temperature
70
40
30
80
60
20
40
10
20
0
0
0
1
2
3
Vdd1 (V)
4
5
6
Figure 17. Idd1 vs Vdd1 and Temperature
85° C
25° C
-40° C
45
40
35
30
0
5
10
15
Pout (dBm)
0
1
2
3
Vdd2 (V)
Figure 18. Idd2 vs Vdd2 and Temperature
50
OIP3 (dBm)
-15
-25
0.3
1.1
Figure 15. IRL vs Frequency and Temperature
20
Figure 19. OIP3 vs Output Power and Temperature at 900 MHz
6
-10
-20
-25
0.3
25
85° C
25° C
-40° C
25
4
5
6
MGA-13116 Q1 Typical Scattering Parameters, Vdd1 = 5 V, Idd1 = 55 mA
Freq
GHz
S11
S21
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
0.1
0.74
-41.90
28.09
145.39
0.02
63.40
0.29
-39.30
0.5
0.22
-84.68
11.81
105.49
0.05
60.13
0.14
1.62
0.9
0.14
-101.78
7.39
86.79
0.09
60.17
0.18
-12.75
1.0
0.13
-106.05
6.74
83.14
0.09
59.45
0.18
-16.99
1.5
0.10
-128.01
4.69
67.16
0.14
53.73
0.18
-35.56
1.9
0.09
-140.02
3.77
56.17
0.17
47.97
0.17
-50.36
2.0
0.09
-142.35
3.60
53.51
0.18
46.51
0.16
-53.64
2.5
0.08
-154.03
2.93
41.20
0.22
38.81
0.16
-73.64
3.0
0.06
-173.46
2.49
29.38
0.26
30.55
0.15
-91.93
4.0
0.04
129.28
1.92
6.91
0.33
13.36
0.12
-151.01
5.0
0.04
120.65
1.58
-14.44
0.40
-4.62
0.19
158.26
6.0
0.05
84.36
1.34
-35.13
0.45
-22.97
0.26
121.64
7.0
0.05
29.33
1.14
-54.64
0.48
-41.22
0.35
93.85
8.0
0.02
-178.29
0.99
-73.16
0.50
-59.29
0.43
81.24
9.0
0.10
169.39
0.88
-93.10
0.52
-79.56
0.46
62.32
10.0
0.10
178.95
0.74
-111.93
0.50
-99.40
0.45
33.79
11.0
0.13
134.83
0.65
-125.11
0.49
-114.26
0.54
25.75
12.0
0.28
108.23
0.61
-140.87
0.50
-131.91
0.65
19.97
13.0
0.49
103.82
0.51
-157.73
0.45
-151.15
0.62
18.93
14.0
0.62
94.39
0.43
-170.19
0.40
-166.05
0.69
11.24
15.0
0.71
71.83
0.37
172.53
0.36
174.21
0.79
-1.76
16.0
0.81
44.07
0.29
154.33
0.28
153.44
0.82
-10.61
17.0
0.87
17.53
0.20
139.72
0.20
136.55
0.82
-23.84
18.0
0.81
-19.41
0.11
165.37
0.11
162.20
0.89
-42.58
19.0
0.18
29.76
0.34
154.36
0.37
148.88
0.77
-60.35
20.0
0.82
19.19
0.26
126.89
0.27
117.97
0.85
-46.54
15
14
13
1
RF input
Reference Plane
2
3
12
11
bias
LNA1
LNA2
4
Figure 20.
7
10
9
5
6
7
S22
MGA-13116 Q1 Typical Noise Parameters, Vdd1 = 5 V, Idd1 =
55 mA
RF output
Reference Plane
16
S12
8
Freq
GHz
Fmin
dB
Γopt
Mag.
Γopt
Ang.
Rn/50
0.50
0.39
0.090
-21.8
0.0428
0.70
0.35
0.143
-39.2
0.0474
0.75
0.42
0.098
-48.2
0.0378
0.80
0.39
0.054
5.9
0.0402
0.90
0.42
0.064
7.3
0.0402
1.50
0.55
0.068
4.1
0.0538
1.70
0.60
0.074
70.4
0.0492
1.95
0.70
0.097
149
0.0392
Notes: Measurements are made on 10 mils Rogers R04350 TRL Board.
Figure 20 shows the input and output reference plane for Q1.
MGA-13116 Q2 Typical Scattering Parameters, Vdd2 = 5 V, Idd2 = 112 mA
Freq
GHz
S11
S21
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
0.1
0.20
-171.18
11.59
167.44
0.04
0.06
0.49
176.27
0.5
0.22
157.18
11.23
138.79
0.04
-13.51
0.43
147.50
0.9
0.23
129.26
10.61
107.30
0.04
-28.06
0.30
129.04
1.0
0.23
120.60
10.45
99.56
0.04
-32.25
0.27
125.80
1.5
0.21
58.66
9.71
60.61
0.04
-58.34
0.12
129.80
1.9
0.26
-20.17
9.13
27.17
0.04
-88.98
0.12
176.29
2.0
0.30
-38.51
8.93
18.19
0.03
-98.40
0.14
179.35
2.5
0.59
-108.72
7.28
-28.35
0.03
-156.55
0.22
161.20
3.0
0.81
-159.33
5.00
-72.18
0.03
144.59
0.21
118.27
4.0
0.94
137.68
1.99
-137.97
0.03
89.64
0.22
-7.02
5.0
0.95
104.26
0.81
169.65
0.04
77.06
0.49
-86.96
6.0
0.93
79.07
0.32
123.70
0.05
57.14
0.69
-128.37
7.0
0.94
59.92
0.15
87.16
0.05
38.07
0.67
-154.44
8.0
0.96
44.90
0.09
55.20
0.06
23.86
0.65
-172.62
9.0
0.92
25.09
0.07
26.64
0.05
9.36
0.70
178.48
10.0
0.91
13.25
0.05
9.11
0.05
-1.10
0.73
168.17
11.0
0.93
11.43
0.03
2.49
0.04
-8.69
0.75
154.12
12.0
0.93
3.64
0.02
0.78
0.03
-24.56
0.78
135.37
13.0
0.81
-10.41
0.01
29.86
0.02
-45.74
0.82
116.24
14.0
0.90
-22.26
0.02
59.46
0.01
-137.08
0.80
94.18
15.0
0.99
-28.29
0.02
63.39
0.03
134.73
0.80
73.17
16.0
0.96
-29.34
0.04
107.89
0.06
111.70
0.75
60.30
17.0
0.95
-38.67
0.09
96.45
0.10
94.24
0.68
43.03
18.0
0.91
-58.96
0.18
70.31
0.18
69.07
0.67
12.84
19.0
0.81
-78.56
0.30
19.69
0.30
19.67
0.58
-39.24
20.0
0.65
-58.97
0.20
-20.26
0.21
-20.60
0.45
9.78
15
14
13
1
2
3
bias
LNA1
LNA2
4
Figure 21.
8
6
7
8
Freq
GHz
Fmin
dB
*opt
Mag.
*opt
Ang.
Rn/50
0.50
1.70
0.165
-13.2
0.2946
12
0.70
1.76
0.129
-2.3
0.2590
11
0.75
1.76
0.11
-8.7
0.2528
0.80
1.69
0.129
-3.4
0.2526
0.90
1.63
0.108
2.7
0.2392
1.50
1.82
0.079
23.2
0.2460
1.70
1.90
0.116
65.2
0.2350
1.95
1.88
0.133
88.7
0.2376
10
9
5
S22
MGA-13116 Q2 Typical Noise Parameters, Vdd2 = 5 V, Idd2 =
112 mA
RF input
Reference Plane
16
S12
RF output
Reference Plane
Notes: Measurements are made on 10 mils Rogers R04350 TRL Board.
Figure 21 shows the input and output reference plane for Q2.
Package Dimensions
Pin 1 Dot
By marking
PIN #1 IDENTIFICATION
CHAMFER 0.30 x 45°
0.40 ±0.10
0.30 ±0.10
AVAGO
13116
YYWW
XXXX
4.00 ±0.10
2.70 ±0.10
Exp.DAP
0.203 Ref.
4.00 ±0.10
2.70 ±0.10
Exp.DAP
0.65 Bsc
1.95
Ref.
0.00 0.10
0.85 ±0.10
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PCB Land Patterns and Stencil Design
4.00
2.70
3.96
2.16
0.65
2.16
3.96
2.70
4.00
0.65
0.40
0.36
0.30
0.27
LAND PATTERN
STENCIL OPENING
2.70
2.16
2.16
2.70
3.96
4.00
0.65
0.36
0.40
0.27
0.30
COMBINATION OF LAND PATTERN & STENCIL OPENING
Notes:
1. All dimensions are in milimeters.
2. 4 mil stencil thickness recommended.
9
Device Orientation
REEL
USER FEED DIRECTION
AVAGO
13116
YYWW
XXXX
CARRIER
TAPE
USER
FEED
DIRECTION
AVAGO
13116
YYWW
XXXX
AVAGO
13116
YYWW
XXXX
TOP VIEW
END VIEW
COVER TAPE
Tape Dimensions
2.00 ±0.05
8.00 ±0.10
Ø 1.50 ±0.10
1.75 ±0.10
4.00 ±0.10
5.50 ±0.05
12.0 ±0.30
–0.10
Ø1.50 ±0.25
0.279 ±0.02
10° MAX
10° MAX
4.25 ±0.10
1.13 ±0.10
4.25 ±0.10
A.
K.
B.
Part Number Ordering Information
Part Number
No. of Devices
Container
MGA-13116-TR1G
1000
7” Reel
MGA-13116-BLKG
100
antistatic bag
10
Reel Dimensions (7 inch reel)
6.25mm EMBOSSED LETTERS
LETTERING THICKNESS: 1.6mm
SLOT HOLE "a"
SEE DETAIL "X"
Ø178.0±0.5
SLOT HOLE "b"
FRONT
BACK
6
PS
SLOT HOLE(2x)
180° APART.
6
PS
RECYCLE LOGO
SLOT HOLE "a": 3.0±0.5mm(1x)
SLOT HOLE "b": 2.5±0.5mm(1x)
FRONT VIEW
45°
+0.5
Ø13.0 -0.2
Ø20.2 MIN.
°
R10.65
120
65°
1.5 MIN.
+1.5*
12.4
-0.0
R5.2
45°
EMBOSSED RIBS
RAISED: 0.25mm, WIDTH: 1.25mm
Ø178.0±0.5
Ø51.2±0.3
BACK VIEW
For product information and a complete list of distributors, please go to our web site:
18.0*
MAX.
SEE DETAIL "Y"
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2877EN - December 19, 2011
DETAIL "X"
3.5
DETAIL "Y"
(Slot Hole)
1.0
Ø55.0±0.5
BACK
Ø178.0±0.5
FRONT