Vicor B048K120M30 Vi chip - bcm bus converter module Datasheet

PRELIMINARY
V•I Chip Voltage Transformation Module
BCM
V•I Chip – BCM
Bus Converter Module
TM
B048K120T30
K indicates BGA configuration. For other
mounting options see Part Numbering below.
• 48 V to 12 V V•I Chip Converter
• 96% efficiency
• 300 Watt (450 Watt for 1 ms)
• 125°C operation
• High density – 1200
W/in3
©
• <1 µs transient response
• Small footprint – 280 W/in2
• 3.5 million hours MTBF
• Low weight – 0.5 oz (14 g)
• No output filtering required
• ZVS/ZCS isolated sine
amplitude converter
• Surface mount BGA or J-Lead
packages
Product Description
Vin = 38 - 55 V
Vout = 9.5 - 13.7 V
Iout = 25 A
K = 1/4
Rout = 13.9 mΩ max
Absolute Maximum Ratings
The V•I Chip Bus Converter Module (BCM) is a high
efficiency (>96%), narrow input range Sine Amplitude
Converter (SAC) operating from a 38 to 55 Vdc primary
bus to deliver an isolated 9.5 V to 13.7 V secondary. The
BCM may be used to power non-isolated POL converters
or as an independent 9.5 – 13.7 V source. Due to the
fast response time and low noise of the BCM, the need
for limited life aluminum electrolytic or tantalum
capacitors at the input of POL converters is reduced—or
eliminated—resulting in savings of board area, materials
and total system cost.
The BCM achieves a power density of 1200 W/in3 and
may be surface mounted with a profile as low as 0.16"
(4 mm) over the PCB. Its V•I Chip power package is
compatible with onboard or inboard surface mounting.
The V•I Chip package provides flexible thermal
management through its low Junction-to-Case and
Junction-to-BGA thermal resistance. Owing to its high
conversion efficiency and safe operating temperature
range, the BCM does not require a discrete heat sink in
typical applications. It is also available with heat sink
options, assuring low junction temperatures and long
life in the harshest environments.
Parameter
Values
Unit
-1.0 to 60
Vdc
+In to -In
100
Vdc
PC to -In
-0.3 to 7.0
Vdc
+Out to -Out
-0.5 to 30.0
Vdc
2,250
Vdc
25
A
Continuous
37.5
A
For 1 ms
+In to -In
Isolation voltage
Output current
Peak output current
Notes
For 100 ms
Input to Output
Output power
300
W
Continuous
Peak output power
450
W
For 1 ms
Case temperature
208
°C
During reflow
Operating junction temperature (1)
-40 to 125
-55 to 125
°C
°C
T - Grade
M - Grade
Storage temperature
-40 to 150
°C
-65 to 150
°C
T - Grade
M - Grade
Note:
(1) The referenced junction is defined as the semiconductor having the highest temperature.
This temperature is monitored by a shutdown comparator.
Part Numbering
B
048
Bus Converter
Module
K
Input Voltage
Designator
Configuration Options
F = Onboard (Figure 20)
K = Inboard (Figure 19)
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Actual size
800-735-6200
V•I Chip Bus Converter Module
120
Output Voltage
Designator
(=VOUT x10)
T
30
Output Power
Designator
(=POUT/10)
Product Grade Temperatures (°C)
Grade
Storage Operating
T
-40 to150 -40 to125
M
-65 to150 -55 to125
B048K120T30
Rev. 1.0
Page 1 of 16
PRELIMINARY
Specifications
V•I Chip Voltage Transformation Module
Input (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Input voltage range
Input dV/dt
Input undervoltage turn-on
Input undervoltage turn-off
Input overvoltage turn-on
Input overvoltage turn-off
Input quiescent current
Inrush current overshoot
Input current
Input reflected ripple current
No load power dissipation
Internal input capacitance
Internal input inductance
Recommended external input capacitance
Min
Typ
Max
Unit
38
48
55
1
37.4
Vdc
V/µs
Vdc
Vdc
Vdc
Vdc
mA
A
Adc
mA p-p
W
µF
nH
µF
32.6
55
59
2.5
2.0
6.8
170
4.7
4
20
47
5.7
Note
PC low
Using test circuit in Figure 21; See Figure 1
Using test circuit in Figure 21; See Figure 4
200 nH maximum source inductance; See Figure 21
Input Waveforms
Figure 1— Inrush transient current at full load and 48 Vin with PC enabled
Figure 2— Output voltage turn-on waveform with PC enabled at full load
and 48 Vin
Figure 3—Output voltage turn-on waveform with input turn-on at full load
and 48 Vin
Figure 4— Input reflected ripple current at full load and 48 Vin
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B048K120T30
Rev. 1.0
Page 2 of 16
PRELIMINARY
Specifications
V•I Chip Voltage Transformation Module
(continued)
Output (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Min
Typ
9.5
9.2
0
Output voltage
Rated DC current
Peak repetitive current
DC current limit
Current share accuracy
Efficiency
Half load
Full load
Internal output inductance
Internal output capacitance
Load capacitance
Output overvoltage setpoint
Output ripple voltage
No external bypass
10 µF bypass capacitor
Average short circuit current
Effective switching frequency
Line regulation
K
Load regulation
ROUT
Transient response
Voltage overshoot
Response time
Recovery time
Output overshoot
Input turn-on
PC enable
Output turn-on delay
From application of power
From release of PC pin
25.5
30.0
5
95.0
95.0
Max
Unit
Note
13.7
13.4
25
Vdc
Vdc
Adc
37.5
A
No load
Full load
Module will shut down when current limit is
reached or exceeded
Max pulse width 1ms, max duty cycle 10%,
baseline power 50%
36.3
10
Adc
%
95.5
96.0
1.1
55
1,000
13.8
214
2.5
144
12.8
0.16
2.8
0.2475
1/4
0.2525
11.7
13.9
3.2
See Parallel Operation on Page 12
%
%
nH
µF
µF
Vdc
See Figure 5
See Figure 5
mV
mV
A
MHz
See Figures 7 and 9
See Figure 8
Effective value
Fixed, 1.4 MHz per phase
VOUT = K•VIN at no load
mΩ
355
200
1
mV
ns
µs
100% load step; See Figures 10 and 11
See Figures 10 and 11
See Figures 10 and 11
0
0
mV
mV
No output filter; See Fig.3
No output filter; See Fig.2
308
80
ms
ms
No output filter; See Fig.3
No output filter
Output Waveforms
Power Dissipation vs. Output Power
14
96
12
Power Dissipation (W)
Efficiency (%)
Efficiency vs. Output Power
98
94
92
90
88
86
84
10
8
6
4
2
0
0
30
60
90
120
150
180
210
240
270
300
0
30
60
Output Power (W)
120
150
180
210
240
270
300
Output Power (W)
Figure 5— Efficiency vs. output power at 48 Vin
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90
Figure 6—Power dissipation as a function of output power
800-735-6200
V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
Page 3 of 16
PRELIMINARY
Specifications
V•I Chip Voltage Transformation Module
(continued)
Figure 7— Output voltage ripple at full load and 48 Vin; without any
external bypass capacitor.
Figure 8—Output voltage ripple at full load and 48 Vin with 10 µF ceramic
external bypass capacitor and 20 nH of distribution inductance.
Ripple Voltage vs. Output Power
160
Output Ripple (mVpk-pk)
140
120
100
80
60
40
20
0
0
30
60
90
120
150
180
210
240
270
300
Output Power (W)
Figure 9— Output voltage ripple vs. output power at 48 Vin line without
any external bypass capacitor.
Figure 10— 0 -25 A load step with 47 µF input capacitor and no
output capacitor.
Figure 11— 25- 0 A load step with 47 µF input capacitance.
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B048K120T30
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Page 4 of 16
PRELIMINARY
Specifications
V•I Chip Voltage Transformation Module
(continued)
General
Parameter
Min
Typ
Max
Unit
Note
25°C, GB
MTBF
MIL-HDBK-217F
3.5
Mhrs
Telcordia TR-NT-000332
4.2
Mhrs
Isolation specifications
Voltage
2,250
Capacitance
3,000
Resistance
10
Agency approvals (pending)
Vdc
Input to Output
pF
Input to Output
MΩ
Input to Output
cTÜVus
UL/CSA 60950, EN 60950
CE Mark
Low voltage directive
Mechanical parameters
See Mechanical Drawing, Figures 15 and 17
Weight
0.50 / 14
oz / g
Dimensions
Length
1.26 / 32
in / mm
Width
0.85 / 21.5
in / mm
Height
0.23 / 6
in / mm
Auxiliary Pins (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter
Min
Typ
Max
Unit
DC voltage
4.8
5.0
5.2
Vdc
Module disable voltage
2.4
2.5
2.6
Vdc
2.5
2.9
mA
Note
Primary control (PC)
Module enable voltage
Current limit
2.4
2.5
Vdc
Enable delay time
80
ms
Disable delay time
10
µs
Figure 12— VOUT at full load vs. PC disable
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Source only
See Fig.12 time from PC low to output low
Figure 13— PC signal during fault
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V•I Chip Bus Converter Module
B048K120T30
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Page 5 of 16
PRELIMINARY
Specifications
V•I Chip Voltage Transformation Module
(continued)
Thermal
Symbol
Parameter
Min
Typ
Max
Unit
Over temperature shutdown
125
130
135
°C
Thermal capacity
0.61
Ws/°C
RθJC
Junction-to-case thermal impedance
1.1
1.5
RθJB
Junction-to-BGA thermal impedance
2.1
2.5
°C/W
RθJA
Junction-to-ambient (1)
6.5
7.2
°C/W
RθJA
Junction-to-ambient (2)
5.0
5.5
°C/W
Note
Junction temperature
BGA package
°C/W
Notes:
(1 B048K120T30 surface mounted in-board to a 2" x 2" FR4 board, 4 layers 2 oz Cu, 300 LFM.
(2) B048K120T30 with optional 0.25"H Pin Fins surface mounted on FR4 board, 300 LFM.
V•I Chip Stress Driven Product Qualification Process
Test
Standard
Environment
High Temperature Operational Life (HTOL)
Temperature cycling
High temperature storage
Moisture resistance
Temperature Humidity Bias Testing (THB)
Pressure cooker testing (Autoclave)
Highly Accelerated Stress Testing (HAST)
Solvent resistance/marking permanency
Mechanical vibration
Mechanical shock
Electro static discharge testing – human body model
Electro static discharge testing – machine model
JESD22-A-108-B
JESD22-A-104B
JESD22-A-103A
JESD22-A113-B
EIA/JESD22-A-101-B
JESD22-A-102-C
JESD22-A-110B
JESD22-B-107-A
JESD22-B-103-A
JESD22-B-104-A
EIA/JESD22-A114-A
EIA/JESD22-A115-A
Per Vicor Internal
Test Specification(1)
125°C, Vmax, 1,008 hrs
-55°C to 125°C, 1,000 cycles
150°C, 1,000 hrs
Moisture sensitivity Level 5
85°C, 85% RH, Vmax, 1,008 hrs
121°C, 100% RH, 15 PSIG, 96 hrs
130°C, 85% RH, Vmax, 96 hrs
Solvents A, B & C as defined
20g peak, 20-2,000 Hz, test in X, Y & Z directions
1,500g peak 0.5 ms pulse duration, 5 pulses in 6 directions
Meets or exceeds 2,000 Volts
Meets or exceeds 200 Volts
Highly Accelerated Life Testing (HALT)
Per Vicor internal
test specification(1)
Dynamic cycling
Operation limits verified, destruct margin determined
Constant line, 0-100% load, -20°C to 125°C
Note:
(1) For details of the test protocols see Vicor’s website.
V•I Chip Ball Grid Array Interconnect Qualification
Test
BGA solder fatigue evaluation
Solder ball shear test
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Standard
Environment
IPC-9701
Cycle condition: TC3 (-40 to +125°C)
IPC-SM-785
Test duration: NTC-B (500 failure free cycles)
IPC-9701
Failure through bulk solder or copper pad lift-off
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V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
Page 6 of 16
PRELIMINARY
Pin/Control Functions
V•I Chip Voltage Transformation Module
+IN/-IN – DC Voltage Input Ports
The V•I Chip input voltage range should not be exceeded. An internal
under/over voltage lockout-function prevents operation outside of the
normal operating input range. The BCM turns ON within an input
voltage window bounded by the “Input under-voltage turn-on” and
“Input over-voltage turn-off” levels, as specified. The V•I Chip may be
protected against accidental application of a reverse input voltage by
the addition of a rectifier in series with the positive input, or a reverse
rectifier in shunt with the positive input located on the load side of the
input fuse.
The connection of the V•I Chip to its power source should be
implemented with minimal distribution inductance. If the interconnect
inductance exceeds 100 nH, the input should be bypassed with a RC
damper to retain low source impedance and stable operation. With an
interconnect inductance of 200 nH, the RC damper may be a 47 µF in
series with 0.3Ω. A single electrolytic or equivalent low-Q capacitor
may be used in place of the series RC bypass.
4 3
+Out
-Out
+Out
-Out
21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
+In
TM
RSV
PC
-In
Bottom View
PC – Primary Control
The Primary Control port is a multifunction node that provides the
following functions:
Enable/Disable – If the PC port is left floating, the BCM output is
enabled. Once this port is pulled lower than 2.4 Vdc with respect
to –In, the output is disabled. This action can be realized by
employing a relay, opto-coupler, or open collector transistor. Refer
to Figures 1-3, 12 and 13 for the typical Enable/Disable
characteristics. This port should not be toggled at a rate higher
than 1 Hz. The PC port should also not be driven by or pulled up to
an external voltage source.
Primary Auxiliary Supply – The PC port can source up to 2.4 mA at
5.0 Vdc. The PC port should never be used to sink current.
Alarm – The BCM contains circuitry that monitors output overload,
input over voltage or under voltage, and internal junction
temperatures. In response to an abnormal condition in any of the
monitored parameters, the PC port will toggle. Refer to Figure 13
for PC alarm characteristics.
Signal
NameDesignation
+In
–In
TM
RSV
PC
+Out
–Out
BGA
A1-L1, A2-L2
AA1-AL1, AA2-AL2
P1, P2
T1, T2
V1, V2
A3-G3, A4-G4,
U3-AC3, U4-AC4
J3-R3, J4-R4,
AE3-AL3, AE4-AL4
Figure 14—BCM BGA configuration
TM and RSV – Reserved for factory use.
+OUT/-OUT – DC Voltage Output Ports
Two sets of contacts are provided for the +Out port. They must be
connected in parallel with low interconnect resistance. Similarly, two
sets of contacts are provided for the –Out port. They must be
connected in parallel with low interconnect resistance. Within the
specified operating range, the average output voltage is defined by the
Level 1 DC behavioral model of Figure 25. The current source capability
of the BCM is rated in the specifications section of this document.
The low output impedance of the BCM, reduces or eliminates the need
for limited life aluminum electrolytic or tantalum capacitors at the input
of POL converters.
Total load capacitance at the output of the BCM should not exceed the
specified maximum. Owing to the wide bandwidth and low output
impedance of the BCM, low frequency bypass capacitance and
significant energy storage may be more densely and efficiently provided
by adding capacitance at the input of the BCM.
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V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
Page 7 of 16
PRELIMINARY
Mechanical Drawings
V•I Chip Voltage Transformation Module
1,00
0.039
5,9
0.23
21,5
0.85
SOLDER BALL
#A1 INDICATOR
0.020
(106) X Ø 0.51
1,00
0.039
18,00
0.709
9,00
0.354
SOLDER BALL
SOLDER BALL #A1
OUTPUT
28,8
1.13
30,00
1.181
INPUT
OUTPUT
32,0
1.26
INPUT
1,00 TYP
0.039
C
L
15,00
0.591
16,0
0.63
C
L
1,6
0.06
TOP VIEW (COMPONENT SIDE)
1,00
0.039
BOTTOM VIEW
3,9
0.15
15,6
0.62
NOTES:
mm
1- DIMENSIONS ARE inch .
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
3- PRODUCT MARKING ON TOP SURFACE
SEATING PLANE
Figure 15— BCM BGA mechanical outline; Inboard mounting
IN-BOARD MOUNTING
BGA surface mounting requires a
cutout in the PCB in which to recess the V•I Chip
1,50
0.059
( 1,00 )
0.039
(ø
0,51
)
0.020
0,50
0.020
SOLDER MASK
DEFINED PADS
ø 0,53 PLATED VIA
0.021
CONNECT TO
INNER LAYERS
0,50
0.020
( 1,00 )
0.039
1,00
0.039
1,00
0.039
18,00
0.709
1,00
0.039
9,00
0.354
SOLDER PAD #A1
1
(4) X 6,00
0.236
+IN
+OUT1
(2) X 10,00
0.394
-OUT1
(COMPONENT SIDE SHOWN)
29,26
1.152
RSV
TM
RECOMMENDED LAND AND VIA PATTERN
PCB CUTOUT
24,00
0.945
16,00
0.630
NOTES:
mm
1- DIMENSIONS ARE inch .
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
8,00
0.315
-OUT2
-IN
PC
+OUT2
20,00
0.787 17,00
0.669 15,00 13,00
0.591
0.512
31
0,51
(106) X ø
0.020
SOLDER MASK
DEFINED PAD
0,37
0.015
8,08
0.318
16,16
0.636
1,6
(4) X R 0.06
Figure 16—BCM BGA PCB land/VIA layout information; Inboard mounting
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V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
Page 8 of 16
PRELIMINARY
Mechanical Drawings (continued)
V•I Chip Voltage Transformation Module
6,1
0.24
22,0
0.87
15,99
0.630
3,01
0.118
3,01
0.118
INPUT
OUTPUT
11,10 (2) PL.
0.437
24,00
0.945
OUTPUT
32,0
1.26
INPUT
(4) PL. 7,10
0.280
CL
16,00
0.630
15,55
0.612
12,94
0.509
8,00
0.315
20,00
0.787
C
L
0,45
0.018
TOP VIEW (COMPONENT SIDE)
14,94
0.588
16,94
0.667
BOTTOM VIEW
NOTES:
1- DIMENSIONS ARE mm/[INCH].
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
3- PRODUCT MARKING ON TOP SURFACE.
Figure 17— BCM J-Lead mechanical outline; Onboard mounting
3,26
0.128
3,26
0.128
15,74
0.620
0,51
TYP
0.020
(2) X14,94
0.588
-OUT2
12,94
(2) X 0.509
-IN
20,00
(2) X 0.787
(2) X16,94
0.667
+OUT2
PC RSV TM
1,60
0.063
7,48
(8) X 0.295
-OUT1
(6) X
+OUT1
(4) X 11,48
0.452
+IN
1,38
0.054 TYP
(2) X 24,00
0.945
(2) X 16,00
0.630
8,00
(2) X 0.315
RECOMMENDED LAND PATTERN
(COMPONENT SIDE SHOWN)
NOTES:
1- DIMENSIONS ARE mm/[INCH].
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
Figure 18— BCM J-Lead PCB land layout information; Onboard mounting
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V•I Chip Bus Converter Module
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Page 9 of 16
PRELIMINARY
Configuration Options
V•I Chip Voltage Transformation Module
Configuration
Inboard (1)
(Package K)
Onboard (1)
(Package F)
Inboard with 0.25"
Pin Fins (2)
Onboard with 0.25"
Pin Fins (2)
Effective power density
1750 W/in3
1090 W/in3
680 W/in3
550 W/in3
2.1 °C/W
2.4 °C/W
2.1 °C/W
2.4 °C/W
1.1 °C/W
1.1 °C/W
N/A
N/A
6.5 °C/W
6.8 °C/W
5.0 °C/W
5.0 °C/W
Junction-Board
thermal resistance
Junction-Case
thermal resistance
Junction-Ambient
thermal resistance 300LFM
Notes:
(1) Surface mounted to a 2" x 2" FR4 board, 4 layers 2 oz Cu
(2) Pin Fin heat sink available as a separate item
21.5
0.85
22.0
0.87
32.0
1.26
32.0
1.26
4.0
0.16
6.3
0.25
ONBOARD MOUNT
INBOARD MOUNT
(V•I Chip recessed into PCB)
mm
in
mm
in
Figure 20— Onboard mounting – package F
Figure 19—Inboard mounting – package K
Input reflected ripple
measurement point
F1
15 A
Fuse
+Out
+In
+
Enable/Disable Switch
-Out
C1
47 µF
R2
2K Ω
electrolytic
SW1
TM
RSV
PC
D1
-In
BCM
K
Ro
R3
10 mΩ
typ.
+Out
-Out
Load
C3
10 µF
–
Notes:
Source inductance should be no more than 200 nH. If source inductance is
greater than 200 nH, additional bypass capacitance may be required.
C3 should be placed close to the load.
R3 may be ESR of C3 or a seperate damping resistor.
D1 power good indicator will dim when a module fault is detected.
Figure 21—BCM test circuit
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V•I Chip Bus Converter Module
B048K120T30
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Page 10 of 16
PRELIMINARY
Application Note
V•I Chip Voltage Transformation Module
Parallel Operation
The BCM will inherently current share when properly configured in an
array of BCMs. Arrays may be used for higher power or redundancy in
an application.
Current sharing accuracy is maximized when the source and load
impedance presented to each BCM within an array are equal.
The recommended method to achieve matched impedances is to
dedicate common copper planes within the PCB to deliver and return the
current to the array, rather than rely upon traces of varying lengths. In
typical applications the current being delivered to the load is larger than
that sourced from the input, allowing traces to be utilized on the input
side if necessary. The use of dedicated power planes is, however,
preferable.
CASE 2—Conduction to the PCB
The low thermal resistance Junction-to-BGA, RθJB, allows use of the PCB
to exchange heat from the V•I Chip, including convection from the PCB
to the ambient or conduction to a cold plate.
For example, with a V•I Chip surface mounted on a 2" x 2" area of a
multi-layer PCB, with an aggregate 8 oz of effective copper weight, the
total Junction-to-Ambient thermal resistance, RθJA, is 6.5°C/W in 300
LFM air flow (see Thermal Resistance section, Page 1). Given a maximum
junction temperature of 125°C and 13 W dissipation at 300 W of output
power, a temperature rise of 85°C allows the V•I Chip to operate at
rated output power at up to 41°C ambient temperature.
The BCM power train and control architecture allow bi-directional power
transfer, including reverse power processing from the BCM output to its
input. Reverse power transfer is enabled if the BCM input is within its
operating range and the BCM is otherwise enabled. The BCM’s ability to
process power in reverse improves the BCM transient response to an
output load dump.
Output Power
300
Thermal Management
The high efficiency of the V•I Chip results in relatively low power
dissipation and correspondingly low generation of heat. The heat
generated within internal semiconductor junctions is coupled with low
effective thermal resistances, RθJC and RθJB, to the V•I Chip case and its
Ball Grid Array allowing thermal management flexibility to adapt to
specific application requirements (Figure 22).
0
-40
-20
0
20
40
60
80
100
120
140
Operating Junction Temperature
CASE 1 Convection via optional Pin Fins to air.
Figure 23— Thermal derating curve
BCM with 0.25'' optional Pin Fins
10
9
8
Tja
If the application is in a typical environment with forced convection over
the surface of the PCB and greater than 0.4" headroom, a simple
thermal management strategy is to procure V•I Chips with the Pin Fin
option. The total Junction-to-Ambient thermal resistance, RθJA, of a
surface mounted V•I Chip with optional 0.25" Pin Fins is 4.8 °C/W in
300 LFM air flow (Figure 24). At full rated output power of 300 W, the
heat generated by the BCM is approximately 13 W (Figure 6). Therefore,
the junction temperature rise to ambient is approximately 62°C. Given a
maximum junction temperature of 125°C, a temperature rise of 62°C
allows the V•I Chip to operate at rated output power at up to 63°C
ambient temperature. At 100 W of output power, operating ambient
temperature extends to 103°C.
7
6
5
4
3
θJC = 1.1°C/W
0
100
200
300
400
500
600
Airflow (LFM)
θJB = 2.1°C/W
Figure 22—Thermal resistance
Figure 24—Junction-to-ambient thermal resistance of BCM with 0.25"
Pin Fins (Pin Fins available as a separate item.)
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V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
Page 11 of 16
PRELIMINARY
Application Note (continued)
V•I Chip Voltage Transformation Module
The TM (Temperature Monitor) port monitors the V•I Chip junction
temperature and provides feedback and validation of the thermal
management of V•I Chips, as applied in diverse power systems and
environments.
The thermal resistance of the PCB to the surrounding environment in
proximity to V•I Chips may be reduced by low profile heat sinks surface
mounted to the PCB.The PCB may also be coupled to a cold plate by low
thermal resistance standoff elements as a means of achieving effective
cooling for an array of V•I Chips, without a direct interface to their case.
CASE 3—Combined direct convection to the air and conduction to the PCB.
Parallel use of the V•I Chip internal thermal resistances (including Junctionto-Case and Junction-to-BGA) in series with external thermal resistances
provides an efficient thermal management strategy as it reduces total
thermal resistance. This may be readily estimated as the parallel network of
two pairs of series configured resistors.
V•I Chip Bus Converter Level 1 DC Behavioral Model for 48 V to 12 V, 300 W
ROUT
IOUT
+
+
11.7 mΩ
1/4 • Iout
VIN
V•I
+
+
–
IQ
99 mA
1/4 • Vin
VOUT
–
K
–
–
©
Figure 25—This model characterizes the DC operation of the V•I Chip bus converter, including the converter transfer function and its losses. The model enables
estimates or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation.
V•I Chip Bus Converter Level 2 Transient Behavioral Model for 48 V to 12 V, 300 W
8.5 nH
ROUT
IOUT
L IN = 20 nH
+
11.7 mΩ
RCIN
2.5 mΩ
CIN
VIN
Lout = 1.1 nH
V•I
1/4 • Iout
+
+
–
4µF
IQ
99 mA
RCOUT
40 mΩ
+
1 mΩ
1/4 • Vin
COUT
55 µF
VOUT
–
K
–
–
©
Figure 26—This model characterizes the AC operation of the V•I Chip bus converter including response to output load or input voltage transients or steady state
modulations. The model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load with or
without external filtering elements.
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V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
Page 12 of 16
PRELIMINARY
Application Note (continued)
V•I Chip Voltage Transformation Module
Input Impedance Recommendations
Input Fuse Recommendations
To take full advantage of the BCM capabilities, the impedance presented
to its input terminals must be low from DC to approximately 5 MHz. The
source should exhibit low inductance (less than 100 nH) and should have a
critically damped response. If the interconnect inductance exceeds 100 nH,
the BCM input pins should be bypassed with an RC damper (e.g., 47 µF in
series with 0.3 ohm) to retain low source impedance and stable
operations. Given the wide bandwidth of the BCM, the source response is
generally the limiting factor in the overall system response.
V•I Chips are not internally fused in order to provide flexibility in
configuring power systems. However, input line fusing of V•I Chips must
always be incorporated within the power system. A fast acting fuse should
be placed in series with the +IN port.
Anomalies in the response of the source will appear at the output of the
BCM multiplied by its K factor. The DC resistance of the source should be
kept as low as possible to minimize voltage deviations. This is especially
important if the BCM is operated near low or high line as the over/under
voltage detection circuitry could be activated.
Application Circuits
Vo = 9.5 - 13.7 V
+Out
+In
-Out
48 Vin
(38 - 55 Vdc)
BCM
TM
RSV
PC
-In
K
Ro
+Out
-Out
NiPOL
1
NiPOL
2
NiPOL
3
NiPOL
4
LOAD
1
LOAD
2
LOAD
3
LOAD
4
Figure 27—The BCM provides an isolated output from a narrow range input ideal for driving non-isolated point of load converters (niPOLs)
In the following figure;
K = BCM Transformation Ratio
RO = BCM Output Resistance
VO = BCM Output
Vf = PRM Output (Factorized Bus Voltage)
VL = Desired Load Voltage
VS = PRM Output Set Point Voltage
FPA Local Loop
Vo = VL – IO • RO
VC
PC
TM
IL
NC
PR
PRM-AL
+In
VH
SC
SG
OS
NC
CD
ROS
Factorized
Power Bus
+Out
48 Vin
(36 - 75 Vdc)
Vf =
–In
VL
K
–Out
+Out
+In
-Out
TM
RSV
PC
-In
BCM
K
Ro
+Out
L
O
A
D
-Out
VS range = 38 - 55 Vdc
B048K120T30
(K = 1/4 : RO = 11.7 mΩ)
Figure 28—The PRM regulates its output to provide a constant factorized bus voltage. The output voltage is the nominal load voltage, Vo, at no
load and decreases with load at a constant rate equal to the BCM output resistance Ro.
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V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
Page 13 of 16
PRELIMINARY
Application Note (continued)
V•I Chip Voltage Transformation Module
V•I Chip soldering recommendations
Removal and rework
V•I Chip modules are intended for reflow soldering processes. The
following information defines the processing conditions required for
successful attachment of a V•I Chip to a PCB. Failure to follow the
recommendations provided can result in aesthetic or functional failure
of the module.
V•I Chip modules can be removed from PCBs using special tools such
as those made by Air-Vac. These tools heat a very localized region of
the board with a hot gas while applying a tensile force to the
component (using vacuum). Prior to component heating and removal,
the entire board should be heated to 80-100ºC to decrease the
component heating time as well as local PCB warping. If there are
adjacent moisture-sensitive components, a 125ºC bake should be used
prior to component removal to prevent popcorning. V•I Chip modules
should not be expected to survive a removal operation.
Storage
V•I Chip modules are currently rated at MSL 5. Exposure to ambient
conditions for more than 72 hours requires a 24 hour bake at 125ºC to
remove moisture from the package.
Solder paste stencil design
239
Solder paste is recommended for a number of reasons, including
overcoming minor solder sphere co-planarity issues as well as simpler
integration into overall SMD process.
63/37 SnPb, either no-clean or water-washable, solder paste should be
used. Pb-free development is underway.
The recommended stencil thickness is 6 mils. The apertures should be
20 mils in diameter for the Inboard (BGA) application and 0.9-0.9:1 for
the Onboard (J-Leaded).
Joint Temperature, 220ºC
Case Temperature, 208ºC
183
165
degC
91
Pick and place
Inboard (BGA) modules should be placed as accurately as possible
to minimize any skewing of the solder joint; a maximum offset of
10 mils is allowable. Onboard (J-Leaded) modules should be placed
within ±5 mils.
16
Soldering Time
Figure 29—Thermal profile diagram
To maintain placement position, the modules should not be subjected
to acceleration greater than 500 in/sec2 prior to reflow.
Reflow
There are two temperatures critical to the reflow process; the solder
joint temperature and the module’s case temperature. The solder joint’s
temperature should reach at least 220ºC, with a time above liquidus
(183ºC) of ~30 seconds.
The module’s case temperature must not exceed 208 ºC at anytime
during reflow.
Because of the ∆T needed between the pin and the case, a forced-air
convection oven is preferred for reflow soldering. This reflow method
generally transfers heat from the PCB to the solder joint. The module’s
large mass also reduces its temperature rise. Care should be taken to
prevent smaller devices from excessive temperatures. Reflow of
modules onto a PCB using Air-Vac-type equipment is not recommended
due to the high temperature the module will experience.
Figure 30— Properly reflowed V•I Chip J-Lead
Inspection
For the BGA-version, a visual examination of the post-reflow solder
joints should show relatively columnar solder joints with no bridges. An
inspection using x-ray equipment can be done, but the module’s
materials may make imaging difficult.
The J-Lead versions solder joints should conform to IPC 12.2
• Properly wetted fillet must be evident.
• Heel fillet height must exceed lead thickness plus solder thickness.
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V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
Page 14 of 16
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in
normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper
application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended
to the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT
NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgement. For service under this
warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping
instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges
incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within
the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is
assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve
reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or
circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not
recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten
life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes
all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC
and DC-DC modules and accessory components, fully configurable AC-DC
and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for
its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or
malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are
available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent
applications) relating to the products described in this data sheet. Interested parties should contact Vicor's
Intellectual Property Department.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Vicor Express: [email protected]
Technical Support: [email protected]
vicorpower.com
800-735-6200
V•I Chip Bus Converter Module
B048K120T30
Rev. 1.0
01/05