512K x 8 Static RAM MSM8512C - 020 Issue 5.2 April 2001 Description The MSM8512C is a 512K x 8 SRAM monolithic device available in Chip Size BGA (Ball Grid Array) package, with access times of 20ns. The device is available to commercial and industrial temperature grades. The Chip Size BGA provides an ultra high density memory packaging solution. The Chip Size BGA occupies less than 50% of the board area of conventional SOP, SOJ and TSOP II packages. Block Diagram /CS A0 A1 A2 A3 A4 A5 A6 A7 A8 /OE /WE D0 D1 D2 D3 D4 D5 D6 D7 512K x 8 SRAM Features Package Details 48D - 48 Ball, 1mm pitch Chip Size BGA Max. Dimensions (mm) - 8.00 x 10.00 x 1.40 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 • Access times of 20 ns. • 5V + 10%, (3.3V Under Development) • Commercial & Industrial temperature grades • Chip Size BGA. • 48 pad, 1mm pad pitch, package. • Eutectic 63/67 solder ball attach. • Low Power Dissipation. Operating 1 W (max) Standby (CMOS) 66mW (max) • Completely Static Operation. • 4 layer BT substrate with power and ground planes. • Pinout and footprint will remain the same in the event of a die shrink. Pin Definition See page 2. Pin Functions Description Signal Address Input Data Input/Output Chip Select Write Enable Output Enable No Connect Power Ground A0~A18 D0~D7 /CS /WE /OE NC VCC GND Pin Definition - MSM8512B Pinout (Top View) 1 2 3 4 A A4 A2 A0 A17 A15 NC B NC /CS A1 A16 NC NC C D0 NC A3 /OE NC D7 D VCC D1 A18 NC D6 VSS E VSS D2 NC A9 D5 VCC F D3 NC A5 A13 NC D4 G NC /WE A7 A11 A14 NC H NC A8 A10 A12 NC 5 6 Pin A1 Ident. A6 Note : Pinout shows top view, balls facing down. PAGE 2 Issue 5.2 April 2001 Absolute Maximum Ratings(1) Symbol Voltage on any pin relative to VSS VT Power Dissipation PT Storage Temperature TSTG Min -0.5 to Max Unit +6.0 V 1 -55 W to O +150 C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 - 6.0 V Input Low Voltage VIL -0.3 - 0.8 V Operating Temperature TA 0 - 70 TAI -40 - 85 O C O C (I Suffix) DC Electrical Characteristics (VCC=5V+10%, TA= -40OC to 85OC) Parameter Symbol Test Condition Min Typ Max Unit Input Leakage Current ILI VIN=VSS to VCC -2 - 2 µA Output Leakage Current ILO /CS=VIH or /OE=VIH or /WE=VIL, VOUT=VSS to VCC -2 - 2 µA Operating Supply Current ICC1 Min. Cycle, 100% Duty /CS=VIL, VIN=VIH or VIL, IOUT=0mA - - 180 mA Standby Supply Current ISB Min. Cycle, /CS=VIH - - 60 mA ISB1 f=0MHz, CS>VCC-0.2V, VIN>VCC-0.2V or VIN<0.2V - - 12 mA VOL IOL=8.0mA - - 0.4 V VOH IOH=-4.0mA 2.4 - - V Output Voltage PAGE 3 Issue 5.2 April 2001 DC Operating Conditions Parameter Capacitance (VCC = 5.0V+10% TA = 0OC to 70OC) Parameter Symbol Test Condition Typ max Unit Input Capacitance CIN VIN=0V - 10 pF I/O Capacitance CI/O VI/O=0V - 10 pF Test Conditions • • • • • Output Load Input pulse levels : 0V to 3.0V Input rise and fall times : 3ns Input and Output timing reference levels : 1.5V Output Load : See Load Diagram. VCC = 5V+10% I/O Pin 166Ω 1.76V 30pF Functional Description /CS /WE /OE Mode I/O Pin Supply Current H X X Not Select High-Z ISB,ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC Note : X = Don’t Care PAGE 4 Issue 5.2 April 2001 AC Operating Conditions Read Cycle 20 Parameter Symbol Min Max Units Read Cycle Time tRC 20 - ns Address Access Time tAA - 20 ns Chip Select to Output tCO - 20 ns Output Enable to Valid Output tOE - 9 ns Chip Enable to Low-Z Output tLZ 3 - ns Output Enable to Low-Z Output tOLZ 0 - ns Chip Disable to High-Z Output tHZ 0 9 ns Output Disable to High-Z Output tOHZ 0 9 ns Output Hold from Address Change tOH 3 - ns Min Max Units Write Cycle 20 Parameter PAGE 5 Symbol Write Cycle Time tWC 20 - ns Chip Select to End of Write tCW 14 - ns Address Set-up Time tAS 0 - ns Address Valid to End of Write tAW 14 - ns Write Pulse Width (/OE High) tWP 14 - ns Write Recovery Time tWR 0 - ns Write to Output High-Z tWHZ 0 9 ns Data to Write Time Overlap tDW 10 - ns Data Hold from Write Time tDH 0 - ns End Write to Output Low-Z tOW 3 - ns Issue 5.2 April 2001 Timing Waveforms Read Cycle 1 (Address Controlled, /CS=/OE=VIL, /WE=VIH) tRC Address tAA tOH Data Out Previous Data Valid Data Valid Read Cycle 2 (/WE = VIH) tRC Address tAA tCO tHZ(3,4,5) /CS tOHZ tOE /OE tOLZ tOH tLZ(4,5) Data Out Valid Data NOTES(READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=VIL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. PAGE 6 Issue 5.2 April 2001 Write Cycle 1 (/OE = Clock) tWC Address tAW tWR(5) /OE tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z Data In Valid Data tOHZ(6) High Z(8) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. PAGE 7 Issue 5.2 April 2001 Write Cycle 2 (/OE = Low Fixed) tWC Address tAW tWR(5) tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z Data In Valid Data tOW tWHZ(6) High Z(8) (10) (9) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. PAGE 8 Issue 5.2 April 2001 Write Cycle 3 (/CS = Controlled) tWC Address tAW tWR(5) tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z High Z Valid Data Data In tLZ High Z tWHZ(6) High Z(8) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. PAGE 9 Issue 5.2 April 2001 Package Details Chip Size BGA - 48 pad 8.00 Max. 10.00 Max. Top View 1.40 Max. Pin A1 Ident. 1.00+0.07 CL A1 1.00+0.07 CL Bottom View H6 General Reliability Data 125 C / 6V / 1000hrs High Temperature Storage Life 150 C / 1000hrs Autoclave 121 C / 100% RH / 168hrs Temperature Cycling -55 ~ 125 C / 1000 cycles Moisture Sensitivity JEDEC Level 3 30 C / 60% RH / 192hrs O JA Thermal Performance PAGE 10 O High Temperature Operating Life O O O O O 30 ~ 45 C/Watt Issue 5.2 April 2001 Ordering Information 48D 48D = 48 Pad package, 1mm Pitch Speed 020 = 20ns Temp. Range/Screening Blank = Commercial I = Industrial Power Consumption Blank = Standard Power Package B = Chip Size BGA Die Revision C = ‘C’ Rev die. Memory Organisation 8512 = 512K x 8 Family M = Monolithic Technology S = SRAM Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. PAGE 11 Issue 5.2 April 2001 Ordering Information MSM8512CB I - 020/48D