NX9548 9A SINGLE CHANNEL MOBILE PWM SWITCHING REGULATOR PRELIMINARY DATA SHEET Pb Free Product FEATURES DESCRIPTION The NX9548 is buck switching converter in multi chip module designed for step down DC to DC converter in portable applications. It is optimized to convert single supply up to 24V bus voltage to as low as 0.75V output voltage.The output current can be up to 9A. It can be selected to operate in synchronous mode or non-synchronous mode to improve the efficiency at light load. Constant on time control provides fast response, good line regulation and nearly constant frequency under wide voltage input range. Over current protection and FB UVLO followed by latch feature. Other features includes: internal boost schottky diode, 5V gate drive capability, power good indicator, over current protection, over voltage protection and adaptive dead band control.NX9548 is available in 5x5 MCM package. n Internal Boost Schottky Diode n Ultrasonic mode operation available n Bus voltage operation from 4.5V to 24V n Less than 1uA shutdown current with Enable low n Excellent dynamic response with constant on time control n Selectable between Synchronous CCM mode and diode emulation mode to improve efficiency at light load n Programmable switching frequency n Current limit and FB UVLO with latch off n Over voltage protection with latch off n n n n APPLICATIONS UMPC, Notebook PCs and Desknotes Tablet PCs/Slates On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Hand-held portable instruments TYPICAL APPLICATION PGOOD 1M PGOOD TON 1n 100k VIN 8V~22V D1 2x10uF PVCC 5V 1u VCC 1u ENSW /MODE NX9 5 4 8 10 HG BST 4.7 1u 3.3uH S1 D2 Vout 1.5V/9A 2R5TPE330MC 330uF 10k OCP VOUT 330p 7.5k FB HDRV 7.5k GND S2 Figure 1 - Typical application of 9548 ORDERING INFORMATION Device NX9548CMTR Rev.1.6 03/06/09 Temperature 0 to 70oC Package 5X5 MCM-32L Pb-Free Yes 1 NX9548 ABSOLUTE MAXIMUM RATINGS VCC,PVCC to GND & BST to SW voltage ........... -0.3V to 6.5V TON to GND ................................................. .... -0.3V to 28V HDRV to SW Voltage ....................................... -0.3V to 6.5V D1 to S1and D2 to S2 ........................................ 30V All other pins .................................................... -0.3V to VCC+0.3V or 6.5V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC ESD Susceptibility ........................................... 2kV Power Dissipation ............................................. TBD Output Current ...................................................TBD CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION VCC FB PGOOD GND HG D1 D1 D1 32-LEAD PLASTIC MCM 5 x 5 32 31 30 29 28 27 26 25 Rev.1.6 03/06/09 24 TON S1 1 S1 2 S1 3 D1 4 21 GND D2 5 20 BST D2 6 D2 7 D2 8 D1 (PAD2) 23 VOUT GND (PAD1) 22 ENSW/MODE 19 D2 D2 (PAD3) 18 HDRV OCP PVCC S2 S2 S2 S2 10 11 12 13 14 15 16 S2 9 S2 17 NC 2 NX9548 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc = 5V, VIN = 12V and TA= 0 to 70oC. Typical values refer to TA = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER SYM Test Condition Min TYP MAX Units VIN recommended voltage range Shut down current VCC,PVCC Supply Input voltage range Operating quiescent current Shut down current VCC UVLO Under-voltage Lockout threshold Falling VCC threshold ON and OFF time TON operating current ON -time Minimum off time FB voltage Internal FB voltage Input bias current Line regulation OUTPUT voltage Output range VOUT shut down discharge resistance Soft start time PGOOD PGOOD high rising threshold PGOOD delay after softstart PGOOD propagation delay filter PGOOD hysteresis PGOOD output switch impedance PGOOD leakage current ENSW/MODE threshold and bias current 4.5 ENSW=GND Vin FB=0.85V, ENSW =5V ENSW=GND Rev.1.6 03/06/09 5.5 1.8 V mA 1 uA 4.1 3.9 V V 15 uA 390 590 ns ns VCC_UVLO VIN=15V, Rton=1Mohm VIN=9V,VOUT=0.75V,Rton= 1Mohm Vref 0.75 VCC from 4.5V to 5.5V -1 200 1 V nA % 0.75 3.3 V ENSW/MODE=GND NOTE1 NOTE1 30 1.5 ohm ms 90 1.6 % Vref ms 2 5 us % 13 1 ohm uA 80% VCC 60% VCC Ultrasonic Mode Input bias current V uA 1 4.5 PFM/Non Synchronous Mode Synchronous Mode Shutdown mode 24 Leave it open or use limits in spec ENSW/MODE=VCC ENSW/MODE=GND VCC+0 .3V 80% VCC 60% VCC 0.8 2 0 5 -5 V V V V uA uA 3 NX9548 PARAMETER SYM Test Condition Min TYP MAX Units SW zero cross comparator Offset voltage Current Limit Ocset setting current Over temperature Threshold Hysteresis Under voltage FB threshold Over voltage Over voltage tripp point Internal Schottky Diode Forward voltage drop Ouput Stage High Side MOSFET RDSON Low Side MOSFET R DSON Output Current NOTE1 forward current=50mA 5 mV 24 uA 155 15 o C C o 70 %Vref 125 %Vref 500 mV 20 17 9 mohm mohm A NOTE1: This parameter is guaranteed by design but not tested in production(GBNT). Rev.1.6 03/06/09 4 NX9548 PIN DESCRIPTIONS PIN # 1-3 PIN SYMBOL PIN DESCRIPTION S1 Source of high side MOSFET.These pins must be connected directly to the drain of low side MOSFET via a plane connection. 4,30-32 PAD2 D1 Drain of high side MOSFET. 5-8,19, PAD3 D2 Drain of low side MOSFET and the controller pin out SW. 9-14 S2 Source of low side MOSFET and need to be directly connected to power ground via multiple vias. 15 PVCC 16 OCP 17 NC 18 HDRV High side gate driver output which needs to be connected to high side MOSFET gate HG pin. A small value resistor may be placed between two pins to slow down the high side MOSFET, reducing the ringing on SW nodes. 20 BST This pin supplies voltage to high side FET driver. A minimum high freq 0.47uF ceramic capacitor is placed as close as possible to and connected to this pin and respected pin 19.A 4.7ohm resister is recommended in series with this capacitor. 22 ENSW/ MODE Switching converter enable input. Connect to VCC for PFM/Non synchronous mode, connected to an external resistor divider equals to 70%VCC for ultrasonic, connected to GND for shutdown mode, floating or connected to 2V for the synchronous mode. 23 VOUT This pin is directly connected to the output of the switching regulator and senses the VOUT voltage. An internal MOSFET discharges the output during turn off. 24 TON VIN sensing input. A resistor connects from this pin to VIN will set the frequency. A 1nF capacitor from this pin to GND is recommended to ensure the proper operation. 25 VCC This pin supplies the internal 5V bias circuit. A 1uF X7R ceramic capacitor is placed as close as possible to this pin and ground pin. 26 FB 27 PGOOD 21,28 PAD1 GND 29 HG Rev.1.6 03/06/09 This pin provides the voltage supply to the lower MOSFET drivers. Place a high frequency decoupling capacitor 1uF X5R from this pin to GND. This pin is connected to the drain of the external low side MOSFET via resistor and is the input of the over current protection(OCP) comparator. An internal current source is flown from this pin to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rdson. Once this threshold is reached the chip is latched out. Not used. This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage from 0.75V to 3.3V. PGOOD indicator for switching regulator. It requires a pull up resistor to Vcc or lower voltage. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state. Ground pin. High side MOSFET gate. 5 NX9548 BLOCK DIAGRAM BST HDRV HG D1 VCC Bias 4.3/4.1 Disable_B Thermal shutdown TON ON time pulse genearation VOUT POR start ODB HD R S FET Driver HD_IN Q S1 D2 FB Mini offtime 400ns OCP_COMP S2 VREF=0.75V start POR FBUVLO_latch soft start Diode emulation HD PVCC VCC ENSW /MODE 1M 1M Disable MODE SELECTION PFM_nonultrasonic Sync OCP FB 1.25*Vref/0.7VREF OCP_COMP OVP GND FB FBUVLO_latch 0.7*Vref SS_finished VOUT VOUT start PGOOD 0.9*Vref Figure 2 - Simplified block diagram of the NX9548 Rev.1.6 03/06/09 6 NX9548 Demoboard design and waveforms sdfd 27 PGOOD PGOOD TON R6 10k D1 15 5V C6 1u 25 VCC C7 1u ENSW 22 /MODE 29 18 HG HDRV NX9548 R5 10 PVCC BST R1 1M 24 C3 1n 4,30-32,PAD2 C1 2 x 4.7uF,25V,X5R 20 S1 1-3 5-8,19,PAD3 D2 VOUT C2 10uF,25V,X5R R6 4.7 C4 1u OCP 16 VIN 8V~22V DO5010H-332MLD L1 3.3uH Vout 1.5V/9A 2R5TPE330MC C5 330uF R2 10k 23 FB 26 C8 330p R3 7.5k R4 7.5k GND S2 9-14 21,28,PAD1 Figure 3 - Demoboard schematic of NX9548 Rev.1.6 03/06/09 7 NX9548 Bill of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 Rev.1.6 03/06/09 Quantity 2 1 1 3 1 1 1 2 2 1 1 1 1 Reference C1 C2 C3 C4,C6,C7 C5 C8 R1 R2,R6 R3,R4 R5 R6 L1 U1 Part 4.7uF,25V,X5R 10uF,25V,X5R 1nF,50V,X7R 1uF,10V,X7R 2R5TPE330MC 330pF 1MEG 10k 7.5k 10 4.7 DO5010H-332MLD NX9548 Manufacturer SANYO COILCRAFT NEXSEM INC. 8 NX9548 Demoboard Waveforms Fig.4 Startup when 5V is present and 12V bus is started up, output load current is at 1.5A. Fig.6 Shutdown when 12V bus is present and 5V is shuted down. Fig.8 5A step response(VIN=5V) Rev.1.6 03/06/09 Fig.5 Startup when 12V bus is present and 5V is started up. Fig.7Output ripple (VIN=15V IOUT=1.2A) Fig.9 5A step response(VIN=20V) 9 NX9548 Demoboard Waveforms(Cont') VIN=12V, VOUT=1.5V 92.00% 90.00% EFFICIENCY 88.00% 86.00% 84.00% 82.00% 80.00% 78.00% 10 100 1000 10000 OUTPUT CURRENT(mA) Fig.10 Output efficiency at different load IOUT=10A, VOUT=1.5V 79.00% EFFICIENCY 78.60% 78.20% 77.80% 77.40% 77.00% 0 5 10 15 20 25 VIN(V) Fig.11 Output efficiency at different VIN bus voltage Rev.1.6 03/06/09 10 NX9548 APPLICATION INFORMATION Symbol Used In Application Information: VIN - Input voltage VOUT - Output voltage IOUT - Output current Output Inductor Selection The value of inductor is decided by inductor ripple current and working frequency. Larger inductor value normally means smaller ripple current. However if the in- DVRIPPLE - Output voltage ripple FS is around 220kHz. ductance is chosen too large, it brings slow response - Working frequency and lower efficiency. The ripple current is a design free- DIRIPPLE - Inductor current ripple dom which can be decided by design engineer according to various application requirements. The inductor value Design Example can be calculated by using the following equations: The following is typical application for NX9548, the schematic is figure 1. LOUT = VIN = 8 to 22V ( VIN -VOUT ) × TON IRIPPLE ...(3) IRIPPLE =k × IOUTPUT VOUT=1.5V FS=220kHz where k is percentage of output current. In this example, inductor from COILCRAFT DO5010H-332 with L=3.3uH is chosen. IOUT=9A DVRIPPLE <=60mV DVDROOP<=60mV @ 3A step Current Ripple is recalculated as below: On_Time and Frequency Calculation IRIPPLE = The constant on time control technique used in NX9548 delivers high efficiency, excellent transient dynamic response, make it a good candidate for step down (VIN -VOUT ) × TON L OUT (22V-1.5V) × 310nS 3.3uH =1.925A = ...(4) notebook applications. An internal one shot timer turns on the high side driver with an on time which is proportional to the input supply VIN as well inversely proportional to the output voltage VOUT. During this time, the output inductor charges the output cap increasing the output voltage by the amount equal to the output ripple. Once the timer turns off, the Hdrv turns off and cause the output voltage to decrease until reaching the internal FB voltage of 0.75V on the PFM comparator. At this point the comparator trips causing the cycle to repeat itself. A minimum off time of 400nS is internally set. 4.45 × 10 −12 × R TON × VOUT VIN − 0.5V VOUT FS = VIN × TON state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both conditions. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(5). ∆IRIPPLE ...(5) 8 × FS × COUT Where ESR is the output capacitors' equivalent ...(1) series resistance,COUT is the value of output capacitors. Typically POSCAP is recommended to use in ...(2) In this application example, the RTON is chosen to be 1Mohm, when VIN=22V, the TON is 310nS and FS Rev.1.6 03/06/09 Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady ∆VRIPPLE = ESR × ∆IRIPPLE + The equation setting the On Time is as follows: TON = Output Capacitor Selection NX9548's applications. The amount of the output voltage ripple is dominated by the first term in equation(5) and the second term can be neglected. For this example, one POSCAP 2R5TPE330MC 11 NX9548 is chosen as output capacitor, the ESR and inductor in parallel. current typically determines the output voltage ripple. The above equation shows that if the selected out- When VIN reach maximum voltage, the output voltage put inductor is smaller than the critical inductance, the ripple is in the worst case. voltage droop or overshoot is only dependent on the ESR ESRdesire = ∆VRIPPLE 30mV = = 15.5mΩ ∆IRIPPLE 1.925A of output capacitor. For low frequency capacitor such ...(6) as electrolytic capacitor, the product of ESR and ca- If low ESR is required, for most applications, mul- pacitance is high and L ≤ L crit is true. In that case, the tiple capacitors in parallel are needed. The number of transient spec is mostly like to dependent on the ESR output capacitor can be calculate as the following: of capacitor. Most case, the output capacitor is multiple capaci- E S R E × ∆ IR I P P L E N = ∆ VR IPPLE ...(7) tor in parallel. The number of capacitor can be calculated by the following 12mΩ×1.925A N= 30mV N= ESR E × ∆Istep ∆Vtran N =0.77 The number of capacitor has to be round up to a + VOUT × τ2 2 × L × C E × ∆Vtran where 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT integer. Choose N =1. Based On Transient Requirement ...(11) if L ≥ L crit ...(12) Typically, the output voltage droop during transient is specified as ∆V droop < ∆V tran @step load DISTEP For example, assume voltage droop during tran- During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other section is sient is 60mV for 3A load step. If one POSCAP 2R5TPE330MC(330uF, 12mohm ESR) is used, the crticial inductance is given as a function of the inductor, output capacitance as well as Lcrit = input, output voltage. For example, for the overshoot 12mΩ× 3300µF ×1.8V = 23.76µH 3A when load from high load to light load with a DISTEP transient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation. ∆Vovershoot = ESR × ∆Istep + VOUT × τ2 2 × L × COUT ...(8) where τ is the a function of capacitor,etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT if L ≥ L crit where L crit = The selected inductor is 3.3uH which is smaller than critical inductance. In that case, the output voltage transient mainly dependent on the ESR. number of capacitor is N= ...(9 ESR × COUT × VOUT ESR E × C E × VOUT = ...(10) ∆Istep ∆Istep ESRE × CE × VOUT = ∆Istep ESR E × ∆Istep ∆Vtran 12mΩ × 4.5A 60mV = 0.9 = Choose N=1. Based On Stability Requirement where ESRE and CE represents ESR and capaci- ESR of the output capacitor can not be chosen too tance of each capacitor if multiple capacitors are used low which will cause system unstable. The zero caused Rev.1.6 03/06/09 12 NX9548 by output capacitor's ESR must satisfy the requirement Vout as below: FESR = F 1 ≤ SW ...(13) 2 × π × ESR × COUT 4 R2 Fb Besides that, ESR has to be bigger enough so that the output voltage ripple can provide enough voltage ramp to error amplifier through FB pin. If ESR is too R1 Vref small, the error amplifier can not correctly dectect the ramp, high side MOSFET will be only turned off for minimum time 400nS. Double pulsing and bigger output ripple will be observed. In summary, the ESR of output capaci- Figure 12 - Voltage Divider tor has to be big enough to make the system stable, but also has to be small enough to satify the transient and DC ripple requirements. R 1= R 2 × VR E F V O U T -V R E F ...(15) where R2 is part of the compensator, and the value Input Capacitor Selection of R1 value can be set by voltage divider. Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic ca- Mode Selection pacitors bypass the high frequency noise, and bulk ca- NX9548 can be operated in PFM mode, ultrasonic pacitors supply switching current to the MOSFETs. Usu- PFM mode, CCM mode and shutdown mode by apply- ally 1uF ceramic capacitor is chosen to decouple the ing different voltage on ENSW/MODE pin. high frequency noise.The bulk input capacitors are de- When VCC applied to ENSW/MODE pin, NX9548 cided by voltage rating and RMS current rating. The RMS is In PFM mode. The low side MOSFET emulates the current in the input capacitors can be calculated as: function of diode when discontinuous continuous mode IRMS = IOUT × D × 1- D D = TON × FS happens, often in light load condition. During that time, ...(14) When VIN = 22V, VOUT=1.5V, IOUT=9A, the result of the inductor current crosses the zero ampere border and becomes negative current. When the inductor current reaches negative territory, the low side MOSFET is input RMS current is 2.3A. For higher efficiency, low ESR capacitors are recommended. One 10uF/X5R/25V and two 4.7uF/X5R /25V ceramic capacitors are chosen as input capaci- turned off and it takes longer time for the output voltage to drop, the high side MOSFET waits longer to be turned on. At the same time, no matter light load and heavy load, the on time of high side MOSFET keeps the same. tors. Therefore the lightier load, the lower the switching fre- Output Voltage Calculation quency will be. In ultrosonic PFM mode, the lowest fre- Output voltage is set by reference voltage and ex- quency is set to be 25kHz to avoid audio frequency ternal voltage divider. The reference voltage is fixed at modulation. This kind of reduction of frequency keeps 0.75V. The divider consists of two ratioed resistors so the system running at light light with high efficiency. that the output voltage applied at the Fb pin is 0.75V when the output voltage is at the desired value. The following equation applies to figure 12, which shows the relationship between age divider. Rev.1.6 03/06/09 In CCM mode, inductor current zero-crossing sensing is disabled, low side MOSFET keeps on even when inductor current becomes negative. In this way the effi- VOUT , VREF and volt- ciency is lower compared with PFM mode at light load, but frequency will be kept constant. 13 NX9548 Over Current Protection reset VCC or EN is necessary. Over current protection for NX9548 is achieved by sensing current through the low side MOSFET. An typi- Under Output Voltage Protection cal internal current source of 24uA flows through an ex- Typically when the FB pin voltage is under 70% of ternal resistor connected from OCSET pin to SW node VREF, the high side and low side MOSFET will be turned sets the over current protection threshold. When syn- off. To resume the switching operation, VCC or ENSW chronous FET is on, the voltage at node SW is given as has to be reset. VSW =-IL × RDSON The voltage at pin OCSET is given as IOCP × ROCP +VSW When the voltage is below zero, the over current occurs as shown in figure below. vbus I OCP 24uA OCP SW R OCP OCP comparator Figure 13 - Over Voltage Protection The over current limit can be set by the following equation. ISET = IOCP × ROCP /RDSON The low side MOSFET RDSON is 24mΩ at the OCP occuring moment, and the current limit is set at 10A, then ROCP = ISET × RDSON 10A × 24mΩ = = 10k Ω IOCP 24uA Choose ROCP=10kΩ Power Good Output Power good output is open drain output, a pull up resistor is needed. Typically when softstart is finised and FB pin voltage is over 90% of VREF, the PGOOD pin is pulled to high after a 1.6ms delay. Over Output Voltage Protection Typically when the FB pin voltage is over 125% of VREF, the high side MOSFET will be turned off and the low side MOSFET will be latched to be on to discharge the output voltage. To resume the switching operation, Rev.1.6 03/06/09 14 NX9548 Demoboard Schematic R18 R16 7.5k 7.5k C19 R3 330p VBUS 1M 5V 1n 24 17 21 23 26 22 C10 HG TON NC GND1 29 VOUT EN FB PGOOD PGOOD R17 27 100k PVCC 18 20 R8 4.7 28 G 15 HDRV BST R5 10 U1 GND2 VCC 25 C2 1u 19 R7 16 NX9548 MLPQ32 D2-5 S2-6 OCP 6k S2-5 13 12 11 10 9 D2(PAD3) D2-4 14 D2 8 7 6 5 2 1 D2-3 S2-1 D2-2 D1-3 D2-1 S2-2 D1-4 D1-2 4 32 S2-3 S1-1 VIN D1-1 S1-3 31 S2-4 S1-2 30 D1(PAD2) 3 D1 VBUS C17 1u GND(PAD1) C11 0.1u VSW 5V 5V VSW 2 L2 1 DO5010H-332HC R13 10 CIN1 CIN2 CIN3 10u/25V 4.7u/25V 4.7u/25V VOUT VOUT CO1 2R5TPE330MC CO2 4.7u GND C24 470p Figure 14 - NX9548 schematic for the demoboard layout Rev.1.6 03/06/09 15 NX9548 Demoboard Layout Figure 15 Top layer Figure 16 Ground layer Rev.1.6 03/06/09 16 NX9548 Figure 17 Power layer Figure 18 Bottom layer Rev.1.6 03/06/09 17 NX9548 MCM 32 PIN 5 x 5 PACKAGE OUTLINE DIMENSIONS NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS. Rev.1.6 03/06/09 18