MCP4821/MCP4822 12-Bit DACs with Internal VREF and SPI™ Interface Features Description • • • • • • • The Microchip Technology Inc. MCP482X devices are 2.7V–5.5V, low-power, low DNL, 12-bit Digital-to-Analog Converters (DACs) with internal band gap voltage reference, optional 2x-buffered output and Serial Peripheral Interface (SPI™). The MCP482X family of DACs provide high accuracy and low noise performance for industrial applications where calibration or compensation of signals (such as temperature, pressure and humidity) are required. The MCP482X devices are available in the extended temperature range and PDIP, SOIC and MSOP packages. The MCP482X devices utilize a resistive string architecture, with its inherent advantages of low DNL error, low ratio metric temperature coefficient and fast settling time. These devices are specified over the extended temperature range. The MCP482X family includes double-buffered registers, allowing simultaneous updates using the LDAC pin. These devices also incorporate a Power-On Reset (POR) circuit to ensure reliable power-up. • • • • • Set Point or Offset Trimming Sensor Calibration Precision Selectable Voltage Reference Portable Instrumentation (Battery-Powered) Calibration of Optical Communication Devices Package Types 8-Pin PDIP, SOIC, MSOP VDD 1 Block Diagram CS SDI SCK CS 2 LDAC SCK 3 Power-on Reset Interface Logic VDD AVSS Input Register A DACA Register Input Register B DACB Register SDI 4 CS 2 SCK 3 SDI 4 String DACA Gain Logic 8 VOUTA 7 AVSS 6 SHDN 5 LDAC 8-Pin PDIP, SOIC, MSOP VDD 1 2.048V VREF MCP4821 Applications MCP4822 • • • • • • 12-Bit Resolution ±0.2 LSb DNL (typ.) ±2 LSb INL (typ.) Single or Dual Channel Rail-to-Rail Output SPI™ Interface with 20 MHz Clock Support Simultaneous Latching of the Dual DACs with LDAC pin Fast Settling Time of 4.5 µs Selectable Unity or 2x Gain Output 2.048V Internal Band Gap Voltage Reference 50 ppm/°C VREF Temperature Coefficient 2.7V to 5.5V Single-Supply Operation Extended Temperature Range: -40°C to +125°C 8 VOUTA 7 AVSS 6 VOUTB 5 LDAC String DACB Gain Logic Output Op Amps Output Logic VOUTA SHDN © 2005 Microchip Technology Inc. VOUTB DS21953A-page 1 MCP4821/MCP4822 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD ............................................................................................................. 6.5V All inputs and outputs ...................AVSS – 0.3V to VDD + 0.3V Current at Input Pins ....................................................±2 mA Current at Supply Pins ...............................................±50 mA Current at Output Pins ...............................................±25 mA Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-55°C to +125°C ESD protection on all pins ........... ≥ 4 kV (HBM), ≥ 400V (MM) Maximum Junction Temperature (TJ) . .........................+150°C 5V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at +25°C. Parameters Sym Min Typ Max Units Input Voltage VDD 2.7 — 5.5 Input Current - MCP4821 Input Current - MCP4822 IDD — — 330 415 400 750 µA Conditions Power Requirements Hardware Shutdown Current ISHDN — 0.3 2 µA Software Shutdown Current ISHDN_SW — 3.3 6 µA Power-on-Reset Threshold VPOR — 2.0 — V Digital inputs grounded, Output unloaded, code = 0x000 DC Accuracy Resolution n 12 — — Bits INL Error INL -12 2 12 LSb DNL (Note 1) DNL -0.75 ±0.2 +0.75 LSb Offset Error VOS -1 ±0.02 1 % of FSR VOS/°C — 0.16 — ppm/°C -45°C to 25°C — -0.44 — ppm/°C +25°C to 85°C gE -2 -0.10 2 % of FSR ΔG/°C — -3 — ppm/°C VREF 2.008 2.048 2.088 V ΔVREF/°C — 125 325 ppm/°C -40°C to 0°C — 0.25 0.65 LSb/°C -40°C to 0°C Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Device is monotonic Code = 0x000h Code 0xFFFh, not including offset error Internal Voltage Reference (VREF) Nominal Reference Voltage Temperature Coefficient (Note 1) Output Noise (VREF Noise) Output Noise Density 1/f Corner Frequency Note 1: 2: VOUTA when G = 1x and Code = 0xFFFh — 45 160 ppm/°C 0°C to +85°C — 0.09 0.32 LSb/°C 0°C to +85°C ENREF (0.1-10 Hz) — 290 — µVp-p Code = 0xFFFh, G = 1 eNREF (1 kHz) — 1.2 — µV/√Hz Code = 0xFFFh, G = 1 eNREF (10 kHz) — 1.0 — µV/√Hz Code = 0xFFFh, G = 1 fCORNER — 400 — Hz By design, not production tested. Too small to quantify. DS21953A-page 2 © 2005 Microchip Technology Inc. MCP4821/MCP4822 5V AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at +25°C. Parameters Sym Min Typ Max Units Conditions Output Swing VOUT — 0.010 to VDD – 0.040 — Phase Margin PM — 66 — ° Slew Rate SR — 0.55 — V/µs ISC — 15 24 mA tSETTLING — 4.5 — µs DAC-to-DAC Crosstalk — <10 — nV-s Note 2 Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry (0111...1111 to 1000...0000) Output Amplifier Short Circuit Current Settling Time Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD – 40 mV) Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Dynamic Performance Digital Feedthrough — <10 — nV-s Note 2 Analog Crosstalk — <10 — nV-s Note 2 Note 1: 2: By design, not production tested. Too small to quantify. 3V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x, RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at 25°C Parameters Sym Min Typ Max Units Input Voltage VDD 2.7 — 5.5 Input Current - MCP4821 Input Current - MCP4822 IDD — — 300 415 400 750 µA Conditions Power Requirements Hardware Shutdown Current ISHDN — 0.25 2 µA Software Shutdown Current ISHDN_SW — 2 6 µA Power-On Reset threshold VPOR — 2.0 — V Digital inputs grounded, Output unloaded, code = 0x000 DC Accuracy Resolution n 12 — — Bits INL Error INL -12 ±3 12 LSb DNL (Note 1) DNL -0.75 ±0.3 0.75 LSb VOS -1 ±0.02 1 % of FSR VOS/°C — 0.5 — ppm/°C -45°C to +25°C — -0.77 — ppm/°C +25°C to +85°C gE -2 -0.15 2 % of FSR ΔG/°C — -3 — ppm/°C Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Note 1: 2: Device is monotonic Code 0x000h Code 0xFFFh, not including offset error By design, not production tested. Too small to quantify. © 2005 Microchip Technology Inc. DS21953A-page 3 MCP4821/MCP4822 3V AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x, RL = 5 kΩ to GND, CL = 100 pF, TA = -40 to +85°C. Typical values at 25°C Parameters Sym Min Typ Max Units Conditions VREF 2.008 2.048 2.088 V ΔVREF/°C — 125 325 ppm/°C -40°C to 0°C — 0.25 0.65 LSb/°C -40°C to 0°C Internal Voltage Reference (VREF) Nominal Reference Voltage Temperature Coefficient (Note 1) VOUTA when G = 1x and Code = 0xFFFh — 45 160 ppm/°C 0°C to +85°C — 0.09 0.32 LSb/°C 0°C to +85°C ENREF (0.1-10 Hz) — 290 — µVp-p Code = 0xFFFh, G = 1 eNREF (1 kHz) — 1.2 — µV/√Hz Code = 0xFFFh, G = 1 eNREF (10 kHz) — 1.0 — µV/√Hz Code = 0xFFFh, G = 1 fCORNER — 400 — Hz Output Swing VOUT — 0.010 to VDD – 0.040 — Phase Margin PM — 66 — ° Slew Rate SR — 0.55 — V/µs ISC — 14 24 mA tSETTLING — 4.5 — µs DAC-to-DAC Crosstalk — <10 — nV-s Note 2 Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry (0111...1111 to 1000...0000) Output Noise (VREF Noise) Output Noise Density 1/f Corner Frequency Output Amplifier Short Circuit Current Settling Time Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD – 40 mV) Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Dynamic Performance Digital Feedthrough — <10 — nV-s Note 2 Analog Crosstalk — <10 — nV-s Note 2 Note 1: 2: By design, not production tested. Too small to quantify. 5V EXTENDED TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF. Typical values at +125°C by characterization or simulation. Parameters Sym Min Typ Max Input Voltage VDD Input Current - MCP4821 Input Current - MCP4822 IDD 2.7 — 5.5 — — 350 440 — Units Conditions Power Requirements µA Hardware Shutdown Current ISHDN — 1.5 — µA Software Shutdown Current ISHDN_SW — 5 — µA Power-On Reset threshold VPOR — 1.85 — V n 12 — — Bits INL — ±4 — LSb Digital inputs grounded, Output unloaded, code = 0x000 DC Accuracy Resolution INL Error Note 1: 2: By design, not production tested. Too small to quantify. DS21953A-page 4 © 2005 Microchip Technology Inc. MCP4821/MCP4822 5V EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF. Typical values at +125°C by characterization or simulation. Parameters Sym Min Typ DNL (Note 1) DNL — ±0.25 — LSb Offset Error VOS — ±0.02 — % of FSR VOS/°C — -5 — ppm/°C gE — -0.10 — % of FSR ΔG/°C — -3 — ppm/°C VREF — 2.048 — V ΔVREF/°C — 125 — ppm/°C — 0.25 — LSb/°C -40°C to 0°C — 45 — ppm/°C 0°C to +85°C Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Max Units Conditions Device is monotonic Code 0x000h +25°C to +125°C Code 0xFFFh, not including offset error Internal Voltage Reference (VREF) Nominal Reference Voltage Temperature Coefficient (Note 1) VOUTA when G = 1x and Code = 0xFFFh -40°C to 0°C — 0.09 — LSb/°C ENREF (0.1 - 10 Hz) — 290 — µVp-p Code = 0xFFFh, G = 1 eNREF (1 kHz) — 1.2 — µV/√Hz Code = 0xFFFh, G = 1 eNREF (10 kHz) — 1.0 — µV/√Hz Code = 0xFFFh, G = 1 fCORNER — 400 — Hz Output Swing VOUT — 0.010 to VDD – 0.040 — Phase Margin PM — 66 — ° Slew Rate SR — 0.55 — V/µs Short Circuit Current ISC — 17 — mA tSETTLING — 4.5 — µs DAC-to-DAC Crosstalk — <10 — nV-s Note 2 Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry (0111...1111 to 1000...0000) Output Noise (VREF Noise) Output Noise Density 1/f Corner Frequency 0°C to +85°C Output Amplifier Settling Time Accuracy is better than 1 LSb for VOUT = 10 mV to (VDD – 40 mV) Within 1/2 LSb of final value from 1/4 to 3/4 full-scale range Dynamic Performance Digital Feedthrough — <10 — nV-s Note 2 Analog Crosstalk — <10 — nV-s Note 2 Note 1: 2: By design, not production tested. Too small to quantify. © 2005 Microchip Technology Inc. DS21953A-page 5 MCP4821/MCP4822 AC CHARACTERISTICS (SPI™ TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C. Typical values are at +25°C. Parameters Sym Min Typ Max Units Schmitt Trigger High-Level Input Voltage (All digital input pins) VIH 0.7 VDD — — V Schmitt Trigger Low-Level Input Voltage (All digital input pins) VIL — — 0.2 VDD V VHYS — 0.05 VDD — Input Leakage Current ILEAKAGE -1 — 1 μA SHDN = LDAC = CS = SDI = SCK + VREF = VDD or AVSS Digital Pin Capacitance (All inputs/outputs) CIN, COUT — 10 — pF VDD = 5.0V, TA = +25°C, fCLK = 1 MHz (Note 1) Clock Frequency FCLK — — 20 MHz Clock High Time tHI 15 — — ns Note 1 Clock Low Time tLO 15 — — ns Note 1 tCSSR 40 — — ns Applies only when CS falls with CLK high. (Note 1) Data Input Setup Time tSU 15 — — ns Note 1 Data Input Hold Time tHD 10 — — ns Note 1 SCK Rise to CS Rise Hold Time tCHS 15 — — ns Note 1 CS High Time tCSH 15 — — ns Note 1 LDAC Pulse Width tLD 100 — — ns Note 1 LDAC Setup Time tLS 40 — — ns Note 1 tIDLE 40 — — ns Note 1 Hysteresis of Schmitt Trigger Inputs CS Fall to First Rising CLK Edge SCK Idle Time before CS Fall Note 1: Conditions TA = +25°C (Note 1) By design and characterization, not production tested. tCSH CS tIDLE tCSSR Mode 1,1 tHI tLO tCHS SCK Mode 0,0 tSU tHD SI MSb in LSb in LDAC tLS FIGURE 1-1: DS21953A-page 6 tLD SPI™ Input Timing. © 2005 Microchip Technology Inc. MCP4821/MCP4822 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, AVSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 8L-PDIP θJA — 85 — °C/W Thermal Resistance, 8L-SOIC θJA — 163 — °C/W Thermal Resistance, 8L-MSOP θJA — 206 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Note 1: The MCP482X family of DACs operate over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150°C. © 2005 Microchip Technology Inc. DS21953A-page 7 MCP4821/MCP4822 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 0.3 0.1 INL (LSB) DNL (LSB) 0.2 0 -0.1 -0.2 -0.3 0 1024 2048 3072 5 4 3 2 1 0 -1 -2 -3 -4 -5 Ambient Temperature 125C 4096 0 1024 Code (Decimal) FIGURE 2-1: DNL vs. Code. FIGURE 2-4: Temperature. Absolute INL (LSB) 0.1 DNL (LSB) 2048 3072 Code (Decimal) 25 4096 INL vs. Code and Ambient 2.5 0.2 0 -0.1 2 1.5 1 0.5 0 -0.2 0 1024 2048 3072 Code (Decimal) FIGURE 2-2: Temperature. 125C -40 4096 85C -20 DNL vs. Code and Ambient 0 20 40 60 80 100 120 Ambient Temperature (ºC) 25C FIGURE 2-5: Temperature. Absolute INL vs. Ambient 2 0.0766 0.0764 0 0.0762 INL (LSB) Absolute DNL (LSB) 85 0.076 0.0758 0.0756 -2 -4 0.0754 0.0752 -6 0.075 -40 -20 0 20 40 60 80 0 100 120 1024 DS21953A-page 8 Absolute DNL vs. Ambient 3072 4096 Code (Decimal) Ambient Temperature (ºC) FIGURE 2-3: Temperature. 2048 FIGURE 2-6: Note: INL vs. Code. Single device graph for illustration of 64 code effect. © 2005 Microchip Technology Inc. MCP4821/MCP4822 2.050 2.049 2.048 2.047 2.046 2.045 2.044 2.043 2.042 2.041 2.040 100 1.E-04 Output Noise Voltage Density (μV/Hz) Full Scale VOUT (V) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 10 1.E-05 VDD: 4V VDD: 3V VDD: 2.7V -40 -20 0 20 40 60 80 1 1.E-06 0.1 1.E-07 0.1 1E-1 100 120 1 1E+0 10 1E+1 FIGURE 2-7: Full-Scale VOUTA w/G = 1 (VREF) vs. Ambient Temperature and VDD. 4.100 1k 1E+3 10k 1E+4 100k 1E+5 FIGURE 2-9: Output Noise Voltage Density (VREF Noise Density w/G = 1) vs. Frequency. 1.E-02 10.0 4.096 4.092 Output Noise Voltage (mV) Full Scale VOUT (V) 100 1E+2 Frequency (Hz) Ambient Temperature (°C) 1.E-03 1.00 4.088 VDD: 5.5V VDD: 5V 4.084 Eni (in VP-P) 0.10 1.E-04 4.080 4.076 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (°C) FIGURE 2-8: Full-Scale VOUTA w/G = 2 (2VREF) vs.Ambient Temperature and VDD. © 2005 Microchip Technology Inc. Eni (in VRMS) 0.01 1.E-05 100 1E+2 Maximum Measurement Time = 10s 1k 1E+3 10k 100k 1E+4 1E+5 Bandwidth (Hz) 1M 1E+6 FIGURE 2-10: Output Noise Voltage (VREF Noise Voltage w/G = 1) vs. Bandwidth. DS21953A-page 9 MCP4821/MCP4822 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 5.5V 5.0V 4.0V 3.0V 2.7V VDD 320 IDD (μA) 300 280 260 240 600 5.5V 5.0V 4.0V 3.0V 2.7V VDD 550 500 IDD (μA) 340 450 400 220 350 200 180 300 -40 -20 0 20 40 60 80 100 120 -40 -20 FIGURE 2-11: MCP4821 IDD vs. Ambient Temperature and VDD. 20 40 80 100 120 FIGURE 2-14: MCP4822 IDD vs. Ambient Temperature and VDD. Occurrence 20 15 10 FIGURE 2-13: (VDD = 5.0V). DS21953A-page 10 MCP4821 IDD Histogram 440 430 425 420 435 435 430 425 420 350 >350 345 340 335 330 325 320 315 310 305 300 295 290 285 0 415 2 410 4 405 6 400 8 385 Occurrence 10 395 14 22 20 18 16 14 12 10 8 6 4 2 0 390 16 12 MCP4822 IDD Histogram FIGURE 2-15: (VDD = 2.7V). 18 IDD (μA) 415 IDD (μA) MCP4821 IDD Histogram FIGURE 2-12: (VDD = 2.7V). 410 405 400 395 390 380 385 0 >320 320 315 310 305 300 295 290 285 280 275 270 5 IDD (μA) Occurrence 60 25 20 18 16 14 12 10 8 6 4 2 0 265 Occurrence 0 Ambient Temperature (ºC) Ambient Temperature (°C) IDD (μA) FIGURE 2-16: (VDD = 5.0V). MCP4822 IDD Histogram © 2005 Microchip Technology Inc. MCP4821/MCP4822 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 0.7 ISHDN (μA) 0.5 0.4 0.3 0.2 -0.05 -0.1 VDD -0.15 Gain Error (%) 5.5V 5.0V 4.0V 3.0V 2.7V VDD 0.6 5.5V 5.0V 4.0V 3.0V 2.7V -0.2 -0.25 -0.3 -0.35 -0.4 0.1 -0.45 -0.5 0 -40 -20 0 20 40 60 80 100 -40 120 -20 Ambient Temperature (ºC) FIGURE 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD. 4 40 60 80 100 120 3 4.0V 2.5 3.0V 2.7V 2 VDD 1.5 VDD 4 5.0V VIN Hi Threshold (V) ISHDN_SW (μA) 20 FIGURE 2-20: Gain Error vs. Ambient Temperature and VDD. 5.5V 3.5 1 5.5V 3.5 5.0V 3 4.0V 2.5 2 3.0V 2.7V 1.5 1 -40 -20 0 20 40 60 80 100 120 -40 -20 Ambient Temperature (ºC) 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-18: Software Shutdown Current vs. Ambient Temperature and VDD. FIGURE 2-21: VIN High Threshold vs. Ambient Temperature and VDD. 1.6 0.09 0.07 0.05 5.5V 0.03 VDD 0.01 5.0V 4.0V 3.0V 2.7V -0.01 -0.03 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-19: Offset Error vs. Ambient Temperature and VDD. © 2005 Microchip Technology Inc. VIN Low Threshold (V) 0.11 Offset Error (%) 0 Ambient Temperature (ºC) VDD 1.5 5.5V 1.4 5.0V 1.3 1.2 4.0V 1.1 1 3.0V 2.7V 0.9 0.8 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-22: VIN Low Threshold vs. Ambient Temperature and VDD. DS21953A-page 11 MCP4821/MCP4822 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 16 2.5 5.5V 2 5.0V 1.75 1.5 4.0V 1.25 1 3.0V 2.7V 0.75 0.5 15 IOUT_HI_SHORTED (mA) VIN_SPI Hysteresis (V) 5.5V 5.0V 4.0V 3.0V 2.7V VDD 2.25 14 VDD 13 12 11 0.25 10 0 -40 -20 0 20 40 60 80 -40 100 120 -20 Ambient Temperature (ºC) FIGURE 2-23: Input Hysteresis vs. Ambient Temperature and VDD. 40 60 80 100 120 6.0 4.0V 0.033 5.0 0.031 VREF = 4.096V 0.029 0.027 0.025 3.0V 0.023 2.7V VDD 0.021 VOUT (V) VOUT_HI Limit (VDD-Y)(V) 20 FIGURE 2-26: IOUT High Short vs. Ambient Temperature and VDD. 0.035 4.0 Output Shorted to VDD 3.0 2.0 1.0 0.019 0.017 Output Shorted to VSS 0.0 0.015 -40 -20 0 20 40 60 80 0 100 120 2 Ambient Temperature (ºC) FIGURE 2-24: VOUT High Limit vs. Ambient Temperature and VDD. 0.0028 VOUT_LOW Limit (Y-AVSS)(V) 0 Ambient Temperature (ºC) FIGURE 2-27: 4 6 8 10 IOUT (mA) 12 14 16 IOUT vs. VOUT. Gain = 2. VDD 0.0026 0.0024 5.5V 0.0022 5.0V 0.0020 4.0V 3.0V 2.7V 0.0018 0.0016 0.0014 0.0012 0.0010 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-25: VOUT Low Limit vs. Ambient Temperature and VDD. DS21953A-page 12 © 2005 Microchip Technology Inc. MCP4821/MCP4822 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. VOUT VOUT SCK LDAC LDAC Time (1 µs/div) FIGURE 2-28: VOUT Rise Time 100%. Time (1 µs/div) FIGURE 2-31: VOUT Rise Time 25% - 75%. VOUT VOUT SCK SCK LDAC LDAC Time (1 µs/div) VOUT Fall Time. FIGURE 2-32: Shutdown. VOUT SCK LDAC Time (1 µs/div) FIGURE 2-30: VOUT Rise Time Exit Ripple Rejection (dB) FIGURE 2-29: Time (1 µs/div) VOUT Rise Time 50%. © 2005 Microchip Technology Inc. Frequency (Hz) FIGURE 2-33: PSRR vs. Frequency. DS21953A-page 13 MCP4821/MCP4822 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP4821 Pin No. MCP4822 Pin No. Symbol 1 1 VDD Positive Power Supply Input (2.7V to 5.5V) 2 2 CS Chip Select Input 3 3 SCK Serial Clock Input 4 4 SDI Serial Data Input 5 5 LDAC Synchronization input used to transfer DAC settings from serial latches to output latches 6 — SHDN Hardware Shutdown Input — 6 VOUTB DACB Output 7 7 AVSS Analog Ground 8 8 VOUTA DACA Output 3.1 Function Positive Power Supply Input (VDD) VDD is the positive power supply input. The input power supply is relative to AVSS and can range from 2.7V to 5.5V. A decoupling capacitor on VDD is recommended to achieve maximum performance. 3.6 SHDN is the hardware shutdown input that requires an active-low input signal to configure the DACs in their low-power Standby mode. 3.7 3.2 Chip Select (CS) CS is the chip select input, which requires an active-low signal to enable serial clock and data functions. Serial Clock Input (SCK) DACx Outputs (VOUTA, VOUTB) VOUTA and VOUTB are DAC outputs. The DAC output amplifier drives these pins with a range of AVSS to VDD. 3.8 3.3 Hardware Shutdown Input (SHDN) Analog Ground (AVSS) AVSS is the analog ground pin. SCK is the SPI compatible serial clock input. 3.4 Serial Data Input (SDI) SDI is the SPI compatible serial data input. 3.5 Latch DAC Input (LDAC) LDAC (the latch DAC synchronization input) transfers the input latch registers to the DAC registers (output latches) when low. Can also be tied low if transfer on the rising edge of CS is desired. DS21953A-page 14 © 2005 Microchip Technology Inc. MCP4821/MCP4822 4.0 GENERAL OVERVIEW INL < 0 The MCP482X devices are voltage-output string DACs. These devices include rail-to-rail output amplifiers, internal voltage reference, shutdown and reset-management circuitry. Serial communication conforms to the SPI protocol. The MCP482X devices operate from 2.7V to 5.5V supplies. The coding of these devices is straight binary, with the ideal output voltage given by Equation 4-1, where G is the selected gain (1x or 2x), DN represents the digital input value and n represents the number of bits of resolution (n = 12). EQUATION 4-1: 111 110 Actual Transfer Function 101 Digital Input Code 100 011 Ideal Transfer Function 010 001 LSb SIZE 2.048V ⋅ G ⋅ D N VOUT = ------------------------------------n 2 000 INL < 0 DAC Output 1 LSb is the ideal voltage difference between two successive codes. Table 4-1 illustrates how to calculate LSb. TABLE 4-1: LSb SIZES Device Gain LSb Size MCP482X MCP482X 1x 2x 2.048V/4096 4.096V/4096 4.0.1 FIGURE 4-1: 4.0.2 Positive INL represents transition(s) later than ideal. Negative INL represents transition(s) earlier than ideal. DNL ACCURACY DNL error is the measure of variations in code widths from the ideal code width. A DNL error of zero would imply that every code is exactly 1 LSb wide. INL ACCURACY INL error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point once offset and gain errors have been removed. These endpoints are from 0x000 to 0xFFF. Refer to Figure 4-1. INL Accuracy. 111 110 Actual Transfer Function 101 Digital Input Code 100 Ideal Transfer Function 011 010 001 Wide Code > 1 LSb 000 Narrow Code < 1 LSb DAC Output FIGURE 4-2: 4.0.3 DNL Accuracy. OFFSET ERROR Offset error is the deviation from zero voltage output when the digital input code is zero. 4.0.4 GAIN ERROR Gain error is the deviation from the ideal output, VREF – 1 LSb, excluding the effects of offset error. © 2005 Microchip Technology Inc. DS21953A-page 15 MCP4821/MCP4822 4.1.1 Circuit Descriptions OUTPUT AMPLIFIERS 5V Supply Voltages 4.1 The DACs’ outputs are buffered with a low-power, precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section 1.0 “Electrical Characteristics” for range and load conditions. In addition to resistive load-driving capability, the amplifier will also drive high capacitive loads without oscillation. The amplifiers’ strong outputs allow VOUT to be used as a programmable voltage reference in a system. The rail-to-rail output amplifier has configurable gain, allowing optimal full-scale outputs for differing voltage reference inputs. The output amplifier gain has two selections, a gain of 1 V/V (GA = 1) or a gain of 2 V/V (GA = 0). 4.1.2 VOLTAGE REFERENCE The MCP482X devices utilize internal 2.048V voltage reference. The voltage reference has low temperature coefficient and low noise characteristics. Refer to Section 1.0 “Electrical Characteristics” for the voltage reference specifications. 4.1.3 POWER-ON RESET CIRCUIT The Power-On Reset (POR) circuit ensures that the DACs power-up with SHDN = 0 (high-impedance). The devices will continue to have a high-impedance output until a valid Write command is performed to either of the DAC registers and the LDAC pin meets the input low threshold. Transient Duration 10 Programmable Gain Block The output range is ideally 0.000V to 4095/4096 * 2.048V when G = 1, and 0.000 to 4095/4096 * 4.096V when G = 2. The default value for this bit is a gain of 2, yielding an ideal full-scale output of 0.000V to 4.096V due to the internal 2.048V VREF. Note that the near railto-rail CMOS output buffer’s ability to approach AVSS and VDD establish practical range limitations. The output swing specification in Section 1.0 “Electrical Characteristics” defines the range for a given load condition. VDD - VPOR Time Transient Duration (µs) 4.1.1.1 VPOR 8 6 4 Transients above the curve will cause a reset 2 0 FIGURE 4-3: 4.1.4 TA = +25°C Transients below the curve will NOT cause a reset 1 2 3 4 VDD – VPOR (V) 5 Typical Transient Response. SHUTDOWN MODE Shutdown mode can be entered by using either hardware or software commands. The hardware pin (SHDN) is only available on the MCP4821. During Shutdown mode, the supply current is isolated from most of the internal circuitry. The serial interface remains active, thus allowing a Write command to bring the device out of Shutdown mode. When the output amplifiers are shut down, the feedback resistance (typically 500 kΩ) produces a high-impedance path to AVSS. The device will remain in Shutdown mode until the SHDN pin is brought high and a write command with SD = 1 is latched into the device. When a DAC is changed from Shutdown to Active mode, the output settling time takes < 10 µs, but greater than the standard Active mode settling time (4.5 µs). If the power supply voltage is less than the POR threshold (VPOR = 2.0V, typical), the DACs will be held in their reset state. They will remain in that state until VDD > VPOR and a subsequent Write command is received. Figure 4-3 shows a typical power supply transient pulse and the duration required to cause a reset to occur, as well as the relationship between the duration and trip voltage. A 0.1 µF decoupling capacitor, mounted as close as possible to the VDD pin, provides additional transient immunity. DS21953A-page 16 © 2005 Microchip Technology Inc. MCP4821/MCP4822 5.0 SERIAL INTERFACE 5.1 Overview 5.2 The write command is initiated by driving the CS pin low, followed by clocking the four configuration bits and the 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to be latched into the selected DAC’s input registers. The MCP482X devices utilize a double-buffered latch structure to allow both DACA’s and DACB’s outputs to be synchronized with the LDAC pin, if desired. Upon the LDAC pin achieving a low state, the values held in the DAC’s input registers are transferred into the DACs’ output registers. The outputs will transition to the value and held in the DACX register. The MCP482X family is designed to interface directly with the SPI port, available on many microcontrollers, and supports Mode 0,0 and Mode 1,1. Commands and data are sent to the device via the SDI pin, with data being clocked-in on the rising edge of SCK. The communications are unidirectional and, thus, data cannot be read out of the MCP482X devices. The CS pin must be held low for the duration of a write command. The write command consists of 16 bits and is used to configure the DAC’s control and data latches. Register 5-1 details the input registers used to configure and load the DACA and DACB registers. Refer to Figure 1-1 and the AC Electrical Characteristics tables for detailed input and output timing specifications for both Mode 0,0 and Mode 1,1 operation. REGISTER 5-1: Write Command All writes to the MCP482X devices are 16-bit words. Any clocks past 16 will be ignored. The most significant four bits are configuration bits. The remaining 12 bits are data bits. No data can be transferred into the device with CS high. This transfer will only occur if 16 clocks have been transferred into the device. If the rising edge of CS occurs prior, shifting of data into the input registers will be aborted. WRITE COMMAND REGISTER Upper Half: W-x W-x W-x W-0 W-x W-x W-x W-x A/B — GA SHDN D11 D10 D9 D8 bit 15 bit 8 Lower Half: W-x D7 bit 7 bit 15 W-x D6 W-x D5 W-x D4 W-x D3 W-x D2 W-x D1 W-x D0 bit 0 A/B: DACA or DACB Select bit Write to DACB Write to DACA 1= 0= bit 14 bit 13 — Don’t Care GA: Output Gain Select bit 1x (VOUT = VREF * D/4096) 2x (VOUT = 2 * VREF * D/4096) 1= 0= bit 12 SHDN: Output Power-down Control bit 1 = Output Power-down Control bit 0 = Output buffer disabled, Output is high-impedance bit 11-0 D11:D0: DAC Data bits 12-bit number “D” which sets the output value. Contains a value between 0 and 4095. Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared © 2005 Microchip Technology Inc. x = bit is unknown DS21953A-page 17 MCP4821/MCP4822 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK (Mode 0,0) config bits SDI (Mode 1,1) A/B 12 data bits — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LDAC VOUT FIGURE 5-1: DS21953A-page 18 Write Command. © 2005 Microchip Technology Inc. MCP4821/MCP4822 6.0 TYPICAL APPLICATIONS 6.3 Output Noise Considerations The MCP482X devices are general purpose DACs intended to be used in applications where a precision, low-power DAC with moderate bandwidth and internal voltage reference is required. The voltage noise density (in µV/√Hz) is illustrated in Figure 2-9. This noise appears at VOUTX, and is primarily a result of the internal reference voltage. Its 1/f corner (fCORNER) is approximately 400 Hz. Applications generally suited for the MCP482X devices include: Figure 2-10 illustrates the voltage noise (in mVRMS or mVP-P). A small bypass capacitor on VOUTX is an effective method to produce a single-pole Low-Pass Filter (LPF) that will reduce this noise. For instance, a bypass capacitor sized to produce a 1 kHz LPF would result in an ENREF of about 100 µVRMS. This would be necessary when trying to achieve the low DNL performance (at G = 1) that the MCP482X devices are capable of. The tested range for stability is .001µF thru 4.7 µF. Digital Interface The MCP482X devices utilize a 3-wire synchronous serial protocol to transfer the DACs’ setup and output values from the digital source. The serial protocol can be interfaced to SPI™ or Microwire peripherals common on many microcontroller units (MCUs), including Microchip’s PICmicro® MCUs and dsPIC® DSC family of MCUs. In addition to the three serial connections (CS, SCK and SDI), the LDAC signal synchronizes when the serial settings are latched into the DAC’s output from the serial input latch. Figure 6-1 illustrates the required connections. Note that LDAC is active-low. If desired, this input can be tied low to reduce the required connections from 4 to 3. Write commands will be latched directly into the output latch when a valid 16 clock transmission has been received and CS has been raised. 6.2 Power Supply Considerations The typical application will require a bypass capacitor in order to filter high-frequency noise. The noise can be induced onto the power supply's traces or as a result of changes on the DAC's output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 6-1 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close to the device power pin (VDD) as possible (within 4 mm). The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, AVDD and AVSS should reside on the analog plane. VDD VDD 0.1 µF 0.1 µF VDD VOUTA 0.1 µF 1 µF VOUTB VOUTA 1 µF VOUTB SDI CS1 SDI AVSS SDO SCK LDAC CS0 AVSS FIGURE 6-1: Diagram. 6.4 PICmicro® Microcontroller 6.1 MCP482X Set Point or Offset Trimming Sensor Calibration Precision Selectable Voltage Reference Portable Instrumentation (Battery-Powered) Calibration of Optical Communication Devices MCP482X • • • • • AVSS Typical Connection Layout Considerations Inductively-coupled AC transients and digital switching noise can degrade the output signal integrity, potentially masking the MCP482X family’s performance. Careful board layout will minimize these effects and increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the MCP482X devices are capable of providing. Particularly harsh environments may require shielding of critical signals. Breadboards and wire-wrapped boards are not recommended if low noise is desired. © 2005 Microchip Technology Inc. DS21953A-page 19 MCP4821/MCP4822 6.5 6.5.1.1 Single-Supply Operation If the application is calibrating the threshold of a diode, transistor or resistor tied to AVSS, a threshold range of 0.8V may be desired to provide 200 µV resolution. Two common methods to achieve a 0.8V range is to either reduce VREF to 0.82V (would require MCP492X device and external voltage reference) or use a voltage divider on the DAC’s output. Typically, when using a lowvoltage VREF, the noise floor causes SNR error that is intolerable. The voltage divider method provides some advantages when VREF needs to be very low or when the desired output voltage is not available. Using two resistors to scale the output range down to the precise desired level is a simple, low-cost method to achieve very small step sizes. Example 6-1 illustrates this concept. Note that the bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. The MCP482X devices are Rail-to-Rail (R-R) input and output DACs designed to operate with a VDD range of 2.7V to 5.5V. Its output amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of an external buffer for most applications. 6.5.1 Decreasing The Output Step Size DC SET POINT OR CALIBRATION A common application for a DAC with the MCP482X family’s performance is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. 12-bit resolution provides 4096 output steps. If G = 1 is selected, then the internal 2.048 VREF would produce 500 µV of resolution. If G = 2 is selected, the internal 2.048 VREF would produce 1 mV of resolution. The MCP482X family’s low ±0.75 (max.) DNL performance is critical to meeting calibration accuracy in production. VDD VCC+ RSENSE VDD MCP482X VOUT Comparator R1 VTRIP R2 0.1 uF VCC– SPI™ 3 D V OUT = 2.048 ⋅ G --------12 2 ⎛ R2 ⎞ V trip = VOUT ⎜ --------------------⎟ ⎝ R 1 + R 2⎠ EXAMPLE 6-1: DS21953A-page 20 G = Gain select (1x or 2x) D = Digital value of DAC (0 – 4096) Set Point or Threshold Calibration. © 2005 Microchip Technology Inc. MCP4821/MCP4822 6.5.1.2 Building a “Window” DAC creating a “window” around the threshold has several advantages. One simple method to create this “window” is to use a voltage divider network with a pullup and pull-down resistor. Example 6-2 and Example 6-4 illustrates this concept. When calibrating a set point or threshold of a sensor, rarely does the sensor utilize the entire output range of the DAC. If the LSb size is adequate to meet the application’s accuracy needs, the resolution is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. If the threshold is not near VREF, 2VREF or AVSS, then VCC+ The MCP482X family’s low ±0.75 (max.) DNL performance is critical to meet calibration accuracy in production. VCC+ RSENSE VDD MCP482X VOUT R3 R1 VTRIP R2 0.1 µF Comparator VCC- SPI™ 3 VCCD V OUT = 2.048 ⋅ G ------12 2 Thevenin Equivalent R2R3 R 23 = -----------------R2 + R 3 V 23 R1 VOUT VO ( V CC+ R 2 ) + ( VCC- R 3 ) = -----------------------------------------------------R 2 + R3 V OUT R23 + V 23 R 1 V trip = -------------------------------------------R 2 + R 23 EXAMPLE 6-2: G = Gain select (1x or 2x) D = Digital value of DAC (0 – 4096) R23 V23 Single-Supply “Window” DAC. © 2005 Microchip Technology Inc. DS21953A-page 21 MCP4821/MCP4822 6.6 Bipolar Operation Example 6-3 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VDD, instead of AVSS, if a higher offset is desired. Note that a pull-up to VDD could be used, instead of R4 or in addition to R4, if a higher offset is desired. Bipolar operation is achievable using the MCP482X devices by using an external operational amplifier (op amp). This configuration is desirable due to the wide variety and availability of op amps. This allows a general purpose DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. R2 VDD VDD VCC+ R1 VOUT R3 VO VIN+ MCP482X VCC– 0.1 µF R4 SPI™ 3 D V OUT = 2.048 ⋅ G ------12 2 V OUT R4 VIN+ = -------------------R3 + R 4 R2 R2 VO = V IN+ ⎛ 1 + ------⎞ – V DD ⎛ ------⎞ ⎝ R 1⎠ ⎝ R 1⎠ EXAMPLE 6-3: 6.6.1 Digitally-Controlled Bipolar Voltage Source. DESIGN A BIPOLAR DAC USING EXAMPLE 6-3 An output step magnitude of 1 mV, with an output range of ±2.05V, is desired for a particular application. 1. 2. G = Gain select (1x or 2x) D = Digital value of DAC (0 – 4096) Calculate the range: +2.05V – (-2.05V) = 4.1V. Calculate the resolution needed: 4.1V/1 mV = 4100 4. Next, solve for R3 and R4 by setting the DAC to 4096, knowing that the output needs to be +2.05V. R4 2.05V + ( 0.5 ⋅ 4.096V ) 2 ---------------------- = ------------------------------------------------------- = --( R 3 + R4 ) 1.5 ⋅ 4.096V 3 If R4 = 20 kΩ, then R3 = 10 kΩ Since 212 = 4096, 12-bit resolution is desired. 3. The amplifier gain (R2/R1), multiplied by fullscale VOUT (4.096V), must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R1+R2), the VREF value must be selected first. If a VREF of 4.096V is used (G=2), solve for the amplifier’s gain by setting the DAC to 0, knowing that the output needs to be -2.05V. The equation can be simplified to: –R2 – 2.05 --------- = ----------------R1 4.096V R 1 -----2- = --2 R1 If R1 = 20 kΩ and R2 = 10 kΩ, the gain will be 0.5 DS21953A-page 22 © 2005 Microchip Technology Inc. MCP4821/MCP4822 6.7 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC In some applications, precision digital control of the output range is desirable. Example 6-4 illustrates how to use the MCP482X family to achieve this in a bipolar or single-supply application. This circuit is typically used for linearizing a sensor whose slope and offset varies. The equation to design a bipolar “window” DAC would be utilized if R3, R4 and R5 are populated. R2 VDD VOUTA VCC+ R1 MCP482X VDD DACA (Gain Adjust) VOUTB VCC+ VO R5 R3 MCP482X DACB (Offset Adjust) SPI™ R4 3 0.1 µF VCC– VCC– DB V OUTB = ( 2.048V ⋅ G B ) ------12 2 DA V OUTA = ( 2.048V ⋅ G A ) ------12 2 AVSS = GND VOUTB R 4 + VCC- R3 VIN+ = -----------------------------------------------R3 + R 4 G = Gain select (1x or 2x) R2 R2 V O = V IN+ ⎛ 1 + ------⎞ – VOUTA ⎛ ------⎞ ⎝ R 1⎠ ⎝ R 1⎠ D = Digital value of DAC (0 – 4096) Offset Adjust Gain Adjust Bipolar “Window” DAC using R4 and R5 Thevenin Equivalent V CC+ R 4 + VCC- R5 V45 = -------------------------------------------R 4 + R5 V OUTB R45 + V 45 R 3 V IN+ = ----------------------------------------------R 3 + R 45 R4 R5 R 45 = -----------------R4 + R5 R2 R2 V O = VIN+ ⎛⎝ 1 + ------⎞⎠ – V OUTA ⎛⎝ ------⎞⎠ R1 R1 Offset Adjust Gain Adjust EXAMPLE 6-4: Bipolar Voltage Source with Selectable Gain and Offset. © 2005 Microchip Technology Inc. DS21953A-page 23 MCP4821/MCP4822 6.8 Designing A Double-Precision DAC Using A Dual DAC 1. Example 6-5 illustrates how to design a single-supply voltage output capable of up to 24-bit resolution from a dual 12-bit DAC. This design is simply a voltage divider with a buffered output. 2. As an example, if a similar application to the one developed in Section 6.6.1 “Design a Bipolar DAC Using Example 6-3” required a resolution of 1 µV instead of 1 mV, and a range of 0V to 4.1V, then 12-bit resolution would not be adequate. 3. 4. Calculate the resolution needed: 4.1V/1 µV = 4.1e06. Since 222 = 4.2e06, 22-bit resolution is desired. Since DNL = ±0.75 LSb, this design can be attempted with the MCP482X family. Since DACB‘s VOUTB has a resolution of 1 mV, its output only needs to be “pulled” 1/1000 to meet the 1 µV target. Dividing VOUTA by 1000 would allow the application to compensate for DACB‘s DNL error. If R2 is 100Ω, then R1 needs to be 100 kΩ. The resulting transfer function is shown in the equation of Example 6-5. VDD MCP482X VDD MCP482X VCC+ DACA (Fine Adjust) VO VOUTA R1 R1 >> R2 VOUTB R2 0.1 µF VCC– DACB (Course Adjust) SPI™ 3 DA V OUTA = 2.048V ⋅ G A ------12 2 DB VOUTB = 2.048V ⋅ G B ------12 2 G = Gain select (1x or 2x) D = Digital value of DAC (0 – 4096) V OUTA R2 + V OUTB R1 VO = ----------------------------------------------------R1 + R 2 EXAMPLE 6-5: DS21953A-page 24 Simple, Double-Precision DAC. © 2005 Microchip Technology Inc. MCP4821/MCP4822 6.9 Building A Programmable Current Source Example 6-6 illustrates a variation on a voltage follower design where a sense resistor is used to convert the DAC’s voltage output into a digitally-selectable current source. Adding the resistor network from Example 6-2 would be advantageous in this application. The smaller RSENSE is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled with. The voltage divider, or “window”, DAC configuration would allow the range to be reduced, thus increasing resolution around the range of interest. When working with very small sensor voltages, plan on eliminating the amplifier's offset error by storing the DAC's setting under known sensor conditions. VDD MCP482X VOUT VCC+ Load IL VCC– Ib SPI™ 3 Rsense V OUT D = 2.048V ⋅ G ------12 2 IL I b = ---β V OUT β I L = --------------- × -----------Rsense β + 1 G = Gain select (1x or 2x) D = Digital value of DAC (0 – 4096) EXAMPLE 6-6: Digitally-Controlled Current Source. © 2005 Microchip Technology Inc. DS21953A-page 25 MCP4821/MCP4822 7.0 DEVELOPMENT SUPPORT 7.1 Evaluation & Demonstration Boards The Mixed Signal PICtail™ Demo Board supports the MCP482X family of devices. Refer to www.microchip.com for further information on this product’s capabilities and availability. DS21953A-page 26 7.2 Application Notes Application notes illustrating the performance and implementation of the MCP482X family are planned but are currently not released. Refer to www.microchip.com for further information. © 2005 Microchip Technology Inc. MCP4821/MCP4822 8.0 PACKAGING INFORMATION 8.1 Package Marking Information Example: 8-Lead MSOP XXXXXX YWWNNN 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Legend: XX...X Y YY WW NNN e3 * Note: Example: MCP4821 E/P e^3 256 0524 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 4821E 524256 Example: MCP4821E e3 0524 SN^^ 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2005 Microchip Technology Inc. DS21953A-page 27 MCP4821/MCP4822 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A2 A c φ A1 (F) L β Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0° 0.08 0.22 5° 5° - MIN 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness .006 .000 A1 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width .118 BSC D Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF φ Foot Angle 0° 8° c Lead Thickness .003 .006 .009 .009 .012 .016 Lead Width B α Mold Draft Angle Top 5°5° 15° β 5°5° 15° Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.10 0.95 0.15 0.80 8° 0.23 0.40 15° 15° JEDEC Equivalent: MO-187 Drawing No. C04-111 DS21953A-page 28 © 2005 Microchip Technology Inc. MCP4821/MCP4822 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic § A A2 A1 E E1 D L c B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 © 2005 Microchip Technology Inc. DS21953A-page 29 MCP4821/MCP4822 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21953A-page 30 © 2005 Microchip Technology Inc. MCP4821/4822 APPENDIX A: REVISION HISTORY Revision A (June 2005) • Original Release of this Document. © 2005 Microchip Technology Inc. DS21953A-page 31 MCP4821/4822 NOTES: DS21953A-page 32 © 2005 Microchip Technology Inc. MCP4821/4822 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) Device: MCP4821: MCP4821T: MCP4822: MCP4822T: 12-Bit DAC with SPI™ Interface 12-Bit DAC with SPI Interface (Tape and Reel) (SOIC, MSOP) 12-Bit DAC with SPI Interface 12-Bit DAC with SPI Interface (Tape and Reel) (SOIC, MSOP) Temperature Range: E = -40°C to +125°C Package: MS = Plastic MSOP, 8-lead P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC, (150 mil Body), 8-lead © 2005 Microchip Technology Inc. c) d) e) a) b) c) MCP4821T-E/SN: Tape and Reel Extended Temperature, 8LD SOIC package. MCP4821T-E/MS: Tape and Reel Extended Temperature, 8LD MSOP package. MCP4821-E/SN: Extended Temperature, 8LD SOIC package. MCP4821-E/MS: Extended Temperature, 8LD MSOP package. MCP4821-E/P: Extended Temperature, 8LD PDIP package. MCP4822T-E/SN: Tape and Reel Extended Temperature, 8LD SOIC package. MCP4822-E/P: Extended Temperature, 8LD PDIP package. MCP4822-E/SN: Extended Temperature, 8LD SOIC package. DS21953A-page 33 MCP4821/4822 NOTES: DS21953A-page 34 © 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2005 Microchip Technology Inc. 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