ICST ICS82C404M Dual programmable graphics frequency generator Datasheet

ICS82C404
Integrated
Circuit
Systems, Inc.
Advance Information
Dual Programmable Graphics Frequency Generator
General Description
Features
The ICS82C404 is a fully programmable graphics clock generator. It can generate user specified clock frequencies using
an externally generated input reference or by a single crystal.
The output frequency is programmed by entering a 24-bit
digital word through the serial port.
•
Two fully user-programmable phase-locked loops are offered
in a single package. One PLL is designed to drive the memory
clock, while the second drives the video clock. The outputs
may be changed on-the-fly to any desired frequency between
390 kHz and 120 MHz. The ICS82C404 is ideally suited for
any design where multiple or varying frequencies are required.
This part is ideal for graphics applications. It generates low
jitter, high speed pixel clocks. It can be used to replace
multiple, expensive high speed crystal oscillators. The flexibility of the device allows it to generate non-standard graphics clocks.
The leader in the area of multiple clock output clocks on a
single chip, ICS has been shipping graphics frequency generators since October, 1990, and is constantly improving the
phase-locked loop. The ICS82C404 incorporates a patented
fourth generation PLL that offers the best jitter performance
available.
Block Diagram
ICS82C404RevA111095
•
•
•
•
•
•
•
•
•
•
•
Pin-for-pin and function compatible with ICD’s version
of the 82C404
Dual programmable graphics clock generator
Memory and video clocks are individually programmable
“on-the-fly”
Ideal for designs where multiple or varying frequencies
are required
Increased frequency resolution from optional pre-divideby-2 on the M counter
Output enable feature available for tristating outputs
Independent clock outputs range from 390 kHz to
120 MHz
Operation up to 140 MHz available
Power-down capabilities
Low-power, high speed 0.8µ CMOS technology
Glitch-free transitions
Available in 16-pin PDIP or SOIC package
ICS82C404
SEL0/CLK
SEL1/DATA
VDD
OE
GND
X1
X2
MCLK
1
2
3
4
5
6
7
8
ICS82C404
Pin Configuration
16
15
14
13
12
11
10
9
PD
EXTSEL
INIT1
VDD
INIT0
EXTCLK
FPMODE
VCLK
16-Pin PDIP or SOIC
Pin Descriptions
PIN NUMBER
PIN NAME
1
SEL0-CLK
2
SEL1-DATA
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVDD
OE
GND
X1
X2
MCLK
VCLK
FPMODE
EXTCLK
INIT0
VDD
INIT1
EXTSEL
PD
DESCRIPTION
Clock input in serial programming mode.
Clock select pin in operating mode.
Data input in serial programming mode.
Clock select pin in operating mode.
Power.
Tristates outputs when low.
Ground.
Crystal input.
Crystal output.
Memory clock output.
Video clock output.
Clock select input used to force REG2 programmed frequency.
External clock input.
Selects initial power-up conditions, LSB.
Power.
Selects initial power-up conditions, MSB.
Selects external clock input (EXTCLK) as VCLK output.
Power-down pin, active low.
2
ICS82C404
VCLK Selection
Register Definitions
OE PD EXTSEL FPMODE SEL1 SEL0
The register file consists of the following six registers:
0
1
1
1
1
1
1
1
Register Addressing
Address
Register
Definition
000
001
010
011
100
110
REG0
REG1
REG2
MREG
PWRDWN
CNTL REG
Video Clock Register 1
Video Clock Register 2
Video Clock Register 3
Memory Register
Divisor for Power-down mode
Control Register
MREG
REG0
REG1
REG2
0
1
0
1
32.500
40.000
50.350
56.644
25.175
25.175
40.000
40.000
28.322
28.322
28.322
50.350
28.322
28.322
28.322
50.350
Tristate
Forced High
REG0
REG1
EXTCLK
REG2
REG2
REG2
MCLK Selection
Register Initialization
INIT0
x
x
0
1
0
x
1
x
The memory clock outputs are controlled by PD and OE as
follows:
The registers are initialized as follows:
0
0
1
1
x
x
0
0
1
1
1
x
x
x
1
1
1
1
1
0
As seen in the table above, OE acts to tristate the output. The
PD pin forces the VCLK signal high while powering down the
part. The EXTCLK pin will only be multiplexed in when
EXTSEL and SEL0 are logic 0 and SEL1 is a logic 1.
The ICS82C404 places the three video clock registers and the
memory clock register in a known state upon power-up. The
registers are initialized based on the state of the INIT1 and
INIT0 pins at application of power to the device. The INIT pins
must ramp up with VDD if a logical 1 on either pin is required.
These input pins are internally pulled down and will default to
a logical 0 if left unconnected.
INIT1
x
x
x
x
0
1
x
x
x
0
1
1
1
1
1
1
VCLK
OE
PD
MCLK
0
1
1
x
1
0
Tristate
MREG
PWRDWN
The Clock Select pins SEL0 and SEL1 have two purposes. In
serial programming mode, these pins act as the clock and data
pins. New data bits come in on SEL1 and these bits are clocked
in by a signal on SEL0. While these pins are acquiring new
information, the VCLK signal remains unchanged. When
SEL0 and SEL1 are acting as register selects, a time-out
interval is required to determine whether the user is selecting
a new register or wants to program the part. During this initial
time-out, the VCLK signal remains at its previous frequency.
At the end of this time-out interval, a new register is selected.
A second time-out interval is required to allow the VCO to
settle to its new value. During this period of time, typically 5 ms,
the input reference signal is multiplexed to the VCLK signal.
Register Selection
When the ICS82C404 is operating, the video clock output is
controlled with a combination of the SEL0, SEL1, PD, and OE
pins. The video clock is also multiplexed to an external clock
(EXTCLK) which can be selected with the EXTSEL pin. The
VCLK Selection Table shows how VCLK is selected.
When MCLK or the active VCLK register is being reprogrammed, then the reference signal is multiplexed glitch-free
to the output during the first time-out interval. A second timeout interval is also required to allow the VCO to settle. During
this period, the reference signal is multiplexed to the appropriate output signal.
3
ICS82C404
Control Register Definition
The control register allows the user to adjust various internal options. The register is defined as follows:
Bit
Bit Name
Default Value
Description
9
C5
0
This bit determines which power-down mode the PD pin will
implement. Power-down mode 1, C5=0, forces the MCLK signal to
be a function of the power-down register. Power-down mode 2,
C5=1, turns off the crystal and disables all outputs.
8
C4
0
This bit determines which clock is multiplexed to VCLK during
frequency changes. C4=0 multiplexes the reference frequency to the
VCLK output. C4=1 multiplexes MCLK to the VCLK output for
applications where the graphics controller cannot run as slow as
fREF.
7
C3
0
This bit determines the length of the time-out interval. The time-out
interval is derived from the MCLK VCO. If this VCO is
programmed to certain extremes, the time-out interval maybe too
short. C3=0, normal time-out. C3=1, doubled time-out interval.
6
C2
0
5
C1
1
Reserved, must be set to 0.
4
C0
0
This bit adjusts the duty cycle. C1=0 causes a 1ns decrease in
output high time. C1=1 causes no adjustment. If the load
capacitance is high, the adjustment can bring the duty cycle closer
to 50%.
3
NS2
0
Reserved, must be set to 0.
2
NS1
0
Acts on register 2. NS2=0 prescales the N counter by 2.
NS2=1 prescales the P counter value to 4.
1
NS0
0
Acts on register 1. NS1=0 prescales the N counter by 2.
NS1=1 prescales the P counter value to 4.
Acts on register 0. NS0=0 prescales the P counter by 2.
NS0=1 prescales the P counter value to 4.
4
ICS82C404
Since the VCLK registers are selected by the SEL0 and SEL1
pins, and since any change in their state may affect the output
frequency, new data input on the selection bits is only permitted
to pass through the decode logic after the watchdog timer has
timed out. This delay of SEL0 or SEL1 data permits a serial
program cycle to occur without affecting the current register
selection.
Serial Programming Architecture
The pins SEL0 and SEL1 perform the dual functions of selecting registers and serial programming. In serial programming
mode, SEL0 acts as a clock pin while SEL1 acts as the data pin.
The ICS82C404-01 may not be serially programmed when in
power-down mode.
In order to program a particular register, an unlocking sequence
must occur. The unlocking sequence is detailed in the following
timing diagram:
Serial Data Register
The serial data is clocked into the serial data register in the
order described in Figure 1 below (Serial Data Timing).
The serial data is sent as follows: An individual data bit is
sampled on the rising edge of CLK. The complement of the
data bit must be sampled on the previous falling edge of CLK.
The set-up and hold time requirements must be met on both
CLK edges. For specifics on timing, see the timing diagrams
on pages 10, 11 and 12.
The bits are shifted in this order: a start bit, 21 data bits, 3
address bits (which designate the desired register), and a stop
bit. A total of 24 bits must always be loaded into the serial data
register or an error is issued. Following the entry of the last
data bit, a stop bit or load command is issued by bringing DATA
high and toggling CLK high-to-low and low-to-high. The
unlocking mechanism then resets itself following the load.
Only after a time-out period are the SEL0 and SEL1 pins
allowed to return to a register selection function.
The unlock sequence consists of at least five low-to-high
transitions of CLK while data is high, followed immediately
by a single low-to-high transition while data is low. Following
this unlock sequence, data can be loaded into the serial data
register.
Following any transition of CLK or DATA, the watchdog timer
is reset and begins counting. The watchdog timer ensures that
successive rising edges of CLK and DATA do not violate the
time-out specification of 2ms. If a time-out occurs, the lock
mechanism is reset and the data in the serial data register is
ignored.
Figure 1: Serial Data Timing
5
ICS82C404
The value of FVCO must remain between 50 MHz and
120 MHz. As a result, for output frequencies below 50 MHz,
FVCO must be brought into range. To achieve this, an output
divisor is selected by setting the values of the Mux Field (R)
as follows:
The serial data register is exactly 24 bits long, enough to accept
the data being sent. The stop bit acts a load command that
passes the contents of the Serial Data Register into the register
indicated by the three address bits. If a stop bit is not received
after the serial register is full, and more data is sent, all data in
the register is ignored and an error issued. If correct data is
received, then the unlocking mechanism rearms, all data in the
serial data register is ignored, and an error is issued.
Output Divisor
Programming the ICS82C404
The ICS82C404 has a wide operating range, but it is recommended that it is operated within the following limits:
1 MHz < FREF < 60 MHz
200 kHz < FREF/M < 5 MHz
50 MHz < FVCO < 120 MHz
FCLK < 120 MHz
FREF=Input
Reference Frequency
M=Reference divide
3 to 129
FVCO=VCO output
frequency
FCLK=output
frequency
Index (I)
N counter value (N’)
Mux (R)
M counter value (M’)
Divisor
000
001
010
011
100
101
110
111
1
2
4
8
16
32
64
128
Unlike the ICD’s 82C404, the ICS82C404’s VCO does not
require tuning to place it in certain ranges. The ICS82C404’s
VCO will operate from 50 MHz to 120 MHz without adjusting
the VCO gain. However, to maintain compatibility, the I bits
are programmed as in the ICD2061A.
The frequency of the programmable oscillator FVCO is determined by the following fields:
Field
R
These bits are dummy bits except for the following two cases:
Index Field (I)
# of Bits
I
4
7
3
7
1110
1111
VCLK FVCO
Turn off VCLK
Mux MCLK to VLCK
MCLK FVCO
50-120 MHz
50-120 MHz
When the index field is set to 1111, VCLK is turned off and
both channels run from the same MCLK VCO. This is done in
an effort to reduce jitter, which may increase when VCOs run
at 2n multiples of one another. If the two outputs must be
multiples of one another, it is best to mux MCLK over to the
output of the VCLK VCO, and to power-down the VCLK
VCO. The multiplexed frequency will be divided down by the
correct divisor (M) and output on VCLK.
Where the least significant bit is the last bit of M and the most
significant bit is the first bit of 1.
The equations used to determine the oscillator frequency are:
N=N’ + 3 M=M’+2
FVCO=Prescale • N/M • FCLK
where < M < 129 and 4 < N < 130
and prescale=2 or 4, as set in the control register
6
ICS82C404
Power-down Mode 2
Power Management Issues
When there is no need for any output during power-down, an
alternate mode is available which will completely shut down
all outputs and the reference oscillator, but still preserves all
register contents. Power-down mode 2 is invoked by the first
programming the power-down bit in the CNTL register and
then pulling the PD pin low.
Power-down mode 1
The ICS82C404 contains a mechanism to reduce the quiescent
power when stand-by operation is desired. Power-down mode
1 is invoked by pulling PD low and having the proper CNTL
register bit set to zero. In this mode, VCOs are shut down, the
VCLK output is forced high, and the MCLK output is set to a
user-defined low frequency value to refresh dynamic RAM.
The PD pin
The PD pin has a standard internal pull-up resistor during
normal operation. When the chip goes into power-down mode
1 or 2, the normal pull-up resistor is dynamically switched to
a weak pull-up, which reduces power consumption. If the PD
pin is allowed to float after it has been pulled down, the weak
pull-up will bring the signal high and allow the device to
resume operation.
The power-down MCLK value is determined by the following
equation:
MCLKPD=FREF/(PWRDWN register divisor value)
The power-down register divisor is determined according to
the 4-bit word programmed into the PWRDWN register (see
table below).
Power-Down Register Table
P3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PWRDWN bits
P2
P1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
P0
PWRDWN
Register Value
Power-down
Divisor
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8 (default)
9
A
B
C
D
E
F
n/a
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
7
MCLKPD
(fREF=14.31818)
n/a
447.4 kHz
477.3 kHz
511.4 kHz
550.7 kHz
596.6 kHz
650.8 kHz
715.9 kHz
795.5 kHz
894.9 kHz
1.02 MHz
1.19 MHz
1.43 MHz
1.79 MHz
2.39 MHz
3.58 MHz
ICS82C404
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics
VDD = +5V ± 5%, 0°C ≤ TAMBIENT ≤ +70°C unless otherwise stated
Maximum Ratings
PARAMETER
Supply voltage relative to GND
Input voltage with respect to GND
Operating temperature
Storage temperature
Max soldering temperature (10 sec)
Junction temperature
Package power dissipation
SYMBOL
MIN
MAX
UNITS
VDD
VIN
TOPER
TSTOR
TSOL
Tj
PDISS
-0.5
-0.5
0
-65
7.0
VDD +0.5
+70
+150
+260
+125
350
Volts
Volts
°C
°C
°C
°C
mWatts
DC Characteristics
PARAMETER
High level input voltage
Low level input voltage
High level CMOS output voltage
Low level output voltage
Input high current
Input low current
Output leakage current
Power supply current
Power supply current (typical)
Analog power supply current
Power-down current (Mode 1)
Power-down current (Mode 2)
Input capacitance
SYMBOL
VIH
VIL
VOH
VOL
IIH
IIL
IOZ
IDD
IDD-TYP
IADD
IPD1
IPD2
CIN
TEST CONDITIONS
MIN
TYP
MAX
2.0
0.8
IOH=-4ma
IOL=4ma
VIH=5.25V
VIL=0V
(tristate)
3.84
0.4
100
-250
10
65
15
@60 MHz
35
6
25
8
20
7.5
50
10
UNITS
V
V
V
V
µA
µA
µA
ma
ma
ma
ma
µA
pF
ICS82C404
Electrical Characteristics (continued)
AC Characteristics
DESCRIPTION
Reference oscillator value (Note 1)
1/fREF
Duty cycle for the input oscillator
defined as t1/tREF
Output oscillator values
Duty cycle for the output oscillators
(Note 2)
Rise time for the output oscillators
into a 25pF load
Fall time for the output oscillators
into a 25pF load
Old frequency output
New frequency output
Time clock output remains high while
output muxes to reference frequency
Interval for serial programming and
for VCO changes to settle (Note 3)
Time clock output remains high while
output muxes to new frequency value
Time for the output oscillators to go
into tristate mode after OUTDISsignal assertion
Time for the output oscillators to
recover from tristate mode after
OUTDIS-signal goes high
Time for power-down mode of
operation to take effect
Time for recovery from power-down
mode to a valid CLK
Time for MCLK to go high after
PWRDWN is asserted high
Delay of MCLK prior to fMCLK
signal at output
Clock period of serial clock
Set-up time
Hold time
Load command
NAME
SYMBOL
MIN
TYP
MAX
UNITS
Reference
frequency
Reference period
Input duty cycle
fREF
1
14.31818
60
MHz
tREF
t1
16.6
25%
1000
75%
ns
Output clock
periods
Output duty cycle
t2
8.33
(120 MHz)
45%
2564
(390 kHz)
55%
ns
Rise times
t4
3
ns
Fall times
t5
3
ns
t3
freq1 output
freq2 output
fREF mux time
Time-out interval
tfreq1
tfreq2
tA
0.5
tREF
ttime-out
1.5
2
5
tREF
10
ms
tfreq2muxtime
tB
Tristate
t6
12
ns
CLK valid
t7
12
ns
Power-Down
t8
12
ns
Power-Up
t9
12
ns
MCLKOUT high
t10
tPWRDWN
ns
MCLKOUT delay
t11
tserclk
tSU
tHD
tldcmd
0.5
tREF
0
0.5
tMCLK
2 • tREF
20
10
0
1.5
ns
tREF
1.5
tMCLK
2
t1+30
Notes:
1.
2.
3.
ns
For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally.
Duty cycle is measured at CMOS threshold levels. At 5 volts, VTH=2.5 volts.
If the interval is too short, see the time-out interval section in the control register definition.
9
ns
ms
ns
ns
ns
ICS82C404
Rise and Fall Times
Tristated Timing
10
ICS82C404
Selection Timing
MCLK and Active VCLK Register Programming Timing
11
ICS82C404
Soft Power-down Timing (Mode 2)
Serial Programming Timing
12
ICS82C404
16-Pin PDIP Package
16-Pin SOIC Package
Ordering Information
ICS82C404N or 82C404M
Example:
ICS XXXX M
Package Type
N=DIP (Plastic)
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device
ADVANCE INFORMATION documents contain information on new products in the sampling
or preproduction phase of development. Characteristic data and other specifications are
subject to change without notice.
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