Numonyx M29W640GH60NB6E 64 mbit (8mb x8 or 4mb x16, page) 3v supply flash memory Datasheet

M29W640GH M29W640GL
M29W640GT M29W640GB
64 Mbit (8Mb x8 or 4Mb x16, Page)
3V supply Flash memory
Feature
■
Supply Voltage
– VCC = 2.7 to 3.6 V for Program/Erase/Read
– VPP =12 V for Fast Program (optional)
■
Asynchronous Random/Page Read
– Page Width: 4 words
– Page Access: 25 ns
– Random Access: 60 ns, 70 ns, 90 ns
■
■
■
FBGA
TSOP48 (NA)
12 x 20mm
FBGA
Fast Program commands
– 2 word/4 byte Program (without VPP=12 V)
– 4 word/8 byte Program (with VPP=12 V)
– 16 word/32 byte Write Buffer
Programming time
– 10 µs per byte/word typical
– Chip Program time: 10 s (4-word Program)
Memory organization
– M29W640GH/L:
128 main blocks, 64 Kbytes each
– M29W640GT/B
Eight 8 Kbytes Boot blocks (top or bottom)
127 Main blocks, 64 Kbytes each
TFBGA48 (ZA)
6 x 8mm
TSOP56 (NB)
)
14 x 20mm(1
TBGA64 (ZF)
10 x 13mm(1)
1. Packages only available upon request.
■
128 word Extended Memory block
– Extra block used as security block or to
store additional information
■
Low power consumption:Standby and
Automatic Standby
■
Unlock Bypass Program command
– Faster Production/Batch Programming
■
Program/Erase controller
– Embedded byte/word program algorithms
■
Common Flash Interface: 64-bit Security Code
■
VPP/WP pin for Fast Program and Write Protect
■
Program/Erase Suspend and Resume
– Read from any block during Program
Suspend
– Read and Program another block during
Erase Suspend
■
Temporary Block Unprotection mode
■
100,000 Program/Erase cycles per block
■
Electronic Signature
– Manufacturer Code: 0020h
– Device code (see Table 1)
■
ECOPACK® packages
Table 1.
March 2008
Device summary
Root Part Number
Device code
M29W640GH: Uniform, last block protected by VPP/WP
227Eh + 220Ch + 2201h
M29W640GL: Uniform, first block protected by VPP/WP
227Eh + 220Ch + 2200h
M29W640GT: Top Boot Blocks
227Eh + 2210h + 2201h
M29W640GB: Bottom Boot Blocks
227Eh + 2210h + 2200h
Rev 5
1/90
www.numonyx.com
1
Contents
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
4
2.1
Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4
Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 14
2.5
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8
VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9
Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10
Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11
Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.12
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.13
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.2
Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
2/90
3.6.1
Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.1
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.2
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.3
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M29W640GH, M29W640GL, M29W640GT, M29W640GB
4.2
4.3
5
Contents
4.1.4
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.5
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.6
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.7
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.8
Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.9
Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.10
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.1
Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.2
Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.3
Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.4
Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.5
Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.6
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.7
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.8
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.9
Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.10
Write to Buffer and Program Confirm command . . . . . . . . . . . . . . . . . . 32
4.2.11
Write to Buffer and Program Abort and Reset command . . . . . . . . . . . 32
Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.1
Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.2
Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.3
Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 33
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1
Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2
Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3
Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.4
Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.5
Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6
Write to Buffer and Program Abort Bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . 41
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3/90
Contents
9
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
C.1
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
C.2
Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Appendix D Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
D.1
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
D.2
In-System Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Appendix E
Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protection granularity on the M29W640GH and M29W640GL . . . . . . . . . . . . . . . . . . . . . . . 9
Protection granularity on the M29W640GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protection granularity on the M29W640GB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Electronic Signature addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Program, Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Write ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reset/Block Temporary Unprotect ac Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Data polling and data toggle ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 56
TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data . . . 57
TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data . . . . . . 58
TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data. . . . . . . 59
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
M29W640GH and M29W640GL block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Top boot block addresses, M29W640GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Bottom boot block addresses, M29W640GB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Extended block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5/90
List of figures
M29W640GH, M29W640GL, M29W640GT, M29W640GB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
6/90
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TSOP56 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TBGA64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chip Enable controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chip/Block Erase waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Read Mode ac waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Page Read ac waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Write ac waveforms, Write Enable Controlled (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 50
Write ac waveforms, Chip Enable Controlled (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 51
Reset/Block Temporary Unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Data Polling ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Toggle/alternative Toggle bit polling ac waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . 54
TSOP48 –48 lead Plastic Thin Small Outline, 12x20mm, top view package outline . . . . . 56
TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, top view package outline . . . . 57
TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . . . . 58
TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline . . . . . . . . . . . . . . 59
Programmer Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
In-System Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
In-System Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Write to Buffer and Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 87
M29W640GH, M29W640GL, M29W640GT, M29W640GB
1
Description
Description
The M29W640G is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Program and Erase commands are written to
the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase
operation can be detected and any error conditions identified. The command set required to
control the memory is consistent with JEDEC standards.
The M29W640GH and M29W640GL memory array is organized into 128 uniform Blocks of
64 Kbytes each (or 32 Kwords each).
The M29W640GT and M29W640GB feature an asymmetric block architecture. The devices
have an array of 135 blocks, divided into 8 Parameter Blocks of 8 Kbytes each (or 4 Kwords
each), and 127 Main Blocks of 64 Kbytes each (or 32 Kwords each). The M29W640GT has
the Parameter Blocks at the top of the memory address space while the M29W640GB
locates the Parameter Blocks starting from the bottom.
Blocks are protected by groups to prevent accidental Program or Erase commands from
modifying the memory.
●
Table 3, describes the protection granularity on the M29W640GH and M29W640GL.
●
Table 4, and Table 5. describe the protection granularity on the M29W640GT and
M29W640GB.
The M29W640G support Asynchronous Random Read and Page Read from all blocks of
the memory array.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The VPP/WP signal is used to enable faster programming of the device. Protection from
Program/Erase operation can be obtained by holding VPP/WP to VSS:
●
On the M29W640GH and M29W640GL, the last and the first block is protected,
respectively.
●
On the M29W640GT and M29W640GB, the first two and the last two boot blocks are
protected.
The devices feature a full set of Fast Program commands to improve the programming
throughput:
●
2 Byte Program: it is not necessary to raise VPP/WP to 12V before issuing this
command
●
2 Words/4 Bytes Program: it is not necessary to raise VPP/WP to 12V before issuing
this command.
●
4 Words/8 Bytes Program: VPP/WP must be raised to 12V before issuing this
command.
●
Write to Buffer and Program, allowing to program in one shot a buffer of 16 words/32
bytes.
7/90
Description
M29W640GH, M29W640GL, M29W640GT, M29W640GB
The M29W640G has an extra block, the Extended Block, of 128 words in x16 mode or of
256 bytes in x8 mode that can be accessed using a dedicated command. The Extended
Block can be protected and so is useful for storing security information. However the
protection is not reversible, once protected the protection cannot be undone.
The M29W640GT, M29W640GB, M29W640GH and M29W640GL, are offered in TSOP48
(12x 20mm), TSOP56 (14x 20mm), TFBGA48 (6 x8mm, 0.8mm pitch), and TBGA64 (10x
13mm, 1mm pitch) packages.
In order to meet environmental requirements, Numonyx offers the M29W640GH,
M29W640GL, M29W640GT and M29W640GB in ECOPACK® packages. ECOPACK
packages are Lead-free. The category of second Level Interconnect is marked on the
package and on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label.
The memory is delivered with all the bits erased (set to 1).
Figure 1.
Logic diagram
VCC
VPP/WP
22
15
A0-A21
W
E
G
DQ0-DQ14
M29W640GT
M29W640GB
M29W640GH
M29W640GL
DQ15A–1
BYTE
RB
RP
VSS
ai13694
8/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Description
Signal names(1)
Table 2.
Name
Description
A0-A21
Direction
Address Inputs
Inputs
DQ0-DQ7
Data Inputs/Outputs
Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
Inputs/Outputs
Data Input/Output or Address Input (or Data Input/Output)
Inputs/Outputs
DQ15A–1 (or DQ15)
E
Chip Enable
Input
G
Output Enable
Input
W
Write Enable
Input
RP
Reset/Block Temporary Unprotect
Input
RB
Ready/Busy
BYTE
Output
Byte/Word Organization Select
VCC
VPP/WP
Input
Supply Voltage
Supply voltage
Supply Voltage for Fast Program (optional) or Write Protect
Supply voltage
VSS
Ground
-
NC
Not Connected Internally
-
1. VPP/WP may be left floating since it is internally connected to an pull-up resistor to enable Program/Erase operations,
Table 3.
Protection granularity on the M29W640GH and M29W640GL
Block
Kbytes/Kwords
Protection Block Group
(x8)
(x16)
0 to 3
4 x 64/32
Block level
000000h–03FFFFh(1)
000000h–01FFFFh(1)
4 to 7
4 x 64/32
Protection Group
040000h–07FFFFh
020000h–03FFFFh
--
--
--
--
--
120 to 123
4 x 64/32
Protection Group
780000h–7BFFFFh
3C0000h–3DFFFFh
124 to 127
4x 64/32
Block level
7C0000h–7FFFFFh
3E0000h–3FFFFFh
1. Used as the Extended Block Addresses in Extended Block mode.
Table 4.
Protection granularity on the M29W640GT
Block
Kbytes/Kwords
Protection Block Group
(x8)
(x16)
0 to 3
4 x 64/32
Protection Group
000000h–03FFFFh(1)
000000h–01FFFFh(1)
4 to 7
4 x 64/32
Protection Group
040000h–07FFFFh
020000h–03FFFFh
--
--
--
--
--
120 to 123
4 x 64/32
Protection Group
780000h–7BFFFFh
3C0000h–3DFFFFh
124 to 126
3 x 64/32
Protection Group
7C0000h–7EFFFFh
3E0000h–3F7FFFh
127 to 134
8x 8/4(2)
Block level
7F0000h–7FFFFFh
3F8000h–3FFFFFh
1. Used as the Extended Block Addresses in Extended Block mode.
2. Boot blocks.
9/90
Description
Table 5.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Protection granularity on the M29W640GB
Block
Kbytes/Kwords
Protection Block Group
(x8)
(x16)
0 to 7
8x 8/4(1)
Block level
000000h–00FFFFh(2)
000000h–007FFFh(2)
8 to 10
3 x 64/32
Protection Group
010000h-03FFFFh
008000h-01FFFFh
11 to 14
4 x 64/32
Protection Group
040000h-07FFFFh
020000h-03FFFFh
--
--
--
--
--
127 to 130
4 x 64/32
Protection Group
780000h-7BFFFFh
3C0000h-3DFFFFh
131 to 134
4 x 64/32
Protection Group
7C0000h–7FFFFFh
3E0000h–3FFFFFh
1. Boot blocks.
2. Used as the Extended Block Addresses in Extended Block mode.
Figure 2.
TSOP48 connections
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
W
RP
A21
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
12
13
24
48
M29W640GT
M29W640GB
M29W640GH
M29W640GL
37
36
25
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
AI13695
10/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 3.
Description
TSOP56 connections
NC
NC
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
W
RP
A21
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
14
28
56
M29W640GT
M29W640GB
M29W640GH
M29W640GL
43
29
NC
NC
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
NC
VCC
ai13696
11/90
Description
Figure 4.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
TFBGA48 connections (top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
VPP/WP
RP
A8
A12
C
A2
A6
A18
A21
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI12718
12/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 5.
Description
TBGA64 connections (top view through package)
7
8
A9
A13
NC
RP
A8
A12
NC
A18
A21
A10
A14
NC
A5
A20
A19
A11
A15
VCC(1)
A0
DQ0
DQ2
DQ5
DQ7
A16
VSS
VCC(1)
E
DQ8
DQ10
DQ12
DQ14
BYTE
NC
NC
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
NC
NC
VSS
DQ1
DQ3
DQ4
DQ6
VSS
NC
1
2
3
4
5
6
A
NC
A3
A7
RB
W
B
NC
A4
A17
VPP/WP
C
NC
A2
A6
D
NC
A1
E
NC
F
G
H
AI12719
1. Pads D8 and F1 are not connected (NC) on the M29W640GT and M29W640GB devices.
13/90
Signal descriptions
2
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Signal descriptions
See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals
connected to the device.
2.1
Address Inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
2.2
Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the Program/Erase Controller.
2.3
Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
2.4
Data Input/Output or Address Input (DQ15A–1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the
LSB of the addressed word, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data Input/Output to include this pin when BYTE is High and
references to the Address Inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
2.5
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
14/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
2.7
Signal descriptions
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
2.8
VPP/Write Protect (VPP/WP)
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time required for Unlock Bypass
Program operations. The Write Protect performs hardware protection:
●
It protects the first and last block on M29W640GH and M29W640GL devices.
●
It protects the first two and the last two boot blocks on M29W640GT and M29W640GB
devices.
The VPP/Write Protect pin may be left floating or unconnected (see Table 17: DC
characteristics).
When VPP/Write Protect is Low, VIL, the two outermost (M29W640GH and M29W640GL) or
four outermost blocks (M29W640GT and M29W640GB) are protected. Program and Erase
operations in this block are ignored while VPP/Write Protect is Low, even when RP is at VID.
When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status
of the outermost blocks. Program and Erase operations can now modify the data in the
outermost blocks unless the block is protected using Block Protection.
Applying 12V to the VPP/WP pin will temporarily unprotect any block previously protected
(including the outermost blocks) using a High Voltage Block Protection technique (InSystem or Programmer technique). See Table 6: Hardware Protection for details.
When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock
Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes.
During Unlock Bypass Program operations the memory draws IPP from the pin to supply the
programming circuits. See the description of the Unlock Bypass command in the Command
Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than
tVHVPP, see Figure 18: Accelerated Program Timing waveforms.
Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the
memory may be left in an indeterminate state.
A 0.1µF capacitor should be connected between the VPP/Write Protect pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Unlock Bypass Program, IPP.
Table 6.
Hardware Protection
VPP/WP
RP
VIH
VIL
VID
Function
M29W640GT and
M29W640GB
4 outermost parameter blocks protected from
Program/Erase operations
M29W640GH and
M29W640GL
2 outermost blocks protected from Program/Erase
operations
M29W640GT and
M29W640GB
All blocks temporarily unprotected except the 4 outermost
blocks
M29W640GH and
M29W640GL
All blocks temporarily unprotected except the 2 outermost
blocks
15/90
Signal descriptions
Table 6.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Hardware Protection
VPP/WP
RP
Function
VIH or VID
VID
All blocks temporarily unprotected
VPP
VIH or VID
All blocks temporarily unprotected
16/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
2.9
Signal descriptions
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
Note that if VPP/WP is at VIL, then the two or four outermost blocks will remain protected
even if RP is at VID.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at
least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last.
See the Ready/Busy Output section, Table 20: Reset/Block Temporary Unprotect ac
Characteristics and Figure 17: Reset/Block Temporary Unprotect ac waveforms, for more
details.
Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from VIH to VID must be
slower than tPHPHH.
2.10
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and
Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 20: Reset/Block Temporary Unprotect ac
Characteristics and Figure 17: Reset/Block Temporary Unprotect ac waveforms, for more
details.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11
Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus
modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in
x8 mode, when it is High, VIH, the memory is in x16 mode.
17/90
Signal descriptions
2.12
M29W640GH, M29W640GL, M29W640GT, M29W640GB
VCC Supply Voltage
VCC provides the power supply for all operations (Read, Program and Erase).
The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout
Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Program and Erase operations, ICC3.
2.13
VSS Ground
VSS is the reference for all voltage measurements. The device features two VSS pins which
must be both connected to the system ground.
18/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
3
Bus operations
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 7: Bus Operations, BYTE
= VIL and Table 8: Bus Operations, BYTE = VIH, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 13: Read Mode
ac waveforms (8-bit mode), and Table 18: Read ac characteristics, for details of when the
output becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. To speed up the read operation the
memory array can be read in Page mode where data is internally read and stored in a page
buffer. The Page has a size of 4 words and is addressed by the address inputs A0-A1.
A valid Bus Write operation begins by setting the desired address on the Address Inputs.
The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, VIH, during the whole Bus Write operation. See
Figure 15: Write ac waveforms, Write Enable Controlled (8-bit mode), Figure 16: Write ac
waveforms, Chip Enable Controlled (8-bit mode), and Table 19: Write ac characteristics and
Table 19: Write ac characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the
Standby current level see Table 17: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, ICC3, for Program or Erase operations until the operation completes.
19/90
Bus operations
3.5
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
3.6
Special Bus Operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require VID to be
applied to some pins.
3.6.1
Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 7:
Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, with A9 set to VID.
3.6.2
Block Protect and Chip Unprotect
Groups of blocks can be protected against accidental Program or Erase. The Protection
Groups are shown in Appendix A: Block addresses Table 28 and Table 29. The whole chip
can be unprotected to allow the data inside the blocks to be changed.
The VPP/Write Protect pin can be used to protect the two outermost blocks on the
M29W640GH and M29W640GL, and the four outermost blocks on the M29W640GT and
M29W640GB. When VPP/Write Protect is at VIL the outermost blocks are protected and
remain protected regardless of the Block Protection Status or the Reset/Block Temporary
Unprotect pin status.
Block Protect and Chip Unprotect operations are described in : Revision history.
20/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 7.
Bus operations
Bus Operations, BYTE = VIL (1)
Data Inputs/Outputs
Operation
E
G
W
Address Inputs
DQ15A–1, A0-A21
DQ14DQ8
DQ7-DQ0
Bus Read
VIL
VIL
VIH
Cell Address
Hi-Z
Data Output
Bus Write
VIL
VIH
VIL
Command Address
Hi-Z
Data Input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
Hi-Z
20h
Output Disable
Read Device Code
(cycle 1)
7Eh
Read Device Code
(cycle 2)
VIL
VIL
VIH
Read Device Code
(cycle 3)
Read Extended
Memory Block
Verify Code
Read Block
Protection Status
Hi-Z
M29W640GH,
M29W640GL
0Ch
M29W640GT,
M29W640GB
10h
M29W640GH,
M29W640GT
01h
M29W640GL,
M29W640GB
00h
M29W640GL,
M29W640GT,
M29W640GB
88h (Factory locked)
08h (Customer
Lockable)
M29W640GH
98h(Factory Locked)
18h (Customer
Lockable)
Table 9
VIL
VIL
VIL
VIL
VIH
VIH
Hi-Z
Hi-Z
01h (protected)
00h (unprotected)
1. X = VIL or VIH.
21/90
Bus operations
Table 8.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Bus Operations, BYTE = VIH(1)
E
G
W
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read
VIL
VIL
VIH
Cell Address
Data Output
Bus Write
VIL
VIH
VIL
Command Address
Data Input
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
Operation
Output Disable
0020h
Read Device Code
(cycle 1)
227Eh
Read Device Code
(cycle 2)
VIL
VIL
VIH
Read Device Code
(cycle 3)
Read Extended
Memory Block
Verify Code
220Ch
M29W640GT,
M29W640GB
2210h
M29W640GH,
M29W640GT
2201h
M29W640GL,
M29W640GB
2200h
M29W640GL,
M29W640GT,
M29W640GB
2288h (Factory locked)
2208h (Customer
Lockable)
M29W640GH
2298h(Factory Locked)
2218h (Customer
Lockable)
Table 9
VIL
Read Block
Protection Status
M29W640GH,
M29W640GL
VIL
VIL
VIL
VIH
0001h (protected)
0000h (unprotected)
VIH
1. X = VIL or VIH.
Table 9.
Read Electronic Signature addresses(1)
A7-A0
A6-A0, DQ15A–1
BYTE = VIH
BYTE = VIL
Manufacturer Code
00h
00h
Device Code (cycle 1)
01h
02h
Device Code (cycle 2)
0Eh
1Ch
Device Code (cycle 3)
0Fh
1Eh
Extended Memory Block Verify Code
03h
06h
Code
Block Protection Status
1. A9 = VID; other address bits set to VIL or VIH.
2. A12- A21 must be set to the block address.
22/90
(2)
02h
04h(2)
M29W640GH, M29W640GL, M29W640GT, M29W640GB
4
Command Interface
Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 10, or Table 11, depending on the configuration that is
being used, for a summary of the commands.
4.1
Standard commands
4.1.1
Read/Reset command
The Read/Reset command returns the memory to its Read mode. It also resets the errors in
the Status Register. Either one or three Bus Write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the timeout of a Block Erase operation then the memory will take up to 10µs
to abort. During the abort period no valid data can be read from the memory. The
Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.
4.1.2
Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code, the
Block Protection Status and the Extended Memory Block Verify Code. Three consecutive
Bus Write operations are required to issue the Auto Select command. Once the Auto Select
command is issued the memory remains in Auto Select mode until a Read/Reset command
is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode,
all other commands are ignored.
In Auto Select mode, the Manufacturer Code and the Device Code can be read by using a
Bus Read operation with addresses and control signals set as shown in Table 7: Bus
Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, except for A9 that is
‘Don’t Care’.
The Block Protection Status of each block can be read using a Bus Read operation with
addresses and control signals set as shown in Table 7: Bus Operations, BYTE = VIL and
Table 8: Bus Operations, BYTE = VIH, except for A9 that is ‘Don’t Care’. If the addressed
block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is
output (in 8-bit mode).
The protection status of the Extended Memory block, or Extended Memory Block Verify
code, can be read using a Bus Read operation with addresses and control signals set as
shown in Table 7: Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH,
except for A9 that is ‘Don’t Care’. If the Extended Block is "Factory Locked" then 80h is
output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output (8-bit mode).
23/90
Command Interface
4.1.3
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Read CFI Query command
The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) Memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Autoselected mode.
One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Autoselected mode). A second Read/Reset command would be
needed if the device is to be put in the Read Array mode from Autoselected mode.
See Appendix B: Common Flash Interface (CFI), Tables 30, 31, 32, 33, 34 and 35 for details
on the information contained in the Common Flash Interface (CFI) memory area.
4.1.4
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 12: Program, Erase times and endurance cycles. All Bus
Read operations during the Chip Erase operation will output the Status Register on the Data
Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
Refer to Figure 8: Chip/Block Erase waveforms (8-bit mode) for a description of Chip Erase
ac waveforms.
24/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
4.1.5
Command Interface
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase Controller starts it is not possible to
select any more blocks. Each additional block must therefore be selected within 50µs of the
last block. The 50µs timer restarts when an additional block is selected. The Status Register
can be read after the sixth Bus Write operation. See the Status Register section for details
on how to identify if the Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 12: Program, Erase times
and endurance cycles. All Bus Read operations during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs. See the section on the Status Register for
more details.
After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
Refer to Figure 8: Chip/Block Erase waveforms (8-bit mode) for a description of Block Erase
ac waveforms.
4.1.6
Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.
The Program/Erase Controller will suspend within the Erase Suspend Latency time of the
Erase Suspend Command being issued. Once the Program/Erase Controller has stopped
the memory will be set to Read mode and the Erase will be suspended. If the Erase
Suspend command is issued during the period when the memory is waiting for an additional
block (before the Program/Erase Controller starts) then the Erase is suspended immediately
and will start immediately when the Erase Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
Register.
25/90
Command Interface
M29W640GH, M29W640GL, M29W640GT, M29W640GB
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
4.1.7
Erase Resume command
The Erase Resume command must be used to restart the Program/Erase Controller after an
Erase Suspend. The device must be in Read Array mode before the Resume command will
be accepted. An erase can be suspended and resumed more than once.
4.1.8
Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that
data can be read from any block. When the Program Suspend command is issued during a
program operation, the device suspends the program operation within the Program Suspend
Latency time (see Table 12: Program, Erase times and endurance cycles for value) and
updates the Status Register bits.
After the program operation has been suspended, the system can read array data from any
address. However, data read from Program-Suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresses not in Erase
Suspend or Program Suspend. If a read is needed from the Extended Block area (One-time
Program area), the user must use the proper command sequences to enter and exit this
region.
The system may also issue the Auto Select command sequence when the device is in the
Program Suspend mode. The system can read as many Auto Select codes as required.
When the device exits the Auto Select mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See Auto Select command sequence for
more information.
4.1.9
Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. See Write Operation Status for more
information.
The system must write the Program Resume command, to exit the Program Suspend mode
and to continue the programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.
26/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
4.1.10
Command Interface
Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final write operation latches
the address and data, and starts the Program/Erase Controller.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively (see Section 4.1.8: Program
Suspend command and Section 4.1.9: Program Resume command).
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table 12: Program, Erase times and endurance cycles. Bus Read operations during the
program operation will output the Status Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
Refer to Figure 6: Write Enable controlled Program waveforms (8-bit mode) and Figure 7:
Chip Enable controlled Program waveforms (8-bit mode) for a description of Program ac
waveforms.
27/90
Command Interface
4.2
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Fast Program commands
There are five Fast Program commands available to improve the programming throughput,
by writing several adjacent words or bytes in parallel:
●
Quadruple and Octuple Byte Program, available for x8 operations
●
Double and Quadruple Word Program, available for x16 operations
●
Write to Buffer and Program
Fast Program commands can be suspended and then resumed by issuing a Program
Suspend command and a Program Resume command, respectively (see Section 4.1.8:
Program Suspend command and Section 4.1.9: Program Resume command).
4.2.1
Double Byte Program command
The Double Byte Program command is used to write a page of two adjacent bytes in
parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to
issue the Double Byte Program command.
1.
The first bus cycle sets up the Double Byte Program Command.
2.
The second bus cycle latches the Address and the Data of the first byte to be written.
3.
The third bus cycle latches the Address and the Data of the second byte to be written.
Note:
It is not necessary to raise VPP/WP to 12V before issuing this command.
4.2.2
Quadruple Byte Program command
The Quadruple Byte Program command is used to write a page of four adjacent bytes in
parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles
are necessary to issue the Quadruple Byte Program command:
Note:
28/90
1.
The first bus cycle sets up the Quadruple Byte Program Command.
2.
The second bus cycle latches the Address and the Data of the first byte to be written.
3.
The third bus cycle latches the Address and the Data of the second byte to be written.
4.
The fourth bus cycle latches the Address and the Data of the third byte to be written.
5.
The fifth bus cycle latches the Address and the Data of the fourth byte to be written and
starts the Program/Erase Controller.
It is not necessary to raise VPP/WP to 12V before issuing this command.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
4.2.3
Command Interface
Octuple Byte Program command
This is used to write eight adjacent bytes, in x8 mode, simultaneously. The addresses of the
eight bytes must differ only in A1, A0 and DQ15A-1.
12V must be applied to the VPP/Write Protect pin, VPP/WP, prior to issuing an Octuple Byte
Program command. Care must be taken because applying a 12V voltage to the VPP/WP pin
will temporarily unprotect any protected block.
Nine bus write cycles are necessary to issue the command:
4.2.4
1.
The first bus cycle sets up the command.
2.
The second bus cycle latches the Address and the Data of the first byte to be written.
3.
The third bus cycle latches the Address and the Data of the second byte to be written.
4.
The fourth bus cycle latches the Address and the Data of the third byte to be written.
5.
The fifth bus cycle latches the Address and the Data of the fourth byte to be written.
6.
The sixth bus cycle latches the Address and the Data of the fifth byte to be written.
7.
The seventh bus cycle latches the Address and the Data of the sixth byte to be written.
8.
The eighth bus cycle latches the Address and the Data of the seventh byte to be
written.
9.
The ninth bus cycle latches the Address and the Data of the eighth byte to be written
and starts the Program/Erase Controller.
Double Word Program command
The Double Word Program command is used to write a page of two adjacent words in
parallel. The two words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double Word Program command.
●
The first bus cycle sets up the Double Word Program Command.
●
The second bus cycle latches the Address and the Data of the first word to be written.
●
The third bus cycle latches the Address and the Data of the second word to be written
and starts the Program/Erase Controller.
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations will continue to output
the Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical Program times are given in Table 12: Program, Erase times and endurance cycles.
Note:
It is not necessary to raise VPP/WP to 12V before issuing this command.
29/90
Command Interface
4.2.5
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Quadruple Word Program command
This is used to write a page of four adjacent words (or 8 adjacent bytes), in x16 mode,
simultaneously. The addresses of the four words must differ only in A1 and A0.
12V must be applied to the VPP/Write Protect pin, VPP/WP, prior to issuing a Quadruple Byte
Program command. Care must be taken because applying a 12V voltage to the VPP/WP pin
will temporarily unprotect any protected block.
Five bus write cycles are necessary to issue the command:
4.2.6
●
The first bus cycle sets up the command.
●
The second bus cycle latches the Address and the Data of the first word to be written.
●
The third bus cycle latches the Address and the Data of the second word to be written.
●
The fourth bus cycle latches the Address and the Data of the third word to be written.
●
The fifth bus cycle latches the Address and the Data of the fourth word to be written
and starts the Program/Erase Controller.
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When
the cycle time to the device is long, considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.
When VPP is applied to the VPP/Write Protect pin the memory automatically enters the
Unlock Bypass mode and the Unlock Bypass Program command can be issued
immediately.
4.2.7
Unlock Bypass Program command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the cycle time to the device is long, considerable
time saving can be made by using these commands. Three Bus Write operations are
required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.
The memory offers accelerated program operations through the VPP/Write Protect pin.
When the system asserts VPP on the VPP/Write Protect pin, the memory automatically
enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass
program command sequence. The memory uses the higher voltage on the VPP/Write
Protect pin, to accelerate the Unlock Bypass Program operation.
Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the
memory may be left in an indeterminate state.
30/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
4.2.8
Command Interface
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
4.2.9
Write to Buffer and Program command
The Write to Buffer and Program command makes use of the device’s 32-byte Write Buffer
to speed up programming. 16 words/32 bytes can be loaded into the Write Buffer. Each
Write Buffer has the same A4-A22 addresses.The Write to Buffer and Program command
dramatically reduces system programming time compared to the standard non-buffered
Program command.
When issuing a Write to Buffer and Program command, the VPP/WP pin can be either held
High, VIH or raised to VPPH.
See Table 12 for details on typical Write to Buffer and Program times in both cases.
Five successive steps are required to issue the Write to Buffer and Program command:
1.
The Write to Buffer and Program command starts with two unlock cycles.
2.
The third Bus Write cycle sets up the Write to Buffer and Program command. The setup
code can be addressed to any location within the targeted block.
3.
The fourth Bus Write cycle sets up the number of words to be programmed. Value n is
written to the same block address, where n+1 is the number of words to be
programmed. n+1 must not exceed the size of the Write Buffer or the operation will
abort.
4.
The fifth cycle loads the first address and data to be programmed.
5.
Use n Bus Write cycles to load the address and data for each word into the Write
Buffer. Addresses must lie within the range from the start address+1 to the start
address + n-1. Optimum performance is obtained when the start address corresponds
to a 64 byte boundary. If the start address is not aligned to a 64 byte boundary, the total
programming time is doubled.
All the addresses used in the Write to Buffer and Program operation must lie within the
same page. If an address is written several times during a Write to Buffer and Program
operation, the address/data counter will be decremented at each data load operation and
the data will be programmed to the last word loaded into the Buffer. Invalid address
combinations or failing to follow the correct sequence of Bus Write cycles will abort the Write
to Buffer and Program.
The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a Write to Buffer and Program operation. It is possible to detect Program operation
fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a
portion of memory already programmed. The resulting data will be the logical OR between
the previous value and the current value.
To program the content of the Write Buffer, this command must be followed by a Write to
Buffer and Program Confirm command.
A Write to Buffer and Program Abort and Reset command must be issued to abort the Write
to Buffer and Program operation and reset the device in Read mode.
31/90
Command Interface
M29W640GH, M29W640GL, M29W640GT, M29W640GB
The Write Buffer Programming Sequence can be aborted in the following ways:
●
Load a value that is greater than the page buffer size during the Number of Locations to
Program step.
●
Write to an address in a block different than the one specified during the Write-BufferLoad command.
●
Write an Address/Data pair to a different write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation.
●
Write data other than the Confirm Command after the specified number of data load
cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location
loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence
must be written to reset the device for the next operation. Note that the full 3-cycle Write-toBuffer-Abort Reset command sequence is required when using Write-Buffer-Programming
features in Unlock Bypass mode.
See Appendix E: Flowchart, Figure 29: Write to Buffer and Program flowchart and pseudo
code, for a suggested flowchart on using the Write to Buffer and Program command.
4.2.10
Write to Buffer and Program Confirm command
The Write to Buffer and Program Confirm command is used to confirm a Write to Buffer and
Program command and to program the n+1 words loaded in the Write Buffer by this
command.
4.2.11
Write to Buffer and Program Abort and Reset command
The Write to Buffer and Program Abort and Reset command is used to reset the device after
a Write to Buffer and Program command has been aborted.
4.3
Block Protection commands
4.3.1
Enter Extended Block command
The device has an extra 256 byte block (Extended Block) that can only be accessed using
the Enter Extended Block command. Three Bus write cycles are required to issue the
Extended Block command. Once the command has been issued the device enters
Extended Block mode where all Bus Read or Write operations to the Boot Block addresses
access the Extended Block. The Extended Block (with the same address as the Boot
Blocks) cannot be erased, and can be treated as one-time programmable (OTP) memory. In
Extended Block mode the Boot Blocks are not accessible.
To exit from the Extended Block mode the Exit Extended Block command must be issued.
The Extended Block can be protected, however once protected the protection cannot be
undone.
4.3.2
Exit Extended Block command
The Exit Extended Block command is used to exit from the Extended Block mode and return
the device to Read mode. Four Bus Write operations are required to issue the command.
32/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
4.3.3
Command Interface
Block Protect and Chip Unprotect commands
Groups of blocks can be protected against accidental Program or Erase. The Protection
Groups are shown in Appendix A: Block addresses, Table 28: Top boot block addresses,
M29W640GT and Table 29: Bottom boot block addresses, M29W640GB. The whole chip
can be unprotected to allow the data inside the blocks to be changed.
Block Protect and Chip Unprotect operations are described in : Revision history.
33/90
Command Interface
Table 10.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Commands, 16-bit mode, BYTE = VIH(1)
Command
Length
Bus Write Operations
1st
2nd
3rd
Addr Data Addr Data
Addr
4th
5th
6th
Data Addr Data Addr Data Addr Data
1
X
F0
3
555
AA
2AA
55
X
F0
Auto Select
3
555
AA
2AA
55
555
90
Program
4
555
AA
2AA
55
555
A0
Double Word
Program
3
555
50
PA0
PD0
PA1
PD1
Quadruple Word
Program
5
555
56
PA0
PD0
PA1
PD1
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Write to Buffer and
Program
N+5
555
AA
2AA
55
BA
25
Write to Buffer and
Program Abort and
Reset
3
555
AA
2AA
55
555
F0
Write to Buffer and
Program Confirm
1
BA(5)
29
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
Program/Erase
Suspend
1
X
B0
Program/Erase
Resume
1
X
30
Read CFI Query
1
55
98
Enter Extended Block
3
555
AA
2AA
Exit Extended Block
4
555
AA
2AA
Read/Reset
PA
PD
PA2
PD2
PA3
PD3
BA
N(2)
PA(3)
PD
80
555
AA
2AA
555
80
555
AA
2AA
55
555
88
55
555
90
X
00
WBL
(4)
PD
55
555
10
55
BA
30
1. X Don’t Care, PA Program Address, PD Program Data, BA any address in the Block. All values in the table are in
hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during the
Write to Buffer and Program operation.
3. Each buffer has the same A4-A22 addresses. A0-A3 are used to select a word within the N+1 word page.
4. The 6th cycle has to be issued N time. WBL scans the word inside the page.
5. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
34/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Commands, 8-bit mode, BYTE = VIL
Command
Read/Reset
Length
Table 11.
Command Interface
1
Bus Write Operations(1)
1st
2nd
3rd
4th
5th
6th
7th
8th
9th
Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data
X
F0
3 AAA AA 555 55
X
F0
Auto Select
3 AAA AA 555 55 AAA 90
Program
4 AAA AA 555 55 AAA A0
Double Byte
Program
3 AAA 50 PA0 PD0 PA1 PD1
Quadruple
Byte Program
5 AAA 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Octuple Byte
Program
9 AAA 8B PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7
PA
PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
2
Program
X
A0
PA
PD
Unlock Bypass
2
Reset
X
90
X
00
Write to Buffer N+
AAA AA 555 55
and Program
5
BA
25
BA N(2)
PA
(3)
PD
WBL
(4)
PD
Write to Buffer
and Program
Abort and
Reset
3 AAA AA 555 55 AAA F0
Write to Buffer
and Program
Confirm
1
Chip Erase
6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase
6+ AAA AA 555 55 AAA 80 AAA AA 555 55
BA
(5)
29
Program/Erase
1
Suspend
X
B0
Program/Erase
1
Resume
X
30
AA
98
Read CFI
Query
1
Enter
Extended
Block
3 AAA AA 555 55 AAA 88
Exit Extended
Block
4 AAA AA 555 55 AAA 90
X
BA
30
00
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
2.
The maximum number of cycles in the command sequence is 68. N+1 is the number of bytes to be programmed during the Write to Buffer and
Program operation.
3.
Each buffer has the same A4-A22 addresses. A0-A3 and DQ15A-1 are used to select a byte within the N+1 byte page.
4.
The 6th cycle has to be issued N time. WBL scans the byte inside the page.
5.
BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles.
35/90
Command Interface
Table 12.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Program, Erase times and endurance cycles
Parameter
Symbol
Min
Chip Erase
(4)(5)
Block Erase (64 Kbytes)
tWHWH2
Typ(1)(2)
Max(2)
Unit
80
400(3)
s
0.5
Erase Suspend Latency Time
50
Program (byte or word)
Double Byte
Double Word /Quadruple Byte Program
Quadruple Word / Octuple Byte Program
Single Byte and Word Program(7)
s
tWHWH1
(6)
µs
10
200(3)
µs
10
(3)
µs
10
(3)
200
µs
10
200(3)
µs
200
10
µs
32 Byte/16 Word Program using Write to Buffer and Program
180
µs
32 Byte/16 Word Program using Write to Buffer and Program
(VPP/WP = 12V)
45
µs
Chip Program (byte by byte)
80
400(3)
s
Chip Program (word by word)
40
(3)
200
s
Chip Program (Double Word/Quadruple Byte Program)
20
100(3)
s
10
50(3)
s
4
µs
Chip Program (Quadruple Word/Octuple Byte Program)
Program Suspend Latency Time
Program/Erase Cycles (per Block)
100,000
cycles
20
years
Data Retention
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
4. This time does not include the pre-programming time.
5. Block erase polling cycle time (see Figure 19).
6. Maximum value measured at worst case conditions for both temperature and VCC.
7. Program polling cycle time (see Figure 6, Figure 7 and Figure 19).
36/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 6.
Command Interface
Write Enable controlled Program waveforms (8-bit mode)
3rd cycle
4th cycle
A0-A20/
A–1
Read cycle
Data Polling
tAVAV
tAVAV
555h
PA
PA
tAVWL
tWLAX
tELQV
tWHEH
tELWL
E
tGLQV
tGHWL
G
tWLWH
tWHWL
W
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHWH1
AOh
PD
DQ7 DOUT
tGHQZ
tAXQX
DOUT
tWHDX
AI12779
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous
Program command.
2. PA is address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 5.1: Data Polling Bit (DQ7)).
4.
Addresses differ in x8 mode.
5.
See Table 19: Write ac characteristics and Table 18: Read ac characteristics for details on the timings.
37/90
Command Interface
Figure 7.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Chip Enable controlled Program waveforms (8-bit mode)
3rd cycle
4th cycle
Data Polling
PA
PA
tAVAV
A0-A20/
A–1
555h
tAVEL
tELAX
tEHWH
tWLEL
W
tGHEL
G
tELEH
tEHEL1
E
tDVEH
DQ0-DQ7/
DQ8-DQ15
tWHWH1
AOh
PD
DQ7 DOUT
tEHDX
AI12780
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status register Data Polling bit.
2. PA is address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 5.1: Data Polling Bit (DQ7)).
4.
Addresses differ in x8 mode.
5.
See Table 19: Write ac characteristics and Table 18: Read ac characteristics for details on the timings.
38/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 8.
Command Interface
Chip/Block Erase waveforms (8-bit mode)
tAVAV
A0-A20/
A–1
555h
2AAh
tAVWL
555h
555h
2AAh
555h/BA
(1)
tWLAX
tWHEH
tELWL
E
tGHWL
G
tWLWH
tWHWL
W
tDVWH
DQ0-DQ7/
DQ8-DQ15
AAh
55h
80h
AAh
55h
10h/
30h
tWHDX
AI12781
1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BA and 30h for a Block
Erase command.
2. BA is the block address.
3.
See Table 19: Write ac characteristics and Table 18: Read ac characteristics for details on the timings.
39/90
Status Register
5
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Status Register
Bus Read operations from any address always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block
being erased is accessed.
The bits in the Status Register are summarized in Table 13: Status Register bits.
5.1
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure 9: Data polling flowchart, gives an example of how to use the Data Polling Bit. A Valid
Address is the address being programmed or an address within the block being erased.
Table 20: Reset/Block Temporary Unprotect ac Characteristics gives a description of the
data polling operation and timings.
5.2
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure 10: Data toggle flowchart, gives an example of how to use the Data Toggle Bit.
Figure 20: Toggle/alternative Toggle bit polling ac waveforms (8-bit mode) gives a
description of the data polling operation and timings.
40/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
5.3
Status Register
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
5.4
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Interface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.
5.5
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.
Figure 20: Toggle/alternative Toggle bit polling ac waveforms (8-bit mode) gives a
description of the data polling operation and timings.
5.6
Write to Buffer and Program Abort Bit (DQ1)
The Write to Buffer and Program Abort bit, DQ1, is set to ‘1’ when a Write to Buffer and
Program operation aborts. Otherwise, DQ1 bit is set to ‘0’. The Write to Buffer and Program
Abort and Reset command must be issued to return the device to Read mode (see Write to
Buffer and Program in COMMANDS section).
41/90
Status Register
Table 13.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Status Register bits(1)
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
DQ1
RB
Program
Any Address
DQ7
Toggle
0
–
–
0
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
–
–
0
Write to Buffer and
Program Abort
Any Address
DQ7
Toggle
0
–
–
1
0
Write to Buffer and
Program
Any Address
DQ7
Toggle
0
–
–
0
0
Program Error
Any Address
DQ7
Toggle
1
–
–
–
Hi-Z
Chip Erase
Any Address
0
Toggle
0
1
Toggle
–
0
Block Erase before
timeout
Erasing Block
0
Toggle
0
0
Toggle
–
0
Non-Erasing Block
0
Toggle
0
0
No Toggle
–
0
Erasing Block
0
Toggle
0
1
Toggle
–
0
Non-Erasing Block
0
Toggle
0
1
No Toggle
–
0
Erasing Block
1
No Toggle
0
–
Toggle
–
Hi-Z
–
Hi-Z
Block Erase
Erase Suspend
Non-Erasing Block
Data read as normal
Good Block Address
0
Toggle
1
1
No Toggle
–
Hi-Z
Faulty Block Address
0
Toggle
1
1
Toggle
–
Hi-Z
Erase Error
1. Unspecified data bits should be ignored.
42/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 9.
Status Register
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
=1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
FAIL
PASS
AI90194
43/90
Status Register
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 10. Data toggle flowchart
START
READ DQ6
READ
DQ5 & DQ6
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
TWICE
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI90195B
44/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
6
Maximum rating
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the Numonyx SURE
Program and other relevant quality documents.
Table 14.
Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature Under Bias
–50
125
°C
TSTG
Storage Temperature
–65
150
°C
–0.6
VCC +0.6
V
Voltage(1)(2)
VIO
Input or Output
VCC
Supply Voltage
–0.6
4
V
VID
Identification Voltage
–0.6
13.5
V
Program Voltage
–0.6
13.5
V
VPP(3)
1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.
3. VPP must not remain at 12V for more than a total of 80hrs.
45/90
DC and ac parameters
7
M29W640GH, M29W640GL, M29W640GT, M29W640GB
DC and ac parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 15.
Operating and ac measurement conditions
M29W640GT, M29W640GB,
M29W640GH, M29W640GL
Parameter
Min
Max
VCC Supply Voltage
2.7
3.6
V
Ambient Operating Temperature
–40
85
°C
Load Capacitance (CL)
30
pF
Input Rise and Fall Times
10
Input Pulse Voltages
V
VCC/2
V
Figure 11. AC measurement I/O waveform
VCC
VCC/2
0V
AI05557
Figure 12. AC measurement load circuit
VPP
VCC
VCC
25kΩ
DEVICE
UNDER
TEST
CL
0.1µF
ns
0 to VCC
Input and Output Timing Ref. Voltages
25kΩ
0.1µF
CL includes JIG capacitance
AI05558
46/90
Unit
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 16.
DC and ac parameters
Device capacitance
Symbol
CIN
Parameter
Test Condition
Input Capacitance
COUT
Output Capacitance
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
1. Sampled only, not 100% tested.
Table 17.
Symbol
DC characteristics
Parameter
Max
Unit
0V ≤VIN ≤VCC
±1
µA
Output Leakage Current
0V ≤VOUT ≤VCC
±1
µA
ICC1
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
10
mA
ICC2
Supply Current (Standby)
E = VCC ±0.2V,
RP = VCC ±0.2V
100
µA
Supply Current
(Program/Erase)
VPP/WP =
VIL or VIH
20
mA
ICC3
VPP/WP = VPP
20
mA
ILI(1)
Input Leakage Current
ILO
Test Condition
Program/Erase
Controller active
Min
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7VCC
VCC +0.3
V
VPP
Voltage for VPP/WP
Program Acceleration
VCC = 2.7V ±10%
11.5
12.5
V
IPP
Current for VPP/WP
Program Acceleration
VCC = 2.7V ±10%
15
mA
VOL
Output Low Voltage
IOL = 1.8mA
0.45
V
VOH
Output High Voltage
IOH = –100µA
VID
Identification Voltage
11.5
12.5
V
Program/Erase Lockout
Supply Voltage
1.8
2.3
V
VLKO(2)
VCC –0.4
V
1. The maximum input leakage current is ± 5µA on the VPP/WP pin.
2. Sampled only, not 100% tested.
47/90
DC and ac parameters
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 13. Read Mode ac waveforms (8-bit mode)
tAVAX
A0-A20/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGHQZ
tGLQV
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI05559
1. Data are output on DQ0-DQ7. DQ8-DQ15 are Hi-Z.
Figure 14. Page Read ac waveforms (8-bit mode)
A2-A20
VALID ADDRESS
A–1-A1
VALID
VALID
VALID
VALID
tAVQV
E
tELQV
tEHQX
tEHQZ
G
tGHQX
tGLQV
DQ0-DQ7
tGHQZ
tAVQV1
VALID
DATA
VALID DATA
VALID DATA
VALID DATA
AI12796b
48/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 18.
Symbol
DC and ac parameters
Read ac characteristics
Alt
Parameter
Test Condition
M29W640GT,
M29W640GB,
M29W640GH,
M29W640GL
60
70
90
Unit
tAVAX
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
60
70
90
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
60
70
90
ns
tAVQV1
tPAGE Address Valid to Output Valid (Page)
E = VIL,
G = VIL
Max
25
30
30
ns
tELQX(1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
60
70
90
ns
tGLQX(1)
tOLZ
Output Enable Low to Output Transition
E = VIL
Min
0
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
25
30
30
ns
tEHQZ(1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
25
30
30
ns
tGHQZ
tEHQZ(1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
25
30
30
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or Address
Transition to Output Transition
Min
0
0
0
ns
tELBL
tELBH
tELFL
tELFH
Chip Enable to BYTE Low or High
Max
5
5
5
ns
tBLQZ
tFLQZ
BYTE Low to Output Hi-Z
Max
25
25
25
ns
tBHQV
tFHQV BYTE High to Output Valid
Max
25
30
30
ns
1. Sampled only, not 100% tested.
49/90
DC and ac parameters
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 15. Write ac waveforms, Write Enable Controlled (8-bit mode)
tAVAX
A0-A20/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL1
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI05560
50/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
DC and ac parameters
Figure 16. Write ac waveforms, Chip Enable Controlled (8-bit mode)
tAVAV
A0-A20/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL1
G
tGHEL
tELEH
E
tEHEL1
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI05561
51/90
DC and ac parameters
Table 19.
Symbol
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Write ac characteristics
Alt
M29W640GT, M29W640GB,
M29W640GH, M29W640GL
Parameter
60
70
90
Unit
tAVAX
tWC
Address Valid to Next Address Valid
Min
60
70
90
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
0
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
35
35
35
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
35
35
35
ns
tDVWH
tDVEH
tDS
Input Valid to Write Enable or Chip Enable
High
Min
30
30
30
ns
tWHDX
tEHDX
tDH
Write Enable or Chip Enable High to Input
Transition
Min
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
25
25
25
ns
tWHGL1
tEHGL1
tOEH
Output Enable Hold time
Min
0
0
0
ns
tEHEL1
tCPH
Chip Enable High to Chip Enable Low
Min
25
25
25
ns
tAVWL
tAVEL
tAS
Address Valid to Write Enable or Chip Enable
Low
Min
0
0
0
ns
tWLAX
tELAX
tAH
Write Enable or Chip Enable Low to Address
Transition
Min
45
45
45
ns
tGHWL
tGHWL
Output Enable High to Write Enable Low
Min
0
0
0
ns
tGHEL
tGHEL
Output Enable High to Chip Enable Low
Min
0
0
0
ns
tBUSY
Program/Erase Valid to RB Low
Max
0
0
0
ns
tVCS
VCC High to Chip Enable Low
Min
50
50
50
µs
tWHRL(1)
tEHRL
tVCHEL
tVCHWL
1. Sampled only, not 100% tested.
52/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
DC and ac parameters
Figure 17. Reset/Block Temporary Unprotect ac waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI02931B
Figure 18. Accelerated Program Timing waveforms
VPP
VPP/WP
VIL or VIH
tVHVPP
tVHVPP
AI05563
Table 20.
Reset/Block Temporary Unprotect ac Characteristics
M29W640GT, M29W640GB,
M29W640GH, M29W640GL
Unit
Min
200
ns
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
0
ns
RP Pulse Width
Min
500
ns
Max
50
µs
RP Rise Time to VID
Min
500
ns
VPP Rise and Fall Time
Min
500
ns
Symbol
Alt
tPHWL(1)
tPHEL
tPHGL(1)
tRH
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
tRHWL(1)
tRHEL(1)
tRHGL(1)
tRB
tPLPX
tRP
tPLYH
tPHPHH(1)(2)
tVHVPP(1)
Parameter
tREADY RP Low to Read Mode
tVIDR
1. Sampled only, not 100% tested.
2. For Fast program operations using VPP/WP at 12V.
53/90
DC and ac parameters
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 19. Data Polling ac waveforms
tWHEH
tEHQZ
tGHQZ
tELQV
E
tGLQV
G
tWHGL2
W
tWHWH1 or tWHWH2
DQ7
DATA
DQ6-DQ0
DATA
DQ7=
Valid data
DQ7
DQ6-DQ0=
Output flag
DQ6-DQ0=
Valid data
Hi-Z
Hi-Z
tWHRL
R/B
AI12782
1. DQ7 returns valid data bit when the ongoing Program or Erase command is completed.
2. See Table 21: Data polling and data toggle ac characteristics and Table 18: Read ac characteristics for details on the
timings.
Figure 20. Toggle/alternative Toggle bit polling ac waveforms (8-bit mode)
A0-A20/
A–1
tGHAX
tAXGL
E
tWHGL2
tAVEL
tEHAX
W
tEHEL2
tGHGL2
tGHGL2
G
tGLQV
tWHDX
DQ6/DQ2
Data
Toggle
tELQV
Toggle
Toggle
Stop
toggling
Output
Valid
tWHRL
R/B
AI12783
1. DQ6 stops toggling when the ongoing Program or Erase command is completed. DQ2 stops toggling when the ongoing
Chip Erase or Block Erase command is completed.
2. See Table 21: Data polling and data toggle ac characteristics and Table 18: Read ac characteristics for details on the
timings.
54/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 21.
Symbol
DC and ac parameters
Data polling and data toggle ac characteristics
Alt
M29W640GT, M29W640GB,
M29W640GH, M29W640GL
Parameter
60
70
90
Unit
tAXGL
tASO
Address setup time to Output Enable Low
during Toggle bit polling
Min
10
10
10
ns
tGHAX
tEHAX
tAHT
Address hold time from Output Enable during
Toggle bit polling
Min
10
10
10
ns
Min
10
10
10
ns
Min
20
20
20
ns
tEHEL2
tCEPH Chip Enable High during Toggle bit polling
tWHGL2
tGHGL2
tOEH
Output Hold time during Data and Toggle bit
Polling
55/90
Package mechanical
8
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Package mechanical
Figure 21. TSOP48 –48 lead Plastic Thin Small Outline, 12x20mm, top view package outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-G
1. Drawing is not to scale.
Table 22.
TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
56/90
Max
0.100
0.0039
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
α
3°
0°
5°
0.0315
0°
5°
3°
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Package mechanical
Figure 22. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, top view package outline
1
56
e
B
D1
L1
29
28
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-K
1. Drawing is not to scale.
Table 23.
TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.20
Max
0.047
A1
0.10
0.05
0.15
0.004
0.002
0.006
A2
1.00
0.95
1.05
0.039
0.037
0.041
B
0.22
0.17
0.27
0.009
0.007
0.011
0.10
0.21
0.004
0.008
C
CP
0.10
0.004
D1
14.00
13.90
14.10
0.551
0.547
0.555
E
20.00
19.80
20.20
0.787
0.780
0.795
E1
18.40
18.30
18.50
0.724
0.720
0.728
e
0.50
–
–
0.020
–
–
L
0.60
0.50
0.70
0.024
0.020
0.028
α
3°
0°
5°
3°
0°
5°
57/90
Package mechanical
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 23. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z32
1. Drawing is not to scale.
Table 24.
TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
A1
0.0102
0.900
b
Max
0.0472
0.260
A2
0.350
0.450
0.0354
0.0138
0.0177
D
6.000
5.900
6.100
0.2362
0.2323
0.2402
D1
4.000
–
–
0.1575
–
–
ddd
58/90
Max
0.100
0.0039
E
8.000
7.900
8.100
0.3150
0.3110
0.3189
E1
5.600
–
–
0.2205
–
–
e
0.800
–
–
0.0315
–
–
FD
1.000
–
–
0.0394
–
–
FE
1.200
–
–
0.0472
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Package mechanical
Figure 24. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline
D
D1
FD
FE
E
SD
SE
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
1. Drawing is not to scale.
Table 25.
TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
0.300
A2
0.800
b
0.200
0.350
Max
0.0472
0.0118
0.0079
0.0138
0.0138
0.0197
0.0315
0.350
0.500
D
10.000
9.900
10.100
0.3937
0.3898
0.3976
D1
7.000
–
–
0.2756
–
–
ddd
0.100
0.0039
e
1.000
–
–
0.0394
–
–
E
13.000
12.900
13.100
0.5118
0.5079
0.5157
E1
7.000
–
–
0.2756
–
–
FD
1.500
–
–
0.0591
–
–
FE
3.000
–
–
0.1181
–
–
SD
0.500
–
–
0.0197
–
–
SE
0.500
–
–
0.0197
–
–
59/90
Part numbering
9
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Part numbering
Table 26.
Ordering information scheme
Example:
M29W640GT
70
N
6
F
Device Type
M29
Operating Voltage
W = VCC = 2.7 to 3.6 V
Device Function
640G = 64 Mbit (x8/x16), Boot Block, Uniform or Boot
Block
Array Matrix
T = Top Boot
B = Bottom Boot
H = Last Block protected by VPP/WP
L = First Block protected by VPP/WP
Speed
60 = 60 ns
70 = 70 ns
90 = 90 ns
Package
NA = TSOP48: 12 x 20mm
NB = TSOP56: 14 x 20mm(1)
ZA= TFBGA48: 6 x 8mm - 0.8mm pitch
ZF = TBGA64: 10x13mm -1mm pitch(1)
Temperature Range
6 = −40 to 85 °C
Option
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
1. Packages only available upon request.
Note:
This product is also available with the Extended Block factory locked. For further details and
ordering information contact your nearest Numonyx sales office.
Devices are shipped from the factory with the memory content bits erased to 1. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact your nearest Numonyx Sales Office.
60/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Appendix A
Table 27.
Block addresses
Block addresses
M29W640GH and M29W640GL block addresses
Block Kbytes/Kwords Protection Block Group
(x8)
(x16)
0
64/32
Protection Group
000000h–00FFFFh(1) 000000h–007FFFh(1)
1
64/32
Protection Group
010000h–01FFFFh(1)
(1)
008000h–00FFFFh
010000h–017FFFh(1)
2
64/32
Protection Group
020000h–02FFFFh
3
64/32
Protection Group
030000h–03FFFFh(1) 018000h–01FFFFh(1)
4
64/32
5
64/32
040000h–04FFFFh
020000h–027FFFh
050000h–05FFFFh
028000h–02FFFFh
Protection Group
6
64/32
060000h–06FFFFh
030000h–037FFFh
7
64/32
070000h–07FFFFh
038000h–03FFFFh
8
64/32
080000h–08FFFFh
040000h–047FFFh
9
64/32
090000h–09FFFFh
048000h–04FFFFh
Protection Group
10
64/32
0A0000h–0AFFFFh
050000h–057FFFh
11
64/32
0B0000h–0BFFFFh
058000h–05FFFFh
12
64/32
0C0000h–0CFFFFh
060000h–067FFFh
13
64/32
0D0000h–0DFFFFh
068000h–06FFFFh
Protection Group
14
64/32
0E0000h–0EFFFFh
070000h–077FFFh
15
64/32
0F0000h–0FFFFFh
078000h–07FFFFh
16
64/32
100000h–10FFFFh
080000h–087FFFh
17
64/32
110000h–11FFFFh
088000h–08FFFFh
Protection Group
18
64/32
120000h–12FFFFh
090000h–097FFFh
19
64/32
130000h–13FFFFh
098000h–09FFFFh
20
64/32
140000h–14FFFFh
0A0000h–0A7FFFh
21
64/32
150000h–15FFFFh
0A8000h–0AFFFFh
Protection Group
22
64/32
160000h–16FFFFh
0B0000h–0B7FFFh
23
64/32
170000h–17FFFFh
0B8000h–0BFFFFh
24
64/32
180000h–18FFFFh
0C0000h–0C7FFFh
25
64/32
190000h–19FFFFh
0C8000h–0CFFFFh
Protection Group
26
64/32
1A0000h–1AFFFFh
0D0000h–0D7FFFh
27
64/32
1B0000h–1BFFFFh
0D8000h–0DFFFFh
28
64/32
1C0000h–1CFFFFh
0E0000h–0E7FFFh
29
64/32
1D0000h–1DFFFFh
0E8000h–0EFFFFh
Protection Group
30
64/32
1E0000h–1EFFFFh
0F0000h–0F7FFFh
31
64/32
1F0000h–1FFFFFh
0F8000h–0FFFFFh
61/90
Block addresses
Table 27.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
M29W640GH and M29W640GL block addresses (continued)
Block Kbytes/Kwords Protection Block Group
32
64/32
33
64/32
(x8)
(x16)
200000h–20FFFFh
100000h–107FFFh
210000h–21FFFFh
108000h–10FFFFh
Protection Group
34
64/32
220000h–22FFFFh
110000h–117FFFh
35
64/32
230000h–23FFFFh
118000h–11FFFFh
36
64/32
240000h–24FFFFh
120000h–127FFFh
37
64/32
250000h–25FFFFh
128000h–12FFFFh
Protection Group
38
64/32
260000h–26FFFFh
130000h–137FFFh
39
64/32
270000h–27FFFFh
138000h–13FFFFh
40
64/32
280000h–28FFFFh
140000h–147FFFh
41
64/32
290000h–29FFFFh
148000h–14FFFFh
Protection Group
42
64/32
2A0000h–2AFFFFh
150000h–157FFFh
43
64/32
2B0000h–2BFFFFh
158000h–15FFFFh
44
64/32
2C0000h–2CFFFFh
160000h–167FFFh
45
64/32
2D0000h–2DFFFFh
168000h–16FFFFh
Protection Group
46
64/32
2E0000h–2EFFFFh
170000h–177FFFh
47
64/32
2F0000h–2FFFFFh
178000h–17FFFFh
48
64/32
300000h–30FFFFh
180000h–187FFFh
49
64/32
310000h–31FFFFh
188000h–18FFFFh
Protection Group
50
64/32
320000h–32FFFFh
190000h–197FFFh
51
64/32
330000h–33FFFFh
198000h–19FFFFh
52
64/32
340000h–34FFFFh
1A0000h–1A7FFFh
53
64/32
350000h–35FFFFh
1A8000h–1AFFFFh
Protection Group
54
64/32
360000h–36FFFFh
1B0000h–1B7FFFh
55
64/32
370000h–37FFFFh
1B8000h–1BFFFFh
56
64/32
380000h–38FFFFh
1C0000h–1C7FFFh
57
64/32
390000h–39FFFFh
1C8000h–1CFFFFh
Protection Group
58
64/32
3A0000h–3AFFFFh
1D0000h–1D7FFFh
59
64/32
3B0000h–3BFFFFh
1D8000h–1DFFFFh
60
64/32
3C0000h–3CFFFFh
1E0000h–1E7FFFh
61
64/32
3D0000h–3DFFFFh
1E8000h–1EFFFFh
Protection Group
62/90
62
64/32
3E0000h–3EFFFFh
1F0000h–1F7FFFh
63
64/32
3F0000h–3FFFFFh
1F8000h–1FFFFFh
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 27.
Block addresses
M29W640GH and M29W640GL block addresses (continued)
Block Kbytes/Kwords Protection Block Group
64
64/32
65
64/32
(x8)
(x16)
400000h–40FFFFh
200000h–207FFFh
410000h–41FFFFh
208000h–20FFFFh
Protection Group
66
64/32
420000h–42FFFFh
210000h–217FFFh
67
64/32
430000h–43FFFFh
218000h–21FFFFh
68
64/32
440000h–44FFFFh
220000h–227FFFh
69
64/32
450000h–45FFFFh
228000h–22FFFFh
Protection Group
70
64/32
460000h–46FFFFh
230000h–237FFFh
71
64/32
470000h–47FFFFh
238000h–23FFFFh
72
64/32
480000h–48FFFFh
240000h–247FFFh
73
64/32
490000h–49FFFFh
248000h–24FFFFh
Protection Group
74
64/32
4A0000h–4AFFFFh
250000h–257FFFh
75
64/32
4B0000h–4BFFFFh
258000h–25FFFFh
76
64/32
4C0000h–4CFFFFh
260000h–267FFFh
77
64/32
4D0000h–4DFFFFh
268000h–26FFFFh
Protection Group
78
64/32
4E0000h–4EFFFFh
270000h–277FFFh
79
64/32
4F0000h–4FFFFFh
278000h–27FFFFh
80
64/32
500000h–50FFFFh
280000h–287FFFh
81
64/32
510000h–51FFFFh
288000h–28FFFFh
Protection Group
82
64/32
520000h–52FFFFh
290000h–297FFFh
83
64/32
530000h–53FFFFh
298000h–29FFFFh
84
64/32
540000h–54FFFFh
2A0000h–2A7FFFh
85
64/32
550000h–55FFFFh
2A8000h–2AFFFFh
Protection Group
86
64/32
560000h–56FFFFh
2B0000h–2B7FFFh
87
64/32
570000h–57FFFFh
2B8000h–2BFFFFh
88
64/32
580000h–58FFFFh
2C0000h–2C7FFFh
89
64/32
590000h–59FFFFh
2C8000h–2CFFFFh
Protection Group
90
64/32
5A0000h–5AFFFFh
2D0000h–2D7FFFh
91
64/32
5B0000h–5BFFFFh
2D8000h–2DFFFFh
92
64/32
5C0000h–5CFFFFh
2E0000h–2E7FFFh
93
64/32
5D0000h–5DFFFFh
2E8000h–2EFFFFh
Protection Group
94
64/32
5E0000h–5EFFFFh
2F0000h–2F7FFFh
95
64/32
5F0000h–5FFFFFh
2F8000h–2FFFFFh
63/90
Block addresses
Table 27.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
M29W640GH and M29W640GL block addresses (continued)
Block Kbytes/Kwords Protection Block Group
96
64/32
97
64/32
(x8)
(x16)
600000h–60FFFFh
300000h–307FFFh
610000h–61FFFFh
308000h–30FFFFh
Protection Group
98
64/32
620000h–62FFFFh
310000h–317FFFh
99
64/32
630000h–63FFFFh
318000h–31FFFFh
100
64/32
640000h–64FFFFh
320000h–327FFFh
101
64/32
650000h–65FFFFh
328000h–32FFFFh
Protection Group
102
64/32
660000h–66FFFFh
330000h–337FFFh
103
64/32
670000h–67FFFFh
338000h–33FFFFh
104
64/32
680000h–68FFFFh
340000h–347FFFh
105
64/32
690000h–69FFFFh
348000h–34FFFFh
Protection Group
106
64/32
6A0000h–6AFFFFh
350000h–357FFFh
107
64/32
6B0000h–6BFFFFh
358000h–35FFFFh
108
64/32
6C0000h–6CFFFFh
360000h–367FFFh
109
64/32
6D0000h–6DFFFFh
368000h–36FFFFh
Protection Group
110
64/32
6E0000h–6EFFFFh
370000h–377FFFh
111
64/32
6F0000h–6FFFFFh
378000h–37FFFFh
112
64/32
700000h–70FFFFh
380000h–387FFFh
113
64/32
710000h–71FFFFh
388000h–38FFFFh
Protection Group
114
64/32
720000h–72FFFFh
390000h–397FFFh
115
64/32
730000h–73FFFFh
398000h–39FFFFh
116
64/32
740000h–74FFFFh
3A0000h–3A7FFFh
117
64/32
750000h–75FFFFh
3A8000h–3AFFFFh
Protection Group
118
64/32
760000h–76FFFFh
3B0000h–3B7FFFh
119
64/32
770000h–77FFFFh
3B8000h–3BFFFFh
120
64/32
780000h–78FFFFh
3C0000h–3C7FFFh
121
64/32
790000h–79FFFFh
3C8000h–3CFFFFh
Protection Group
122
64/32
7A0000h–7AFFFFh
3D0000h–3D7FFFh
123
64/32
7B0000h–7BFFFFh
3D8000h–3DFFFFh
124
64/32
Protection Group
7C0000h–7CFFFFh
3E0000h–3E7FFFh
125
64/32
Protection Group
7D0000h–7DFFFFh
3E8000h–3EFFFFh
126
64/32
Protection Group
7E0000h–7EFFFFh
3F0000h–3F7FFFh
127
64/32
Protection Group
7F0000h–7FFFFFh
3F8000h–3FFFFFh
1. Used as the Extended Block Addresses in Extended Block mode.
64/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 28.
Block addresses
Top boot block addresses, M29W640GT
Block Kbytes/Kwords Protection Block Group
0
64/32
1
64/32
Protection Group
(x8)
(x16)
000000h–00FFFFh(1)
000000h–007FFFh(1)
010000h–01FFFFh(1)
008000h–00FFFFh(1)
2
64/32
020000h–02FFFFh(1)
010000h–017FFFh(1)
3
64/32
030000h–03FFFFh(1)
018000h–01FFFFh(1)
4
64/32
040000h–04FFFFh
020000h–027FFFh
5
64/32
050000h–05FFFFh
028000h–02FFFFh
Protection Group
6
64/32
060000h–06FFFFh
030000h–037FFFh
7
64/32
070000h–07FFFFh
038000h–03FFFFh
8
64/32
080000h–08FFFFh
040000h–047FFFh
9
64/32
090000h–09FFFFh
048000h–04FFFFh
Protection Group
10
64/32
0A0000h–0AFFFFh
050000h–057FFFh
11
64/32
0B0000h–0BFFFFh
058000h–05FFFFh
12
64/32
0C0000h–0CFFFFh
060000h–067FFFh
13
64/32
0D0000h–0DFFFFh
068000h–06FFFFh
Protection Group
14
64/32
0E0000h–0EFFFFh
070000h–077FFFh
15
64/32
0F0000h–0FFFFFh
078000h–07FFFFh
16
64/32
100000h–10FFFFh
080000h–087FFFh
17
64/32
110000h–11FFFFh
088000h–08FFFFh
Protection Group
18
64/32
120000h–12FFFFh
090000h–097FFFh
19
64/32
130000h–13FFFFh
098000h–09FFFFh
20
64/32
140000h–14FFFFh
0A0000h–0A7FFFh
21
64/32
150000h–15FFFFh
0A8000h–0AFFFFh
Protection Group
22
64/32
160000h–16FFFFh
0B0000h–0B7FFFh
23
64/32
170000h–17FFFFh
0B8000h–0BFFFFh
24
64/32
180000h–18FFFFh
0C0000h–0C7FFFh
25
64/32
190000h–19FFFFh
0C8000h–0CFFFFh
Protection Group
26
64/32
1A0000h–1AFFFFh
0D0000h–0D7FFFh
27
64/32
1B0000h–1BFFFFh
0D8000h–0DFFFFh
28
64/32
1C0000h–1CFFFFh
0E0000h–0E7FFFh
29
64/32
1D0000h–1DFFFFh
0E8000h–0EFFFFh
Protection Group
30
64/32
1E0000h–1EFFFFh
0F0000h–0F7FFFh
31
64/32
1F0000h–1FFFFFh
0F8000h–0FFFFFh
65/90
Block addresses
Table 28.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Top boot block addresses, M29W640GT (continued)
Block Kbytes/Kwords Protection Block Group
32
64/32
33
64/32
(x8)
(x16)
200000h–20FFFFh
100000h–107FFFh
210000h–21FFFFh
108000h–10FFFFh
Protection Group
34
64/32
220000h–22FFFFh
110000h–117FFFh
35
64/32
230000h–23FFFFh
118000h–11FFFFh
36
64/32
240000h–24FFFFh
120000h–127FFFh
37
64/32
250000h–25FFFFh
128000h–12FFFFh
Protection Group
38
64/32
260000h–26FFFFh
130000h–137FFFh
39
64/32
270000h–27FFFFh
138000h–13FFFFh
40
64/32
280000h–28FFFFh
140000h–147FFFh
41
64/32
290000h–29FFFFh
148000h–14FFFFh
Protection Group
42
64/32
2A0000h–2AFFFFh
150000h–157FFFh
43
64/32
2B0000h–2BFFFFh
158000h–15FFFFh
44
64/32
2C0000h–2CFFFFh
160000h–167FFFh
45
64/32
2D0000h–2DFFFFh
168000h–16FFFFh
Protection Group
46
64/32
2E0000h–2EFFFFh
170000h–177FFFh
47
64/32
2F0000h–2FFFFFh
178000h–17FFFFh
48
64/32
300000h–30FFFFh
180000h–187FFFh
49
64/32
310000h–31FFFFh
188000h–18FFFFh
Protection Group
50
64/32
320000h–32FFFFh
190000h–197FFFh
51
64/32
330000h–33FFFFh
198000h–19FFFFh
52
64/32
340000h–34FFFFh
1A0000h–1A7FFFh
53
64/32
350000h–35FFFFh
1A8000h–1AFFFFh
Protection Group
54
64/32
360000h–36FFFFh
1B0000h–1B7FFFh
55
64/32
370000h–37FFFFh
1B8000h–1BFFFFh
56
64/32
380000h–38FFFFh
1C0000h–1C7FFFh
57
64/32
390000h–39FFFFh
1C8000h–1CFFFFh
Protection Group
58
64/32
3A0000h–3AFFFFh
1D0000h–1D7FFFh
59
64/32
3B0000h–3BFFFFh
1D8000h–1DFFFFh
60
64/32
3C0000h–3CFFFFh
1E0000h–1E7FFFh
61
64/32
3D0000h–3DFFFFh
1E8000h–1EFFFFh
Protection Group
66/90
62
64/32
3E0000h–3EFFFFh
1F0000h–1F7FFFh
63
64/32
3F0000h–3FFFFFh
1F8000h–1FFFFFh
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 28.
Block addresses
Top boot block addresses, M29W640GT (continued)
Block Kbytes/Kwords Protection Block Group
64
64/32
65
64/32
(x8)
(x16)
400000h–40FFFFh
200000h–207FFFh
410000h–41FFFFh
208000h–20FFFFh
Protection Group
66
64/32
420000h–42FFFFh
210000h–217FFFh
67
64/32
430000h–43FFFFh
218000h–21FFFFh
68
64/32
440000h–44FFFFh
220000h–227FFFh
69
64/32
450000h–45FFFFh
228000h–22FFFFh
Protection Group
70
64/32
460000h–46FFFFh
230000h–237FFFh
71
64/32
470000h–47FFFFh
238000h–23FFFFh
72
64/32
480000h–48FFFFh
240000h–247FFFh
73
64/32
490000h–49FFFFh
248000h–24FFFFh
Protection Group
74
64/32
4A0000h–4AFFFFh
250000h–257FFFh
75
64/32
4B0000h–4BFFFFh
258000h–25FFFFh
76
64/32
4C0000h–4CFFFFh
260000h–267FFFh
77
64/32
4D0000h–4DFFFFh
268000h–26FFFFh
Protection Group
78
64/32
4E0000h–4EFFFFh
270000h–277FFFh
79
64/32
4F0000h–4FFFFFh
278000h–27FFFFh
80
64/32
500000h–50FFFFh
280000h–287FFFh
81
64/32
510000h–51FFFFh
288000h–28FFFFh
Protection Group
82
64/32
520000h–52FFFFh
290000h–297FFFh
83
64/32
530000h–53FFFFh
298000h–29FFFFh
84
64/32
540000h–54FFFFh
2A0000h–2A7FFFh
85
64/32
550000h–55FFFFh
2A8000h–2AFFFFh
Protection Group
86
64/32
560000h–56FFFFh
2B0000h–2B7FFFh
87
64/32
570000h–57FFFFh
2B8000h–2BFFFFh
88
64/32
580000h–58FFFFh
2C0000h–2C7FFFh
89
64/32
590000h–59FFFFh
2C8000h–2CFFFFh
Protection Group
90
64/32
5A0000h–5AFFFFh
2D0000h–2D7FFFh
91
64/32
5B0000h–5BFFFFh
2D8000h–2DFFFFh
92
64/32
5C0000h–5CFFFFh
2E0000h–2E7FFFh
93
64/32
5D0000h–5DFFFFh
2E8000h–2EFFFFh
Protection Group
94
64/32
5E0000h–5EFFFFh
2F0000h–2F7FFFh
95
64/32
5F0000h–5FFFFFh
2F8000h–2FFFFFh
67/90
Block addresses
Table 28.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Top boot block addresses, M29W640GT (continued)
Block Kbytes/Kwords Protection Block Group
96
64/32
97
64/32
(x8)
(x16)
600000h–60FFFFh
300000h–307FFFh
610000h–61FFFFh
308000h–30FFFFh
Protection Group
98
64/32
620000h–62FFFFh
310000h–317FFFh
99
64/32
630000h–63FFFFh
318000h–31FFFFh
100
64/32
640000h–64FFFFh
320000h–327FFFh
101
64/32
650000h–65FFFFh
328000h–32FFFFh
Protection Group
102
64/32
660000h–66FFFFh
330000h–337FFFh
103
64/32
670000h–67FFFFh
338000h–33FFFFh
104
64/32
680000h–68FFFFh
340000h–347FFFh
105
64/32
690000h–69FFFFh
348000h–34FFFFh
Protection Group
106
64/32
6A0000h–6AFFFFh
350000h–357FFFh
107
64/32
6B0000h–6BFFFFh
358000h–35FFFFh
108
64/32
6C0000h–6CFFFFh
360000h–367FFFh
109
64/32
6D0000h–6DFFFFh
368000h–36FFFFh
Protection Group
110
64/32
6E0000h–6EFFFFh
370000h–377FFFh
111
64/32
6F0000h–6FFFFFh
378000h–37FFFFh
112
64/32
700000h–70FFFFh
380000h–387FFFh
113
64/32
710000h–71FFFFh
388000h–38FFFFh
Protection Group
114
64/32
720000h–72FFFFh
390000h–397FFFh
115
64/32
730000h–73FFFFh
398000h–39FFFFh
116
64/32
740000h–74FFFFh
3A0000h–3A7FFFh
117
64/32
750000h–75FFFFh
3A8000h–3AFFFFh
Protection Group
118
64/32
760000h–76FFFFh
3B0000h–3B7FFFh
119
64/32
770000h–77FFFFh
3B8000h–3BFFFFh
120
64/32
780000h–78FFFFh
3C0000h–3C7FFFh
121
64/32
790000h–79FFFFh
3C8000h–3CFFFFh
Protection Group
68/90
122
64/32
7A0000h–7AFFFFh
3D0000h–3D7FFFh
123
64/32
7B0000h–7BFFFFh
3D8000h–3DFFFFh
124
64/32
7C0000h–7CFFFFh
3E0000h–3E7FFFh
125
64/32
7D0000h–7DFFFFh
3E8000h–3EFFFFh
126
64/32
7E0000h–7EFFFFh
3F0000h–3F7FFFh
127
8/4
Protection Group
7F0000h–7F1FFFh
3F8000h–3F8FFFh
128
8/4
Protection Group
7F2000h–7F3FFFh
3F9000h–3F9FFFh
129
8/4
Protection Group
7F4000h–7F5FFFh
3FA000h–3FAFFFh
130
8/4
Protection Group
7F6000h–7F7FFFh
3FB000h–3FBFFFh
Protection Group
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 28.
Block addresses
Top boot block addresses, M29W640GT (continued)
Block Kbytes/Kwords Protection Block Group
(x8)
(x16)
131
8/4
Protection Group
7F8000h–7F9FFFh
3FC000h–3FCFFFh
132
8/4
Protection Group
7FA000h–7FBFFFh
3FD000h–3FDFFFh
133
8/4
Protection Group
7FC000h–7FDFFFh
3FE000h–3FEFFFh
134
8/4
Protection Group
7FE000h–7FFFFFh
3FF000h–3FFFFFh
1. Used as the Extended Block Addresses in Extended Block mode.
Table 29.
Bottom boot block addresses, M29W640GB
Block Kbytes/Kwords
Protection Block Group
(x8)
(x16)
0
8/4
Protection Group
000000h-001FFFh(1) 000000h–000FFFh(1)
1
8/4
Protection Group
002000h-003FFFh(1) 001000h–001FFFh(1)
2
8/4
Protection Group
004000h-005FFFh(1) 002000h–002FFFh(1)
3
8/4
Protection Group
006000h-007FFFh(1) 003000h–003FFFh(1)
4
8/4
Protection Group
008000h-009FFFh
004000h–004FFFh
5
8/4
Protection Group
00A000h-00BFFFh
005000h–005FFFh
6
8/4
Protection Group
00C000h-00DFFFh
006000h–006FFFh
7
8/4
Protection Group
00E000h-00FFFFh
007000h–007FFFh
8
64/32
010000h-01FFFFh
008000h–00FFFFh
9
64/32
020000h-02FFFFh
010000h–017FFFh
10
64/32
030000h-03FFFFh
018000h–01FFFFh
11
64/32
040000h-04FFFFh
020000h–027FFFh
12
64/32
050000h-05FFFFh
028000h–02FFFFh
Protection Group
Protection Group
13
64/32
060000h-06FFFFh
030000h–037FFFh
14
64/32
070000h-07FFFFh
038000h–03FFFFh
15
64/32
080000h-08FFFFh
040000h–047FFFh
16
64/32
090000h-09FFFFh
048000h–04FFFFh
Protection Group
17
64/32
0A0000h-0AFFFFh
050000h–057FFFh
18
64/32
0B0000h-0BFFFFh
058000h–05FFFFh
19
64/32
0C0000h-0CFFFFh
060000h–067FFFh
20
64/32
0D0000h-0DFFFFh
068000h–06FFFFh
Protection Group
21
64/32
0E0000h-0EFFFFh
070000h–077FFFh
22
64/32
0F0000h-0FFFFFh
078000h–07FFFFh
23
64/32
100000h-10FFFFh
080000h–087FFFh
24
64/32
110000h-11FFFFh
088000h–08FFFFh
Protection Group
25
64/32
120000h-12FFFFh
090000h–097FFFh
26
64/32
130000h-13FFFFh
098000h–09FFFFh
69/90
Block addresses
Table 29.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Bottom boot block addresses, M29W640GB (continued)
Block Kbytes/Kwords
27
64/32
28
64/32
Protection Block Group
(x8)
(x16)
140000h-14FFFFh
0A0000h–0A7FFFh
150000h-15FFFFh
0A8000h–0AFFFFh
Protection Group
29
64/32
160000h-16FFFFh
0B0000h–0B7FFFh
30
64/32
170000h-17FFFFh
0B8000h–0BFFFFh
31
64/32
180000h-18FFFFh
0C0000h–0C7FFFh
32
64/32
190000h-19FFFFh
0C8000h–0CFFFFh
Protection Group
33
64/32
1A0000h-1AFFFFh
0D0000h–0D7FFFh
34
64/32
1B0000h-1BFFFFh
0D8000h–0DFFFFh
35
64/32
1C0000h-1CFFFFh
0E0000h–0E7FFFh
36
64/32
1D0000h-1DFFFFh
0E8000h–0EFFFFh
Protection Group
37
64/32
1E0000h-1EFFFFh
0F0000h–0F7FFFh
38
64/32
1F0000h-1FFFFFh
0F8000h–0FFFFFh
39
64/32
200000h-20FFFFh
100000h–107FFFh
40
64/32
210000h-21FFFFh
108000h–10FFFFh
Protection Group
41
64/32
220000h-22FFFFh
110000h–117FFFh
42
64/32
230000h-23FFFFh
118000h–11FFFFh
43
64/32
240000h-24FFFFh
120000h–127FFFh
44
64/32
250000h-25FFFFh
128000h–12FFFFh
Protection Group
45
64/32
260000h-26FFFFh
130000h–137FFFh
46
64/32
270000h-27FFFFh
138000h–13FFFFh
47
64/32
280000h-28FFFFh
140000h–147FFFh
48
64/32
290000h-29FFFFh
148000h–14FFFFh
Protection Group
49
64/32
2A0000h-2AFFFFh
150000h–157FFFh
50
64/32
2B0000h-2BFFFFh
158000h–15FFFFh
51
64/32
2C0000h-2CFFFFh
160000h–167FFFh
52
64/32
2D0000h-2DFFFFh
168000h–16FFFFh
Protection Group
53
64/32
2E0000h-2EFFFFh
170000h–177FFFh
54
64/32
2F0000h-2FFFFFh
178000h–17FFFFh
55
64/32
300000h-30FFFFh
180000h–187FFFh
56
64/32
310000h-31FFFFh
188000h–18FFFFh
Protection Group
70/90
57
64/32
320000h-32FFFFh
190000h–197FFFh
58
64/32
330000h-33FFFFh
198000h–19FFFFh
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 29.
Block addresses
Bottom boot block addresses, M29W640GB (continued)
Block Kbytes/Kwords
59
64/32
60
64/32
Protection Block Group
(x8)
(x16)
340000h-34FFFFh
1A0000h–1A7FFFh
350000h-35FFFFh
1A8000h–1AFFFFh
Protection Group
61
64/32
360000h-36FFFFh
1B0000h–1B7FFFh
62
64/32
370000h-37FFFFh
1B8000h–1BFFFFh
63
64/32
380000h-38FFFFh
1C0000h–1C7FFFh
64
64/32
390000h-39FFFFh
1C8000h–1CFFFFh
Protection Group
65
64/32
3A0000h-3AFFFFh
1D0000h–1D7FFFh
66
64/32
3B0000h-3BFFFFh
1D8000h–1DFFFFh
67
64/32
3C0000h-3CFFFFh
1E0000h–1E7FFFh
68
64/32
3D0000h-3DFFFFh
1E8000h–1EFFFFh
Protection Group
69
64/32
3E0000h-3EFFFFh
1F0000h–1F7FFFh
70
64/32
3F0000h-3FFFFFh
1F8000h–1FFFFFh
71
64/32
400000h-40FFFFh
200000h–207FFFh
72
64/32
410000h-41FFFFh
208000h–20FFFFh
Protection Group
73
64/32
420000h-42FFFFh
210000h–217FFFh
74
64/32
430000h-43FFFFh
218000h–21FFFFh
75
64/32
440000h-44FFFFh
220000h–227FFFh
76
64/32
450000h-45FFFFh
228000h–22FFFFh
Protection Group
77
64/32
460000h-46FFFFh
230000h–237FFFh
78
64/32
470000h-47FFFFh
238000h–23FFFFh
79
64/32
480000h-48FFFFh
240000h–247FFFh
80
64/32
490000h-49FFFFh
248000h–24FFFFh
Protection Group
81
64/32
4A0000h-4AFFFFh
250000h–257FFFh
82
64/32
4B0000h-4BFFFFh
258000h–25FFFFh
83
64/32
4C0000h-4CFFFFh
260000h–267FFFh
84
64/32
4D0000h-4DFFFFh
268000h–26FFFFh
Protection Group
85
64/32
4E0000h-4EFFFFh
270000h–277FFFh
86
64/32
4F0000h-4FFFFFh
278000h–27FFFFh
87
64/32
500000h-50FFFFh
280000h–287FFFh
88
64/32
510000h-51FFFFh
288000h–28FFFFh
Protection Group
89
64/32
520000h-52FFFFh
290000h–297FFFh
90
64/32
530000h-53FFFFh
298000h–29FFFFh
71/90
Block addresses
Table 29.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Bottom boot block addresses, M29W640GB (continued)
Block Kbytes/Kwords
91
64/32
92
64/32
Protection Block Group
(x8)
(x16)
540000h-54FFFFh
2A0000h–2A7FFFh
550000h-55FFFFh
2A8000h–2AFFFFh
Protection Group
93
64/32
560000h-56FFFFh
2B0000h–2B7FFFh
94
64/32
570000h-57FFFFh
2B8000h–2BFFFFh
95
64/32
580000h-58FFFFh
2C0000h–2C7FFFh
96
64/32
590000h-59FFFFh
2C8000h–2CFFFFh
Protection Group
97
64/32
5A0000h-5AFFFFh
2D0000h–2D7FFFh
98
64/32
5B0000h-5BFFFFh
2D8000h–2DFFFFh
99
64/32
5C0000h-5CFFFFh
2E0000h–2E7FFFh
100
64/32
5D0000h-5DFFFFh
2E8000h–2EFFFFh
Protection Group
101
64/32
5E0000h-5EFFFFh
2F0000h–2F7FFFh
102
64/32
5F0000h-5FFFFFh
2F8000h–2FFFFFh
103
64/32
600000h-60FFFFh
300000h–307FFFh
104
64/32
610000h-61FFFFh
308000h–30FFFFh
Protection Group
105
64/32
620000h-62FFFFh
310000h–317FFFh
106
64/32
630000h-63FFFFh
318000h–31FFFFh
107
64/32
640000h-64FFFFh
320000h–327FFFh
108
64/32
650000h-65FFFFh
328000h–32FFFFh
Protection Group
109
64/32
660000h-66FFFFh
330000h–337FFFh
110
64/32
670000h-67FFFFh
338000h–33FFFFh
111
64/32
680000h-68FFFFh
340000h–347FFFh
112
64/32
690000h-69FFFFh
348000h–34FFFFh
Protection Group
113
64/32
6A0000h-6AFFFFh
350000h–357FFFh
114
64/32
6B0000h-6BFFFFh
358000h–35FFFFh
115
64/32
6C0000h-6CFFFFh
360000h–367FFFh
116
64/32
6D0000h-6DFFFFh
368000h–36FFFFh
Protection Group
117
64/32
6E0000h-6EFFFFh
370000h–377FFFh
118
64/32
6F0000h-6FFFFFh
378000h–37FFFFh
119
64/32
700000h-70FFFFh
380000h–387FFFh
120
64/32
710000h-71FFFFh
388000h–38FFFFh
Protection Group
72/90
121
64/32
720000h-72FFFFh
390000h–397FFFh
122
64/32
730000h-73FFFFh
398000h–39FFFFh
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 29.
Block addresses
Bottom boot block addresses, M29W640GB (continued)
Block Kbytes/Kwords
123
64/32
124
64/32
Protection Block Group
(x8)
(x16)
740000h-74FFFFh
3A0000h–3A7FFFh
750000h-75FFFFh
3A8000h–3AFFFFh
Protection Group
125
64/32
760000h-76FFFFh
3B0000h–3B7FFFh
126
64/32
770000h-77FFFFh
3B8000h–3BFFFFh
127
64/32
780000h-78FFFFh
3C0000h–3C7FFFh
128
64/32
790000h-79FFFFh
3C8000h–3CFFFFh
Protection Group
129
64/32
7A0000h-7AFFFFh
3D0000h–3D7FFFh
130
64/32
7B0000h-7BFFFFh
3D8000h–3DFFFFh
131
64/32
7C0000h-7CFFFFh
3E0000h–3E7FFFh
132
64/32
7D0000h-7DFFFFh
3E8000h–3EFFFFh
Protection Group
133
64/32
7E0000h-7EFFFFh
3F0000h–3F7FFFh
134
64/32
7F0000h-7FFFFFh
3F8000h–3FFFFFh
1. Used as the Extended Block Addresses in Extended Block mode.
73/90
Common Flash Interface (CFI)
Appendix B
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query Command is issued the device enters CFI Query mode and the data
structure is read from the memory. Tables 30, 31, 32, 33, 34, and 35, show the addresses
used to retrieve the data. The CFI data structure also contains a security area where a 64 bit
unique security number is written (see Table 35: Security code area). This area can be
accessed only in Read mode by the final user. It is impossible to change the security
number after it has been written by Numonyx.
Query structure overview(1)
Table 30.
Address
Sub-section Name
Description
x16
x8
10h
20h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
36h
System Interface Information
Device timing & voltage information
27h
4Eh
Device Geometry Definition
Flash device layout
40h
80h
Primary Algorithm-specific Extended
Query table
Additional information specific to the
Primary Algorithm (optional)
61h
C2h
Security Code Area
64 bit unique device number
1. Query data are always presented on the lowest order data outputs.
Table 31.
CFI query identification string(1)
Address
Data
Description
Value
x16
x8
10h
20h
0051h
“Q”
11h
22h
0052h Query Unique ASCII String "QRY"
"R"
12h
24h
0059h
"Y"
13h
26h
14h
28h
0002h Primary Algorithm Command Set and Control Interface ID code
0000h 16 bit ID code defining a specific algorithm
15h
2Ah
16h
2Ch
17h
2Eh
18h
30h
0000h Alternate Vendor Command Set and Control Interface ID Code
0000h second vendor - specified algorithm supported
19h
32h
0000h
1Ah
34h
0000h
0040h Address for Primary Algorithm extended Query table (see
0000h Table 34)
Address for Alternate Algorithm extended Query table
AMD
Compatible
P = 40h
NA
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
74/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 32.
Common Flash Interface (CFI)
CFI query system interface information
Address
Data
x16
Description
Value
x8
1Bh
36h
0027h
VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
1Ch
38h
0036h
VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
3.6V
1Dh
3Ah
00B5h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
11.5V
1Eh
3Ch
00C5h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12.5V
1Fh
3Eh
0004h
Typical timeout per single Byte/Word program = 2n µs
16µs
20h
40h
0000h
Typical timeout for minimum size write buffer program = 2n µs
NA
21h
42h
000Ah
Typical timeout per individual Block Erase = 2n ms
1s
22h
23h
44h
46h
0000h
0004h
n
Typical timeout for full Chip Erase = 2 ms
2.7V
NA
n
Maximum timeout for Byte/Word program = 2 times typical
n
256µs
24h
48h
0000h
Maximum timeout for write buffer program = 2 times typical
NA
25h
4Ah
0003h
Maximum timeout per individual Block Erase = 2n times typical
8s
26h
4Ch
0000h
Maximum timeout for Chip Erase = 2n times typical
NA
75/90
Common Flash Interface (CFI)
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Device geometry definition(1)
Table 33.
Address
Data
Description
Value
x16
x8
27h
4Eh
0017h
Device Size = 2n in number of bytes
28h
29h
50h
52h
0002h
0000h
Flash Device Interface Code description
x8, x16
Async.
2Ah
2Bh
54h
56h
0005h
0000h
Maximum number of bytes in multi-byte program or page =
2n
32 bytes
M29W640GH,
M29W640GL
2Ch
58h
M29W640GT,
M29W640GB
0001h Number of Erase Block Regions. It specifies the number of
regions containing contiguous Erase Blocks of the same
0002h size.
2Dh
2Eh
5Ah
5Ch
007Fh Region 1 Information
M29W640GH, 0000h Number of Erase Blocks of identical size = 007Fh+1
M29W640GL 0000h Region 1 Information
2Fh
30h
5Eh
60h
2Dh
2Eh
5Ah
5Ch
2Fh
30h
5Eh
60h
31h
32h
62h
64h
007Eh Region 2 Information
0000h Number of Erase Blocks of identical size= 007Eh+1
33h
34h
66h
68h
0000h Region 2 Information
0001h Block size in Region 2 = 0100h * 256 byte
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0001h Block size in Region 1 = 0100h * 256 byte
M29W640GT,
M29W640GB
M29W640GT,
M29W640GB
only
0007h Region 1 Information
0000h Number of Erase Blocks of identical size = 0007h+1
0020h Region 1 Information
0000h Block size in Region 1 = 0020h * 256 byte
0000h
0000h
0000h
0000h
Region 3 Information
Number of Erase Blocks of identical size=007Fh+1
Region 3 Information
Block size in Region 3 = 0000h * 256 byte
0000h
0000h
0000h
0000h
Region 4 Information
Number of Erase Blocks of Identical size=007Fh+1
Region 4 Information
Block size in Region 4 = 0000h * 256 byte
8 Mbytes
1
2
128
64Kbytes
8
8Kbyte
127
64Kbytes
0
0
0
0
1. For Bottom Boot devices, Erase Block Region 1 is located from address 000000h to 007FFFh and Erase Block Region 2
from address 008000h to 3FFFFFh.
For Top Boot devices, Erase Block Region 1 is located from address 000000h to 3F7FFFh and Erase Block Region 2 from
address 3F8000h to 3FFFFFh.
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M29W640GH, M29W640GL, M29W640GT, M29W640GB
Table 34.
Common Flash Interface (CFI)
Primary algorithm-specific extended query table
Address
Data
Description
Value
x16
x8
40h
80h
0050h
"P"
41h
82h
0052h Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
42h
84h
0049h
"I"
43h
86h
0031h Major version number, ASCII
“1”
44h
88h
0033h Minor version number, ASCII
"3"
45h
8Ah
Address Sensitive Unlock (bits 1 to 0)
0000h 00h = required, 01h = not required
Silicon Revision Number (bits 7 to 2)
Yes
46h
8Ch
0002h
Erase Suspend
00h = not supported, 01h = Read only, 02 = Read and Write
2
47h
8Eh
0004h
Block Protection
00h = not supported, x = number of blocks per protection group
4
48h
90h
0001h
Temporary Block Unprotect
00h = not supported, 01h = supported
49h
92h
0004h Block Protect /Unprotect
04
4Ah
94h
0000h Simultaneous Operations, 00h = not supported
No
4Bh
96h
0000h Burst Mode: 00h = not supported, 01h = supported
No
4Ch
98h
0001h Page Mode: 00h = not supported, 01h = 4 page word, 02h = 8 page word
Yes
4Dh
9Ah
VPP Supply Minimum Program/Erase voltage
00B5h bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5V
9Ch
VPP Supply Maximum Program/Erase voltage
00C5h bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12.5V
9Eh
0002h
0003h
0004h
0005h
A0h
Program Suspend
0001h 00h = Not Supported
01h = Supported
4Eh
4Fh
50h
M29W640GB
M29W640GT
M29W640GL
M29W640GH
Top/Bottom Boot Block Flag
02h = Bottom Boot device
03h = Top Boot device
04h = Uniform blocks bottom VPP/WP protect
05h = Uniform blocks top VPP/WP protect
Yes
-
Support
ed
77/90
Common Flash Interface (CFI)
Table 35.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Security code area
Address
Data
x16
x8
61h
C3h, C2h
XXXX
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
Description
64 bit: unique device number
78/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Appendix C
Extended Memory Block
Extended Memory Block
The M29W640G has an extra block, the Extended Block, that can be accessed using a
dedicated command.
This Extended Block is 128 words in x16 mode and 256 bytes in x8 mode. It is used as a
security block to provide a permanent security identification number) or to store additional
information.
The Extended Block is either Factory Locked or Customer Lockable, its status is indicated
by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be
changed. When set to ‘1’, it indicates that the device is factory locked and the Extended
Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the
Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is
another security feature which ensures that a customer lockable device cannot be used
instead of a factory locked one.
Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific
procedure must be followed to read it. See “Extended Memory Block Verify Code” in Table 7:
Bus Operations, BYTE = VIL and Table 8: Bus Operations, BYTE = VIH, for details of how to
read bit DQ7.
The Extended Block can only be accessed when the device is in Extended Block mode. For
details of how the Extended Block mode is entered and exited, refer to the Section 4.3.1:
Enter Extended Block command and Section 4.3.2: Exit Extended Block command, and to
Table 10 and Table 11: Commands, 8-bit mode, BYTE = VIL.
C.1
Factory Locked Extended Block
In devices where the Extended Block is factory locked, the Security Identification Number is
written to the Extended Block address space (see Table 36: Extended block address and
data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.
C.2
Customer Lockable Extended Block
A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to
‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the
Extended Block but care must be taken because the protection of the Extended Block is not
reversible.
There are two ways of protecting the Extended Block:
●
Issue the Enter Extended Block command to place the device in Extended Block mode,
then use the In-System Technique with RP either at VIH or at VID (refer to Section D.2:
In-System Technique and to the corresponding flowcharts, Figure 27 and Figure 28, for
a detailed explanation of the technique).
●
Issue the Enter Extended Block command to place the device in Extended Block mode,
then use the Programmer Technique (refer to, Section D.1: Programmer Technique and
to the corresponding flowcharts, Figure 25 and Figure 26, for a detailed explanation of
the technique).
Once the Extended Block is programmed and protected, the Exit Extended Block command
must be issued to exit the Extended Block mode and return the device to Read mode.
79/90
Extended Memory Block
Table 36.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Extended block address and data
Address
80/90
Data
x8
x16
Factory Locked
Customer Lockable
000000h-00007Fh
000000h-00003Fh
Security Identification Number
000080h-0000FFh
000040h-00007Fh
Unavailable
Determined by
Customer
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Appendix D
Block Protection
Block Protection
Block protection can be used to prevent any operation from modifying the data stored in the
memory. The blocks are protected in groups, refer to Appendix A: Block addresses, Table 28
and Table 29 for details of the Protection Groups. Once protected, Program and Erase
operations within the protected group fail to change the data.
There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is
described in the Signal Descriptions section.
D.1
Programmer Technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in Programming Equipment.
To protect a group of blocks follow the flowchart in Figure 25: Programmer Equipment Group
Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all groups can be unprotected at the same time. To unprotect the chip follow Figure 26:
Programmer Equipment Chip Unprotect flowchart. Table 37: Programmer technique bus
operations, BYTE = VIH or VIL, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
D.2
In-System Technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP(1). This can be achieved without violating the maximum ratings of the
components on the microprocessor bus, therefore this technique is suitable for use after the
memory has been fitted to the system.
To protect a group of blocks follow the flowchart in Figure 27: In-System Equipment Group
Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all the groups can be unprotected at the same time. To unprotect the chip follow
Figure 28: In-System Equipment Chip Unprotect flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip Unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.
Note:
RP can be either at VIH or at VID when using the In-System Technique to protect the
Extended Block.
81/90
Block Protection
Table 37.
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Programmer technique bus operations, BYTE = VIH or VIL
Operation
E
G
W
Address Inputs
A0-A21
Data
Inputs/Outputs
DQ15A–1, DQ14DQ0
A9 = VID, A12-A21 = Block Address
Others = X
X
A9 = VID, A12 = VIH, A15 = VIH
Others = X
X
Block (Group)
Protect(1)
VIL
Chip Unprotect
VID VID VIL Pulse
Block (Group)
Protection Verify
VIL
VIL
VIH
A0, A2, A3 = VIL, A1 = VIH, A6 = VIL,
A9 = VID, A12-A21 = Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block (Group)
VIL
Unprotection Verify
VIL
VIH
A0, A2, A3 = VIL, A1 = VIH, A6 = VIH,
A9 = VID, A12-A21 = Block Address
Others = X
Retry = XX01h
Pass = XX00h
VID VIL Pulse
1. Block Protection Groups are shown in Appendix A, Tables 28 and 29.
82/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Block Protection
Figure 25. Programmer Equipment Group Protect flowchart
START
Set-up
ADDRESS = GROUP ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Protect
Wait 4µs
W = VIL
Wait 100µs
W = VIH
E, G = VIH,
A0, A2, A3 = VIL, A1 =VIH,
A6 =VIL, A9 = VID, Others = X
E = VIL
Verify
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA
NO
=
01h
YES
++n
= 25
A9 = VIH
E, G = VIH
NO
End
YES
PASS
A9 = VIH
E, G = VIH
FAIL
AI11555
1. Block Protection Groups are shown in Appendix A, Tables 28 and 29.
83/90
Block Protection
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 26. Programmer Equipment Chip Unprotect flowchart
START
Set-up
PROTECT ALL GROUPS
n=0
CURRENT GROUP = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Unprotect
Wait 4µs
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS
A0, A2, A3 = VIL, A1 =VIH,
A6 =VIH, A9 = VID, Others = X
E = VIL
Wait 4µs
G = VIL
INCREMENT
CURRENT GROUP
Verify
Wait 60ns
Read DATA
NO
End
NO
DATA
=
00h
YES
++n
= 1000
YES
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
FAIL
PASS
1. Block Protection Groups are shown in Appendix A, Tables 28 and 29.
84/90
LAST
GROUP
NO
AI11556b
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Block Protection
Figure 27. In-System Equipment Group Protect flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
WRITE 60h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
Wait 100µs
Verify
WRITE 40h
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0, A2, A3, A6 = VIL, A1 = VIH
DATA
NO
=
01h
YES
++n
= 25
End
RP = VIH
YES
ISSUE READ/RESET
COMMAND
PASS
NO
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
AI11563
2. Block Protection Groups are shown in Appendix A, Tables 28 and 29.
3. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.
85/90
Block Protection
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 28. In-System Equipment Chip Unprotect flowchart
START
Set-up
PROTECT ALL GROUPS
n=0
CURRENT GROUP = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3, A6 = VIL, A1 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0, A2, A3 = VIL, A1, A6 = VIH
Wait 10ms
Verify
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0, A2, A3 = VIL, A1, A6 = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0, A2, A3 = VIL, A1, A6 = VIH
NO
End
NO
DATA
=
00h
INCREMENT
CURRENT GROUP
YES
++n
= 1000
LAST
GROUP
NO
YES
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI11564
1. Block Protection Groups are shown in Appendix A, Tables 28 and 29.
86/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Appendix E
Flowchart
Flowchart
Figure 29. Write to Buffer and Program flowchart and pseudo code
Start
Write to Buffer F0h
Command,
Block Address
Write n(1),
Block Address
First Part of the
Write to Buffer and Program Command
Write Buffer Data,
Start Address
X=n
YES
X=0
NO
Abort Write
to Buffer
YES
Write to a Different
Block Address
NO
Write Next Data,(3)
Program Address Pair
Write to Buffer and
Program Aborted(2)
X = X-1
Program Buffer
to Flash Block Address
Read Status Register
(DQ1, DQ5, DQ7) at
Last Loaded Address
YES
DQ7 = Data
NO
NO
DQ1 = 1
YES
NO
DQ5 = 1
YES
Check Status Register
(DQ5, DQ7) at
Last Loaded Address
DQ7 = Data
YES
(4)
NO
FAIL OR ABORT(5)
END
AI12777
87/90
Flowchart
M29W640GH, M29W640GL, M29W640GT, M29W640GB
1. n+1 is the number of addresses to be programmed.
2. A Write to Buffer and Program Abort and Reset must be issued to return the device in Read mode.
3. When the block address is specified, any address in the selected block address space is acceptable. However when
loading Write Buffer address with data, all addresses must fall within the selected Write Buffer page.
4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously.
5. If this flowchart location is reached because DQ5=’1’, then the Write to Buffer and Program command failed. If this
flowchart location is reached because DQ1=’1’, then the Write to Buffer and Program command aborted. In both cases, the
appropriate reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a
Write to Buffer and Program Abort and Reset command if the operation aborted.
6. See Table 10 and Table 11, for details on Write to Buffer and Program command sequence.
88/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Revision history
Revision history
Table 38.
Document revision history
Date
Version
Changes
20-Jul-2006
1
Initial release.
21-Aug-2006
2
Datasheet status updated to full datasheet; added an explanation of how to
abort the Write Buffer Programming Sequence in Section 4.2.9: Write to
Buffer and Program command; amended text of 4.2.11: Write to Buffer and
Program Abort and Reset command.
25-Oct-2006
3
Table 13: Status Register bitsupdated.
22-Feb-2007
4
90ns access time added.
27-Mar-2008
5
Applied Numonyx branding.
89/90
M29W640GH, M29W640GL, M29W640GT, M29W640GB
Please Read Carefully:
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90/90