AD ADUM121N0BRZ-RL7 3.0 kv rms, dual-channel digital isolator Datasheet

3.0 kV rms,
Dual-Channel Digital Isolators
ADuM120N/ADuM121N
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1
ADuM120N
8
VDD2
VIA 2
ENCODE
DECODE
7
VOA
VIB 3
ENCODE
DECODE
6
VOB
5
GND2
GND1 4
Figure 1. ADuM120N Functional Block Diagram
VDD1 1
ADuM121N
8
VDD2
VOA 2
DECODE
ENCODE
7
VIA
VIB 3
ENCODE
DECODE
6
VOB
5
GND2
GND1 4
14122-002
High common-mode transient immunity: 100 kV/µs typical
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps minimum data rate
Safety and regulatory approvals (pending)
UL recognition: 3000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
CQC certification per GB4943.1-2011
Backward compatibility
ADuM120N0 pin-compatible with ADuM1285
ADuM120N1 pin-compatible with ADuM1280 and
ADuM1200
ADuM121N0 pin-compatible with ADuM1286
ADuM121N1 pin-compatible with ADuM1281 and
ADuM1201
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Failsafe high or low options
8-lead, RoHS-compliant, SOIC package
Qualified for automotive applications
14122-001
FEATURES
Figure 2. ADuM121N Functional Block Diagram
APPLICATIONS
General-purpose multichannel isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM120N/ADuM121N are dual-channel digital isolators
based on Analog Devices, Inc., iCoupler® technology. Combining
high speed, complementary metal-oxide semiconductor (CMOS)
and monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices and other
integrated couplers. The maximum propagation delay is 13 ns
with a pulse width distortion of less than 3 ns at 5 V operation.
Channel matching is tight at 3.0 ns maximum.
1
The ADuM120N/ADuM121N data channels are independent and
are available in a variety of configurations with a withstand voltage
rating of 3 kV rms (see the Ordering Guide). The devices operate
with the supply voltage on either side ranging from 1.8 V to 5 V,
1
providing compatibility with lower voltage systems as well as
enabling voltage translation functionality across the isolation
barrier.
Unlike other optocoupler alternatives, dc correctness is ensured in
the absence of input logic transitions. Two different fail-safe options
are available in which the outputs transition to a predetermined
state when the input power supply is not applied or the inputs
are disabled.
The ADuM120N0 is pin-compatible with the ADuM1285, and
the ADuM120N1 is pin-compatible with the ADuM1280 and
the ADuM1200. The ADuM121N0 is pin-compatible with
ADuM1286, and the ADuM121N0 is pin-compatible with the
ADuM1281 and the ADuM1201.
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. A
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ADuM120N/ADuM121N
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 12
Applications ....................................................................................... 1
Absolute Maximum Ratings ......................................................... 13
Functional Block Diagrams ............................................................. 1
ESD Caution................................................................................ 13
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ......................... 14
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 15
Specifications..................................................................................... 3
Applications Information .............................................................. 16
Electrical Characteristics—5 V Operation................................ 3
Overview ..................................................................................... 16
Electrical Characteristics—3.3 V Operation ............................ 5
PCB Layout ................................................................................. 16
Electrical Characteristics—2.5 V Operation ............................ 7
Propagation Delay Related Parameters ................................... 17
Electrical Characteristics—1.8 V Operation ............................ 9
Jitter Measurement ..................................................................... 17
Insulation and Safety Related Specifications .......................... 10
Insulation Lifetime ..................................................................... 17
Package Characteristics ............................................................. 10
Outline Dimensions ....................................................................... 19
Regulatory Information ............................................................. 11
Ordering Guide .......................................................................... 19
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 12
Automotive Products ................................................................. 19
REVISION HISTORY
4/16—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Jitter Measurement Section....................................... 17
Changes to Ordering Guide .......................................................... 19
Added Automotive Products Section .......................................... 19
1/16—Revision 0: Initial Version
Rev. A | Page 2 of 19
Data Sheet
ADuM120N/ADuM121N
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM120N
ADuM121N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
Symbol
Min
PW
6.6
150
4.8
tPHL, tPLH
PWD
Typ
7.2
0.5
1.5
tPSK
Max
Unit
Test Conditions/Comments
13
3
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
6.0
tPSKCD
tPSKOD
0.5
0.5
380
55
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
3.0
3.0
ns
ns
ps p-p
ps rms
Between any two units at the same
temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx 1 = −20 µA, VIx = VIxH 2
IOx1 = −4 mA, VIx = VIxH2
IOx1 = 20 µA, VIx = VIxL 3
IOx1 = 4 mA, VIx = VIxL3
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.9
1.3
6.4
1.4
1.1
1.1
4.0
4.9
1.3
1.8
10.0
1.9
1.6
1.5
5.8
6.4
mA
mA
mA
mA
mA
mA
mA
mA
VI 4 = 0 (N0), 1 (N1) 5
VI4 = 0 (N0), 1 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 0 (N0), 1 (N1)5
VI4 = 0 (N0), 1 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 1 (N0), 0 (N1)5
IDDI (D)
IDDO (D)
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
0.01
0.02
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
1.6
1.5
0.1
V
V
V
VOL
II
−10
Rev. A | Page 3 of 19
ADuM120N/ADuM121N
Parameter
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 6
Data Sheet
Symbol
Min
Typ
tR/tF
|CMH|
75
|CML|
75
Max
Unit
Test Conditions/Comments
2.5
100
ns
kV/µs
100
kV/µs
10% to 90%
VIx = VDDx, VCM = 1000 V, transient
magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
IOx is the Channel x output current, where x = A or B.
VIxH is the input side logic high voltage.
VIxL is the input side logic low voltage.
4
VI is the input voltage.
5
N0 is the ADuM120N0/ADuM121N0 models, and N1 is the ADuM120N1/ADuM121N1 models. See the Ordering Guide.
6
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum commonmode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
1
2
3
Table 2. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM120N
Supply Current Side 1
Supply Current Side 2
ADuM121N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
3.7
1.4
6.8
2.0
4.2
2.5
7.2
3.2
6.2
6.0
9.3
8.1
mA
mA
IDD1
IDD2
2.6
3.0
4.5
4.9
3.2
3.7
5.4
5.9
5.4
5.8
8.2
8.6
mA
mA
Rev. A | Page 4 of 19
Data Sheet
ADuM120N/ADuM121N
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM120N
ADuM121N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
Symbol
Min
PW
6.6
150
4.8
tPHL, tPLH
PWD
Typ
6.8
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
14
3
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
7.0
tPSKCD
tPSKOD
0.7
0.7
290
45
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
3.0
3.0
ns
ns
ps p-p
ps rms
Between any two units at the same
temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx 1 = −20 µA, VIx = VIxH 2
IOx1 = −2 mA, VIx = VIxH2
IOx1 = 20 µA, VIx = VIxL 3
IOx1 = 2 mA, VIx = VIxL3
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.8
1.2
6.3
1.3
1.0
1.0
3.9
4.8
1.3
1.8
9.7
1.8
1.6
1.5
5.8
6.4
mA
mA
mA
mA
mA
mA
mA
mA
VI 4 = 0 (N0), 1 (N1) 5
VI4 = 0 (N0), 1 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 0 (N0), 1 (N1)5
VI4 = 01 (N0), 1 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 1 (N0), 0 (N1)5
IDDI (D)
IDDO (D)
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
1.6
1.5
0.1
V
V
V
VOL
II
−10
Rev. A | Page 5 of 19
ADuM120N/ADuM121N
Parameter
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 6
Data Sheet
Symbol
Min
Typ
tR/tF
|CMH|
75
|CML|
75
Max
Unit
Test Conditions/Comments
2.5
100
ns
kV/µs
100
kV/µs
10% to 90%
VIx = VDDx, VCM = 1000 V, transient
magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
IOx is the Channel x output current, where x = A or B.
VIxH is the input side logic high voltage.
VIxL is the input side logic low voltage.
4
VI is the input voltage.
5
N0 is the ADuM120N0/ADuM121N0 models, and N1 is the ADuM120N1/ADuM121N1 models. See the Ordering Guide.
6
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDx. |CML| is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
3
Table 4. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM120N
Supply Current Side 1
Supply Current Side 2
ADuM121N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
3.6
1.3
6.2
1.9
4.0
2.3
6.7
3.1
5.6
5.2
9.1
6.8
mA
mA
IDD1
IDD2
2.5
2.9
4.6
4.8
3.0
3.5
5.5
5.8
5.0
5.4
8.1
8.3
mA
mA
Rev. A | Page 6 of 19
Data Sheet
ADuM120N/ADuM121N
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM120N
ADuM121N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
Symbol
Min
PW
6.6
150
5.0
tPHL, tPLH
PWD
Typ
7.0
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
14
3
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
7.0
tPSKCD
tPSKOD
0.7
0.7
320
65
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
3.0
3.0
ns
ns
ps p-p
ps rms
Between any two units at the same
temperature, voltage, load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx 1 = −20 µA, VIx = VIxH 2
IOx1 = −2 mA, VIx = VIxH2
IOx1 = 20 µA, VIx = VIxL 3
IOx1 = 2 mA, VIx = VIxL3
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.8
1.2
6.2
1.3
1.0
1.0
3.9
4.8
1.2
1.8
9.5
1.8
1.5
1.4
5.8
6.4
mA
mA
mA
mA
mA
mA
mA
mA
VI 4 = 0 (N0), 1 (N1) 5
VI4 = 0 (N0), 1 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 0 (N0), 1 (N1)5
VI4 = 0 (N0), 1 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 1 (N0), 0 (N1)5
IDDI (D)
IDDO (D)
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
VDDxUV+
VDDxUV−
VDDxUVH
1.6
1.5
0.1
V
V
V
VOL
II
−10
Rev. A | Page 7 of 19
ADuM120N/ADuM121N
Parameter
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 6
Data Sheet
Symbol
Min
Typ
tR/tF
|CMH|
75
|CML|
75
Max
Unit
Test Conditions/Comments
2.5
100
ns
kV/µs
100
kV/µs
10% to 90%
VIx = VDDx, VCM = 1000 V, transient
magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
IOx is the Channel x output current, where x = A or B.
VIxH is the input side logic high voltage.
VIxL is the input side logic low voltage.
4
VI is the input voltage.
5
N0 is the ADuM120N0/ADuM121N0 models, and N1 is the ADuM120N1/ADuM121N1 models. See the Ordering Guide.
6
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDx. |CML| is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
3
Table 6. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM120N
Supply Current Side 1
Supply Current Side 2
ADuM121N
Supply Current Side 1
Supply Current Side 2
Symbol
Min
1 Mbps
Typ
Max
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
3.5
1.3
6.2
1.9
3.9
2.0
6.6
2.8
5.4
4.2
9.0
5.8
mA
mA
IDD1
IDD2
2.4
2.9
4.7
4.9
2.9
3.3
5.5
5.7
4.5
4.9
8.0
7.7
mA
mA
Rev. A | Page 8 of 19
Data Sheet
ADuM120N/ADuM121N
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
Channel Matching
Codirectional
Opposing Direction
Jitter
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
Logic Low
Output Voltage
Logic High
Logic Low
Input Current per Channel
Quiescent Supply Current
ADuM120N
ADuM121N
Dynamic Supply Current
Dynamic Input
Dynamic Output
Undervoltage Lockout
Positive VDDx Threshold
Negative VDDx Threshold
VDDx Hysteresis
Symbol
Min
PW
6.6
150
5.8
tPHL, tPLH
PWD
Typ
8.7
0.7
1.5
tPSK
Max
Unit
Test Conditions/Comments
15
3
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
7.0
tPSKCD
tPSKOD
0.7
0.7
630
190
VIH
VIL
0.7 × VDDx
VOH
VDDx − 0.1
VDDx − 0.4
3.0
3.0
ns
ns
ps p-p
ps rms
Between any two units at the same
temperature, voltage, and load
See the Jitter Measurement section
See the Jitter Measurement section
0.3 × VDDx
V
V
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
V
V
V
V
µA
IOx 1 = −20 µA, VIx = VIxH 2
IOx1 = −2 mA, VIx = VIxH2
IOx1 = 20 µA, VIx = VIxL 3
IOx1 = 2 mA, VIx = VIxL3
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.7
1.2
6.2
1.3
1.0
1.0
3.8
4.7
1.2
1.8
9.6
1.8
1.5
1.4
5.8
6.4
mA
mA
mA
mA
mA
mA
mA
mA
VI 4 = 0 (N0), 1 (N1) 5
VI4 = 0 (N0), 1 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 0 (N0), 1 (N1)5
VI4 = 0 (N0), 1 (N1)5
VI4 = 1 (N0), 0 (N1)5
VI4 = 1 (N0), 0 (N1)5
IDDI (D)
IDDO (D)
UVLO
VDDxUV+
VDDxUV−
VDDxUVH
0.01
0.01
mA/Mbps
mA/Mbps
Inputs switching, 50% duty cycle
Inputs switching, 50% duty cycle
1.6
1.5
0.1
V
V
V
VOL
II
−10
Rev. A | Page 9 of 19
ADuM120N/ADuM121N
Parameter
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity 6
Data Sheet
Symbol
Min
Typ
tR/tF
|CMH|
75
|CML|
75
Max
Unit
Test Conditions/Comments
2.5
100
ns
kV/µs
100
kV/µs
10% to 90%
VIx = VDDx, VCM = 1000 V, transient
magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
IOx is the Channel x output current, where x = A or B.
VIxH is the input side logic high voltage.
VIxL is the input side logic low voltage.
4
VI is the input voltage.
5
N0 is the ADuM120N0/ADuM121N0 models, N1 is the ADuM120N1/ADuM121N1 models. See the Ordering Guide.
6
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDx. |CML| is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
1
2
3
Table 8. Total Supply Current vs. Data Throughput
Parameter
SUPPLY CURRENT
ADuM120N
Supply Current Side 1
Supply Current Side 2
ADuM121N
Supply Current Side 1
Supply Current Side 2
Symbol
1 Mbps
Typ
Max
Min
Min
25 Mbps
Typ
Max
Min
100 Mbps
Typ
Max
Unit
IDD1
IDD2
3.4
1.2
6.0
1.8
3.8
1.9
6.4
2.8
5.2
4.0
8.4
5.8
mA
mA
IDD1
IDD2
2.4
2.8
4.7
4.8
2.8
3.2
5.5
5.6
4.4
4.8
7.8
7.9
mA
mA
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 9.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L (I01)
Value
3000
4.0
Unit
V rms
mm min
Minimum External Tracking (Creepage)
L (I02)
4.0
mm min
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB)
4.5
mm min
CTI
25.5
>400
II
µm min
V
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 10.
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction to Ambient Thermal Resistance
1
2
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1013
2
4.0
80
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside
The device is considered a 2-terminal device: Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
Input capacitance is from any input data pin to ground.
Rev. A | Page 10 of 19
Data Sheet
ADuM120N/ADuM121N
REGULATORY INFORMATION
See Table 15 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 11.
UL (Pending)
Recognized under UL 1577
Component Recognition
Program 1
Single Protection, 3000 V rms
Isolation Voltage
Double Protection, 3000 V rms
Isolation Voltage
File E214100
1
2
CSA (Pending)
Approved under CSA Component
Acceptance Notice 5A
VDE (Pending)
DIN V VDE V 0884-10 (VDE V
0884-10):2006-12 2
CQC (Pending)
Certified under
CQC11-471543-2012
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
Basic insulation at 400 V rms
(565 V peak)
Reinforced insulation at 200 V rms
(283 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 MOPP), 250 V rms
(354 V peak)
CSA 61010-1-12 and IEC 61010-1
third edition
Basic insulation at 300 V rms mains,
400 V rms (565 V peak)
Reinforced insulation at 300 V rms
mains, 200 V secondary (283 V peak)
File 205078
Reinforced insulation, 565 V
peak, VIOSM = 6000 V peak
Basic insulation, 565 V peak,
VIOSM = 10000 V peak
GB4943.1-2011
File 2471900-4880-0001
Basic insulation at 770 V rms
(1089 V peak) working voltage
Reinforced insulation at
385 V rms (545 V peak)
File (pending)
In accordance with UL 1577, each ADuM120N/ADuM121N is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 sec.
In accordance with DIN V VDE V 0884-10, each ADuM120N/ADuM121N is proof tested by applying an insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge
detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
Rev. A | Page 11 of 19
ADuM120N/ADuM121N
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 12.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage Basic
V peak = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
V peak = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
Maximum value allowed in the event of a
failure (see Figure 3)
Surge Isolation Voltage Reinforced
Safety Limiting Values
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
VIO = 500 V
Characteristic
Unit
VIORM
Vpd (m)
I to IV
I to III
I to III
40/105/21
2
565
1059
V peak
V peak
Vpd (m)
848
V peak
678
V peak
VIOTM
VIOSM
4200
10000
V peak
V peak
VIOSM
6000
V peak
TS
PS
RS
150
1.56
>109
°C
W
Ω
RECOMMENDED OPERATING CONDITIONS
1.8
1.6
SAFETY LIMITING POWER (W)
Symbol
Table 13.
1.4
Parameter
Operating Temperature
Supply Voltages
Input Signal Rise and Fall Times
1.2
1.0
0.8
0.6
0.4
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
14122-003
0.2
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
Rev. A | Page 12 of 19
Symbol
TA
VDD1, VDD2
Rating
−40°C to +125°C
1.7 V to 5.5 V
1.0 ms
Data Sheet
ADuM120N/ADuM121N
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 14.
Parameter
Supply Voltages (VDD1, VDD2)
Input Voltages (VIA, VIB)1
Output Voltages (VOA, VOB)2
Average Output Current per Pin3
Side 1 Output Current (IO1)
Side 2 Output Current (IO2)
Common-Mode Transients4
Storage Temperature (TST) Range
Ambient Operating Temperature
(TA) Range
Rating
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
−10 mA to +10 mA
−150 kV/µs to +150 kV/µs
−65°C to +150°C
−40°C to +125°C
ESD CAUTION
VDDI is the input side supply voltage.
VDDO is the output side supply voltage.
3
See Figure 3 for the maximum rated current values for various temperatures.
4
Common-mode transients refer to the common-mode transients across the
insulation barrier. Common-mode transients exceeding the absolute
maximum ratings may cause latch-up or permanent damage.
1
2
Table 15. Maximum Continuous Working Voltage1
Parameter
AC VOLTAGE
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC VOLTAGE
Basic Insulation
Reinforced Insulation
1
2
Rating
Constraint2
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
789 V peak
403 V peak
909 V peak
469 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
558 V peak
285 V peak
Maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Insulation lifetime for the specified test condition is greater than 50 years.
Truth Tables
Table 16. ADuM120N/ADuM121N Truth Table (Positive Logic)
VIx Input 1
Low
High
Don’t Care 3
Don’t Care3
VDDI State1
Powered
Powered
Unpowered
Powered
VDDO State1
Powered
Powered
Powered
Unpowered
Default Low (N0),
VOx Output1, 2
Low
High
Low
Indeterminate
Default High (N1),
VOx Output1, 2
Low
High
High
Indeterminate
Test Conditions/Comments
Normal operation
Normal operation
Fail-safe output
VIx and VOx refer to the input and output signals of a given channel (A or B). VDDI and VDDO refer to the supply voltages on the input and output sides of the given
channel, respectively.
N0 is the ADuM120N0/ADuM121N0 models, N1 is the ADuM120N1/ADuM121N1 models. See the Ordering Guide.
3
Input pins (VIx) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.
1
2
Rev. A | Page 13 of 19
ADuM120N/ADuM121N
Data Sheet
VDD1 1
VIA 2
ADuM120N
VIB 3
TOP VIEW
(Not to Scale)
GND1 4
8
VDD2
7
VOA
6
VOB
5
GND2
14122-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADuM120N Pin Configuration
Reference the AN-1109 Application Note for specific layout guidelines.
Table 17. ADuM120N Pin Function Descriptions
Mnemonic
VDD1
VIA
VIB
GND1
GND2
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Input A.
Logic Input B.
Ground 1. This pin is the ground reference for Isolator Side 1.
Ground 2. This pin is the ground reference for Isolator Side 2.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2.
VDD1 1
VOA 2
ADuM121N
VIB 3
TOP VIEW
(Not to Scale)
GND1 4
8
VDD2
7
VIA
6
VOB
5
GND2
14122-005
Pin No.
1
2
3
4
5
6
7
8
Figure 5. ADuM121N Pin Configuration
Reference the AN-1109 Application Note for specific layout guidelines.
Table 18. ADuM121N Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
VDD1
VOA
VIB
GND1
GND2
VOB
VIA
VDD2
Description
Supply Voltage for Isolator Side 1.
Logic Output A.
Logic Input B.
Ground 1. This pin is the ground reference for Isolator Side 1.
Ground 2. This pin is the ground reference for Isolator Side 2.
Logic Output B.
Logic Input A.
Supply Voltage for Isolator Side 2.
Rev. A | Page 14 of 19
Data Sheet
ADuM120N/ADuM121N
10
9
9
8
8
5
4
3
2
5V
3.3V
2.5V
1.8V
1
0
0
20
60
40
100
80
120
160
140
DATA RATE (Mbps)
5
4
3
2
0
9
8
8
IDD2 SUPPLY CURRENT (mA)
10
6
5
4
3
5V
3.3V
2.5V
1.8V
1
0
0
20
40
60
100
80
120
160
140
DATA RATE (Mbps)
4
3
2
0
6
4
5V
3.3V
2.5V
1.8V
60
80
TEMPERATURE (°C)
100
120
140
40
60
100
80
120
160
10
8
6
4
5V
3.3V
2.5V
1.8V
2
Figure 8. Propagation Delay for Logic High Output (tPLH) vs. Temperature at
Various Voltages
140
Figure 10. ADuM121N IDD2 Supply Current vs. Data Rate at Various Voltages
0
–40
14122-108
40
20
DATA RATE (Mbps)
PROPAGATION DELAY, tPHL (ns)
8
20
5V
3.3V
2.5V
1.8V
0
12
10
160
140
5
12
0
120
6
14
–20
100
80
7
14
0
–40
60
1
Figure 7. ADuM120N IDD2 Supply Current vs. Data Rate at Various Voltages
2
40
Figure 9. ADuM121N IDD1 Supply Current vs. Data Rate at Various Voltages
9
7
20
DATA RATE (Mbps)
10
2
5V
3.3V
2.5V
1.8V
0
14122-109
IDD2 SUPPLY CURRENT (mA)
6
1
Figure 6. ADuM120N IDD1 Supply Current vs. Data Rate at Various Voltages
PROPAGATION DELAY, tPLH (ns)
7
14122-110
6
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
14122-111
7
14122-107
IDD1 SUPPLY CURRENT (mA)
10
14122-106
IDD1 SUPPLY CURRENT (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11. Propagation Delay for Logic Low Output (tPHL) vs. Temperature at
Various Voltages
Rev. A | Page 15 of 19
ADuM120N/ADuM121N
Data Sheet
APPLICATIONS INFORMATION
The ADuM120N/ADuM121N use a high frequency carrier to
transmit data across an isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide
isolation. With an on/off keying (OOK) technique and the
differential architecture shown in Figure 13 and Figure 14, the
ADuM120N/ADuM121N have very low propagation delay and
high speed. Internal regulators and input/output design techniques
allow logic and supply voltages over a wide range from 1.7 V to
5.5 V, offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V
logic. The architecture is designed for high common-mode
transient immunity and high immunity to electrical noise and
magnetic interference. Radiated emissions are minimized with a
spread spectrum OOK carrier and other techniques.
Figure 13 shows the operation block diagram of a single channel
for the ADuM120N0/ADuM121N0 models, which have the
condition of the fail-safe output state equal to low, where the
carrier waveform is off when the input state is low. If the input
side is off or not operating, the fail-safe output state of low
(noted by the 0 in the model number) sets the output to low.
For the ADuM120N1/ADuM121N1, which have a fail-safe output
state of high, Figure 14 shows the conditions where the carrier
waveform is off when the input state is high. When the input
side is off or not operating, the fail-safe output state of high
(noted by the 1 in the model number) sets the output to high.
See the Ordering Guide for the model numbers that have the
fail-safe output state of low or the fail-safe output state of high.
PCB LAYOUT
The ADuM120N/ADuM121N digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at the input and output supply pins
(see Figure 12). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 4 for VDD1 and between Pin 5 and Pin 8
for VDD2. The recommended bypass capacitor value is between
0.01 μF and 0.1 μF. The total lead length between both ends of
the capacitor and the input power supply pin must not exceed
10 mm.
VDD2
VOA/VIA
VOB
GND2
VDD1
VIA/VOA
VIB
GND1
14122-010
OVERVIEW
Figure 12. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
GND1
14122-011
VOUT
GND2
Figure 13. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VIN
GND1
GND2
Figure 14. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
Rev. A | Page 16 of 19
14122-012
VOUT
Data Sheet
ADuM120N/ADuM121N
PROPAGATION DELAY RELATED PARAMETERS
INSULATION LIFETIME
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
INPUT (VIx)
50%
tPHL
OUTPUT (VOx)
14122-013
tPLH
50%
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation delay
differs between channels within a single ADuM120N/ADuM121N
component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM120N/ADuM121N
components operating under the same conditions
JITTER MEASUREMENT
Figure 16 shows the eye diagram for the ADuM120N/ADuM121N.
The measurement was taken using an Agilent 81110A pulse
pattern generator at 150 Mbps with pseudorandom bit sequences
(PRBS) 2(n − 1), n = 14, for 5 V supplies. Jitter was measured
with the Tektronix Model 5104B oscilloscope, 1 GHz, 10 GS/s
with the DPOJET jitter and eye diagram analysis tools. The result
shows a typical measurement on the ADuM120N/ADuM121N
with 380 ps p-p jitter.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage
across the isolation, pollution degree, and material group. The
material group and creepage for the ADuM120N/ADuM121N
isolators are presented in Table 9.
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. It is the working voltage
applicable to tracking that is specified in most standards.
5
4
3
2
1
0
–10
–5
0
5
10
TIME (ns)
14122-014
VOLTAGE (V)
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation
wear out. Surface breakdown is the phenomenon of surface
tracking and the primary determinant of surface creepage
requirements in system level standards. Insulation wear out is the
phenomenon where charge injection or displacement currents
inside the insulation material cause long-term insulation
degradation.
Testing and modeling show that the primary driver of longterm degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as
dc stress, which causes very little wear out because there is
no displacement current, and an ac component time varying
voltage stress, which causes wear out.
Figure 16. ADuM120N/ADuM121N Eye Diagram
Rev. A | Page 17 of 19
ADuM120N/ADuM121N
Data Sheet
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this the reflects isolation
from line voltage. However, many practical applications have
combinations of 60 Hz ac and dc across the barrier as shown
in Equation 1. Because only the ac portion of the stress causes
wear out, the equation can be rearranged to solve for the ac rms
voltage, as is shown in Equation 2. For insulation wear out with
the polyimide materials used in these products, the ac rms
voltage determines the product lifetime.
VRMS = VAC RMS 2 + VDC 2
(1)
VAC RMS = VRMS 2 − VDC 2
(2)
The working voltage across the barrier from Equation 1 is
VRMS = VAC RMS 2 + VDC 2
VRMS = 240 2 + 400 2
VRMS = 466 V
This is the working voltage used together with the material group
and pollution degree when looking up the creepage required by
a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
or
VAC RMS = VRMS 2 − VDC 2
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
VAC RMS = 4662 − 4002
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 15 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Calculation and Use of Parameters Example
Note that the dc working voltage limit in Table 15 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.
VAC RMS
VPEAK
VDC
VRMS
TIME
14122-015
ISOLATION VOLTAGE
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 VAC RMS and a 400 VDC bus voltage is present on
the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 17 and
the following equations.
Figure 17. Critical Voltage Example
Rev. A | Page 18 of 19
Data Sheet
ADuM120N/ADuM121N
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 18. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2
ADuM120N1BRZ
ADuM120N1BRZ-RL7
Temperature
Range
−40°C to +125°C
−40°C to +125°C
No. of
Inputs,
VDD1 Side
2
2
No. of
Inputs,
VDD2 Side
0
0
Withstand Voltage
Rating (kV rms)
3
3
Fail-Safe
Output
State
High
High
ADuM120N0BRZ
ADuM120N0BRZ-RL7
−40°C to +125°C
−40°C to +125°C
2
2
0
0
3
3
Low
Low
ADuM121N1BRZ
ADuM121N1BRZ-RL7
−40°C to +125°C
−40°C to +125°C
1
1
1
1
3
3
High
High
ADuM121N0BRZ
ADuM121N0BRZ-RL7
−40°C to +125°C
−40°C to +125°C
1
1
1
1
3
3
Low
Low
ADuM121N1WBRZ
ADuM121N1WBRZ-RL7
−40°C to +125°C
−40°C to +125°C
1
1
1
1
3
3
High
High
1
2
Package
Description
8-Lead SOIC_N
8-Lead SOIC_N,
Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N,
Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N,
Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N,
Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N,
Tape and Reel
Package
Option
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADuM121N1WBRZ and the ADuM121N1WBRZ-RL7 models are available with controlled manufacturing to support the quality and
reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the
commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade
products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific
product ordering information and to obtain the specific Automotive Reliability reports for these models.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
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