CD54/74AC32, CD54/74ACT32 Data sheet acquired from Harris Semiconductor SCHS230A Quad 2-Input OR Gate September 1998 - Revised May 2000 Features Description • Buffered Inputs The ’AC32 and ’ACT32 are quad 2-input OR gates that utilize Advanced CMOS Logic technology. • Typical Propagation Delay - 4.5ns at VCC = 5V, TA = 25oC, CL = 50pF Ordering Information • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 [ /Title (CD74 AC32, CD74 ACT32 ) /Subject (Quad 2-Input OR Gate) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS , Harris Semiconductor, Advan ced TTL) /Creator () PART NUMBER • SCR-Latchup-Resistant CMOS Process and Circuit Design TEMP. RANGE (oC) PACKAGE CD54AC32F3A -55 to 125 14 Ld CERDIP • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption CD74AC32E -55 to 125 14 Ld PDIP CD74AC32M -55 to 125 14 Ld SOIC • Balanced Propagation Delays CD54ACT32F3A -55 to 125 14 Ld CERDIP • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply CD74ACT32E -55 to 125 14 Ld PDIP CD74ACT32M -55 to 125 14 Ld SOIC • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinout Functional Diagram CD54AC32, CD54ACT32 (CERDIP) CD74AC32, CD74ACT32 (PDIP, SOIC) TOP VIEW 1 14 2 13 1A 4B 1B 1Y 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 2Y 6 9 3A GND GND 7 8 3Y 2A 2B VCC 3 12 4 11 5 10 6 9 7 8 4A 4Y 3B 3A 3Y TRUTH TABLE INPUTS nA nB nY L L L L H H H L H H H H CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © 2000, Texas Instruments Incorporated 1 OUTPUT CD54/74AC32, CD54/74ACT32 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 5) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VIH - - 1.5 1.2 - 1.2 - 1.2 - V 3 2.1 - 2.1 - 2.1 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL - -0.05 5.5 3.85 - 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V 2 CD54/74AC32, CD54/74ACT32 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 4 - 40 - 80 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V Input Leakage Current Quiescent Device Current SSI ACT TYPES Low Level Output Voltage Input Leakage Current Quiescent Device Current SSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 4 - 40 - 80 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD All 0.42 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 3 CD54/74AC32, CD54/74ACT32 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC PARAMETER -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 108 - - 119 ns 3.3 (Note 9) 3.4 - 12.1 3.3 - 13.3 ns 5 (Note 10) 2.4 - 8.6 2.4 - 9.5 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 47 - - 47 - pF tPHL tPLH 5 (Note 10) 3.1 - 11 3 - 12.1 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 47 - - 47 - pF AC TYPES Propagation Delay, Input to Output Input Capacitance Power Dissipation Capacitance ACT TYPES Propagation Delay, Input to Output Input Capacitance Power Dissipation Capacitance NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V. 11. CPD is used to determine the dynamic power consumption per gate. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. OUTPUT tr = 3ns RL (NOTE) 500Ω INPUT (A, B) LEVEL 90% VS 10% DUT GND OUTPUT LOAD CL 50pF tPHL tPLH VS Y NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. FIGURE 2. AC ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level FIGURE 1. PROPAGATION DELAY TIMES 4 tf = 3ns IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated