Microchip MCP23017-E/SO 16-bit i/o expander with serial interface Datasheet

MCP23017/MCP23S17
16-Bit I/O Expander with Serial Interface
• Configurable Interrupt Source:
- Interrupt-on-change from configured register
defaults or pin changes
• Polarity Inversion Register to Configure the
Polarity of the Input Port Data
• External Reset Input
• Low Standby Current: 1 µA (max.)
• Operating Voltage:
- 1.8V to 5.5V @ -40°C to +85°C
- 2.7V to 5.5V @ -40°C to +85°C
- 4.5V to 5.5V @ -40°C to +125°C
Features
• 16-Bit Remote Bidirectional I/O Port:
- I/O pins default to input
• High-Speed I2C Interface (MCP23017):
- 100 kHz
- 400 kHz
- 1.7 MHz
• High-Speed SPI Interface (MCP23S17):
- 10 MHz (maximum)
• Three Hardware Address Pins to Allow Up to
Eight Devices On the Bus
• Configurable Interrupt Output Pins:
- Configurable as active-high, active-low or
open-drain
• INTA and INTB Can Be Configured to Operate
Independently or Together
Packages
•
•
•
•
28-pin QFN, 6 x 6 mm Body
28-pin SOIC, Wide, 7.50 mm Body
28-pin SPDIP, 300 mil Body
28-pin SSOP, 5.30 mm Body
Package Types
MCP23017
SOIC
SPDIP
SSOP
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
VDD
VSS
CS
SCK
SI
SO
GPB4
GPB5
GPB6
GPB7
VDD
VSS
28 2726 2524 2322
21
20
19
EP
18
29 *
17
16
15
8 9 1011 121314
SCK
SDA
NC
A0
A1
A2
RESET
NC
1
2
3
4
5
6
7
 2005-2016 Microchip Technology Inc.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
RESET
A2
A1
A0
GPB3
GPB2
GPB1
GPB0
GPA7
GPA6
GPA5
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
RESET
A2
A1
A0
GPB3
GPB2
GPB1
GPB0
GPA7
GPA6
GPA5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
QFN
GPB4
GPB5
GPB6
GPB7
VDD
VSS
CS
* Includes Exposed Thermal Pad; see Table 2-1.
1
2
3
4
5
6
7
28 2726 25 24 23 22
21
20
19
EP
18
29 *
17
16
15
8 9 10 11 121314
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
SCK
SI
SO
A0
A1
A2
RESET
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
VDD
VSS
NC
SCK
SDA
NC
MCP23S17
DS20001952C-page 1
MCP23017/MCP23S17
Functional Block Diagram
MCP23S17
CS
SCK
SI
SO
SPI
MCP23017
SCL
SDA
2
I C
3
A2:A0
GPIO
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
Decode
RESET
INTA
INTB
GPIO
GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0
Serializer/
Deserializer
Control
16
Interrupt
Logic
8
Configuration/
Control
Registers
DS20001952C-page 2
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +5.5V
Voltage on all other pins with respect to VSS (except VDD)............................................................. -0.6V to (VDD + 0.6V)
Total power dissipation.........................................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................125 mA
Input clamp current, IIK (VI < 0 or VI > VDD).......................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA
Maximum output current sunk by any output pin ....................................................................................................25 mA
Maximum output current sourced by any output pin ...............................................................................................25 mA
ESD protection on all pins (HBM:MM) ..............................................................................................................4 kV:400V
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
 2005-2016 Microchip Technology Inc.
DS20001952C-page 3
MCP23017/MCP23S17
1.1
DC Characteristics
TABLE 1-1:
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, 1.8V VDD  5.5V at -40C  TA  +125C
Param.
No.
Characteristic
Sym.
Min.
Typ.(1)
Max.
Units
Conditions
D001
Supply Voltage
VDD
1.8
—
5.5
V
D002
VDD Start Voltage to
ensure Power-on Reset
VPOR
—
VSS
—
V
D003
VDD Rise Rate to ensure
Power-on Reset
SVDD
0.05
—
—
V/ms
D004
Supply Current
IDD
—
—
1
mA
SCL/SCK = 1 MHz
D005
Standby current
IDDS8
—
—
1
µA
-40°C  TA  +85°C
—
—
3
µA
4.5V VDD 5.5V
+85°C  TA +125C
(Note 1)
Design guidance only.
Not tested.
Input Low Voltage
D030
A0, A1, A2 (TTL buffer)
VIL
VSS
—
0.15 VDD
V
D031
CS, GPIO, SCL/SCK,
SDA, RESET
(Schmitt Trigger)
VIL
VSS
—
0.2 VDD
V
Input High Voltage
D040
A0, A1, A2 (TTL buffer)
VIH
0.25 VDD + 0.8
—
VDD
V
D041
CS, GPIO, SCL/SCK,
SDA, RESET
(Schmitt Trigger)
VIH
0.8 VDD
—
VDD
V
For entire VDD range
IIL
—
—
±1
µA
VSS VPIN VDD
Input Leakage Current
D060
I/O port pins
Output Leakage Current
D065
I/O port pins
ILO
—
—
±1
µA
VSS VPIN VDD
D070
GPIO weak pull-up
current
IPU
40
75
115
µA
VDD = 5V
GP pins = VSS
GPIO
VOL
—
—
0.6
V
IOL = 8.0 mA
VDD = 4.5V
INT
VOL
—
—
0.6
V
IOL = 1.6 mA
VDD = 4.5V
SO, SDA
VOL
—
—
0.6
V
IOL = 3.0 mA
VDD = 1.8V
SDA
VOL
—
—
0.8
V
IOL = 3.0 mA
VDD = 4.5V
VOH
VDD – 0.7
—
—
V
IOH = -3.0 mA
VDD = 4.5V
VDD – 0.7
—
—
Output Low-Voltage
D080
Output High-Voltage
D090
GPIO, INT, SO
IOH = -400 µA
VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101
GPIO, SO, INT
CIO
—
—
50
pF
D102
SDA
CB
—
—
400
pF
Note 1:
This parameter is characterized, not 100% tested.
DS20001952C-page 4
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
1.2
AC Characteristics
FIGURE 1-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
VDD
Pin
1 k
SCL and
SDA pin
MCP23017
50 pF
135 pF
FIGURE 1-2:
RESET AND DEVICE RESET TIMER TIMING
VDD
RESET
30
32
Internal
RESET
34
Output pin
TABLE 1-2:
DEVICE RESET SPECIFICATIONS
AC Characteristics: Unless otherwise noted, 1.8V VDD  5.5V at -40C  TA  +125C
Param.
No.
Characteristic
Sym.
Min.
Typ. (1)
Max.
Units
30
RESET Pulse Width
(Low)
TRSTL
1
—
—
µs
32
Device Active After Reset
high
THLD
—
0
—
ns
34
Output High-Impedance
From RESET Low
TIOZ
—
—
1
µs
Note 1:
Conditions
VDD = 5.0V
This parameter is characterized, not 100% tested.
 2005-2016 Microchip Technology Inc.
DS20001952C-page 5
MCP23017/MCP23S17
I2C BUS START/STOP BITS TIMING
FIGURE 1-3:
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
I2C BUS DATA TIMING
FIGURE 1-4:
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
TABLE 1-3:
I2C BUS DATA REQUIREMENTS
I2C Interface AC Characteristics: Unless otherwise noted, 1.8V VDD  5.5V at -40C  TA  +125C, RPU (SCL,
SDA) = 1 k, CL (SCL, SDA) = 135 pF
Param.
No.
100
Characteristic
Clock High Time:
Sym.
—
µs
1.8V – 5.5V
0.6
—
—
µs
2.7V – 5.5V
0.12
—
—
µs
4.5V – 5.5V
4.7
—
—
µs
1.8V – 5.5V
Clock Low Time:
TLOW
400 kHz mode
1.3
—
—
µs
2.7V – 5.5V
1.7 MHz mode
0.32
—
—
µs
4.5V – 5.5V
—
1000
ns
1.8V – 5.5V
SDA and SCL Rise Time:
TR (1)
—
400 kHz mode
20 + 0.1 CB
1.7 MHz mode
SDA and SCL Fall Time:
100 kHz mode
400 kHz mode
1.7 MHz mode
Note 1:
2:
—
Conditions
1.7 MHz mode
100 kHz mode
103
4.0
Max. Units
400 kHz mode
100 kHz mode
102
Typ.
THIGH
100 kHz mode
101
Min.
(2)
20
—
300
ns
2.7V – 5.5V
—
160
ns
4.5V – 5.5V
—
300
ns
1.8V – 5.5V
—
300
ns
2.7V – 5.5V
—
80
ns
4.5V – 5.5V
TF (1)
—
20 + 0.1 CB
20
(2)
This parameter is characterized, not 100% tested.
CB is specified to be from 10 to 400 pF.
DS20001952C-page 6
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
TABLE 1-3:
I2C BUS DATA REQUIREMENTS (CONTINUED)
I2C Interface AC Characteristics: Unless otherwise noted, 1.8V VDD  5.5V at -40C  TA  +125C, RPU (SCL,
SDA) = 1 k, CL (SCL, SDA) = 135 pF
Param.
No.
Characteristic
Sym.
90
START Condition Setup Time:
TSU:STA
Min.
Typ.
100 kHz mode
4.7
—
—
µs
1.8V – 5.5V
400 kHz mode
0.6
—
—
µs
2.7V – 5.5V
0.16
—
—
µs
4.5V – 5.5V
100 kHz mode
4.0
—
—
µs
1.8V – 5.5V
400 kHz mode
0.6
—
—
µs
2.7V – 5.5V
0.16
—
—
µs
4.5V – 5.5V
100 kHz mode
0
—
3.45
µs
1.8V – 5.5V
400 kHz mode
0
—
0.9
µs
2.7V – 5.5V
0
—
0.15
µs
4.5V – 5.5V
100 kHz mode
250
—
—
ns
1.8V – 5.5V
400 kHz mode
100
—
—
ns
2.7V – 5.5V
0.01
—
—
µs
4.5V – 5.5V
100 kHz mode
4.0
—
—
µs
1.8V – 5.5V
400 kHz mode
0.6
—
—
µs
2.7V – 5.5V
0.16
—
—
µs
4.5V–5.5V
100 kHz mode
—
—
3.45
µs
1.8V – 5.5V
400 kHz mode
—
—
0.9
µs
2.7V – 5.5V
—
—
0.18
µs
4.5V – 5.5V
100 kHz mode
4.7
—
—
µs
1.8V – 5.5V
400 kHz mode
1.3
—
—
µs
2.7V – 5.5V
N/A
—
N/A
µs
4.5V – 5.5V
100 kHz and 400 kHz
—
—
400
pF
Note 1
1.7 MHz
—
—
100
pF
Note 1
100 kHz and 400 kHz
—
—
50
ns
1.7 MHz
—
—
10
ns
1.7 MHz mode
91
START Condition Hold Time:
Data Input Hold Time:
THD:DAT
1.7 MHz mode
107
Data Input Setup Time:
TSU:DAT
1.7 MHz mode
92
Stop Condition Setup Time:
TSU:STO
1.7 MHz mode
109
Output Valid From Clock:
TAA
1.7 MHz mode
110
Bus Free Time:
TBUF
1.7 MHz mode
111
112
Note 1:
2:
Bus Capacitive Loading:
Input Filter Spike Suppression
(SDA and SCL):
Conditions
THD:STA
1.7 MHz mode
106
Max. Units
CB
TSP
Spike suppression off
This parameter is characterized, not 100% tested.
CB is specified to be from 10 to 400 pF.
 2005-2016 Microchip Technology Inc.
DS20001952C-page 7
MCP23017/MCP23S17
FIGURE 1-5:
SPI INPUT TIMING
3
CS (1)
11
10
6
1
2
7
Mode 1,1
SCK Mode 0,0
4
5
SI
MSB in
LSB in
High-Impedance
SO
Note 1:
When using SPI Mode 1,1 the CS pin needs to be toggled once before the first communication after
power-up.
FIGURE 1-6:
SPI OUTPUT TIMING
CS
8
2
9
SCK
Mode 1,1
Mode 0,0
12
14
13
SO
MSB out
LSB out
Don’t Care
SI
TABLE 1-4:
SPI INTERFACE REQUIREMENTS
SPI Interface AC Characteristics: Unless otherwise noted, 1.8V VDD  5.5V at -40C  TA  +125C
Param.
No.
—
Characteristic
Clock Frequency
Sym.
Min.
Typ.
Max.
Units
Conditions
FCLK
—
—
5
MHz
1.8V – 5.5V
—
—
10
MHz
2.7V – 5.5V
—
—
10
MHz
4.5V – 5.5V
1
CS Setup Time
TCSS
50
—
—
ns
2
CS Hold Time
TCSH
100
—
—
ns
1.8V – 5.5V
50
—
—
ns
2.7V – 5.5V
100
—
—
ns
1.8V – 5.5V
50
—
—
ns
2.7V – 5.5V
20
—
—
ns
1.8V – 5.5V
10
—
—
ns
2.7V – 5.5V
3
4
Note 1:
CS Disable Time
Data Setup Time
TCSD
TSU
This parameter is characterized, not 100% tested.
DS20001952C-page 8
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
TABLE 1-4:
SPI INTERFACE REQUIREMENTS (CONTINUED)
SPI Interface AC Characteristics: Unless otherwise noted, 1.8V VDD  5.5V at -40C  TA  +125C
Param.
No.
5
Characteristic
Data Hold Time
Sym.
Min.
Typ.
Max.
Units
Conditions
THD
20
—
—
ns
1.8V – 5.5V
10
—
—
ns
2.7V – 5.5V
—
2
µs
Note 1
6
CLK Rise Time
TR
—
7
CLK Fall Time
TF
—
—
2
µs
Note 1
8
Clock High Time
THI
90
—
—
ns
1.8V – 5.5V
45
—
—
ns
2.7V – 5.5V
90
—
—
ns
1.8V – 5.5V
45
—
—
ns
2.7V – 5.5V
—
—
ns
9
Clock Low Time
TLO
10
Clock Delay Time
TCLD
50
11
Clock Enable Time
TCLE
50
—
—
ns
12
Output Valid from Clock Low
TV
—
—
90
ns
1.8V – 5.5V
—
—
45
ns
2.7V – 5.5V
13
Output Hold Time
THO
0
—
—
ns
14
Output Disable Time
TDIS
—
—
100
ns
Note 1:
This parameter is characterized, not 100% tested.
FIGURE 1-7:
GPIO AND INT TIMING
SCL/SCK
SDA/SI
In
D1
D0
LSb of data byte zero
during a write or read
command, depending
on parameter
50
GPn
Output
Pin
51
INT
Pin
INT Pin Active
GPn
Input
Pin
Inactive
53
52
Register
Loaded
 2005-2016 Microchip Technology Inc.
DS20001952C-page 9
MCP23017/MCP23S17
TABLE 1-5:
GP AND INT PINS REQUIREMENTS
GP and INT Pins AC Characteristics: Unless otherwise noted, 1.8V VDD  5.5V at -40C  TA  +125C
Param.
No.
Characteristic
Sym.
Min.
Typ.
Max.
Units
50
Serial Data to Output Valid
TGPOV
—
—
500
ns
51
Interrupt Pin Disable Time
TINTD
—
—
600
ns
52
GP Input Change to
Register Valid
TGPIV
—
—
450
ns
53
IOC Event to INT Active
TGPINT
—
—
600
ns
Glitch Filter on GP Pins
TGLITCH
—
—
150
ns
Note 1:
Conditions
Note 1
This parameter is characterized, not 100% tested.
DS20001952C-page 10
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PINOUT DESCRIPTION
QFN
SOIC
SPDIP
SSOP
Pin
Type
Function
GPB0
25
1
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB1
26
2
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB2
27
3
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB3
28
4
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB4
1
5
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB5
2
6
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB6
3
7
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB7
4
8
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
VDD
5
9
P
Power
VSS
6
10
P
Ground
NC/CS
7
11
I
NC (MCP23017)/Chip Select (MCP23S17)
SCK
8
12
I
Serial clock input
SDA/SI
9
13
I/O
Serial data I/O (MCP23017)/Serial data input (MCP23S17)
NC/SO
10
14
O
NC (MCP23017)/Serial data out (MCP23S17)
A0
11
15
I
Hardware address pin. Must be externally biased.
A1
12
16
I
Hardware address pin. Must be externally biased.
A2
13
17
I
Hardware address pin. Must be externally biased.
RESET
14
18
I
Hardware reset. Must be externally biased.
INTB
15
19
O
Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
INTA
16
20
O
Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.
GPA0
17
21
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA1
18
22
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA2
19
23
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA3
20
24
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA4
21
25
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA5
22
26
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA6
23
27
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA7
24
28
I/O
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
EP
29
—
—
Exposed Thermal Pad. Either connect to VSS, or leave unconnected.
Pin
Name
 2005-2016 Microchip Technology Inc.
DS20001952C-page 11
MCP23017/MCP23S17
3.0
DEVICE OVERVIEW
The MCP23017/MCP23S17 (MCP23X17) device
family provides 16-bit, general purpose parallel I/O
expansion for I2C bus or SPI applications. The two
devices differ only in the serial interface:
• MCP23017 – I2C interface
• MCP23S17 – SPI interface
The MCP23X17 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits (IODIRA/B).
The data for each input or output is kept in the
corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity
Inversion register. All registers can be read by the
system master.
The 16-bit I/O port functionally consists of two 8-bit
ports (PORTA and PORTB). The MCP23X17 can be
configured to operate in the 8-bit or 16-bit modes via
IOCON.BANK.
There are two interrupt pins, INTA and INTB, that can
be associated with their respective ports, or can be
logically OR’ed together so that both pins will activate if
either port causes an interrupt.
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1.
2.
When any input state differs from its
corresponding Input Port register state. This is
used to indicate to the system master that an
input state has changed.
When an input state differs from a preconfigured
register value (DEFVAL register).
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
3.2
Serial Interface
This block handles the functionality of the I2C
(MCP23017) or SPI (MCP23S17) interface protocol.
The MCP23X17 contains 22 individual registers (11
register pairs) that can be addressed through the Serial
Interface block, as shown in Table 3-1.
TABLE 3-1:
REGISTER ADDRESSES
Address
Address
IOCON.BANK = 1 IOCON.BANK = 0
00h
10h
01h
11h
02h
12h
03h
13h
04h
14h
05h
15h
06h
16h
07h
17h
08h
18h
09h
19h
0Ah
1Ah
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
Access to:
IODIRA
IODIRB
IPOLA
IPOLB
GPINTENA
GPINTENB
DEFVALA
DEFVALB
INTCONA
INTCONB
IOCON
IOCON
GPPUA
GPPUB
INTFA
INTFB
INTCAPA
INTCAPB
GPIOA
GPIOB
OLATA
OLATB
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pins are used to determine the
device address.
3.1
Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until
VDD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in Section 1.0
“Electrical Characteristics”.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
DS20001952C-page 12
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.2.1
BYTE MODE AND SEQUENTIAL
MODE
These two modes are not to be confused with single
writes/reads and continuous writes/reads that are
serial protocol sequences. For example, the device
may be configured for Byte mode and the master may
perform a continuous read. In this case, the
MCP23X17 would not increment the Address Pointer
and would repeatedly drive data from the same
location.
The MCP23X17 family has the ability to operate in Byte
mode or Sequential mode (IOCON.SEQOP).
Byte mode disables automatic Address Pointer
incrementing. When operating in Byte mode, the
MCP23X17 family does not increment its internal
address counter after each byte during the data
transfer. This gives the ability to continually access the
same address by providing extra clocks (without
additional control bytes). This is useful for polling the
GPIO register for data changes or for continually
writing to the output latches.
3.2.2
3.2.2.1
I2C Write Operation
The I2C write operation includes the control byte and
register address sequence, as shown in Figure 3-1.
This sequence is followed by eight bits of data from the
master and an Acknowledge (ACK) from the
MCP23017. The operation is ended with a Stop (P) or
Restart (SR) condition being generated by the master.
A special mode (Byte mode with IOCON.BANK = 0)
causes the address pointer to toggle between
associated A/B register pairs. For example, if the BANK
bit is cleared and the Address Pointer is initially set to
address 12h (GPIOA) or 13h (GPIOB), the pointer will
toggle between GPIOA and GPIOB. Note that the
Address Pointer can initially point to either address in
the register pair.
Data is written to the MCP23017 after every byte
transfer. If a Stop or Restart condition is generated
during a data transfer, the data will not be written to the
MCP23017.
Sequential mode enables automatic address pointer
incrementing. When operating in Sequential mode, the
MCP23X17 family increments its address counter after
each byte during the data transfer. The Address Pointer
automatically rolls over to address 00h after accessing
the last register.
FIGURE 3-1:
I2C INTERFACE
Both “byte writes” and “sequential writes” are
supported by the MCP23017. If Sequential mode is
enabled
(IOCON,
SEQOP = 0) (default),
the
MCP23017 increments its address counter after each
ACK during the data transfer.
BYTE AND SEQUENTIAL WRITE
S - Start
SR - Restart
Byte
S
OP
W
ADDR
DIN
Sequential
S
OP
W ADDR
DIN
P
....
DIN
P
P - Stop
W - Write
R - Read
OP
- Device opcode
ADDR
- Device register address
DOUT
- Data out from MCP23017
DIN
- Data in to MCP23017
 2005-2016 Microchip Technology Inc.
DS20001952C-page 13
MCP23017/MCP23S17
3.2.2.2
I2C Read Operation
I2C Read operations include the control byte sequence,
as shown in Figure 3-2. This sequence is followed by
another control byte (including the Start condition and
ACK) with the R/W bit set (R/W = 1). The MCP23017
then transmits the data contained in the addressed
register. The sequence is ended with the master
generating a Stop or Restart condition.
FIGURE 3-2:
3.2.2.3
BYTE AND SEQUENTIAL READ
Byte S
OP
W
SR
OP
R
DOUT
Sequential S
OP
W
SR
OP
R
DOUT
I2C Sequential Write/Read
P
DOUT
....
P
The sequence ends with the master sending a Stop or
Restart condition.
For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 3.2.1 “Byte Mode
and Sequential Mode” for details regarding sequential
operation control).
The MCP23017 Address Pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 3-3.
MCP23017 I2C DEVICE PROTOCOL
FIGURE 3-3:
S
OP
DIN
W ADDR
DIN
....
P
SR
OP
R
DOUT ....
D OUT
P
SR
OP
W
DIN
DIN
P
....
P
S
OP
DOUT
R
SR
SR
OP
OP
W
DOUT
....
R
ADDR
P
DOUT
....
DOUT
P
DIN
....
DIN
P
P
DS20001952C-page 14
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.2.3
SPI INTERFACE
3.2.3.1
four fixed bits and three user-defined hardware
address bits (pins A2, A1 and A0). Figure 3-4 shows
the control byte format.
SPI Write Operation
The SPI write operation is started by lowering CS. The
Write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
3.2.3.2
3.3.2
ADDRESSING SPI DEVICES
(MCP23S17)
The MCP23S17 is a slave SPI device. The slave
address contains four fixed bits and three user-defined
hardware address bits (if enabled via IOCON.HAEN)
(pins A2, A1 and A0) with the read/write bit filling out
the control byte. Figure 3-5 shows the control byte
format. The address pins should be externally biased
even if disabled (IOCON.HAEN = 0).
SPI Read Operation
The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
I2C CONTROL BYTE
FORMAT
FIGURE 3-4:
3.2.3.3
SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the Address Pointer. (see Section 3.2.1
“Byte Mode and Sequential Mode” for details
regarding sequential operation control).
Control Byte
S
1
0
0
A2 A1 A0 R/W ACK
Slave Address
The sequence ends by the raising of CS.
Start
bit
The MCP23S17 Address Pointer will roll over to
address zero after reaching the last register address.
3.3
0
R/W bit
ACK bit
R/W = 0 = write
R/W = 1 = read
Hardware Address Decoder
FIGURE 3-5:
The hardware address pins are used to determine the
device address. To address a device, the corresponding address bits in the control byte must match the pin
state. The pins must be biased externally.
3.3.1
SPI CONTROL BYTE
FORMAT
CS
ADDRESSING I2C DEVICES
(MCP23017)
Control Byte
0
1
The MCP23017 is a slave I2C interface device that
supports 7-bit slave addressing, with the read/write bit
filling out the control byte. The slave address contains
0
0
A2 A1 A0 R/W
Slave Address
R/W bit
R/W = 0 = write
R/W = 1 = read
I2C ADDRESSING REGISTERS
FIGURE 3-6:
S
0
1
0
0
A2 A1 A0
0
ACK *
A7
A6
A5
A4
A3
A2
A1
A0
ACK *
R/W = 0
Device Opcode
Register Address
*The ACKs are provided by the MCP23017.
 2005-2016 Microchip Technology Inc.
DS20001952C-page 15
MCP23017/MCP23S17
FIGURE 3-7:
SPI ADDRESSING REGISTERS
CS
0
1
0
0
A2 * A1 * A0 * R/W
A7
A6
A5
Device Opcode
A4
A3
A2
A1
A0
Register Address
* Address pins are enabled/disabled via IOCON.HAEN.
3.4
GPIO Port
Reading the GPIOn register reads the value on the
port. Reading the OLATn register only reads the
latches, not the actual value on the port.
The GPIO module is a general purpose, 16-bit wide,
bidirectional port that is functionally split into two
8-bit wide ports.
Writing to the GPIOn register actually causes a write to
the latches (OLATn). Writing to the OLATn register
forces the associated output drivers to drive to the level
in OLATn. Pins configured as inputs turn off the
associated output driver and put it in high-impedance.
The GPIO module contains the data ports (GPIOn),
internal pull-up resistors and the output latches
(OLATn).
TABLE 3-2:
Register
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1)
Address
(hex)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
POR/RST
value
IODIRA
00
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IPOLA
01
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
GPINTENA
02
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
GPPUA
06
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
GPIOA
09
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
OLATA
0A
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
IODIRB
10
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IPOLB
11
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
GPINTENB
12
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
GPPUB
16
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
GPIOB
19
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
OLATB
1A
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
TABLE 3-3:
Register
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0)
Address
(hex)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
POR/RST
value
IODIRA
00
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IODIRB
01
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IPOLA
02
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
IPOLB
03
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
GPINTENA
04
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
GPINTENB
05
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
GPPUA
0C
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
GPPUB
0D
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
GPIOA
12
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
GPIOB
13
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
OLATA
14
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
OLATB
15
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
DS20001952C-page 16
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.5
Configuration and Control
Registers
associated with PORTB. One register (IOCON) is
shared between the two ports. The PORTA registers
are identical to the PORTB registers, therefore, they
will be referred to without differentiating between the
port designation (i.e., they will not have the “A” or “B”
designator assigned) in the register tables.
There are 21 registers associated with the MCP23X17,
as shown in Tables 3-4 and3-5. The two tables show
the register mapping with the two BANK bit values. Ten
registers are associated with PORTA and ten are
TABLE 3-4:
Register
Name
CONTROL REGISTER SUMMARY (IOCON.BANK = 1)
Address
(hex)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
POR/RST
value
00
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IODIRA
IPOLA
01
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
GPINTENA
02
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
DEFVALA
03
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
DEF1
DEF0
0000 0000
INTCONA
04
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
0000 0000
IOCON
05
BANK
MIRROR
SEQOP
DISSLW
HAEN
ODR
INTPOL
—
0000 0000
GPPUA
06
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
INTFA
07
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INTO
0000 0000
INTCAPA
08
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
0000 0000
GPIOA
09
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
OLATA
0A
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
IODIRB
10
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IPOLB
11
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
GPINTENB
12
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
DEFVALB
13
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
DEF1
DEF0
0000 0000
INTCONB
14
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
0000 0000
IOCON
15
BANK
MIRROR
SEQOP
DISSLW
HAEN
ODR
INTPOL
—
0000 0000
GPPUB
16
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
INTFB
17
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INTO
0000 0000
INTCAPB
18
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
0000 0000
GPIOB
19
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
OLATB
1A
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
bit 1
bit 0
POR/RST
value
TABLE 3-5:
Register
Name
CONTROL REGISTER SUMMARY (IOCON.BANK = 0)
Address
(hex)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
IODIRA
00
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IODIRB
01
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1111 1111
IPOLA
02
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
IPOLB
03
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
0000 0000
GPINTENA
04
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
GPINTENB
05
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
0000 0000
DEFVALA
06
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
DEF1
DEF0
0000 0000
DEFVALB
07
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
DEF1
DEF0
0000 0000
INTCONA
08
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
0000 0000
INTCONB
09
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
0000 0000
IOCON
0A
BANK
MIRROR
SEQOP
DISSLW
HAEN
ODR
INTPOL
—
0000 0000
IOCON
0B
BANK
MIRROR
SEQOP
DISSLW
HAEN
ODR
INTPOL
—
0000 0000
GPPUA
0C
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
GPPUB
0D
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
0000 0000
 2005-2016 Microchip Technology Inc.
DS20001952C-page 17
MCP23017/MCP23S17
TABLE 3-5:
CONTROL REGISTER SUMMARY (IOCON.BANK = 0) (CONTINUED)
Address
(hex)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
POR/RST
value
INTFA
0E
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INTO
0000 0000
INTFB
0F
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INTO
0000 0000
INTCAPA
10
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
0000 0000
INTCAPB
11
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
0000 0000
GPIOA
12
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
GPIOB
13
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0000 0000
OLATA
14
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
OLATB
15
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
0000 0000
Register
Name
3.5.1
I/O DIRECTION REGISTER
Controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
becomes an output.
REGISTER 3-1:
IODIR: I/O DIRECTION REGISTER (ADDR 0x00)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
3.5.2
x = Bit is unknown
IO<7:0>: Controls the direction of data I/O <7:0>
1 = Pin is configured as an input.
0 = Pin is configured as an output.
INPUT POLARITY REGISTER
This register allows the user to configure the polarity on
the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inverted value on the pin.
REGISTER 3-2:
IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
IP<7:0>: Controls the polarity inversion of the input pins <7:0>
1 = GPIO register bit reflects the opposite logic state of the input pin.
0 = GPIO register bit reflects the same logic state of the input pin.
DS20001952C-page 18
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.5.3
INTERRUPT-ON-CHANGE
CONTROL REGISTER
The
GPINTEN
register
controls
interrupt-on-change feature for each pin.
the
If a bit is set, the corresponding pin is enabled for
interrupt-on-change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for interrupt-on-change.
REGISTER 3-3:
GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GPINT7
GPINT6
GPINT5
GPINT4
GPINT3
GPINT2
GPINT1
GPINT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
3.5.4
x = Bit is unknown
GPINT<7:0>: General purpose I/O interrupt-on-change bits <7:0>
1 = Enables GPIO input pin for interrupt-on-change event.
0 = Disables GPIO input pin for interrupt-on-change event.
Refer to INTCON.
DEFAULT COMPARE REGISTER
FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
interrupt to occur.
REGISTER 3-4:
DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
DEF1
DEF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
2:
x = Bit is unknown
DEF<7:0>: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>
(Note 1)
If the associated pin level is the opposite from the register bit, an interrupt occurs. (Note 2)
Refer to INTCON.
Refer to INTCON and GPINTEN.
 2005-2016 Microchip Technology Inc.
DS20001952C-page 19
MCP23017/MCP23S17
3.5.5
INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin
value is compared for the interrupt-on-change feature.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in the DEFVAL register. If a
bit value is clear, the corresponding I/O pin is compared
against the previous value.
REGISTER 3-5:
INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
3.5.6
x = Bit is unknown
IOC<7:0>: Controls how the associated pin value is compared for interrupt-on-change <7:0>
1 = Pin value is compared against the associated bit in the DEFVAL register.
0 = Pin value is compared against the previous pin value.
Refer to INTCON and GPINTEN.
CONFIGURATION REGISTER
The IOCON register
configuring the device:
contains
several
bits
for
The BANK bit changes how the registers are mapped
(see Tables 3-4 and3-5 for more details).
• If BANK = 1, the registers associated with each
port are segregated. Registers associated with
PORTA are mapped from address 00h - 0Ah and
registers associated with PORTB are mapped
from 10h - 1Ah.
• If BANK = 0, the A/B registers are paired. For
example, IODIRA is mapped to address 00h and
IODIRB is mapped to the next address (address
01h). The mapping for all registers is from 00h
-15h.
It is important to take care when changing the BANK bit
as the address mapping changes after the byte is
clocked into the device. The address pointer may point
to an invalid location after the bit is modified.
For example, if the device is configured to
automatically increment its internal Address Pointer,
the following scenario would occur:
• BANK = 0
• Write 80h to address 0Ah (IOCON) to set the
BANK bit
• Once the write completes, the internal address
now points to 0Bh which is an invalid address
when the BANK bit is set.
DS20001952C-page 20
For this reason, when changing the BANK bit, it is
advised to only perform byte writes to this register.
The MIRROR bit controls how the INTA and INTB pins
function with respect to each other.
• When MIRROR = 1, the INTn pins are functionally
OR’ed so that an interrupt on either port will cause
both pins to activate.
• When MIRROR = 0, the INT pins are separated.
Interrupt conditions on a port will cause its
respective INT pin to activate.
The Sequential Operation (SEQOP) controls the
incrementing function of the Address Pointer. If the
address pointer is disabled, the Address Pointer does
not automatically increment after each byte is clocked
during a serial transfer. This feature is useful when it is
desired to continuously poll (read) or modify (write) a
register.
The Slew Rate (DISSLW) bit controls the slew rate
function on the SDA pin. If enabled, the SDA slew rate
will be controlled when driving from a high to low.
The Hardware Address Enable (HAEN) bit
enables/disables hardware addressing on the
MCP23S17 only. The address pins (A2, A1 and A0)
must be externally biased, regardless of the HAEN bit
value.
If enabled (HAEN = 1), the device’s hardware address
matches the address pins.
If disabled (HAEN = 0), the device’s hardware address
is A2 = A1 = A0 = 0.
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
The Open-Drain (ODR) control bit enables/disables the
INT pin for open-drain configuration. Setting this bit
overrides the INTPOL bit.
REGISTER 3-6:
The Interrupt Polarity (INTPOL) sets the polarity of the
INT pin. This bit is functional only when the ODR bit is
cleared, configuring the INT pin as active push-pull.
IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
BANK
MIRROR
SEQOP
DISSLW
HAEN
ODR
INTPOL
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
BANK: Controls how the registers are addressed
1 = The registers associated with each port are separated into different banks.
0 = The registers are in the same bank (addresses are sequential).
bit 6
MIRROR: INT Pins Mirror bit
1 = The INT pins are internally connected
0 = The INT pins are not connected. INTA is associated with PORTA and INTB is associated with
PORTB
bit 5
SEQOP: Sequential Operation mode bit
1 = Sequential operation disabled, address pointer does not increment.
0 = Sequential operation enabled, address pointer increments.
bit 4
DISSLW: Slew Rate control bit for SDA output
1 = Slew rate disabled
0 = Slew rate enabled
bit 3
HAEN: Hardware Address Enable bit (MCP23S17 only) (Note 1)
1 = Enables the MCP23S17 address pins.
0 = Disables the MCP23S17 address pins.
bit 2
ODR: Configures the INT pin as an open-drain output
1 = Open-drain output (overrides the INTPOL bit.)
0 = Active driver output (INTPOL bit sets the polarity.)
bit 1
INTPOL: This bit sets the polarity of the INT output pin
1 = Active-high
0 = Active-low
bit 0
Unimplemented: Read as ‘0’
Note 1:
Address pins are always enabled on the MCP23017.
 2005-2016 Microchip Technology Inc.
DS20001952C-page 21
MCP23017/MCP23S17
3.5.7
PULL-UP RESISTOR
CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the
port pins. If a bit is set and the corresponding pin is
configured as an input, the corresponding port pin is
internally pulled up with a 100 k resistor.
REGISTER 3-7:
GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
3.5.8
x = Bit is unknown
PU<7:0> Controls the weak pull-up resistors on each pin (when configured as an input)
1 = Pull-up enabled
0 = Pull-up disabled
INTERRUPT FLAG REGISTER
The INTF register reflects the interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A set bit indicates that the
associated pin caused the interrupt.
This register is read-only. Writes to this register will be
ignored.
REGISTER 3-8:
INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
INT<7:0>: Reflects the interrupt condition on the port. It reflects the change only if interrupts are
enabled per GPINTEN<7:0>.
1 = Pin caused interrupt.
0 = Interrupt not pending
DS20001952C-page 22
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.5.9
INTERRUPT CAPTURED REGISTER
The INTCAP register captures the GPIO port value at
the time the interrupt occurred. The register is
read-only and is updated only when an interrupt
occurs. The register remains unchanged until the
interrupt is cleared via a read of INTCAP or GPIO.
REGISTER 3-9:
INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ICP7
ICP6
ICP5
ICP4
ICP3
ICP2
ICP1
ICP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
3.5.10
x = Bit is unknown
ICP<7:0>: Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0>
1 = Logic-high
0 = Logic-low
PORT REGISTER
The GPIO register reflects the value on the port.
Reading from this register reads the port. Writing to this
register modifies the Output Latch (OLAT) register.
REGISTER 3-10:
GPIO: GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
GP<7:0>: Reflects the logic level on the pins <7:0>
1 = Logic-high
0 = Logic-low
 2005-2016 Microchip Technology Inc.
DS20001952C-page 23
MCP23017/MCP23S17
3.5.11
OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modifies the pins
configured as outputs.
REGISTER 3-11:
OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OL7
OL6
OL5
OL4
OL3
OL2
OL1
OL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
3.6
x = Bit is unknown
OL<7:0>: Reflects the logic level on the output latch <7:0>
1 = Logic-high
0 = Logic-low
Interrupt Logic
If enabled, the MCP23X17 activates the INTn interrupt
output when one of the port pins changes state or when
a pin does not match the preconfigured default. Each
pin is individually configurable as follows:
• Enable/disable interrupt via GPINTEN
• Can interrupt on either pin change or change from
default as configured in DEFVAL
Both conditions are referred to as Interrupt-on-Change
(IOC).
The interrupt control module uses the following
registers/bits:
If IOCON.MIRROR = 1, the internal signals are OR’ed
together and routed to the INTn pads. In this case, the
interrupt will only be cleared if the associated GPIO or
INTCAP is read (see Table 3-6).
TABLE 3-6:
Interrupt
Condition
GPIOA
GPIOB
INTERRUPT OPERATION
(IOCON.MIRROR = 1)
Interrupt
Result
Read PORTn (1)
PORTA
Clear
PORTB
Unchanged
PORTA
Unchanged
PORTB
Clear
• IOCON.MIRROR – controls if the two interrupt
pins mirror each other
• GPINTEN – Interrupt enable register
• INTCON – controls the source for the IOC
• DEFVAL – contains the register default for IOC
operation
Note 1:
PORTn = GPIOn or INTCAPn
3.6.1
3.6.2
IOC FROM PIN CHANGE
INTA AND INTB
There are two interrupt pins: INTA and INTB. By
default, INTA is associated with GPAn pins (PORTA)
and INTB is associated with GPBn pins (PORTB).
Each port has an independent signal which is cleared if
its associated GPIO or INTCAP register is read.
3.6.1.1
Mirroring the INT pins
Additionally, the INTn pins can be configured to mirror
each other so that any interrupt will cause both pins to
go active. This is controlled via IOCON.MIRROR.
GPIOA and
GPIOB
PORTA
Unchanged
PORTB
Unchanged
Both PORTA and
PORTB
Clear
If enabled, the MCP23X17 generates an interrupt if a
mismatch condition exists between the current port
value and the previous port value. Only IOC-enabled
pins will be compared. Refer to Registers 3-3 and 3-5.
3.6.3
IOC FROM REGISTER DEFAULT
If enabled, the MCP23X17 generates an interrupt if a
mismatch occurs between the DEFVAL register and
the port. Only IOC enabled pins are compared. Refer to
Registers 3-3, 3-4 and 3-5.
If IOCON.MIRROR = 0, the internal signals are routed
independently to the INTA and INTB pads.
DS20001952C-page 24
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
3.6.4
INTERRUPT OPERATION
The INTn interrupt output can be configured as
active-low, active-high or open-drain via the IOCON
register.
Only those pins that are configured as an input (IODIR
register) with Interrupt-On-Change (IOC) enabled
(IOINTEN register) can cause an interrupt. Pins
defined as an output have no effect on the interrupt
output pin.
Input change activity on a port input pin that is enabled
for IOC generates an internal device interrupt and the
device captures the value of the port and copies it into
INTCAP. The interrupt remains active until the INTCAP
or GPIO register is read. Writing to these registers does
not affect the interrupt. The interrupt condition is
cleared after the LSb of the data is clocked out during
a read command of GPIO or INTCAP.
The first interrupt event causes the port contents to be
copied into the INTCAP register. Subsequent interrupt
conditions on the port will not cause an interrupt to
occur as long as the interrupt is not cleared by a read
of INTCAP or GPIO.
Note:
3.6.5
The value in INTCAP can be lost if GPIO
is read before INTCAP while another IOC
is pending. After reading GPIO, the
interrupt will clear and then set due to the
pending IOC, causing the INTCAP
register to update.
2.
INTERRUPT-ON-PIN
CHANGE
GPx
INT
ACTIVE
Port value
is captured
into INTCAP
ACTIVE
Read GPIO
or INTCAP
FIGURE 3-9:
Port value
is captured
into INTCAP
INTERRUPT-ON-CHANGE
FROM REGISTER
DEFAULT
DEFVAL REGISTER
GPx<7:0> 7
6
5
4
3
2
1
0
X
X
X
X
X
0
X
X
GP2
Pin
INT
Pin
ACTIVE
ACTIVE
INTERRUPT CONDITIONS
There are two possible configurations that cause
interrupts (configured via INTCON):
1.
FIGURE 3-8:
Pins configured for interrupt-on-pin change
will cause an interrupt to occur if a pin changes
to the opposite state. The default state is reset
after an interrupt occurs and after clearing the
interrupt condition (i.e., after reading GPIO or
INTCAP). For example, an interrupt occurs by
an input changing from ‘1’ to ‘0’. The new initial
state for the pin is a logic ‘0’ after the interrupt is
cleared.
Pins configured for interrupt-on-change from
register value will cause an interrupt to occur if
the corresponding input pin differs from the
register bit. The interrupt condition will remain as
long as the condition exists, regardless if the
INTCAP or GPIO is read.
Port value
is captured
into INTCAP
Read GPIO
or INTCAP
(INT clears only if interrupt
condition does not exist.)
See Figures 3-8 and 3-9 for more information on
interrupt operations.
 2005-2016 Microchip Technology Inc.
DS20001952C-page 25
MCP23017/MCP23S17
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
28-Lead QFN
Example:
23017
E/ML e3
1628256
28-Lead SOIC
Example:
MCP23017-E/SO e3
1628256
28-Lead SPDIP
Example:
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNN
28-Lead SSOP
Example:
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20001952C-page 26
MCP23017-E/SP e3
1628256
MCP23017
E/SS e3
1628256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
 2005-2016 Microchip Technology Inc.
DS20001952C-page 27
MCP23017/MCP23S17
DS20001952C-page 28
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
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 2005-2016 Microchip Technology Inc.
DS20001952C-page 29
MCP23017/MCP23S17
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001952C-page 30
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2005-2016 Microchip Technology Inc.
DS20001952C-page 31
MCP23017/MCP23S17
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001952C-page 32
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
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DS20001952C-page 33
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DS20001952C-page 34
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2005-2016 Microchip Technology Inc.
DS20001952C-page 35
MCP23017/MCP23S17
NOTES:
DS20001952C-page 36
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
APPENDIX A:
REVISION HISTORY
Revision C (July 2016)
The following is the list of modifications:
1.
2.
3.
4.
Added ESD data to Section 1.0, Electrical
Characteristics.
Updated Table 2-1.
Updated package outline drawings.
Minor typographical errors
Revision B (February 2007)
1.
2.
3.
4.
Changed Byte and Sequential Read in
Figure 1-1 from “R” to “W”.
Table 2-4, Param No. 51 and 53: Changed from
450 to 600 and 500 to 600, respecively.
Added disclaimers to package outline drawings.
Updated package outline drawings.
Revision A (June 2005)
• Original release of this document.
 2005-2016 Microchip Technology Inc.
DS20001952C-page 37
MCP23017/MCP23S17
NOTES:
DS20001952C-page 38
 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
–
X
/XX
Temperature
Range
Package
MCP23017:
MCP23S17:
X (1)
Tape and Reel
Option
16-Bit I/O Expander with I2C Interface
16-Bit I/O Expander with SPI Interface
Temperature
Range:
E
=
-40C to +125C (Extended)
Package:
ML
=
SO
=
Plastic Quad Flat, No Lead Package, 6x6 mm
Body, QFN, 28-lead
Plastic Small Outline, Wide, 7.50 mm Body, SOIC,
28-Lead
Skinny Plastic Dual In-Line, 300 mil Body, SPDIP,
28-Lead
Plastic Shrink Small Outline, 5.30 mm Body,
SSOP, 28-Lead
Tape and Reel
Option:
SP
=
SS
=
T
= Tape and Reel (1)
Blank = Tube
Examples:
a)
MCP23017-E/ML:
b)
MCP23017T-E/ML:
c)
MCP23017-E/SP:
d)
MCP23017-E/SO:
e)
MCP23017T-E/SO:
f)
MCP23017-E/SS:
g)
MCP23017T-E/SS:
a)
MCP23S17-E/ML:
b)
MCP23S17T-E/ML:
c)
MCP23S17-E/SP:
d)
MCP23S17-E/SO:
e)
MCP23S17T-E/SO:
f)
MCP23S17-E/SS:
g)
MCP23S17T-E/SS:
Note 1:
 2005-2016 Microchip Technology Inc.
Extended temperature,
28LD QFN package
Extended temperature,
28LD QFN package,
Tape and Reel
Extended temperature ,
28LD SPDIP package
Extended temperature,
28LD SOIC package
Extended temperature,
28LD SOIC package,
Tape and Reel
Extended temperature,
28LD SSOP package
Extended temperature,
28LD SSOP package,
Tape and Reel
Extended temperature,
28LD QFN package
Extended temperature,
28LD QFN package,
Tape and Reel
Extended temperature,
28LD SPDIP package
Extended temperature,
28LD SOIC package
Extended temperature,
28LD SOIC package,
Tape and Reel
Extended temperature,
28LD SSOP package
Extended temperature,
28LD SSOP package
Tape and Reel
Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
DS20001952C-page 39
MCP23017/MCP23S17
NOTES:
DS20001952C-page 40
 2005-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2005-2016 Microchip Technology Inc.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2005-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0755-3
DS20001952C-page 41
Worldwide Sales and Service
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Technical Support:
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Web Address:
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06/23/16
DS20001952C-page 42
 2005-2016 Microchip Technology Inc.
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