HM62256B Series 256k SRAM (32-kword × 8-bit) ADE-203-135F (Z) Rev. 6.0 Nov. 13, 1997 Description The Hitachi HM62256B Series is a CMOS static RAM organized 32,768-word × 8-bit. It realizes higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. The device, packaged in 8 × 14 mm TSOP, 8 × 13.4 mm TSOP with thickness of 1.2 mm, 450 mil SOP (foot print pitch width), 600 mil plastic DIP, or 300 mil plastic DIP, is available for high density mounting. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. Features • Single 5.0 V supply: 5.0 V ± 10% • Access time: 55 ns/70 ns/85 ns (max) • Power dissipation: Active: 25 mW (typ) (f = 1 MHz) Standby: 1.0 µW (typ) • Completely static memory No clock or timing strobe required • Equal access and cycle times • Common data input and output Three state output • Directly TTL compatible all inputs and outputs • Battery backup operation HM62256B Series Ordering Information Type No. Access time Package HM62256BLP-7 70 ns 600-mil 28-pin plastic DIP (DP-28) HM62256BLP-7SL 70 ns HM62256BLSP-7 70 ns HM62256BLSP-7SL 70 ns HM62256BLFP-7T 70 ns HM62256BLFP-5SLT HM62256BLFP-7SLT 55 ns 70 ns HM62256BLFP-7ULT 70 ns HM62256BLT-8 85 ns HM62256BLT-7SL 70 ns HM62256BLTM-8 85 ns HM62256BLTM-5SL HM62256BLTM-7SL 55 ns 70 ns HM62256BLTM-7UL 70 ns 300-mil 28-pin plastic DIP (DP-28NA) 450-mil 28-pin plastic SOP (FP-28DA) 8 mm × 14 mm 32-pin TSOP (TFP-32DA) 8 mm × 13.4 mm 28-pin TSOP (TFP-28DA) Pin Arrangement HM62256BLP/BLFP/BLSP Series A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 VSS 14 15 I/O3 (Top view) 2 HM62256B Series Pin Arrangement (cont.) HM62256BLT Series OE A11 NC A9 A8 A13 WE VCC A14 A12 A7 A6 A5 NC A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A10 CS NC I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 NC A1 A2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 (Top view) HM62256BLTM Series OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 (Top view) Pin Description Pin Name Function A0 to A14 Address input I/O0 to I/O7 Data input/output CS Chip select WE Write enable OE Output enable VCC Power supply VSS Ground NC No connection 3 HM62256B Series Block Diagram VCC (MSB) A12 VSS A5 A7 A6 A8 • • • • A13 A14 • • Row Decoder Memory Matrix 512 × 512 • • • • A4 (LSB) A3 I/O0 • • • • • • • Column I/O • • • • • • Input Data Control Column Decoder • • I/O7 • • A2 A1 A0 A10 A9 A11 (LSB) • • CS WE OE 4 Timing Pulse Generator Read/Write Control (MSB) • • HM62256B Series Operation Table WE CS OE Mode VCC current I/O pin Ref. cycle × H × Standby I SB , I SB1 High-Z — H L H Output disable I CC High-Z — H L L Read I CC Dout Read cycle (1)to (3) L L H Write I CC Din Write cycle (1) L L L Write I CC Din Write cycle (2) Note: ×: H or L Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to V SS VCC –0.5 to +7.0 1 V 2 Terminal voltage on any pin relative to V SS VT –0.5* to V CC+0.3* V Power dissipation PT 1.0 W Operating temperature range Topr 0 to +70 °C Storage temperature range Tstg –55 to +125 °C Storage temperature range under bias Tbias –10 to +85 °C Notes: 1. VT min: –3.0 V for pulse half-width ≤ 50 ns 2. Maximum voltage is 7.0 V DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.2 — VCC + 0.3 V — 0.8 V Input high voltage Input low voltage Note: VIL –0.5* 1 Notes 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns 5 HM62256B Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) Parameter Symbol Min Typ*1 Max Unit Test conditions Input leakage current |ILI| — — 1 µA Vin = VSS to V CC Output leakage current |ILO | — — 1 µA CS = VIH or OE = VIH or WE = VIL, VI/O = VSS to V CC Operating current I CC — 6 15 mA CS = VIL, Others = VIH/VIL, II/O = 0 mA Average HM62256B-5 operating current I CC1 — — 60 mA Min cycle, duty = 100%,II/O = 0 mA, CS = VIL, Others = VIH/VIL HM62256B-7 I CC1 — 33 60 mA HM62256B-8 I CC1 — 29 50 mA I CC2 — 5 15 mA Cycle time = 1 µs, II/O = 0 mA, CS = VIL, VIH = VCC, VIL = 0 I SB — 0.3 2 mA CS = VIH I SB1 — 0.2 µA Vin ≥ 0 V, CS ≥ V CC – 0.2 V Standby current I SB1 — 100 0.2* 2 3 50* 2 µA 10* 3 µA I SB1 — 0.2* Output low voltage VOL — — 0.4 V I OL = 2.1 mA Output high voltage VOH 2.4 — — V I OH = –1.0 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. 2. This characteristic is guaranteed only for L-SL version. 3. This characteristic is guaranteed only for L-UL version. Capacitance (Ta = 25°C, f = 1.0 MHz) Parameter Input capacitance* 1 Input/output capacitance* Note: 6 1 Symbol Min Typ Max Unit Test Conditions Cin — — 8 pF Vin = 0 V CI/O — — 10 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. HM62256B Series AC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10%) Test Conditions • • • • Input pulse levels: 0.8 V to 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + C L (50 pF) (HM62256B-5) 1 TTL Gate + C L (100 pF) (HM62256B-7/8) (Including scope & jig) Read Cycle HM62256B -5 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read cycle time t RC 55 — 70 — 85 — ns Address access time t AA — 55 — 70 — 85 ns Chip select to access time t ACS — 55 — 70 — 85 ns Output enable to output valid t OE — 35 — 40 — 45 ns Chip select to output in low-Z t CLZ 5 — 10 — 10 — ns 2 Output enable to output in low-Z t OLZ 5 — 5 — 5 — ns 2 Chip deselect to output in high-Z t CHZ 0 20 0 25 0 30 ns 1, 2 Output disable to output in high-Z t OHZ 0 20 0 25 0 30 ns 1, 2 Output hold from address change t OH 5 — 5 — 5 — ns 7 HM62256B Series Write Cycle HM62256B -5 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write cycle time t WC 55 — 70 — 85 — ns Chip selection to end of write t CW 40 — 60 — 75 — ns 5 Address setup time t AS 0 — 0 — 0 — ns 6 Address valid to end of write t AW 40 — 60 — 75 — ns Write pulse width t WP 35 — 50 — 55 — ns 4, 13 Write recovery time t WR 0 — 0 — 0 — ns 7 Write to output in high-Z t WHZ 0 20 0 25 0 30 ns 1, 2, 8 Data to write time overlap t DW 25 — 30 — 35 — ns Data hold from write time t DH 0 — 0 — 0 — ns Output active from end of write t OW 5 — 5 — 5 — ns 2 Output disable to output in High-Z t OHZ 0 20 0 25 0 30 ns 1, 2, 8 Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. Address must be valid prior to or simultaneously with CS going low. 4. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition of CS going low or WE going low. A write ends at the earliest transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from CS going low to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS or WE going high to the end of write cycle. 8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 9. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 10. Dout is the same phase of the latest written data in this write cycle. 11. Dout is the read data of next address. 12. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 13. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP ≥ tDW min + tWHZ max 8 HM62256B Series Timing Waveform Read Timing Waveform (1) (WE = VIH) tRC Address Valid address tAA tACS CS tOH tOE tOLZ OE tOHZ tCHZ High impedance Dout Valid data Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL ) tRC Valid address Address tAA tOH tOH Dout Valid data 9 HM62256B Series Read Timing Waveform (3) (WE = VIH, OE = VIL )*3 tACS CS tCLZ Dout tCHZ High impedance Valid data Write Timing Waveform (1) (OE Clock) tWC Address Valid address tAW tWR OE tCW CS *9 tAS tWP WE tOHZ High impedance Dout tDW Din 10 High impedance tDH Valid data HM62256B Series Write Timing Waveform (2) (OE Low Fixed) tWC Address Valid address tWR tCW CS *9 tAW tOH tWP WE tAS tWHZ tOW *10 *11 Dout tDW tDH *12 Din High impedance Valid data 11 HM62256B Series Low VCC Data Retention Characteristics (Ta = 0 to 70°C) Parameter Symbol Min Typ* 1 Max Unit Test conditions*6 VCC for data retention VDR 2.0 — 5.5 V CS ≥ V CC – 0.2 V, Vin ≥ 0V Data retention current I CCDR — 0.05 30* 2 µA VCC = 3.0 V, Vin ≥ 0V CS ≥ V CC – 0.2 V I CCDR — 0.05 10* 3 µA 4 µA I CCDR — 0.05 3* Chip deselect to data retention time t CDR 0 — — ns Operation recovery time tR t RC* 5 — — ms Notes: 1. 2. 3. 4. 5. 6. See retention Waveform Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed. 10 µA max. at Ta = 0 to +40°C. This characteristic is guaranteed only for L-SL version, 3 µA max. at Ta = 0 to +40°C. This characteristic is guaranteed only for L-UL version, 0.6 µA max. at Ta = 0 to +40°C. t RC = Read cycle time. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state. Low V CC Data Retention Timing Waveform Data retention mode VCC 4.5V tCDR tR 2.2V VDR CS 0V 12 CS ≥ VCC − 0.2V HM62256B Series Package Dimensions HM62256BLP Series (DP-28) Unit: mm 35.6 36.5 Max 15 13.4 14.6 Max 28 14 1.2 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 1.9 Max 15.24 2.54 Min 5.70 Max 1 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-28 — Conforms 4.6 g 13 HM62256B Series Package Dimensions (cont.) HM62256BLSP Series (DP-28NA) Unit: mm 36.00 14 1.30 0.48 ± 0.10 0.51 Min 2.54 ± 0.25 5.08 Max 2.20 Max 2.54 Min 1 7.40 Max 15 7.10 28 37.32 Max 7.62 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) 14 DP-28NA — Conforms 2.2 g HM62256B Series Package Dimensions (cont.) HM62256BLFP Series (FP-28DA) Unit: mm 18.00 18.75 Max 15 14 1.27 0.15 0.40 ± 0.08 0.38 ± 0.06 0.15 0.20 +– 0.10 1.12 Max 0.17 ± 0.05 0.15 ± 0.04 1 3.00 Max 8.40 28 11.80 ± 0.30 1.70 0° – 8° 1.00 ± 0.20 0.20 M Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-28DA Conforms Conforms 0.82 g 15 HM62256B Series Package Dimensions (cont.) HM62256BLT Series (TFP-32DA) Unit: mm 8.00 8.20 Max 17 1 16 12.40 32 0.50 0.08 M Dimension including the plating thickness Base material dimension 16 0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0.10 0.80 14.00 ± 0.20 0.45 Max 0.13 ± 0.05 0.22 ± 0.08 0.20 ± 0.06 0° – 5° Hitachi Code JEDEC EIAJ Weight (reference value) 0.50 ± 0.10 TFP-32DA Conforms Conforms 0.26 g HM62256B Series Package Dimensions (cont.) HM62256BLTM Series (TFP-28DA) Unit: mm 8.00 8.20 Max 8 11.80 21 22 7 28 1 0.22 ± 0.05 0.20 ± 0.04 0.55 0.10 M 0.80 13.40 ± 0.30 0.63 Max Dimension including the plating thickness Base material dimension 0.50 ± 0.10 +0.10 0.05 –0.05 0.10 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° Hitachi Code JEDEC EIAJ Weight (reference value) TFP-28DA — — 0.22 g 17 HM62256B Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 18 HM62256B Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Sep. 10, 1993 Initial Issue Y. Saito K. Yoshizaki 1.0 Mar. 23, 1994 DC Characteristics I CC1 Typ: —/—/—/— mA to 33/29/26/24 mA Y. Saito K. Yoshizaki 2.0 Oct. 31, 1994 Deletion of HM62256BLT-7/10SL/12SL Addition of HM62256BLTM-8/7SL/8SL(TFP-28DA) AC Characteristics Addition of note 12 Low VCC data retention characteristics VDR max: — to 5.5 V Note 2: 20 µA max at Ta = 0 to +40°C to 10 µA max at Ta = 0 to +40°C Deletion of description; (only for L-version) Y. Saito K. Yoshizaki 3.0 Jun. 19, 1995 M. Higuchi Change of format Deletion of HM62256BLP-8/10/12/8SL/10SL/12SL Deletion of HM62256BLSP-8/10/12/8SL/10SL/12SL Deletion of HM62256BLFP-8T/10T/12T Deletion of HM62256BLFP-8SLT/10SLT/12SLT Deletion of HM62256BLT-10/12/8SL Deletion of HM62256BLTM-8SL Addition of HM62256BLFP-4SLT/5SLT/7ULT Addition of HM62256BLTM-4SLT/5SLT/7ULT Features Fast access time: 70/85/100/120 ns to 45/55/70/85 ns DC Characteristics I CC1 typ: 33/29/26/24 mA to —/—/33/29 mA max: 60/50/50/45 mA to 70/60/60/50 mA I SB1 typ: 0.3/0.3 µA to 0.2/0.2/0.2 µA max: 100/50 µA to 100/50/10 µA Addition of note 3 AC Characteristics Change order of notes. Test Condition Addition of HM62256B-4: 1TTL Gate + CL (100pF) (Including scope & jig) t RC min: 70/85/100/120 ns to 45/55/70/85 ns t AA max: 70/85/100/120 ns to 45/55/70/85 ns t ACS max: 70/85/100/120 ns to 45/55/70/85 ns t OE max: 40/45/50/60 ns to 30/35/40/45 ns t CLZ min: 10/10/10/10 ns to 5/5/10/10 ns t OHZ max: 25/30/35/40 ns to 20/20/25/30 ns t OH min: 5/5/10/10 ns 5/5/5/5 ns t WC min: 70/85/100/120 ns to 45/55/70/85 ns t CW min: 60/75/80/85 ns to 35/40/60/75 ns t AW min: 60/75/80/85 ns to 35/40/60/75 ns t WP min: 50/55/60/70 ns to 30/35/50/55 ns t WHZ max: 25/30/35/40 ns to 20/20/25/30 ns K. Yoshizaki 19 HM62256B Series Revision Record (cont.) Rev. Date Contents of Modification Drawn by Approved by 3.0 Jun. 19, 1995 AC Characteristics t PW min: 30/35/40/50 ns to 20/25/30/35 ns t OHZ max: 25/30/35/40 ns to 20/20/25/30 ns Low VCC Data Retention Characteristics Addition of note 4. t CCDR typ: 0.2/0.2 µA to 0.05/0.05/0.05 µA max: 30/10 µA to 30/10/3 µA M. Higuchi K. Yoshizaki 4.0 Nov. 29, 1995 Ordering Information (HM62256BLFP-4 Series) Addition of note (Under development) AC Characteristics Test Conditions HM62256-5/7/8:1TTL Gate + CL (100pF) to HM62256-5:1TTL Gate + CL (50pF) and HM62256-7/8:1TTL Gate + CL (100pF) M. Higuchi K. Yoshizaki 5.0 Jul. 9, 1997 Change of format Deletion of HM62256B-4 Series M. Higuchi K. Imato 6.0 Nov. 13,1997 Operation Table Correct Error DC Operating Conditions Correct Error DC Characteristics Correct Error 20