AD AD8130-EVAL Low-cost 270 mhz differential receiver amplifier Datasheet

a
Low-Cost 270 MHz
Differential Receiver Amplifiers
AD8129/AD8130
FEATURES
High Speed
AD8130: 270 MHz, 1090 V/s @ G = 1
AD8129: 200 MHz, 1060 V/s @ G = 10
High CMRR
94 dB Min, DC to 100 kHz
80 dB Min @ 2 MHz
70 dB @ 10 MHz
High-Input Impedance: 1 M Differential
Input Common-Mode Range 10.5 V
Low Noise
AD8130: 12.5 nV/√Hz
AD8129: 4.5 nV/√Hz
Low Distortion, 1 V p-p @ 5 MHz:
AD8130, –79 dBc Worst Harmonic @ 5 MHz
AD8129, –74 dBc Worst Harmonic @ 5 MHz
User-Adjustable Gain
No External Components for G = 1
Power Supply Range +4.5 V to 12.6 V
Power-Down
CONNECTION DIAGRAM
(Top View)
SO-8 (R) and Micro_SO-8 (RM)
+IN 1
–VS 2
8 –IN
7 +VS
+
PD 3
6 OUT
5 FB
REF 4
data transmission. The AD8129 and AD8130 are differentialto-single-ended amplifiers with extremely high CMRR at high
frequency. Therefore, they can also be effectively used as
high-speed instrumentation amps or for converting differential
signals to single-ended signals.
The AD8129 is a low-noise high-gain (10 or greater) version
intended for applications over very long cables where signal
attenuation is significant. The AD8130 is stable at a gain of one
and can be used for those applications where lower gains are
required. Both have user adjustable gain to help compensate for
losses in the transmission line. The gain is set by the ratio of
two resistor values. The AD8129 and AD8130 have very high
input impedance on both inputs regardless of the gain setting.
APPLICATIONS
High-Speed Differential Line Receiver
Differential-to-Single-Ended Converter
High-Speed Instrumentation Amp
Level-Shifting
GENERAL DESCRIPTION
The AD8129 and AD8130 are designed as receivers for the
transmission of high-speed signals over twisted-pair cables to
work with the AD8131 or AD8132 drivers. Either can be
used for analog or digital video signals and for high-speed
120
110
100
CMRR – dB
AD8129/
AD8130
90
80
The AD8129 and AD8130 have excellent common-mode rejection (70 dB @ 10 MHz) allowing the use of low cost unshielded
twisted-pair cables without fear of corruption by external noise
sources or crosstalk.
The AD8129 and AD8130 have a wide power supply range
from single 5 V supply to ± 12 V, allowing wide common-mode
and differential-mode voltage ranges while maintaining signal
integrity. The wide common-mode voltage range will enable
the driver receiver pair to operate without isolation transformers in many systems where the ground potential difference
between drive and receive locations is many volts. The AD8129
and AD8130 have considerable cost and performance improvements over op amps and other multi-amplifier receiving solutions.
70
PD
+VS
60
VIN
50
VOUT
40
30
10k
100k
1M
FREQUENCY – Hz
10M
100M
RG
RF
Figure 1. AD8129 CMRR vs. Frequency
–VS
V OUT = VIN [1+(R F /R G )]
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
Figure 2. Typical Connection Configuration
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD8129/AD8130–SPECIFICATIONS
5 V SPECIFICATIONS
(AD8129 G = 10, AD8130 G = 1, TA = 25C, VS = 5 V, REF = 0 V, PD ≥ VIH, RL = 1 k, CL = 2 pF, unless
otherwise noted. TMIN to TMAX = –40C to +85C, unless otherwise noted.)
Model
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Rise and Fall Time
Output Overdrive Recovery
NOISE/DISTORTION
Second Harmonic/Third Harmonic
IMD
Output IP3
Input Voltage Noise (RTI)
Input Current Noise (+IN, –IN)
Input Current Noise (REF, FB)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio
CMRR with VOUT = 1 V p-p
Common-Mode Voltage Range
Differential Operating Range
Differential Clipping Level
Resistance
Capacitance
DC PERFORMANCE
Closed-Loop Gain Error
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage vs. Supply
Conditions
Min
VOUT ≤ 0.3 V p-p
VOUT = 2 V p-p
VOUT ≤ 0.3 V p-p, SOIC/µSOIC
VOUT = 2 V p-p, 25% to 75%
VOUT = 2 V p-p, 0.1%
VOUT ≤ 1 V p-p, 10% to 90%
175
170
925
VOUT = 1 V p-p, 5 MHz
VOUT = 2 V p-p, 5 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
f ≥ 10 kHz
f ≥ 100 kHz
f ≥ 100 kHz
AD8130, G = 2, NTSC 200 IRE, R L ≥ 150 Ω
AD8130, G = 2, NTSC 200 IRE, R L ≥ 150 Ω
DC to 100 kHz, VCM = –3 V to +3.5 V
VCM = 1 V p-p @ 2 MHz
VCM = 1 V p-p @ 10 MHz
VCM = 2 V p-p @ 1 kHz, VOUT = ±0.5 V dc
V+IN – V–IN = 0 V
OUTPUT PERFORMANCE
Voltage Swing
Output Current
Short Circuit Current
94
80
±0.6
Differential
Common-Mode
Differential
Common-Mode
VOUT = ± 1 V, RL ≥ 150 Ω
TMIN to TMAX
VOUT = ±1 V
VOUT = ±1 V
Output Impedance
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
TMIN to TMAX
TMIN to TMAX
+VS = +5 V, –VS = –4.5 V to –5.5 V
–VS = –5 V, +VS = +4.5 V to +5.5 V
Min
AD8130A
Typ
240
140
950
110
70
100
±3.5
±0.5
±0.75
1
4
3
4
–90
–94
±0.5
±1
5
±0.08
0.2
TMIN to TMAX (+IN, –IN, REF, FB)
(+IN, –IN, REF, FB)
TMIN to TMAX
90
80
±0.85
±2.3
±1.5
1.4
–84
–86
±2
±3.5
To Common
TMIN to TMAX
PD ≤ VIL, In Power-Down Mode
±2.25
Total Supply Voltage
–79/–86
–74/–81
–74/–80
–74/–76
–70
26
12.5
1
1.4
0.13
0.15
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
pA/√Hz
%
Degrees
110
dB
dB
dB
dB
V
V
V
MΩ
MΩ
pF
pF
70
83
±3.8
±2.5
±2.8
6
4
3
4
10.8
36
0.68
±12.6
11.6
±2.25
10.8
36
0.68
0.85
1
1.8
3.5
–74
–74
±2
±3.5
±0.4
12.5
100
0.5
±12.6
11.6
0.85
1
+VS – 2.5
–30
–50
12.5
100
0.5
%
ppm/°C
dB
ppm
mV
µV/°C
mV
dB
dB
µA
µA
nA/°C
µA
nA/°C
±V
mA
mA
µA/°C
pF
+VS – 1.5
+VS – 2.5
–30
–50
Enable Time
±0.6
40
–60/+55
–240
10
+VS – 1.5
PD = Min VIH
PD = Max VIL
PD ≤ +VS – 3 V
PD ≥ +VS – 2 V
±3.3
3.6/4.0
40
–60/+55
–240
10
Unit
MHz
MHz
MHz
V/µs
ns
ns
ns
–78
–80
±0.5
±1
5
±0.08
0.2
±0.4
Max
270
155
45
1090
20
1.4
40
±0.15
10
74
200
0.4
10
0.8
3.6/4.0
TMIN to TMAX
PD ≤ VIL
PD ≤ VIL, TMIN to TMAX
PD PIN
VIH
VIL
IIH
IIL
Input Resistance
200
190
30/50
1060
20
1.7
30
±0.4
20
88
250
0.2
2
RLOAD = 150 Ω/1 kΩ
Max
–74/–84
–68/–74
–67/–81
–61/–70
–67
25
4.5
1
1.4
0.3
0.1
Input Bias Current (+IN, –IN)
Input Bias Current (REF, FB)
Input Offset Current
AD8129A
Typ
V
mA
µA/°C
mA
mA
V
V
µA
µA
kΩ
kΩ
µs
Specifications subject to change without notice.
–2–
REV. 0
AD8129/AD8130
12 V SPECIFICATIONS
(AD8129 G = 10, AD8130 G = 1, TA = 25C, VS = 12 V, REF = 0 V, PD ≥ VIH, RL = 1 k, CL = 2 pF,
unless otherwise noted. TMIN to TMAX = –40C to +85C, unless otherwise noted.)
Model
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Rise and Fall Time
Output Overdrive Recovery
Conditions
Min
VOUT ≤ 0.3 V p-p
VOUT = 2 V p-p
VOUT ≤ 0.3 V p-p, SOIC/µSOIC
VOUT = 2 V p-p, 25% to 75%
VOUT = 2 V p-p, 0.1%
VOUT ≤ 1 V p-p, 10% to 90%
175
170
AD8129A
Typ
935
NOISE/DISTORTION
Second Harmonic/Third Harmonic VOUT = 1 V p-p, 5 MHz
VOUT = 2 V p-p, 5 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
IMD
VOUT = 2 V p-p, 10 MHz
Output IP3
VOUT = 2 V p-p, 10 MHz
Input Voltage Noise (RTI)
f ≥ 10 kHz
Input Current Noise (+IN, –IN)
f ≥ 100 kHz
Input Current Noise (REF, FB)
f ≥ 100 kHz
Differential Gain Error
AD8130, G = 2, NTSC 200 IRE, R L ≥ 150 Ω
Differential Phase Error
AD8130, G = 2, NTSC 200 IRE, R L ≥ 150 Ω
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio
CMRR with VOUT = 1 V p-p
Common-Mode Voltage Range
Differential Operating Range
Differential Clipping Level
Resistance
Capacitance
DC PERFORMANCE
Closed-Loop Gain Error
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage vs. Supply
DC to 100 kHz, V CM = ± 10 V
VCM = 1 V p-p @ 2 MHz
VCM = 1 V p-p @ 10 MHz
VCM = 4 V p-p @ 1 kHz, VOUT = ±0.5 V dc
V+IN – V–IN = 0 V
OUTPUT PERFORMANCE
Voltage Swing
Output Current
Short Circuit Current
92
80
± 0.6
Differential
Common-Mode
Differential
Common-Mode
VOUT = ± 1 V, RL ≥ 150 Ω
TMIN to TMAX
VOUT = ± 1 V
VOUT = ± 1 V
Output Impedance
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
88
80
± 0.85
± 2.3
± 1.8
0.8
1.4
–82
–84
±2
± 3.5
To Common
TMIN to TMAX
PD ≤ VIL, In Power-Down Mode
–79/–86
–74/–81
–74/–80
–74/–74
–70
26
13
1
1.4
0.13
0.2
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
pA/√Hz
%
Degrees
105
dB
dB
dB
dB
V
V
V
MΩ
MΩ
pF
pF
70
80
± 10.5
± 2.5
± 2.8
6
4
3
4
13
43
0.73
±12.6
13.9
±2.25
13
43
0.73
0.9
1.1
3
100
0.5
–3–
1.8
3.5
–70
–70
±2
± 3.5
± 0.4
±12.6
13.9
0.9
1.1
+VS – 2.5
–30
–50
3
100
0.5
%
ppm/°C
dB
ppm
mV
µV/°C
mV
dB
dB
µA
µA
nA/°C
µA
nA/°C
V
mA
mA
µA/°C
pF
+VS – 1.5
+VS – 2.5
–30
–50
Specifications subject to change without notice.
± 0.6
40
–60/+55
–240
10
+VS – 1.5
PD = Min V IH
PD = Max V IL
PD ≤ +VS – 3 V
PD ≥ +VS – 2 V
± 3.3
±10.8
±2.25
Unit
MHz
MHz
MHz
V/µs
ns
ns
ns
–77
–88
± 0.25
± 0.5
2.5
± 0.08
0.2
± 0.4
Max
290
175
110
1100
20
1.4
40
± 0.15
10
73
200
0.4
10
40
–60/+55
–240
10
Enable Time
REV. 0
960
±10.8
TMIN to TMAX
PD ≤ VIL
PD ≤ VIL, TMIN to TMAX
PD PIN
VIH
VIL
IIH
IIL
Input Resistance
70
93
± 10.3
± 0.5
± 0.75
1
4
3
4
–88
–92
± 0.25
± 0.5
2.5
± 0.08
0.2
TMIN to TMAX (+IN, –IN, REF, FB)
(+IN, –IN, REF, FB)
TMIN to TMAX
Total Supply Voltage
AD8130A
Typ
250
150
105
± 0.8
20
87
250
0.2
2
TMIN to TMAX
TMIN to TMAX
+VS = +12 V, –VS = –11.0 V to –13.0 V
–VS = –12 V, +V S = +11.0 V to +13.0 V
RLOAD = 700 Ω
200
195
50/70
1070
20
1.7
40
Min
–71/–84
–65/–74
–65/–82
–59/–70
–67
25
4.6
1
1.4
0.3
0.1
Input Bias Current (+IN, –IN)
Input Bias Current (REF, FB)
Input Offset Current
Max
V
mA
µA/°C
mA
mA
V
V
µA
µA
kΩ
kΩ
µs
AD8129/AD8130–SPECIFICATIONS
5 V SPECIFICATIONS
(AD8129 G = 10, AD8130 G = 1, TA = 25C, +VS = 5 V, –VS = 0 V, REF = 2.5 V, PD ≥ VIH, RL = 1 k, CL = 2 pF
unless otherwise noted. TMIN to TMAX = –40C to +85C, unless otherwise noted.)
Model
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Rise and Fall Time
Output Overdrive Recovery
Conditions
Min
VOUT ≤ 0.3 V p-p
VOUT = 1 V p-p
VOUT ≤ 0.3 V p-p, SOIC/µSOIC
VOUT = 2 V p-p, 25% to 75%
VOUT = 2 V p-p, 0.1%
VOUT ≤ 1 V p-p, 10% to 90%
160
160
AD8129A
Typ
810
NOISE/DISTORTION
Second Harmonic/Third Harmonic VOUT = 1 V p-p, 5 MHz
VOUT = 2 V p-p, 5 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
IMD
VOUT = 2 V p-p, 10 MHz
Output IP3
VOUT = 2 V p-p, 10 MHz
Input Voltage Noise (RTI)
f ≥ 10 kHz
Input Current Noise (+IN, –IN)
f ≥ 100 kHz
Input Current Noise (REF, FB)
f ≥ 100 kHz
Differential Gain Error
AD8130, G = 2, NTSC 100 IRE, R L ≥ 150 Ω
Differential Phase Error
AD8130, G = 2, NTSC 100 IRE, R L ≥ 150 Ω
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio
CMRR with VOUT = 1 V p-p
Common-Mode Voltage Range
Differential Operating Range
Differential Clipping Level
Resistance
Capacitance
DC PERFORMANCE
Closed-Loop Gain Error
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage vs. Supply
DC to 100 kHz, V CM = 1.5 V to 3.5 V
VCM = 1 V p-p @ 1 MHz
VCM = 1 V p-p @ 10 MHz
VCM = 1 V p-p @ 1 kHz, VOUT = ±0.5 V dc
V+IN – V–IN = 0 V
OUTPUT PERFORMANCE
Voltage Swing
Output Current
Short Circuit Current
Output Impedance
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
86
80
± 0.6
Differential
Common-Mode
Differential
Common-Mode
VOUT = ± 1 V, RL ≥ 150 Ω
TMIN to TMAX
VOUT = ± 1 V
VOUT = ± 1 V
TMIN to TMAX
TMIN to TMAX
+VS = 5 V, –VS = –0.5 V to +0.5 V
–VS = 0 V, +VS = +4.5 V to +5.5 V
70
80
1.25 to 3.7
± 0.5
± 0.75
1
4
3
4
–88
–100
± 0.5
±1
5
± 0.08
0.2
TMIN to TMAX (+IN, –IN, REF, FB)
(+IN, –IN, REF, FB)
TMIN to TMAX
RLOAD ≥ 150 Ω
AD8130A
Typ
220
180
810
96
± 0.25
20
86
250
0.2
2
1.1
86
80
± 0.85
± 2.3
± 1.25
0.8
1.4
–80
–86
±2
± 3.5
3.9
To Common
TMIN to TMAX
PD ≤ VIL, In Power-Down Mode
±2.25
Total Supply Voltage
9.9
33
0.65
–72/–79
–65/–71
–60/–62
–68/–68
–70
26
12.3
1
1.4
0.13
0.15
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
pA/√Hz
%
Degrees
96
dB
dB
dB
dB
V
V
V
MΩ
MΩ
pF
pF
70
72
1.25 to 3.8
± 2.5
± 2.8
± 3.3
6
4
3
4
1.1
±2.25
9.9
33
0.65
0.85
1
+VS – 1.5
+VS – 1.5
+VS – 2.5
–30
–50
PD = Min VIH
PD = Max VIL
PD ≤ +VS – 3 V
PD ≥ +VS – 2 V
12.5
100
0.5
Enable Time
± 0.6
1.8
3.5
–70
–76
±2
± 3.5
± 0.4
12.5
100
0.5
%
ppm/°C
dB
ppm
mV
µV/°C
mV
dB
dB
µA
µA
nA/°C
µA
nA/°C
3.9
V
mA
mA
µA/°C
pF
±12.6
10.6
V
mA
µA/°C
mA
mA
35
–60/+55
–240
10
±12.6
10.6
Unit
MHz
MHz
MHz
V/µs
ns
ns
ns
–74
–90
± 0.5
±1
5
± 0.08
0.2
± 0.4
Max
250
205
25
930
20
1.5
30
± 0.1
20
71
200
0.4
10
35
–60/+55
–240
10
TMIN to TMAX
PD ≤ VIL
PD ≤ VIL, TMIN to TMAX
PD PIN
VIH
VIL
IIH
IIL
Input Resistance
185
185
25/40
930
20
1.8
20
Min
–68/–75
–62/–64
–63/–70
–56/–58
–67
25
4.5
1
1.4
0.3
0.1
Input Bias Current (+IN, –IN)
Input Bias Current (REF, FB)
Input Offset Current
Max
0.85
1
V
+VS – 2.5 V
–30
µA
–50
µA
kΩ
kΩ
µs
Specifications subject to change without notice.
–4–
REV. 0
AD8129/AD8130
ABSOLUTE MAXIMUM RATINGS 1, 2
2.0
MAXIMUM POWER DISSIPATION – Watts
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . Refer to Figure 3
Input Voltage (Any Input) . . . . . . . –VS – 0.3 V to +VS + 0.3 V
Differential Input Voltage (AD8129)3 VS ≥ ± 11.5 V . . . ± 0.5 V
Differential Input Voltage (AD8129)3 VS < ± 11.5 V . . . ± 6.2 V
Differential Input Voltage (AD8130) . . . . . . . . . . . . . . ± 8.4 V
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Thermal Resistance measured on SEMI standard 4-layer board.
8-Lead SOIC: θJA= 121°C/W; 8-Lead Micro_SO: θJA = 142°C/W
3
Refer to Applications section, Extreme Operating Condition, and Power Dissipation.
8-LEAD SOIC
PACKAGE
1.5
TJ (MAX) = 150C
1.0
8-LEAD
MICRO_SO
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE – C
80 90
Figure 3. Maximum Power Dissipation vs. Temperature
CONNECTION DIAGRAM
(Top View)
SO-8 (R) and Micro_SO-8 (RM)
+IN 1
–VS 2
AD8129/
AD8130
8 –IN
7 +VS
+
PD 3
6 OUT
5 FB
REF 4
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Branding
Information
AD8129AR
AD8129AR-REEL1
AD8129AR-REEL72
AD8129ARM
AD8129ARM-REEL3
AD8129ARM-REEL72
AD8129-EVAL
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead Micro_SO
8-Lead Micro_SO
8-Lead Micro_SO
Evaluation Board with SOIC
SO-8
13" Tape and Reel
7" Tape and Reel
RM-8
13" Tape and Reel
7" Tape and Reel
HQA
HQA
HQA
AD8130AR
AD8130AR-REEL1
AD8130AR-REEL72
AD8130ARM
AD8130ARM-REEL3
AD8130ARM-REEL72
AD8130-EVAL
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead Micro_SO
8-Lead Micro_SO
8-Lead Micro_SO
Evaluation Board with SOIC
SO-8
13" Tape and Reel
7" Tape and Reel
RM-8
13" Tape and Reel
7" Tape and Reel
HPA
HPA
HPA
Model
NOTES
1
13" Reel of 2500 each.
2
7" Reel of 1000 each.
3
13" Reel of 3000 each.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8129/AD8130 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
AD8129/AD8130
AD8130 Frequency Response Characteristics
(G = 1, RL = 1 k, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25C, unless otherwise noted.)
3
VOUT = 0.3V p-p
2
3
VS = 2.5V
1
–3
0
VS = 5V
–1
VS = 12V
–2
–3
–1
–4
–4
–5
–5
–6
–6
–6
–7
–7
10
100
400
10
1
VS = 5V
5
CL = 10pF
0
–1
0.3
0.2
–4
–0.3
10
100
300
–0.4
–0.5
1
10
100
300
3
G=2
2 VOUT = 0.3V p-p
1
0
G=2
2 VOUT = 2V p-p
VS = 2.5V
1
VS = 12V
–3
0
–1
VS = 5V
–2
GAIN – dB
GAIN – dB
–2
VS = 12V
–3
–1
–4
–4
–5
–5
–6
–6
–6
–7
–7
10
100
400
TPC 7. AD8130 Frequency Response
vs. Supply, RL = 150 Ω
1
10
100
300
FREQUENCY – MHz
TPC 8. AD8130 Frequency Response
vs. Supply, G = 2, VOUT = 0.3 V p-p
–6–
VS = 12V
–3
–5
FREQUENCY – MHz
VS = 5V
–2
–4
1
VS = 2.5V
1
0
VS = 5V
–1
300
TPC 6. AD8130 Fine Scale Response
vs. Supply, RL = 150 Ω
3
VS = 2.5V
100
FREQUENCY – MHz
TPC 5. AD8130 Fine Scale Response
vs. Supply, RL = 1 kΩ
3
10
1
FREQUENCY – MHz
TPC 4. AD8130 Frequency Response
vs. Load Capacitance
RL = 150
VS = 12V
–0.3
VS = 12V
FREQUENCY – MHz
2
0.0
–0.2
–0.1
–0.2
VS = 5V
0.1
–0.1
0.1
–3
1
0.2
0.0
CL = 2pF
–2
0.3
VS = 5V
GAIN – dB
GAIN – dB
1
VS = 2.5V
RL = 150
0.4
0.5
CL = 5pF
300
TPC 3. AD8130 Frequency Response
vs. Supply, VOUT = 2 V p-p
VS = 2.5V
RL = 1k
0.4
2
100
0.5
0.7
0.6
3
10
1
FREQUENCY – MHz
TPC 2. AD8130 Frequency Response
vs. Supply, VOUT = 1 V p-p
CL = 20pF
4
–7
300
FREQUENCY – MHz
TPC 1. AD8130 Frequency Response
vs. Supply, VOUT = 0.3 V p-p
6
100
VS = 12V
–3
–5
1
VS = 5V
–2
–4
FREQUENCY – MHz
GAIN – dB
GAIN – dB
GAIN – dB
GAIN – dB
VS = 12V
–2
VS = 2.5V
1
0
VS = 5V
–1
VOUT = 2V p-p
2
1
0
GAIN – dB
3
VS = 2.5V
VOUT = 1V p-p
2
–7
1
10
100
300
FREQUENCY – MHz
TPC 9. AD8130 Frequency Response
vs. Supply, G = 2, VOUT = 2 V p-p
REV. 0
AD8129/AD8130
3
0
RF = RG = 250
–3
–4
–0.1
VS = 5V
–0.2
–0.3
VS = 12V
–0.4
G=2
VS = 5V
–0.1
–0.4
–0.5
–0.6
–0.6
–7
–0.7
10
100
300
–0.7
10
FREQUENCY – MHz
1
FREQUENCY – MHz
G=2
RL = 150
2
0.2
VS = 2.5V
1
3
VOUT = 2V p-p
VS = 2.5V
VS = 5V
1
0
VS = 12V
–2
–3
0
–0.1
GAIN – dB
GAIN – dB
VS = 5V
–1
VS = 12V
–0.2
VS = 2.5V
–0.3
G=5
–4
–0.4
–5
–0.5
–6
–0.6
10
FREQUENCY – MHz
1
100
300
TPC 13. AD8130 Frequency Response
vs. Supply, G = 2, RL = 150 Ω
12
RL = 150
0
–1
G=5
G = 10
VS = 2.5V
VS = 5V, 12V
–4
OUTPUT VOLTAGE – dBV
VS = 5V, 12V
1
–3
VS = 5V, 12V
–3
VS = 2.5V
1
FREQUENCY – MHz
G = 10
–6
10
30
–7
0.1
10
1
FREQUENCY – MHz
0dB = 1V RMS
1
–12
5
RG
–30
–42
–7
0.1
–48
10
TPC 16. AD8130 Frequency Response
vs. Supply, G = 5, G = 10, RL = 150 Ω
RL
RF
–24
–6
100
6
4
–18
TEK P6245
FET PROBE
8
50
0
–36
10
1
FREQUENCY – MHz
100
TPC 15. AD8130 Frequency Response
vs. Supply, G = 5, G = 10, VOUT = 2 V p-p
–6
–5
REV. 0
–2
6
2
–2
VS = 12V
–5
G = 10
TPC 14. AD8130 Fine Scale Response
vs. Supply, G = 5, G = 10, VOUT = 2 V p-p
3
G=5
–1
–4
VS = 5V, 12V
–0.7
0.1
–7
VOUT = 2V p-p
2
0.1
0
100
TPC 12. AD8130 Fine Scale Response
vs. Supply, G = 2, RL = 150 Ω
0.3
3
10
FREQUENCY – MHz
1
100
TPC 11. AD8130 Fine Scale Response
vs. Supply, G = 2, RL = 1 kΩ
TPC 10. AD8130 Frequency
Response for Various RF /RG
VS = 12V
–0.3
–6
1
VS = 5V
–0.2
–0.5
–5
GAIN – dB
GAIN – dB
GAIN – dB
–2
VS = 2.5V
0.1
0
RF = RG = 499
–1
G=2
RL = 150
0.2
0.1
0
GAIN – dB
VS = 2.5V
G=2
RL = 1k
0.2
RF = RG = 750
1
GAIN – dB
0.3
0.3
RF = RG = 1k
2
VS = 5V
100
FREQUENCY – MHz
RF
RG
1
2
5
10
0
499
8.06k
4.99k
–
499
2k
549
400
TPC 17. AD8130 Frequency Response
for Various Output Levels
–7–
G
TPC 18. AD8130 Basic Frequency
Response Test Circuit
CL
AD8129/AD8130
AD8129 Frequency Response Characteristics
(G = 10, RL = 1 k, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25C, unless otherwise noted.)
3
3
VOUT = 0.3V p-p
2
VS = 2.5V
VS = 5V
–2
–3
VS = 12V
–2
–3
–3
–4
–4
–5
–5
–6
–6
–6
–7
–7
100
TPC 19. AD8129 Frequency Response
vs. Supply, VOUT = 0.3 V p-p
VS = 5V
3
2
0.5
CL = 20pF
CL = 10pF
CL = 5pF
CL = 2pF
0.3
0.1
VS = 5V
0.2
0
–1
–2
0
0.1
0
VS = 12V
–0.1
–0.2
–0.2
–0.4
–0.3
–0.5
–5
–0.4
–0.6
–6
–0.5
1
100
300
TPC 22. AD8129 Frequency Response
vs. Load Capacitance
1
VS = 2.5V
VS = 12V
1
–2
–3
–4
–5
–5
–6
–6
–7
10
–7
100
FREQUENCY – MHz
300
TPC 25. AD8129 Frequency Response
vs. Supply, RL = 150 Ω
VS = 5V, 12V
–1
–4
300
G = 20
VOUT = 2V p-p
2
0
–3
100
3
1
VS = 5V
10
FREQUENCY – MHz
TPC 24. AD8129 Fine Scale Response
vs. Supply, RL = 150 Ω
G = 20
VOUT = 0.3V p-p
2
GAIN – dB
–2
1
3
RL = 150
0
–1
300
VS = 5V, 12V
0
GAIN – dB
2
–0.7
10
100
FREQUENCY – MHz
TPC 23. AD8129 Fine Scale Response
vs. Supply, RL = 1 kΩ
3
VS = 12V
–0.3
–4
10
FREQUENCY – MHz
VS = 5V
–0.1
–3
1
300
VS = 2.5V
RL = 150
0.2
0.3
100
TPC 21. AD8129 Frequency Response
vs. Supply, VOUT = 2 V p-p
VS = 2.5V
RL = 1k
0.4
GAIN – dB
1
TPC 20. AD8129 Frequency Response
vs. Supply, VOUT = 1 V p-p
10
FREQUENCY – MHz
1
300
GAIN – dB
4
–7
10
100
FREQUENCY – MHz
1
300
VS = 12V
–2
–5
10
FREQUENCY – MHz
VS = 5V
–1
–4
1
GAIN – dB
0
–1
GAIN – dB
GAIN – dB
GAIN – dB
VS = 12V
VS = 2.5V
1
0
0
–1
VOUT = 2V p-p
2
VS = 2.5V
1
1
GAIN – dB
3
VS = 5V
VOUT = 1V p-p
2
–1
–2
–3
VS = 2.5V
–4
VS = 2.5V
–5
–6
–7
1
10
FREQUENCY – MHz
100
300
TPC 26. AD8129 Frequency Response
vs. Supply, G = 20, VOUT = 0.3 V p-p
–8–
1
10
FREQUENCY – MHz
100
300
TPC 27. AD8129 Frequency Response
vs. Supply, G = 20, VOUT = 2 V p-p
REV. 0
AD8129/AD8130
0.8
0.2
G = 10
VS = 5V
0.6
2k/221
909/100
0.3
G = 20
RL = 1k
0.1
0
0.4
–0.1
0
–0.2
499/54.9
0.2
SOIC
0
909/100
–0.2
–0.3
VS = 12V
–0.4
–0.5
2k/221
–0.2
–0.1
–0.2
–0.3
–0.4
VS = 2.5V
–0.6
–0.5
–0.4
–0.7
–0.6
–0.6
–0.8
10
100
300
1
10
FREQUENCY – MHz
FREQUENCY – MHz
TPC 28. AD8129 Fine Scale Response
vs. SOIC and µ SOIC for Various RF /RG
TPC 29. AD8129 Fine Scale Response
vs. Supply
3
–0.1
VS = 5V, 12V
–2
–3
–4
–5
10
FREQUENCY – MHz
1
100
G = 50
VS = 2.5V
–0.3
VS = 5V
–0.4
VS = 12V
VS = 5V
VS = 12V
10
–7
0.1
1
10
FREQUENCY – MHz
50
TPC 33. AD8129 Frequency Response
vs. Supply, G = 50, G = 100,
VOUT = 2 V p-p
0dB = 1V RMS
1
0
OUTPUT VOLTAGE – dBV
6
0
–1
G = 100
G = 50
–2
VS = 2.5V
–4
VS = 5V
–5
VS = 12V
50
50
TPC 34. AD8129 Frequency Response
vs. Supply, G = 50, G = 100,
RL = 150 Ω
6
4
–12
5
–18
TEK P6245
FET PROBE
8
–6
RL
RG
RF
–24
–30
–42
1
10
FREQUENCY – MHz
1
–36
–6
REV. 0
VS = 2.5V
12
RL = 150
–7
0.1
–3
–6
1
FREQUENCY – MHz
G = 50
G = 100
–2
–5
TPC 32. AD8129 Fine Scale Response
vs. Supply, G = 50, G = 100,
VOUT = 2 V p-p
2
–3
–1
–4
–0.8
0.1
300
TPC 31. AD8129 Frequency Response
vs. Supply, G = 20, RL = 150 Ω
GAIN – dB
1
–0.7
–7
VOUT = 2V p-p
0
–0.2
–0.6
–6
3
VS = 12V
–0.5
VS = 2.5V
30
3
2
G = 100
–1
GAIN – dB
GAIN – dB
0
10
TPC 30. AD8129 Fine Scale Response
vs. Supply
VOUT = 2V p-p
0
1
FREQUENCY – MHz
0.1
0.1
1
VS = 2.5V
–0.7
0.2
G = 20
RL = 150
2
30
GAIN – dB
1
VS = 5V, 12V
0
GAIN – dB
SOIC
GAIN – dB
GAIN – dB
0.1
VS = 5V
499/54.9
0.2
G = 20
RL = 150
0.2
–48
10
VS = 5V
100
FREQUENCY – MHz
RF
RG
2k
2k
2k
2k
221
105
41.2
20
400
TPC 35. AD8129 Frequency Response
for Various Output Levels
–9–
G
10
20
50
100
TPC 36. AD8129 Basic Frequency
Response Test Circuit
CL
AD8129/AD8130
AD8130 Harmonic Distortion Characteristics
(RL = 1 k, CL = 2 pF, TA = 25C, unless otherwise noted.)
–54
–60
–55
VOUT = 2V p-p
VOUT = 1V p-p
–60
–66
G=1
VS = 5V
G=1
HD2 – dBc
–72
–66
–72
–78
G=2
–84
–90
1
40
TPC 37. AD8130 Second Harmonic
Distortion vs. Frequency
–69
HD3 – dBc
HD3 – dBc
–63
–75
VS = 12V
VOUT = 2V p-p
–51
G=1
VS = 12V
VS = 5V
G=1
G = 2, VS = 12V
fC = 5MHz
–52
–58
–63
–64
–69
VS = 12V
VS = 5V
–75
G=1
VS = 5V
–70
G=2
G=1
–76
VS = 12V
VS = 5V
–88
G=2
–94
0.5
–93
10
FREQUENCY – MHz
40
TPC 40. AD8130 Third Harmonic
Distortion vs. Frequency
–43
VS = 12V
–82
–87
1
10
TPC 39. AD8130 Second Harmonic
Distortion vs. Output Voltage
–57
G=2
–99
1
VOUT – V p-p
G = 2, VS = 5V
–81
–93
–91
0.5
40
–46
–45
G=1
VS = 5V
VOUT = 1V p-p
10
FREQUENCY – MHz
TPC 38. AD8130 Second Harmonic
Distortion vs. Frequency
–51
–57
VS = 5V
VS = 5V
G=2
–85
HD3 – dBc
10
FREQUENCY – MHz
G=1
VS = 12V
VS = 12V
G=2
1
VS = 12V
VS = 5V
–84
–87
G=1
–73
–79
VS = 12V
–81
VS = 5V
–67
HD2 – dBc
HD2 – dBc
VS = 12V
–78
VS = 12V
fC = 5MHz
–61
1
10
FREQUENCY – MHz
40
–42
10
VOUT – V p-p
TPC 41. AD8130 Third Harmonic
Distortion vs. Frequency
VS = 2.5V
1
TPC 42. AD8130 Third Harmonic
Distortion vs. Output Voltage
–46
VS = 2.5V
–48
–52
–54
–58
–49
G = 2, HD3
VS = 2.5V
fC = 5MHz
G = 1, HD3
G=1
–60
–61
G=2
–67
VOUT = 2V p-p
–66
HD – dBc
VOUT = 2V p-p
HD3 – dBc
HD2 – dBc
–55
G=2
–72
G = 1, HD2
–64
G = 2, HD2
–70
G = 2, HD2
–76
G=1
–78
G=1
–84
–73
G=1
–90
VOUT = 1V p-p
G = 2, HD3
–88
VOUT = 1V p-p
G=2
–79
–82
G=2
–94
–96
1
10
FREQUENCY – MHz
40
TPC 43. AD8130 Second Harmonic
Distortion vs. Frequency
1
10
FREQUENCY – MHz
40
TPC 44. AD8130 Third Harmonic
Distortion vs. Frequency
–10–
0
0.5
1.0
1.5
2.0
VOUT – V p-p
2.5
3.0
TPC 45. AD8130 Harmonic Distortion
vs. Output Voltage
REV. 0
AD8129/AD8130
AD8129 Harmonic Distortion Characteristics
(RL = 1 k, CL = 2 pF, TA = 25C, unless otherwise noted.)
–51
–42
VOUT = 1V p-p
–56
G = 10
–54
HD2 – dBc
G = 10,
VS = 12V
–69
G = 10,
VS = 5V
–75
–66
G = 10,
VS = 12V
–68
G = 10,
VS = 5V
–78
G = 20,
VS = 5V
10
FREQUENCY – MHz
G = 20
G = 20,
VS = 12V
–72
–81
1
–62
–84
40
TPC 46. AD8129 Second Harmonic
Distortion vs. Frequency
G = 20,
VS = 12V
G = 20,
VS = 5V
10
FREQUENCY – MHz
1
–86
0.5
40
TPC 48. AD8129 Second Harmonic
Distortion vs. Output Voltage
G = 10,
VS = 12V
–57
–72
–78
G = 20,
VS = 5V
–84
G = 10,
VS = 5V
–63
G = 10,
VS = 12V
–69
1
10
FREQUENCY – MHz
40
–42
VS = 2.5V
VOUT = 2V p-p
VS = 2.5V
–48
–78
G = 20,
VS = 5V
–84
–90
G = 20,
VS = 12V
–96
0.5
40
1
10
VOUT – V p-p
TPC 50. AD8129 Third Harmonic
Distortion vs. Frequency
TPC 49. AD8129 Third Harmonic
Distortion vs. Frequency
–44
10
FREQUENCY – MHz
1
–72
G = 20,
VS = 12V
–87
–96
G = 10,
VS = 5V
–66
G = 20,
VS = 5V
G = 10,
VS = 5V
–81
G = 20,
VS = 12V
G = 10,
VS = 12V
–60
G = 10,
VS = 12V
–75
–90
fC = 5MHz
–54
HD3 – dBc
–66
HD3 – dBc
–51
10
–48
VOUT = 2V p-p
–60
1
VOUT – V p-p
–45
G = 10,
VS = 5V
G = 20,
VS = 5V
–80
TPC 47. AD8129 Second Harmonic
Distortion vs. Frequency
–54
VOUT = 1V p-p
G = 10,
VS = 5V
–74
G = 20,
VS = 12V
–87
G = 10,
VS = 12V
–60
HD2 – dBc
–63
HD2 – dBc
fC = 5MHz
–48
–57
HD3 – dBc
–50
VOUT = 2V p-p
TPC 51. AD8129 Third Harmonic
Distortion vs. Output Voltage
–50
VS = 2.5V
fC = 5MHz
VOUT = 2V p-p
–50
–56
–54
–62
VOUT = 1V p-p
G = 20
–62
–60
G = 20
–66
G = 20
HD3
HD – dBc
HD3 – dBc
HD2 – dBc
–56
–68
VOUT = 1V p-p
–72
–68
G = 10
HD2
–74
G = 10
–78
–74
G = 20
HD2
G = 10
HD3
–80
–84
G = 10
–90
–80
1
10
FREQUENCY – MHz
40
TPC 52. AD8129 Second Harmonic
Distortion vs. Frequency
REV. 0
1
10
FREQUENCY – MHz
TPC 53. AD8129 Third Harmonic
Distortion vs. Frequency
–11–
40
–86
0
0.5
1.0
1.5
2.0
VOUT – V p-p
2.5
3.0
TPC 54. AD8129 Harmonic Distortion vs. Output Voltage
AD8129/AD8130
–61
G=1
VOUT = 2V p-p
VS = 5V
RL = 1k
fC = 5MHz
–67
–57
–63
–69
HD2
–75
VOUT = 1V p-p
–73
HD2
VS = 5V, 12V
HD3
VS = 5V
–85
HD3
VS = 12V
–91
HD3
–81
–87
–5
–4
–3 –2 –1 0
1
VCM – V
2
3
4
–48
–54
–60
–66
HD2
–78
–5
–4
–3 –2 –1
0
1
VOUT = 1V p-p
G = 10
fC = 5MHz
–60
HD2
VS = 2.5V
VS = 12V
VS = 5V
2
3
4
–66
VS = 12V
VS = 5V
–72
–78
VS = 2.5V
VS = 12V
VS = 5V
–62
VS = 2.5V
–68
HD3 VS = 12V
–74
–90
100
5
VS = 5V
–80
100
1k
1k
RL – RL – TPC 59. AD8129 Harmonic Distortion
vs. Load Resistance
VCM
TPC 60. AD8129 Harmonic Distortion
vs. Load Resistance
RL
CL
RF
G
RF
RG
1
2
10
20
0
499
2k
2k
–
499
221
105
TPC 61. AD8129/AD8130 Basic Distortion Test Circuit, VCM = 0 V Unless
Otherwise Noted
100
VOLTAGE NOISE – nV/ Hz
1:2
CURRENT NOISE – pA/ Hz
100
200
VOUT = 2V p-p
–56
VS = 2.5V
TPC 58. AD8129 Harmonic Distortion
vs. Common-Mode Voltage
MINI CIRCUITS:
# T4 – 6T, fC ⱕ 10MHz
# TC4 – 1W, fC ⬎ 10MHz
1k
–50
VCM – V
RG
HD3
VS = 5V, 12V
TPC 57. AD8130 Harmonic Distortion
vs. Load Resistance
–84
HD3
HD3
VS = 2.5V
RL – HD3
–72
–74
–44
G = 10
fC = 5MHz
–54
DISTORTION – dBc
DISTORTION – dBc
–48
G = 10
VOUT = 2V p-p
VS = 5V
RL = 1k
fC = 5MHz
–42
1k
TPC 56. AD8130 Harmonic Distortion
vs. Load Resistance
–36
HD2
VS = 5V, 12V
–68
–86
100
RL – TPC 55. AD8130 Harmonic Distortion
vs. Common-Mode Voltage
HD2
VS = 2.5V
–62
–80
HD3
VS = 2.5V
–97
100
5
–56
HD2
VS = 2.5V
–79
VOUT = 2V p-p
G=1
fC = 5MHz
DISTORTION – dBc
DISTORTION – dBc
–51
DISTORTION – dBc
–45
–50
G=1
fC = 5MHz
DISTORTION – dBc
–39
10
1.0
0.1
AD8130
10
AD8129
1.0
10
100
1k
10k
100k
FREQUENCY – Hz
1M
TPC 62. AD8129/AD8130 Input
Current Noise vs. Frequency
–12–
10M
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 63. AD8129/AD8130 Input
Voltage Noise vs. Frequency
REV. 0
0
0
–40
–10
–10
–50
–60
–70
–80
VS = 2.5V
–100
VS = 5V, 12V
–110
–120
10k
–20
–30
–40
–50
–60
–80
100k
1M
10M
FREQUENCY – Hz
100M
POWER SUPPLY REJECTION – dB
–50
–60
–70
VS = 2.5V
–90
–100
VS = 5V, 12V
–110
–120
10k
100k
1M
10M
FREQUENCY – Hz
10k
100k
1M
FREQUENCY – Hz
10M
–50
–60
VS = 2.5V
–70
–80
–90
VS = 5V
1k
0
–10
–10
–20
–30
–40
–50
–60
–70
VS = 12V
–80
VS = 2.5V
–90
VS = 5V
1k
10k
100k
1M
FREQUENCY – Hz
10M
10k
VS = 12V
100k
1M
FREQUENCY – Hz
10M
100M
TPC 66. AD8130 Negative Power
Supply Rejection vs. Frequency
0
–100
100M
–40
100M
TPC 65. AD8130 Positive Power
Supply Rejection vs. Frequency
–40
–30
–100
1k
–20
–30
–40
–50
–60
–70
–100
1k
100M
VS = 5V
–80 V = 12V
S
–90
VS = 2.5V
10k
100k
1M
10M
100M
FREQUENCY – Hz
TPC 67. AD8129 Common-Mode
Rejection vs. Frequency
TPC 68. AD8129 Positive Power
Supply Rejection vs. Frequency
TPC 69. AD8129 Negative Power
Supply Rejection vs. Frequency
80
90
100
135
40
30
PHASE
+
VOUT
–
20
90
+
1k
2pF
–
10
1k
45
1k
0
VIN
φM = 58
–10
1k
10k
100k
1M
10M
FREQUENCY – Hz
0
100M 300M
TPC 70. AD8130 Open Loop Gain
and Phase vs. Frequency
REV. 0
GAIN
70
60
135
50
PHASE 90
40
VOUT
30
1k
20
100
10
2pF
45
1k
VS = 5V
1
AD8130, G = 1
100m
10m
AD8129, G = 10
0
10k
10
φM = 56
VIN
1k
OUTPUT IMPEDANCE – 50
180
80
OPEN-LOOP GAIN – dB
GAIN
60
PHASE MARGIN – Degrees
180
70
PHASE MARGIN – Degrees
COMMON-MODE REJECTION – dB
VS = 2.5V
–100
–30
OPEN-LOOP GAIN – dB
VS = 5V
–90
TPC 64. AD8130 Common-Mode
Rejection vs. Frequency
–80
VS = 12V
–70
–20
POWER SUPPLY REJECTION – dB
–90
POWER SUPPLY REJECTION – dB
–30
POWER SUPPLY REJECTION – dB
COMMON-MODE REJECTION – dB
AD8129/AD8130
100k
1M
10M
FREQUENCY – Hz
0
100M 300M
TPC 71. AD8129 Open Loop Gain
and Phase vs. Frequency
–13–
1m
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 72. Closed-Loop Output
Impedance vs. Frequency
100M
AD8129/AD8130
AD8130 Transient Response Characteristics
(G = 1, RL = 1 k, CL = 2 pF, VS = 5 V, TA = 25C, unless otherwise noted.)
VOUT = 1V p-p
VS = 5V
VOUT = 1V p-p
VS = 2.5V
250mV
5.00ns
TPC 73. AD8130 Transient Response,
VS = ± 2.5 V, VOUT = 1 V p-p
VS = 2.5V
VS = 5V
VOUT = 0.2V p-p
5.00ns
TPC 76. AD8130 Transient Response
vs. Supply, VOUT = 0.2 V p-p
CL = 10pF
CL = 5pF
CL = 2pF
TPC 74. AD8130 Transient Response,
VS = ± 5 V, VOUT = 1 V p-p
VS = 2.5V
VS = 5V
VOUT = 1V p-p
CL = 5pF
VS = 12V
VS = 12V
50mV
5.00ns
250mV
VOUT = 1V p-p
VS = 12V
TPC 75. AD8130 Transient Response,
VS = ± 12 V, VOUT = 1 V p-p
VS = 2.5V
VS = 5V
VOUT = 2V p-p
CL = 5pF
VS = 12V
5.00ns
250mV
TPC 77. AD8130 Transient Response
vs. Supply, VOUT = 1 V p-p, CL = 5 pF
5.00ns
500mV
TPC 78. AD8130 Transient Response
vs. Supply, VOUT = 2 V p-p, CL = 5 pF
VOUT = 0.2Vp-p
2V p-p
4V p-p
1V p-p
2V p-p
1V p-p
0.5V p-p
50mV
5.00ns
250mV
10.0ns
TPC 79. AD8130 Transient Response
vs. Load Capacitance, VOUT = 0.2 V p-p
5.00ns
500mV
TPC 80. AD8130 Transient Response
vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p
–14–
1.00V
5.00ns
TPC 81. AD8130 Transient Response
vs. Output Amplitude,
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
REV. 0
AD8129/AD8130
VOUT = 1V p-p
G=2
VS = 5V, CL = 10pF
VS = 5V, CL = 2pF
VOUT = 8V p-p
VS = 5V
CL = 10pF
VS = 12V
5.00ns
250mV
VOUT = 2V p-p
G=2
TPC 82. AD8130 Transient Response
vs. Load Capacitance, VOUT = 1 V p-p,
G=2
G=2
VS = 5V
CL = 2pF
5.00ns
500mV
TPC 83. AD8130 Transient Response
vs. Supply, VOUT = 2 V p-p, G = 2
2.00V
5.00ns
TPC 84. AD8130 Transient Response
vs. Load Capacitance, VOUT = 8 V p-p
VOUT = 10V p-p
G=2
VS = 12V
VIN
VOUT
VOUT
VIN
5.00ns
1.00V
TPC 85. AD8130 Transient Response
with +3 V Common-Mode Input
4V p-p
G=5
VS = 5V
CL = 10pF
5.00ns
1.00V
TPC 86. AD8130 Transient Response
with –3 V Common-Mode Input
G=5
VS = 5V
CL = 10pF
VOUT = 8V p-p
2.50V
5.00ns
TPC 87. AD8130 Transient Response,
VOUT = 10 V p-p, G = 2, VS = ± 12 V
VOUT = 20V p-p
G=5
VS = 12V
CL = 10pF
2V p-p
1V p-p
1.00V
10.0ns
TPC 88. AD8130 Transient Response
vs. Output Amplitude
REV. 0
10.0ns
2.00V
TPC 89. AD8130 Transient Response,
VOUT = 8 V p-p, G = 5, VS = ± 5 V
–15–
5.00V
10.0ns
TPC 90. AD8130 Transient Response,
VOUT = 20 V p-p, G = 5, VS = ± 12 V
AD8129/AD8130
AD8129 Transient Response Characteristics
(G = 10, RF = 2 k, RG = 221 , RL = 1 k, CL = 1 pF, VS = 5 V, TA = 25C, unless otherwise noted.)
VS = 2.5V
VOUT = 1V p-p
5.00ns
250mV
TPC 91. AD8129 Transient Response,
VS = ± 2.5 V, VOUT = 1 V p-p
VS = 5V
VS = 2.5V
VOUT = 0.4V p-p
VS = 12V
TPC 94. AD8129 Transient Response
vs. Supply, VOUT = 0.4 V p-p
CL = 5pF
VOUT = 1V p-p
5.00ns
250mV
TPC 92. AD8129 Transient Response,
VS = ± 5 V, VOUT = 1 V p-p
VS = 5V
VS = 2.5V
VOUT = 1V p-p
CL = 5pF
VOUT = 0.4V p-p
VS = 12V
VOUT = 1V p-p
5.00ns
250mV
TPC 93. AD8129 Transient Response,
VS = ± 12 V, VOUT = 1 V p-p
VS = 2.5V
VS = 5V
VOUT = 2V p-p
CL = 5pF
VS = 12V
VS = 12V
5.00ns
100mV
VS = 5V
5.00ns
250mV
TPC 95. AD8129 Transient Response
vs. Supply, VOUT = 1 V p-p, CL = 5 pF
5.00ns
500mV
TPC 96. AD8129 Transient Response
vs. Supply, VOUT = 2 V p-p, CL = 5 pF
VO = 4V p-p
VO = 2V p-p
CL = 10pF
VO = 1V p-p
CL = 2pF
VO = 2V p-p
VO = 0.5V p-p
100mV
5.00ns
TPC 97. AD8129 Transient Response
vs. Load Capacitance, VOUT = 0.4 V p-p
5.00ns
500mV
TPC 98. AD8129 Transient Response
vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p
–16–
VO = 1V p-p
1.00V
5.00ns
TPC 99. AD8129 Transient Response
vs. Output Amplitude,
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
REV. 0
AD8129/AD8130
VOUT = 1V p-p
G = 20
CL = 20pF
5.00ns
250mV
TPC 100. AD8129 Transient Response,
VOUT = 1 V p-p, VS = ±2.5 V to ±12 V
VOUT = 2V p-p
G = 20
CL = 20pF
5.00ns
500mV
TPC 101. AD8129 Transient Response,
VOUT = 2 V p-p, VS = ±5 V
VOUT = 8V p-p
2.00V
G = 20
CL = 20pF
5.00ns
TPC 102. AD8129 Transient Response,
VOUT = 8 V p-p, VS = ±5 V
VOUT = 10V p-p
VIN
G = 20
VS = 12V
CL = 20pF
VOUT
VOUT
VIN
5.00ns
1.00V
TPC 103. AD8129 Transient Response
with +3.5 V Common-Mode Input
4V p-p
G = 50
VS = 5V
CL = 20pF
2.50V
TPC 104. AD8129 Transient Response
with –3.5 V Common-Mode Input
G = 50
VS = 5V
CL = 20pF
VOUT = 8V p-p
5.00ns
TPC 105. AD8129 Transient Response,
VOUT = 10 V p-p, G = 20
VOUT = 20V p-p
G = 50
VS = 12V
CL = 10pF
2V p-p
1V p-p
1.00V
12.5ns
TPC 106. AD8129 Transient Response
vs. Output Amplitude, VOUT = 1 V p-p,
2 V p-p, 4 V p-p
REV. 0
12.5ns
2.00V
TPC 107. AD8129 Transient Response,
VOUT = 8 V p-p, G = 50, VS = ±5 V
–17–
5.00V
12.5ns
TPC 108. AD8129 Transient Response,
VOUT = 20 V p-p, G = 50, VS = ± 12 V
AD8129/AD8130
3.0
AD8130
37
20
17
14
G = 10
VS = 10V
2.0
DIFFERENTIAL INPUT – V
G=1
VS = 5V
SUPPLY CURRENT – mA
SUPPLY CURRENT – mA
23
31
25
VOUT = 100mV AC @ 1kHz
1.0
AD8129
0.0
–1.0
19
AD8130
–2.0
11
–5
–4 –3
–2 –1 0
1
2
3
DIFFERENTIAL INPUT – V
4
5
13
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
DIFFERENTIAL INPUT – V
–3.0
–50 –35 –20 –5
10
25
40
55
70
85 100
TEMPERATURE – C
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
OUTPUT VOLTAGE – V
TPC 112. AD8130 Gain Nonlinearity,
VOUT = 2 V p-p
TPC 111. AD8129/AD8130 Input
Differential Voltage Range vs. Temperature, 1% Gain Compression
4
G=1
VS = 5V
RL = 1k
3
VS = 5V
2
VOUT – V
G=1
VS = 5V
RL = 1k
GAIN NONLINEARITY –
0.005%/DIV
TPC 110. AD8129 DC Power Supply
Current vs. Differential Input Voltage
GAIN NONLINEARITY – 0.08%/DIV
TPC 109. AD8130 DC Power Supply
Current vs. Differential Input Voltage
1
0
–1
–2
–3
–2.5 –2.0 –1.5 –1.0 –0.5
0
–4
–5
0.5 1.0 1.5 2.0 2.5
OUTPUT VOLTAGE – V
TPC 113. AD8130 Gain Nonlinearity,
VOUT = 5 V p-p
–4
–3
–2 –1
0
1
2
3
DIFFERENTIAL INPUT – V
4
5
TPC 114. AD8130 Differential Input
Clipping Level
G = 10
VS = 12V
RL = 1k
6
OUTPUT VOLTAGE – V
GAIN NONLINEARITY –
0.2%/DIV
GAIN NONLINEARITY –
0.005%/DIV
8
G = 10
VS = 5V
RL = 1k
VS = 10V
4
2
0
–2
–4
–6
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8
OUTPUT VOLTAGE – V
1.0
TPC 115. AD8129 Gain Nonlinearity,
VOUT = 2 V p-p
–5
–4
–3
–2 –1 0
1
2
3
OUTPUT VOLTAGE – V
4
5
TPC 116. AD8129 Gain Nonlinearity,
VOUT = 10 V p-p
–18–
–8
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
DIFFERENTIAL INPUT – V
TPC 117. AD8129 Differential Input
Clipping Level
REV. 0
AD8129/AD8130
17
15
0.60
40
13
12
11
15
VS = 12V
14
INPUT BIAS CURRENT – A
SUPPLY CURRENT – mA
SUPPLY CURRENT – mA
14
VS = 5V
13
12
11
VS = 2.5V
10
9
IB
0.45
30
IOS
0.30
20
10
INPUT OFFSET CURRENT – nA
16
8
0
5
10
15
20
25
TOTAL SUPPLY VOLTAGE – V
TPC 118. Quiescent Power Supply
Current vs. Total Supply Voltage
4.00
4.00
3.75
3.75
AD8130
3.50
AD8129
3.25
VS = 5V
3.00
2.75
VOUT = 100mV
AC AT 1kHz
2.50
2.25
2.00
1.75
AD8130
AD8129
1.50
10.5
3.25
VS = 5V
3.00
AD8129
VOUT = 100mV
AC AT 1kHz
2.75
–3.00
–3.25
AD8129
AD8130
–3.50
1.25
–4.00
–50 –35 –20 –5 10 25 40 55 70
TEMPERATURE – C
10.0
4.0
9.5
–9.5
+100C –40C +25C
2.0
SINKING
85 100
3.0
+100C –40C +25C
–3.0
TPC 123. Common-Mode Voltage
Range vs. Temperature, Typical 1%
Gain Compression
5
10 15
20
25
30
OUTPUT CURRENT – mA
35
40
TPC 124. Output Voltage Range vs.
Output Current, Typical 1% Gain
Compression
REV. 0
VS = 12V
9
+100C –40C +25C
–9
–10
VOUT = 100mV
AC AT 1kHz
VOUT = 100mV
AC AT 1kHz
–11
–4.0
0
85 100
10
VOUT = 100mV
AC AT 1kHz
1.0
AD8130
–11.0
–50 –35 –20 –5 10 25 40 55 70
TEMPERATURE – C
11
–3.5
1.5
AD8129
–10.0
OUTPUT VOLTAGE – V
OUTPUT VOLTAGE – V
3.0
VOUT = 100mV
AC AT 1kHz
8.5
–9.0
3.5
SOURCING
AD8129
9.0
VS = 5V
VS = 5V
3.5
VS = 12V
–10.5
TPC 122. Common-Mode Voltage
Range vs. Temperature, Typical 1%
Gain Compression
4.0
OUTPUT VOLTAGE – V
AD8130
AD8130
3.50
1.00
–50 –35 –20 –5 10 25 40 55 70
TEMPERATURE – C
TPC 121. Common-Mode Voltage
Range vs. Temperature, Typical 1%
Gain Compression
TPC 120. Input Bias Current and
Input Offset Current vs. Temperature
11.0
–3.75
85 100
0.15
10
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – C
85 100
TPC 119. Quiescent Power Supply
Current vs. Temperature
INPUT COMMON-MODE – V
INPUT COMMON-MODE – V
7
–50 –35 –20 –5 10 25 40 55 70
TEMPERATURE – C
30
INPUT COMMON-MODE – V
9
0
5
10 15
20
25
30
OUTPUT CURRENT – mA
35
40
TPC 125. Output Voltage Range vs.
Output Current, Typical 1% Gain
Compression
–19–
0
5
10 15
20
25
30
OUTPUT CURRENT – mA
35
40
TPC 126. Output Voltage Range vs.
Output Current, Typical 1% Gain
Compression
AD8129/AD8130
THEORY OF OPERATION
The AD8129/AD8130 use an architecture called active feedback which differs from that of conventional op amps. The
most obvious differentiating feature is the presence of two separate pairs of differential inputs compared to a conventional op
amp’s single pair. Typically for the active-feedback architecture,
one of these input pairs is driven by a differential input signal,
while the other is used for the feedback. This active stage in the
feedback path is where the term “active feedback” is derived.
The active feedback architecture offers several advantages over a
conventional op amp in several types of applications. Among
these are excellent common-mode rejection, wide input commonmode range and a pair of inputs that are high-impedance and
totally balanced in a typical application. In addition, while an
external feedback network establishes the gain response as
in a conventional op amp, its separate path makes it totally
independent of the signal input. This eliminates any interaction
between the feedback and input circuits, which traditionally
causes problems with CMRR in conventional differential-input
op amp circuits.
Thus, the input dynamic ranges are limited to about 2.5 V for
the AD8130 and 0.5 V for the AD8129 (see Specification
section for more detail). For this and other reasons, it is not
recommended to reverse the input and feedback stages of the
AD8129/AD8130, even though some apparently normal functionality might be observed under some conditions.
A few simple circuits can illustrate how the active feedback
architecture of the AD8129/AD8130 operates.
Op Amp Configuration
If only one of the input stages of the AD8129/AD8130 is used,
it will function very much like a conventional op amp. (See
Figure 4.) Classical inverting and noninverting op amps circuits
can be created, and the basic governing equations will be the
same as for a conventional op amp. The unused input pins form
the second input and should be shorted together and tied to
ground or some midsupply voltage when they are not used.
+V
0.1F
Another advantage is the ability to change the polarity of the
gain merely by switching the differential inputs. A high inputimpedance inverting amplifier can be made. Besides a high
input impedance, a unity-gain inverter with the AD8130 will
have a noise gain of unity. This will produce lower output noise
and higher bandwidth than op amps that have noise gain equal
to 2 for a unity gain inverter.
+
VIN
+VS
VOUT
+
–VS
RF
The two differential input stages of the AD8129/AD8130 are each
transconductance stages that are well matched. These stages
convert the respective differential input voltages to internal
currents. The currents are then summed and converted to a
voltage, which is buffered to drive the output. The compensation capacitor is in the summing circuit.
RG
–V
When the feedback path is closed around the part, the output
will drive the feedback input to that voltage which causes the
internal currents to sum to zero. This occurs when the two
differential inputs are equal and opposite; that is, their algebraic
sum is zero.
In a closed-loop application, a conventional op amp will have its
differential input voltage driven to near zero under nontransient
conditions. The AD8129/AD8130 generally will have differential
input voltages at each of its input pairs, even under equilibrium
conditions. As a practical consideration, it is necessary to internally limit the differential input voltage with a clamp circuit.
PD
10F
0.1F
10F
Figure 4. With both inputs grounded, the feedback stage
functions like an op amp: VOUT = VIN (1 + RF/RG). NOTE: This
circuit is provided to demonstrate device operation. It is
not suggested to use this circuit in place of an op amp.
With the unused pair of inputs shorted, there is no differential
voltage between them. This dictates that the differential input
voltage of the used inputs will also be zero for closed-loop
applications. Since this is the governing principle of conventional op amp circuits, an active feedback amplifier can function
as a conventional op amp under these conditions.
Note that this circuit is presented only for illustration purposes,
to show the similarities of the active feedback architecture functionality to conventional op amp functionality. If it is desired to
design a circuit that can be created from a conventional op amp,
it is recommended to choose a conventional op amp whose
specifications are better suited to that application. These op amp
principles are the basis for offsetting the output as described in
the Output Offset/Level Translator section.
–20–
REV. 0
AD8129/AD8130
Twisted-Pair Cable, Composite Video Receiver with Equalization Using an AD8130
APPLICATIONS
Basic Gain Circuits
The gain of the AD8129/AD8130 can be set with a pair of feedback resistors. The basic configuration is shown in Figure 5.
The gain equation is the same as that of a conventional op amp:
G = 1 + RF/RG. For unity gain applications using the AD8130,
RF can be set to zero (short circuit), and RG can be removed.
(See Figure 6.) The AD8129 is compensated to operate at gains
of 10 and higher, so shorting the feedback path to obtain unity
gain will cause oscillation.
+V
AD8129/
AD8130
+
VIN
0.1F
PD
10F
+VS
VOUT
+
–VS
RG
0.1F
–V
10F
Figure 5. Basic Gain Circuit: VOUT = VIN (1 + RF/RG)
+V
AD8130
0.1F
+
These long cables will pick up noise from the environment they
pass through. This noise will not favor one conductor over another, and will therefore be a common-mode signal. A receiver
that rejects the common-mode signal on the cable can greatly
enhance the signal-to-noise ratio performance of the link.
The AD8130 is also very easy to use as a differential receiver,
because the differential inputs and the feedback inputs are
entirely separate. This means that there is no interaction of the
feedback network and the termination network as there would
be in conventional op amp-type receivers.
Another issue to be dealt with on long cables is the attenuation
of the signal at longer distances. This attenuation is a function of
frequency and increases as roughly as the square root of frequency.
RF
VIN
The AD8130 has excellent common-mode rejection at its inputs.
This makes it an ideal candidate for a receiver for signals that
are transmitted over long distances on twisted-pair cables. Category 5 type cables are now very common in office settings and
are extensively used for data transmission. These same cables
can also be used for the analog transmission of signals like video.
PD
10F
+VS
VOUT
+
–VS
0.1F 10F
–V
Figure 6. An AD8130 with Unity Gain
For good fidelity of video circuits, the overall frequency response
of the transmission channel should be flat versus frequency. Since
the cable attenuates the high frequencies, a frequency-selective
boost circuit can be used to undo this effect. These circuits
are called equalizers.
An equalizer uses frequency-dependent elements (Ls and Cs) in
order to create a frequency response that is the opposite of the
rest of the channel’s response in order to create an overall flat
response. There are many ways to create such circuits, but a
common technique is to put the frequency-selective elements in
the feedback path of an op amp circuit. The AD8130 in particular makes this easier than other circuits, because, once again, the
feedback path is totally independent of the input path and there
is no interaction.
The circuit in Figure 7 was developed as a receiver/equalizer for
transmitting composite video over 300 m of Category 5 cable. This
cable has an attenuation of approximately 20 dB at 10 MHz
for 300 m. At 100 MHz, the attenuation is approximately
60 dB. (See Figure 8.)
The input signal can be applied either differentially or singleendedly—all that matters is the magnitude of the differential
signal between the two inputs. For single-ended input applications, applying the signal to the +IN with –IN grounded will
create a noninverting gain, while reversing these connections
will create an inverting gain. Since the two inputs are highimpedance and matched, both of these conditions will provide
the same high input impedance. Thus, an advantage of the
active feedback architecture is the ability to make a high-inputimpedance, inverting op amp. If conventional op amps are used,
a high impedance buffer followed by an inverting stage is needed.
This requires two op amps.
+V
AD8130
VIN
+
100
0.1F
PD
10F
+VS
VOUT
+
–VS
R1
100
C1
200pF
RF
RG
1k
499
0.1F
10F
–V
Figure 7. An Equalizer Circuit for Composite Video
Transmission over 300 m of Category 5 Cable
REV. 0
–21–
20
20
10
10
0
0
–10
–10
I/O RESPONSE
I/O RESPONSE
AD8129/AD8130
–20
–30
–40
–20
–30
–40
–50
–50
–60
–60
–70
–70
–80
10k
100k
1M
FREQUENCY – Hz
10M
–80
10k
100M
100k
1M
FREQUENCY – Hz
10M
100M
Figure 10. Combined Response of Cable Plus Equalizer
Figure 8. Transmission Response of 300 m of
Category 5 Cable
Output Offset/Level Translator
The circuit in Figure 6 has the reference input (Pin 4) tied to
ground, which produces a ground-referenced output signal. If it is
desired to offset the output voltage from ground, the REF input
can be used. (See Figure 11). The level VOFFSET appears at the
output with unity gain.
The feedback network is between Pins 6 and 5 and from Pin 5
to ground. C1 and RF create a corner frequency of about 800 kHz.
The gain increases to provide about 15 dB of boost at 8 MHz.
The response of this circuit is shown in Figure 9.
20
+V
10
0
AD8130
0.1F
I/O RESPONSE
–10
–20
VIN
–30
VOFFSET
–40
+
PD
10F
+VS
VOUT = VIN +VOFFSET
+
–VS
–50
–60
0.1F
–70
–80
10k
10F
–V
100k
1M
FREQUENCY – Hz
10M
100M
Figure 11. The voltage applied to Pin 4 adds to the unitygain output voltage produced by VIN.
Figure 9. Frequency Response of Equalizer Circuit
It is difficult to come up with the exact component values via
strictly mathematical means, because the equations for the cable
attenuation are approximate and have functions that are not
simply related to the responses of RC networks. The method
used in this design was to approximate the required response via
graphical means from the frequency response, and then select
components that would approximate this response. The circuit
was then built and measured, and finally adjusted to obtain an
acceptable response—in this case flat to 9 MHz to within
approximately 1 dB. (See Figure 10.)
If the circuit has a gain higher than unity, the gain has to be
factored in. If RG is connected to ground, the voltage applied to
REF will be multiplied by the gain of the circuit and appear at
the output; just like a noninverting conventional op amp, This
situation is not always desirable and one may want VOFFSET to
appear at the output with unity gain.
One way to accomplish this is to drive both REF and RG with
the desired offset signal. (See Figure 12.) Superposition can be
used to solve this circuit. First break the connection between
VOFFSET and RG. With RG grounded the gain from Pin 4 to
VOUT will be 1 + RF/RG. With Pin 4 grounded, the gain though
RG to VOUT is –RF/RG. The sum of these is +1. If VREF is delivered
from a low-impedance source, this will work fine. However, if
the delivered offset voltage is derived from a high-impedance
source, like a voltage divider, its impedance will affect the gain
equation. This makes the circuit more complicated as it creates
an interaction between the gain and offset voltage.
–22–
REV. 0
AD8129/AD8130
Summer
+V
AD8129/
AD8130
10F
0.1F
+
VIN
VOFFSET
+VS
PD
A general summing circuit can be made by the above technique.
A unity-gain configured AD8130 has one signal applied to +IN,
while the other signal is applied to REF. The output will be the
sum of the two input signals. (See Figure 15.)
+V
V OUT =
V IN (1+ R F /R G ) +V OFFSET
+
–VS
RG
AD8130
RF
0.1F
–V
10F
0.1F
V1
+
V2
+
PD
+VS
10F
VOUT = V1 + V2
–VS
Figure 12. In this circuit, VOFFSET appears at the output
with unity gain. This circuit works well if the VOFFSET
Source Impedance is low.
0.1F
A way around this is to apply the offset voltage to a voltage
divider whose attenuation factor matches the gain of the amplifier, and then apply this voltage to the high-impedance REF
input. This circuit will first divide the desired offset voltage by
the gain, and the amplifier will multiply it back up to unity. (See
Figure 13.)
+V
AD8129/
AD8130
+
VIN
VOFFSET
RF
10F
0.1F
PD
+VS
V OUT =
V IN (1+R F /R G ) + VOFFSET
+
–VS
RG
10F
–V
Figure 15. A Summing Circuit that is Noninverting with
High Input Impedance
This circuit offers several advantages over a conventional op
amp inverting summing circuit. First, the inputs are both highimpedance and the circuit is noninverting. It would require
significant additional circuitry to make an op amp summing
circuit that has high input impedance and is noninverting.
Another advantage is that the AD8130 circuit still preserves the
full bandwidth of the part. In a conventional summing circuit,
the noise gain is increased for every additional input, so the
bandwidth response decreases accordingly. By this technique,
four signals can be summed by applying them to two AD8130s,
and then summing the two outputs by a third AD8130.
Cable-Tap Amplifier
RG
RF
0.1F
–V
10F
Figure 13. Adding an attenuator at the offset input causes
it to appear at the output with unity gain.
Resistorless Gain-of-Two
The voltage applied to the REF input (Pin 4) can also be a high
bandwidth signal. If a unity-gain AD8130 has both +IN and
REF driven with the same signal, there will be unity gain from
VIN and unity gain from VREF. Thus, the circuit will have a gain
of two, and requires no resistors. (See Figure 14.)
It is often desirable to have a video signal drive several different
pieces of equipment. However, the cable should only be terminated once at its end point, so it is not appropriate to have a
termination at each device. A “loop-through” connection allows
a device to tap the video signal while not disturbing it by any
excessive loading.
Such a connection, also referred to as a cable-tap amplifier, can
be simply made with an AD8130. (See Figure 16.) The circuit is
configured with unity gain, and if no output offset is desired,
the REF pin is grounded. The negative differential input is
connected directly to the shield of the cable (or an associated
connector) at the point at which it wants to be “tapped.”
+V
+V
AD8130
AD8130
75
0.1F
VIN
+
PD
0.1F
10F
+
+VS
VOUT
+
PD
10F
+VS
VOUT
+
–VS
–VS
VIDEO
IN
–V
0.1F
0.1F
10F
75
Figure 16. The AD8130 can tap the video signal at any
point along the cable without loading the signal.
Figure 14. Gain-of-Two Connections with No Resistors
REV. 0
10F
–V
–23–
AD8129/AD8130
The center conductor connects to the positive differential input
of the AD8130. The amplitude of the video signal at this point
is unity, because it is between the two termination resistors. The
AD8130 provides a high impedance to this signal, so it does not
disturb it. A buffered, unity-gain version of the video signal
appears at the output.
+V
AD8130
+
1N4148
Power-Down
PD
VOUT
–VS
The AD8129/AD8130 have a power-down pin that can be used
to lower the quiescent current when the amplifier is not being
used. A logic low level on the PD pin will cause the part to
power down.
0.1F
Figure 18. Clamping Diodes at the Input Limit the Input
Swing Amplitude
Another problem can occur with the AD8129 operating at supply
voltage of greater than or equal to ± 12 V. The architecture
causes the supply current to increase as the input differential
voltage increases. If the AD8129 differential inputs are overdriven too far, excessive current can flow in the device and
potentially cause permanent damage.
+VS
A practical means to prevent this from occurring is to differentially
clamp the inputs with a pair of antiparallel Schottky diodes.
(See Figure 19.) These diodes have a lower forward voltage
of approximately 0.4 V. If the differential voltage across the
inputs is restricted to these conditions, no excess current will
be drawn by the AD8129 under these operating conditions.
7
+VS
3 PD
4.99k
2N2222
OR EQ
10F
–V
Since there is no “Ground” pin on the AD8129/AD8130, there
is no logic reference to interface to standard logic levels. For
this reason, the reference level for the PD input is +VS. If the
AD8129/AD8130 are run with +VS = 5 V, there will be direct
compatibility with logic families. However, if +VS is higher
than this, a level-shift circuit will be needed to interface to conventional logic levels. A simple level-shifting circuit that is
compatible with common logic families is presented in Figure 17.
LOW=
POWER-DOWN
+VS
+
VIN
1k
10F
0.1F
VIN
AD8129/
AD8130
If the supply voltage is restricted to less than ± 11 V, the internal
clamping circuit will limit the differential voltage and excessive
supply current will not be drawn. The external clamp circuit is
not needed.
Figure 17. Circuit that Shifts the Logic Level when +VS Is
Not Equal to Approximately 5 V
Extreme Operating Conditions
The AD8129/AD8130 are designed to provide high performance over a wide range of supply voltages. However, there are
some extremes of operating conditions that have been observed
to produce non-optimal results. One of these conditions occurs
when the AD8130 is operated at unity gain with low supply
voltage—less than approximately ± 4 V.
+V
AD8129
0.1F
VIN
+
AGILENT
HSMS 2822
At unity gain, the output drives FB directly. At supplies of ± VS
less than approximately ± 4 V and unity gain, the voltage on FB
can be driven by the output too close to the rail for the circuit to
stay properly biased. This can lead to a parasitic oscillation.
A way to prevent this is to limit the input signal swing with
clamp diodes. Common silicon junction signal diodes like the
1N4148 have a forward bias of approximately 0.7 V when about
1 mA of current flow through them. Two series pairs of such
diodes connected antiparallel across the differential inputs can
be used to clamp the input signal and prevent this condition. It
should be noted that the REF input can also shift the output
signal, so this technique will only work when REF is at ground
or close to it. (See Figure 18.)
VIN
10F
3
1
2
PD
+VS
VOUT
+
–VS
0.1F
10F
–V
Figure 19. Schottky Diodes Across the Inputs Limits the
Input Differential Voltage
In both circuits, the input series resistors function to limit the
current through the diodes when they are forward-biased. As a
practical matter, these resistors need to be matched to the degree
that the CMRR needs to be preserved at high frequency. These
resistor will have minimal effect on the CMRR at low frequency.
–24–
REV. 0
AD8129/AD8130
Power Dissipation
The AD8129/AD8130 can operate with supply voltages from
+5 V to ± 12 V. The major reason for such a wide supply range
is to provide a wide input common-mode range for systems
that might require this. This would be encountered when significant common-mode noise couples into the input path. For
applications that do not require a wide input or output dynamic
range, it is recommended to operate with lower supply voltages.
The AD8129/AD8130 is also available in a very small Micro_SO-8
package. This has higher thermal impedance than larger packages
and will operate at a higher temperature with the same amount
of power dissipation. Certain operating conditions that are within
the specification range of the parts can cause excess power dissipation. Caution should be exercised.
The power dissipation is a function of several operating conditions. These include the supply voltage, the input differential
voltage, the output load and the signal frequency.
A basic starting point is to calculate the quiescent power dissipation with no signal and no differential input voltage. This is just
the product of the total supply voltage and the quiescent operating current. The maximum operating supply voltage is 26.4 V
and the quiescent current is 13 mA. This causes a quiescent
power dissipation of 343 mW. For the Micro_SO package, the
θJA specification is 142°C/W. So the quiescent power will cause
about a 49°C rise above ambient in the Micro_SO package.
The current consumption is also a function of the differential
input voltage. (See TPCs 109 and 110.) This current should be
added on to the quiescent current and then multiplied by the
total supply voltage to calculate the power.
The AD8129/AD8130 can directly drive loads of as low as
100 Ω, such as a terminated 50 Ω cable. The worst-case power
dissipation in the output stage occurs when the output is at
midsupply. As an example, for a 12 V supply and the output
driving a 250 Ω load to ground, the maximum power dissipation
in the output will occur when the output voltage is 6 V.
REV. 0
The load current will be 6 V/250 Ω = 24 mA. This same current
will flow through the output across a 6 V drop from +VS. This
will dissipate 144 mW. For the Micro_SO-8 package, this causes a
temperature rise of 20°C above ambient. Although this is a worstcase number, it is apparent that this can be a considerable
additional amount of power dissipation.
Several changes can be made to alleviate this. One is to use the
standard SO-8 package. This will lower the thermal impedance
to 121°C/W, which is a 15% improvement. Next is to use a
lower supply voltage unless absolutely necessary.
Finally, do not use the AD8129/AD8130 to directly drive a
heavy load when it is operating on high supply voltages. It is
best to use a second op amp after the output stage. Some of the
gain can be shifted to this stage so that the signal swing at the
output of the AD8129/AD8130 is not too large.
Layout, Grounding and Bypassing
The AD8129/AD8130 are very high-speed parts that can be
sensitive to the PCB environment in which they have to operate. Realizing their superior specifications requires attention
to various details of standard high-speed PCB design practice.
The first requirement is for a good solid ground plane that covers as much of the board area around the AD8129/AD8130 as
possible. The only exception to this is that the ground plane
around the FB pin should be kept a few mm away, and ground
should be removed from inner layers and the opposite side of
the board under this pin. This will minimize the stray capacitance on this node and help preserve the gain flatness versus
frequency.
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high-frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 µF to 0.1 µF for each
supply. Further away, low frequency bypassing should be provided
with 10 µF tantalum capacitors from each supply to ground.
The signal routing should be short and direct in order to avoid
parasitic effects. Where possible, signals should be run over
ground planes to avoid radiating, or to avoid being susceptible
to other radiation sources.
–25–
AD8129/AD8130
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
45
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
8
0.0500 (1.27)
0.0098 (0.25) 0
0.0160 (0.41)
0.0075 (0.19)
8-Lead Micro_SO
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
4
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
SEATING 0.008 (0.20)
PLANE
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
–26–
33
27
0.028 (0.71)
0.016 (0.41)
REV. 0
–27–
–28–
PRINTED IN U.S.A.
C02464–2.5–4/01(0)