LINER LT1024 Dual, matched picoampere, microvolt input, low noise op amp Datasheet

LT1024
Dual, Matched
Picoampere, Microvolt Input,
Low Noise Op Amp
DESCRIPTIO
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FEATURES
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Guaranteed Offset Voltage: 50µV Max
Guaranteed Bias Current:
25°C: 120pA Max
–55°C to 125°C: 700pA Max
Guaranteed Drift: 1.5µV/°C Max
Low Noise, 0.1Hz to 10Hz: 0.5µVP-P
Guaranteed Supply Current: 600µA Max
Guaranteed CMRR: 112dB Min
Guaranteed PSRR: 112dB Min
Guaranteed Voltage Gain with 5mA Load Current
Guaranteed Matching Characteristics
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APPLICATIO S
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Strain Gauge Signal Conditioner
Dual Limit Precision Threshold Detection
Charge Integrators
Wide Dynamic Range Logarithmic Amplifiers
Light Meters
Low Frequency Active Filters
Standard Cell Buffers
Thermocouple Amplifiers
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LT ®1024 dual, matched internally compensated
universal precision operational amplifier can be used in
practically all precision applications requiring multiple op
amps. The LT1024 combines picoampere bias currents
(which are maintained over the full –55°C to 125°C
temperature range), microvolt offset voltage (and low drift
with time and temperature), low voltage and current
noise and low power dissipation. Extremely high
common mode and power supply rejection ratios,
practically immeasurable warm-up drift, and the ability to
deliver 5mA load current with a voltage gain of a million,
round out the LT1024’s superb precision specifications.
Tight matching is guaranteed on offset voltage,
noninverting bias currents and common mode and power
supply rejections.
The all-around excellence of the LT1024 eliminates the
necessity of the time-consuming error analysis procedure
of precision system design in many dual applications; the
LT1024 can be stocked as the universal dual op amp in the
14-pin DIP configuration.
For a single op amp with similar specifications, see the
LT1012 data sheet; for a single supply dual precision op
amp in the 8-pin configuration, see the LT1013 data sheet.
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TYPICAL APPLICATIO
Two Op Amp Instrumentation Amplifier
R1*
100k
R2
10k
3
–
1/2 LT1024
–
4
13
R3
10k
10
+
+
+ R3 ) + R2 + R3
( R2
R1 R4
R5
–
1/2 LT1024
11
INPUTS
GAIN = R4 1 + 1
R3
2
100
R4
100k
~ 100
6
OUTPUT
+
INPUT BIAS CURRENT (pA)
R5
2.2k †
Input Bias Current vs Temperature
50
UNDERCANCELLED UNIT
0
OVERCANCELLED UNIT
–50
–100
TYPICAL PERFORMANCE:
OFFSET VOLTAGE = 20µV
BIAS CURRENT = ±30pA
OFFSET CURRENT = 30pA
–150
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LTC1024 • TA02
* TRIM FOR COMMON-MODE REJECTION
† TRIM FOR GAIN
LT1024 • TA01
1024fa
1
LT1024
W W
W
AXI U
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage ...................................................... ±20V
Differential Input Current (Note 2) ...................... ±10mA
Input Voltage ......................................................... ±20V
Output Short Circuit Duration .......................... Indefinite
Operating Temperature Range
LT1024AM/LT1024M (OBSOLETE).....–55°C to 125°C
LT1024AC/LT1024C ................................ 0°C to 70°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
NULL (A)
1
14 V + (A)
NULL (A)
2
13 OUT (A)
–IN (A)
3
ORDER
PART NUMBER
LT1024ACN
LT1024CN
12 V – (A)
–
+ A
+
11 +IN (B)
–
10 –IN (B)
+IN (A)
4
V – (B)
5
OUT (B)
6
9
NULL (B)
V + (B)
7
8
NULL (B)
B
N PACKAGE
14-PIN PDIP
TJMAX = 100°C, θJA = 100°C/W, θJC = 60°C/W (N)
NOTE: DEVICE MAY BE OPERATED EVEN IF
INSERTION IS REVERSED; THIS IS DUE
TO INHERENT SYMMETRY OF PIN LOCATIONS
OF AMPLIFIERS A AND B (NOTE 3)
ORDER
PART NUMBER
D PACKAGE
14-PIN SIDE BRAZED (HERMETIC)
TJMAX = 150°C, θJA = 100°C/W, θJC = 60°C/W (D)
LT1024AMD
LT1024MD
OBSOLETE PACKAGE
Consider the N14 Package as an Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
Individual Amplifiers. VS = ±15V, VCM = 0V, TA = 25°C unless otherwise noted.
LT1O24AM/LT1O24AC
MIN
TYP
MAX
LT1024M/LT1O24C
MIN
TYP
MAX
Input Offset Voltage
15
20
Long Term Input Offset Voltage Stability
0.3
IOS
Input Offset Current
20
100
25
180
pA
IB
Input Bias Current
±25
±120
±30
±200
pA
en
Input Noise Voltage
0.1Hz to 10Hz
0.5
en
Input Noise Voltage Density
fO = 10Hz (Note 4)
fO = 1000Hz (Note 4)
17
14
in
Input Noise Current Density
fO = 10Hz
20
AVOL
Large-Signal Voltage Gain
VOUT = ±12V, RL ≥ 10kΩ
VOUT = ±10V, RL ≥ 2kΩ
250
150
2000
1000
CMRR
Common Mode Rejection Ratio
VCM = ±13.5V
112
PSRR
Power Supply Rejection Ratio
VS = ±2V to ±20V
SYMBOL PARAMETER
VOS
CONDITIONS
Input Voltage Range
VOUT
Output Voltage Swing
Slew Rate
IS
Supply Current per Amplifier
RL = 10kΩ
50
100
0.3
17
14
µV
µV/month
0.5
33
24
UNITS
µVP-P
33
24
nV/√Hz
nV/√Hz
20
fA/√Hz
180
100
2000
1000
V/mV
V/mV
132
108
132
dB
112
132
108
132
dB
±13.5
±14.0
±13.5
±14.0
V
±13
±14
±13
±14
V
0.1
0.2
0.1
0.2
V/µs
380
600
380
700
µA
1024fa
2
LT1024
ELECTRICAL CHARACTERISTICS
Matching Specifications. VS = ±15V, VCM = 0V, TA = 25°C unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
LT1024AM/LT1024AC
MIN
TYP
MAX
LT1O24M /LT1O24C
MIN
TYP
MAX
UNITS
Input Offset Voltage Match
20
75
25
150
µV
+
Average Noninverting Bias
Current
±30
±150
±40
±250
pA
IOS+
Noninverting Offset Current
30
150
30
300
pA
∆CMRR
Common Mode Rejection Ratio
Match
VCM = ±13.5V
110
132
106
132
dB
∆PSRR
Power Supply Rejection Ratio
Match
VS = ±2V to 20V
110
132
106
132
dB
Channel Separation
f ≤ 10Hz (Note 4)
134
150
134
150
dB
IB
Individual Amplifiers. The ● denotes the specifications which apply over the full operating temperature range of 0°C ≤ TA = 70°C for
the LT1024AC and LT1024C; – 55°C ≤ TA ≤ 125°C for the LT1024AM and LT1024M. VS = ±15V, VCM = 0V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VOS
0°C to 70°C
–55°C to 125°C
Input Offset Voltage
Average Temperature Coefficient of
Input Offset Voltage
IOS
Input Offset Current
0°C to 70°C
–55°C to 125°C
Average Temperature Coefficient of
Input Offset Current
IB
LT1024AM/LT1024AC
MIN
TYP
MAX
MIN
LT1024M/LT1024C
TYP
MAX
UNITS
●
●
30
40
120
200
35
50
200
300
µV
µV
●
0.25
1.5
0.3
2.0
µV/°C
●
●
40
80
250
350
50
100
300
500
pA
pA
●
0.5
2.5
0.7
3
pA/°C
Input Bias Current
0°C to 70°C
–55°C to 125°C
●
●
±40
±100
±250
±700
±50
±200
±400
±1300
Average Temperature Coefficient of
Input Bias Current
0°C to 70°C
–55°C to 125°C
●
●
0.4
1
3
6
0.5
2
4
12
AVOL
Large-Signal Voltage Gain
VOUT = ±12V, RL ≥ 10kΩ
VOUT = ±10V, RL ≥ 2kΩ
●
●
150
100
1000
600
150
100
1000
600
V/mV
V/mV
CMRR
Common Mode Rejection Ratio
VCM = ±13.5V
●
108
128
106
128
dB
PSRR
Power Supply Rejection Ratio
VS = ±2.5V to ±18V
●
108
128
106
128
dB
●
±13.5
●
±13
Input Voltage Range
VOUT
Output Voltage Swing
IS
Supply Current
RL = 10kΩ
●
400
±13
800
pA/°C
pA/°C
V
±13.5
±14
pA
pA
V
±14
400
900
µA
1024fa
3
LT1024
ELECTRICAL CHARACTERISTICS
Matching Specifications. The ● denotes the specifications which apply over
the temperature range of 0°C ≤ TA = 70°C for the LT1024AC and LT1024C; – 55°C ≤ TA ≤ 125°C for the LT1024AM and LT1024M,
VS = ±15V, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER
LT1024AM/LT1024AC
MIN
TYP
MAX
CONDITIONS
Input Offset Voltage Match
0°C to 70°C
–55°C to 125°C
Input Offset Voltage Tracking
MIN
LT1024M/LT1024C
TYP
MAX
UNITS
●
●
35
50
170
280
45
70
300
500
µV
µV
●
0.3
2
0.4
3.5
µV/°C
IB +
Average Noninverting Bias Current
0°C to 70°C
–55°C to 125°C
●
●
±40
±100
±300
±800
±50
±200
±500
±1400
pA
pA
IOS+
Noninverting Offset Current
0°C to 70°C
–55°C to 125°C
●
●
40
80
300
800
50
150
500
1500
pA
pA
∆CMRR
Common Mode Rejection Ratio Match VCM = ±13.5V
●
106
128
104
128
dB
∆PSRR
Power Supply Rejection Ratio Match
●
106
128
104
128
dB
VS = ±2.5V to ±18V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Differential input voltages greater than 1V will cause excessive
current to flow through the input protection diodes unless limiting
resistance is used.
Note 3: The V + supply terminals are completely independent and may be
powered by separate supplies if desired (this approach, however, would
sacrifice the advantages of the power supply rejection ratio matching). The
V – supply terminals are both connected to the common substrate and
must be tied to the same voltage. Both V – pins should be used.
Note 4: This parameter is tested on a sample basis only.
Optional Offset Nulling Circuit
V+
5k TO 100k
POT
1 (8)
3
(10)
–
1/2
4
(11)
2 (9)
14 (7)
LT1024
+
12 (5)
V–
13
(6)
OUTPUT
INPUT OFFSET VOLTAGE CAN BE ADJUSTED
OVER A ±800µV RANGE WITH A 5k TO
100k POTENTIOMETER
LT1024 • EC01
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TYPICAL PERFOR A CE CHARACTERISTICS
Offset Voltage vs Source
Resistance (Balanced or Unbalanced)
60
VS = ±15V
INPUT OFFSET CURRENT (pA)
INPUT OFFSET VOLTAGE (µV)
1000
Input Offset Current vs
Temperature
100
– 55°C TO 125°C
25°C
10
1
1k
3k
10k 30k 100k 300k 1M
SOURCE RESISTANCE (Ω)
3M 10M
LT1024 • TPC01
VS = ±15V
VCM = 0V
50
40
30
20
10
0
– 50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
LT1024 • TPC02
1024fa
4
LT1024
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current Over
Common Mode Range
DEVICE WITH POSITIVE
INPUT CURRENT
20
12
RIN CM = 2 x 10 Ω
DEVICE WITH NEGATIVE
INPUT CURRENT
0
–20
IB
–
+
–40
VS = ±15V
TA = 25°C
VS = ±15V
2
40
4
OFFSET VOLTAGE (µV)
INPUT BIAS CURRENT (pA)
60
5
VS = ±15V
TA = 25°C
40
Warm-Up Drift
CHANGE IN OFFSET VOLTAGE (µV)
60
Offset Voltage Drift and
Tracking with Temperatures of
Representative Units
3
2
1
1
20
1
0
2
–20
2
–40
1 INDIVIDUAL AMPLIFIERS
2 TRACKING (MATCH DRIFT)
VCM
– 60
–15
–60
–50 –25
0
10
–5
0
5
–10
COMMON MODE INPUT VOLTAGE (V)
15
0
1
3
4
2
TIME AFTER POWER ON (MINUTES)
5
Supply Current vs Supply
Voltage per Amplifier
0.1Hz to 10Hz Noise
Noise Spectrum
1000
25°C
125°C
–55°C
2
0
6
4
TIME (SECONDS)
LT1024 • TPC06
8
RS = 2R
0.1
AT 10Hz
AT 1kHz
0.01
102
103
RESISTOR NOISE
ONLY
104
105
106
107
SOURCE RESISTANCE (Ω)
108
LT1024 • TPC09
1/f CORNER
2.5Hz
1/f CORNER
120Hz
1
10
100
FREQUENCY (Hz)
1000
LT1024 • TPC08
Power Supply Rejection vs
Frequency
140
POWER SUPPLY REJECTION RATIO (dB)
COMMON MODE REJECTION RATIO (dB)
AT 10Hz
AT 1kHz
1.0
–
+
VOLTAGE NOISE
10
10
140
R
CURRENT NOISE
Common Mode Rejection and
CMRR Match vs Frequency
10.0
R
100
LT1024 • TPC07
Total Noise vs Source
Resistance
TA = 25°C
VS = ±2V TO ± 20V
TA = 25°C
VS ±2 TO ±20V
1
± 20
±10
±15
±5
SUPPLY VOLTAGE (V)
VOLTAGE NOISE DENSITY (nV/√Hz)
CURRENT NOISE DENSITY (fA/√Hz)
400
0
TA = 25°C
VS ±2V TO ± 20V
NOISE VOLTAGE 400nV/DIVISION
SUPPLY CURRENT (µA)
125
LT1024 • TPC05
500
TOTAL NOISE DENSITY (µV/√Hz)
100
LT1024 • TPC04
LT1024 • TPC03
300
50
25
75
0
TEMPERATURE (°C)
120
CMRR
100
MATCH
(∆CMRR)
80
60
40
20
VS = ±15V
TA = 25°C
0
1
10
10k
1k
100
FREQUENCY (Hz)
100k
1M
LT1024 • TPC10
VS = ±15V
TA = 25°C
120
100
80
POSITIVE
SUPPLY
NEGATIVE
SUPPLY
60
40
20
0.1
1
10
100 1k
10k
FREQUENCY (Hz)
100k
1M
LT1024 • TPC11
1024fa
5
LT1024
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TYPICAL PERFOR A CE CHARACTERISTICS
Channel Separation vs
Frequency
160
140
VS = ±15V
TA = 25°C
150
VS = ±15V
TA = 25°C
120
RS = 10Ω
140
130
VOLTAGE GAIN (dB)
CHANNEL SEPARATION (dB)
Voltage Gain vs Frequency
RS = 100Ω
120
110
RS = 1k
100
80
60
40
100
20
90
0
80
100
1k
10k
100k
FREQUENCY (Hz)
–20
0.01 0.1
1M
1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
LT1024 • TPC12
LT1024 • TPC13
Gain, Phase Shift vs Frequency
Voltage Gain vs Load Resistance
10M
100
40
VS = ±15V
V0 = ±10V
TA = 25°C
VS = ±15V
140
GAIN
10
160
PHASE MARGIN
= 70°C
0
– 55°C
3M
VOLTAGE GAIN
GAIN (dB)
PHASE
20
PHASE SHIFT (DEGREES)
120
30
25°C
1M
125°C
300k
180
–10
0.01
100k
200
0.1
1
FREQUENCY (MHz)
1
10
2
5
10
LOAD RESISTANCE (kΩ)
LT1024 • TPC15
LT1024 • TPC14
Small-Signal Transient
Response
AV = +1
CLOAD = 100pF
5µs/DIV
Large-Signal Transient
Response
2V/DIVISION
20mV/DIVISION
20mV/DIVISION
Small-Signal Transient
Response
20
AV = +1
CLOAD = 1000pF
5µs/DIV
AV = +1
20µs/DIV
1024fa
6
LT1024
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APPLICATIO S I FOR ATIO
these two currents (IOS +) is the offset current of the
instrumentation amplifier. Common mode and power
supply rejections will be dependent only on the match
between the two amplifiers (assuming perfect resistor
matching).
The LT1024 may be inserted directly into OP-10, OP-207
or 0P227 sockets with or without removal of external
nulling components.
The LT1024 is specified over a wide range of power supply
voltages from ±2V to ±18V. Operation with lower supplies
is possible down to ±1.2V (two NiCad batteries).
The concepts of common mode and power supply rejection ratio match (∆CMRR and ∆PSRR) are best demonstrated with a numerical example:
Advantages of Matched Dual Op Amps
In many applications, the performance of a system
depends on the matching between two operational
amplifiers rather than the individual characteristics of the
two op amps. Two or three op amp instrumentation
amplifiers, tracking voltage references, and low drift active
filters are some of the circuits requiring matching between
two op amps.
Assume CMRRA = +1.0µV/V or 120dB
and CMRRB = +0.5µV/V or 126dB,
then ∆CMRR = 0.5µV/V or 126dB
if CMRRB = –0.5µV/V, which is still 126dB,
then ∆CMRR = 1.5µV/V or 116.5dB.
Typical performance of the instrumentation amplifier:
Input offset voltage = 25µV.
Input bias current = 30pA.
Input resistance = 1012 Ω.
Input offset current = 30pA.
Input noise = 0.7µVP-P.
Power bandwidth (VO = ±10V) = 80kHz.
The well-known triple op amp configuration illustrates
these concepts. Output offset is a function of the difference between the offsets of the two halves of the
LT1024. This error cancellation principle holds for a
considerable number of input-referred parameters in
addition to offset voltage and its drift with temperature.
Input bias current will be the average of the two
noninverting input currents (IB + ). The difference between
Clearly, the LT1024, by specifying and guaranteeing all of
these matching parameters, can significantly improve the
performance of matching dependent circuits.
Three Op Amp Instrumentation Amplifier
15V
–INPUT
4
3
+
A
1/2 LT1024
–
R4
100Ω
1%
14
13
R6
10k
1%
R1
10k
1%
12
–15V
15V
R3
2.1k
1%
C1
100pF
R8
200Ω
15V
10
+INPUT
11
–
B
1/2 LT1024
+
R2
10k
1%
7
6
2
R10
100k
–15V
TRIM R8 FOR GAIN
TRIM R9 FOR DC COMMON MODE REJECTION
TRIM R10 FOR AC COMMON MODE REJECTION
7
6
LT1037
3
+
OUTPUT
4
–15V
R5
100Ω
1%
5
–
GAIN = 1000
R7
9.76k
1%
R9
500Ω
LT1024 • AI01
1024fa
7
LT1024
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APPLICATIO S I FOR ATIO
Achieving Picoampere/Microvolt Performance
In order to realize the picoampere/microvolt level
accuracy of the LT1024, proper care must be exercised.
For example, leakage currents in circuitry external to the
op amp can significantly degrade performance. High quality insulation should be used (e.g., Teflon™, Kel-F); cleaning of all insulating surfaces to remove fluxes and other
residues will probably be required. Surface coating may be
necessary to provide a moisture barrier in high humidity
environments.
Microvolt level error voltages can also be generated in the
external circuitry. Thermocouple effects, caused by temperature gradients across dissimilar metals at the contacts to the input terminals, can exceed the inherent drift
of the amplifier. Air currents over device leads should be
minimized, package leads should be short, and the two
input leads should be as close together as possible and
maintained at the same temperature.
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close to
that of the inputs: in inverting configurations, the guard
ring should be tied to ground; in noninverting connections, to the inverting input. Guarding both sides of the
printed circuit board is required. Bulk leakage reduction
depends on the guard ring width. Nanoampere level leakage into the offset trim terminals can affect offset voltage
and drift with temperature.
Teflon is a trademark of Dupont.
Test Circuit for Offset Voltage and its Drift with Temperature
R1
50k*
15V
14 (7)
R2
100Ω*
R3
50k*
3
(10)
–
LT1024
4
(11)
+
12 (5)
–15V
13
(6)
V0
* RESISTORS MUST HAVE LOW
THERMOELECTRIC POTENTIAL
** THIS CIRCUIT IS ALSO USED AS THE BURN-IN
CONFIGURATION FOR THE LT1024. WITH SUPPLY
VOLTAGES INCREASED TO ±20V, R1 = R3 = 20k,
R2 = 200Ω, AV = 100
VO = 1000V0S
LT1024 • AI02
1024fa
8
LT1024
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APPLICATIO S I FOR ATIO
Direct Pressure Transducer to Digital Output Signal Conditioner
fCLK ~~ 10kHz
15V
2N3904
330Ω
28k
TRANSDUCER
ZERO
14k
0.0047µF
OUT B
1N4148
10k
–5V
10k
0.01µF
OUT A
15V
120k*
14
+
13
226k*
10
–
GAIN TRIM
LT1024
–
15V
50k
4
LT1024
11
3
+
12
OUTPUT = fOUT A/fOUT B
7
6
CLK
10k
Q
74C74
D
PRE
Q
CLR
5
–15V
–15V
15V
10µF
–5V
2k
+
620Ω
10k
ADJ
–15V
VIN
10k*
LT137A OUT
*1% METAL FILM RESISTOR
GATES = 74C00
**TRANSDUCER = BLH # DHF-100 PSI
PRESSURE TRANSDUCER
0 – 100 PSI = 0 – 1000
COUNTS FULL-SCALE AT CIRCUIT OUTPUT
2N3904
2N2979
100k
–5V
100k
10k
–15V
LT1024 • AI03
1024fa
9
LT1024
W
W
SCHE ATIC DIAGRA
1/2 LT1024
TRIM
TRIM
2 (9)
1 (8)
V+
14
800Ω
1.3k
800Ω
22k
(7)
4.2k
Q20
Q14
22k
Q30
Q29
Q7
Q8
Q22
4k
Q5
1.5k
Q43
30pF
Q25
Q21
Q6
Q27
Q37
Q16
s
Q24
40Ω
Q4
Q3
OUTPUT
13
3k
100Ω
Q13
Q11 Q23
–INPUT
s
s
Q1
3
1.5k
Q28
s
Q15
Q2
50k
Q26
J1
Q9
+INPUT
Q38
1.5k
(10)
Q12
Q33
Q39
4
(11)
16k
Q18
Q17
Q19
Q35
Q36
Q40
20k
3.3k
3.3k
4.3k
V–
Q42
Q32
Q31
Q10
(6)
40Ω
Q34
3.3k
4.8k
Q41
320Ω
40Ω
330Ω
12
(5)
LT1024 * SD01
1024fa
10
LT1024
U
PACKAGE DESCRIPTIO
D Package
14-Lead Side Brazed (Hermetic)
(Reference LTC DWG # 05-08-1210)
.005
(0.127)
MIN
.760
(19.304)
MAX
14
13
12
11
10
9
8
.290
(7.366)
TYP
PIN NO. 1
IDENT
1
.020 – .060
(0.508 – 1.524)
2
3
4
5
6
7
.485
(12.319)
MAX
.165
(4.191)
MAX
.008 – .015
(0.203 – 0.381)
.300
(7.620)
REF
.125
(3.175)
MIN
.100
(2.54)
BSC
.015 – .023
(0.381 – 0.584)
.054
(1.372)
TYP
D14 0801
OBSOLETE PACKAGE
1024fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1024
U
PACKAGE DESCRIPTIO
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.770*
(19.558)
MAX
14
13
12
11
10
9
8
1
2
3
4
5
6
7
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
+.035
.325 –.015
(
+0.889
8.255
–0.381
.120
(3.048)
MIN
)
NOTE:
1. DIMENSIONS ARE
.005
(0.125) .100
MIN (2.54)
BSC
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.018 ± .003
(0.457 ± 0.076)
N14 1002
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1884
Picoamp Input, Precision Op Amp
Rail-to-Rail Output
1024fa
12
Linear Technology Corporation
LW/TP 1002 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 1988