AD AD8008AR Ultralow distortion high speed amplifier Datasheet

Ultralow Distortion
High Speed Amplifiers
AD8007/AD8008
FEATURES
Extremely Low Distortion
Second Harmonic
–88 dBc @ 5 MHz
–83 dBc @ 20 MHz (AD8007)
–77 dBc @ 20 MHz (AD8008)
Third Harmonic
–101 dBc @ 5 MHz
–92 dBc @ 20 MHz (AD8007)
–98 dBc @ 20 MHz (AD8008)
High Speed
650 MHz, –3 dB Bandwidth (G = +1)
1000 V/␮s Slew Rate
Low Noise
2.7 nV/√Hz Input Voltage Noise
22.5 pA/√Hz Input Inverting Current Noise
Low Power
9 mA/Amplifier Typ Supply Current
Wide Supply Voltage Range
5 V to 12 V
0.5 mV Typical Input Offset Voltage
Small Packaging
SOIC-8, MSOP, and SC70 Packages Available
APPLICATIONS
Instrumentation
IF and Baseband Amplifiers
Filters
A/D Drivers
DAC Buffers
CONNECTION DIAGRAMS
SOIC (R)
SC70 (KS-5)
AD8007
NC 1
(Top View)
AD8007
VOUT 1
8 NC
–IN 2
7 +VS
+IN 3
6 VOUT
–VS 4
5 NC
(Top View)
5
+VS
4
–IN
–VS 2
+IN 3
NC = NO CONNECT
SOIC (R) and MSOP (RM)
AD8008
VOUT1 1
(Top View)
8
+VS
–IN1 2
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
The AD8007 is available in a tiny SC70 package as well as a
standard 8-lead SOIC. The dual AD8008 is available in both
8-lead SOIC and 8-lead MSOP packages. These amplifiers are
rated to work over the industrial temperature range of –40°C
to +85°C.
GENERAL DESCRIPTION
The AD8007/AD8008 have 650 MHz bandwidth, 2.7 nV/√Hz
voltage noise, –83 dB SFDR @ 20 MHz (AD8007), and –77 dBc
SFDR @ 20 MHz (AD8008).
With the wide supply voltage range (5 V to 12 V) and wide bandwidth, the AD8007/AD8008 are designed to work in a variety of
applications. The AD8007/AD8008 amplifiers have a low power
supply current of 9 mA/amplifier.
–30
G = +2
RL = 150⍀
VS = 5V
VOUT = 2V p-p
–40
–50
DISTORTION – dBc
The AD8007 (single) and AD8008 (dual) are high performance current feedback amplifiers with ultralow distortion
and noise. Unlike other high performance amplifiers, the low
price and low quiescent current allow these amplifiers to be
used in a wide range of applications. ADI’s proprietary second
generation eXtra-Fast Complementary Bipolar (XFCB)
process enables such high performance amplifiers with low
power consumption.
–60
–70
SECOND
–80
–90
THIRD
–100
–110
1
10
FREQUENCY – MHz
100
Figure 1. AD8007 Second and Third Harmonic
Distortion vs. Frequency
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD8007/AD8008–SPECIFICATIONS
VS = ⴞ5 V (@ T = 25ⴗC, R = 200 ⍀, R = 150 ⍀, R = 499 ⍀, Gain = +2, unless otherwise noted.)
A
S
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Overdrive Recovery Time
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Third Order Intercept
Crosstalk (AD8008)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Transimpedance
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Saturation Voltage
Short Circuit Current, Source
Short Circuit Current, Sink
Capacitive Load Drive
L
F
Conditions
Min
G = +1, VO = 0.2 V p-p, RL = 1 kΩ
G = +1, VO = 0.2 V p-p, RL = 150 Ω
G = +2, VO = 0.2 V p-p, RL = 150 Ω
G = +1, VO = 2 V p-p, RL = 1 kΩ
VO = 0.2 V p-p, G = +2, RL = 150 Ω
± 2.5 V Input Step, G = +2, RL = 1 kΩ
G = +1, VO = 2 V Step
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step
540
250
180
200
50
900
AD8007/AD8008
Typ
Max
Unit
650
500
230
235
90
30
1000
18
35
MHz
MHz
MHz
MHz
MHz
ns
V/µs
ns
ns
fC = 5 MHz, VO = 2 V p-p
fC = 20 MHz, VO = 2 V p-p
fC = 5 MHz, VO = 2 V p-p
fC = 20 MHz, VO = 2 V p-p
fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ,
VO = 2 V p-p
fC = 5 MHz, RL = 1 kΩ
fC = 20 MHz, RL = 1 kΩ
f = 5 MHz, G = +2
f = 100 kHz
–Input, f = 100 kHz
+Input, f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
–88
–83/–77
–101
–92/–98
dBc
dBc
dBc
dBc
–77
43.0/42.5
42.5
–68
2.7
22.5
2
0.015
0.010
dBc
dBm
dBm
dB
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
+Input
–Input
+Input
–Input
VO = ± 2.5 V, RL = 1 kΩ
RL = 150 Ω
1.0
0.4
0.5
3
4
0.4
16
9
1.5
0.8
56
4
1
–3.9 to +3.9
59
MΩ
pF
V
dB
1.1
130
90
8
1.2
V
mA
mA
pF
12
10.2
V
mA
+Input
+Input
VCM = ± 2.5 V
VCC – VOH, VOL – VEE, RL = 1 kΩ
30% Overshoot
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
+PSRR
–PSRR
5
9
59
59
–2–
64
65
4
8
6
mV
µV/°C
µA
µA
nA/°C
nA/°C
MΩ
MΩ
dB
dB
REV. D
AD8007/AD8008
VS = 5 V
(@ TA = 25ⴗC, RS = 200 ⍀, RL = 150 ⍀, RF = 499 ⍀, Gain = +2, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Overdrive Recovery Time
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
Third Order Intercept
Crosstalk (AD8008)
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Transimpedance
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Saturation Voltage
Short Circuit Current, Source
Short Circuit Current, Sink
Capacitive Load Drive
Conditions
Min
G = +1, VO = 0.2 V p-p, RL = 1 kΩ
G = +1, VO = 0.2 V p-p, RL = 150 Ω
G = +2, VO = 0.2 V p-p, RL = 150 Ω
G = +1, VO = 1 V p-p, RL = 1 kΩ
Vo = 0.2 V p-p, G = +2, RL = 150 Ω
2.5 V Input Step, G = +2, RL = 1 kΩ
G = +1, VO = 2 V Step
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step
520
350
190
270
72
fC = 5 MHz, VO = 1 V p-p
fC = 20 MHz, VO = 1 V p-p
fC = 5 MHz, VO = 1 V p-p
fC = 20 MHz, VO = 1 V p-p
fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ,
VO = 1 V p-p
fC = 5 MHz, RL = 1 kΩ
fC = 20 MHz, RL = 1 kΩ
Output to Output f = 5 MHz, G = +2
f = 100 kHz
–Input, f = 100 kHz
+Input, f = 100 kHz
+Input
–Input
+Input
–Input
VO = 1.5 V to 3.5 V, RL = 1 kΩ
RL = 150 Ω
VCM = 1.75 V to 3.25 V
MHz
MHz
MHz
MHz
MHz
ns
V/µs
ns
ns
–96/–95
–83/–80
–100
–85/–88
–89/–87
dBc
dBc
dBc
dBc
dBc
43.0
42.5/41.5
–68
2.7
22.5
2
dBm
dBm
dB
nV/√Hz
pA/√Hz
pA/√Hz
0.5
0.4
54
4
1
1.1 to 3.9
56
VCC – VOH, VOL – VEE, RL = 1 kΩ
1.05
70
50
8
30% Overshoot
5
8.1
59
59
–3–
Unit
580
490
260
320
120
30
740
18
35
0.5
3
4
0.7
15
8
1.3
0.6
+Input
+Input
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
+PSRR
–PSRR
REV. D
665
AD8007/AD8008
Typ
Max
62
63
4
8
6
mV
µV/°C
µA
µA
nA/°C
nA/°C
MΩ
MΩ
MΩ
pF
V
dB
1.15
V
mA
mA
pF
12
9
V
mA
dB
dB
AD8007/AD8008
RMS output voltages should be considered. If RL is referenced
to VS, as in single-supply operation, then the total drive power
is VS ⫻ IOUT.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . See Figure 2
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 1.0 V
Output Short Circuit Duration . . . . . . . . . . . . . . See Figure 2
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (soldering 10 sec) . . . . . . . . . 300°C
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply:
2
VS 
 4
 
PD = (VS × IS ) +
RL
In single-supply operation, with RL referenced to VS, worst case is
V
VOUT = S
2
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes will
reduce the θJA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in
the board layout section.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8007/AD8008
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die will locally reach
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8007/
AD8008. Exceeding a junction temperature of 175°C for an
extended period of time can result in changes in the silicon
devices, potentially causing failure.
Figure 2 shows the maximum safe power dissipation in the package versus ambient temperature for the SOIC-8 (125°C/W),
MSOP (150°C/W), and SC70 (210°C/W) packages on a JEDEC
standard 4-layer board. θJA values are approximations.
MAXIMUM POWER DISSIPATION – W
2.0
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as follows:
TJ = TA + (PD × θJA )
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (VS) times the quiescent current
(IS). Assuming the load (RL ) is referenced to midsupply, the
total drive power is VS/2 ⫻ IOUT, some of which is dissipated in the
package and some in the load (VOUT ⫻ IOUT). The difference
between the total drive power and the load power is the drive
power dissipated in the package.
MSOP-8
SOIC-8
1.0
SC70-5
0.5
0
–60
–40
–20
0
20
40
60
AMBIENT TEMPERATURE – ⴗC
80
100
Figure 2. Maximum Power Dissipation vs.
Temperature for a 4-Layer Board
PD = quiescent power + (total drive power – load power):
V
 V
V
PD = (VS × IS ) +  S × OUT  − OUT
RL 
RL
 2
1.5
OUTPUT SHORT CIRCUIT
2
Shorting the output to ground or drawing excessive current for
the AD8007/AD8008 will likely cause catastrophic failure.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8007/AD8008 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. D
AD8007/AD8008
ORDERING GUIDE
Model
Temperature Range
Package
Description
Package Outline
AD8007AR
AD8007AR-REEL
AD8007AR-REEL7
AD8007AKS-R2
AD8007AKS-REEL
AD8007AKS-REEL7
AD8008AR
AD8008AR-REEL7
AD8008AR-REEL
AD8008ARM
AD8008ARM-REEL
AD8008ARM-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
5-Lead SC70
5-Lead SC70
5-Lead SC70
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
R-8
R-8
R-8
KS-5
KS-5
KS-5
R-8
R-8
R-8
RM-8
RM-8
RM-8
REV. D
–5–
Branding
HTA
HTA
HTA
H2B
H2B
H2B
AD8007/AD8008–Typical Performance Characteristics
(VS = ⴞ5 V, RL = 150 ⍀, RS = 200 ⍀, RF = 499 ⍀, unless otherwise noted.)
3
6.4
2
6.3
G = +1
6.2
0
6.1
G = +2
–1
GAIN – dB
NORMALIZED GAIN – dB
1
G = +2
–2
–3
–4
6.0
VS = +5V
5.9
5.8
VS = ⴞ5V
5.7
G = +10
–5
5.6
G = –1
–6
–7
5.5
1
10
100
FREQUENCY – MHz
5.4
10
1000
3
9
G = +1
G = +2
2
8
1
7
RL = 1k⍀, VS = ⴞ5V
RL = 1k⍀, VS = +5V
6
–1
GAIN – dB
GAIN – dB
0
RL = 150⍀, VS = ⴞ5V
–2
–3
–4
RL = 150⍀, VS = +5V
3
100
FREQUENCY – MHz
RL = 1k⍀, VS = ⴞ5V
–1
10
1000
TPC 2. Small Signal Frequency Response for VS and RLOAD
100
FREQUENCY – MHz
1000
TPC 5. Small Signal Frequency Response for VS and RLOAD
9
3
G = +2
G = +1
RL = 1k⍀
RF = RG = 324⍀
8
1
7
RS = 200⍀
6
–1
5
GAIN – dB
0
–2
RS = 301⍀
RS = 249⍀
RF = RG = 249⍀
4
3
RF = RG = 499⍀
2
1
–5
RF = RG = 649⍀
0
–6
–7
10
RL = 150⍀, VS = ⴞ5V
0
–7
10
–4
RL = 150⍀
VS = +5V
4
1
–6
GAIN – dB
5
2
–5
–3
1000
TPC 4. 0.1 dB Gain Flatness; VS = +5, ± 5 V
TPC 1. Small Signal Frequency Response for Various Gains
2
100
FREQUENCY – MHz
100
FREQUENCY – MHz
–1
10
1000
TPC 3. Small Signal Frequency Response for
Various R S Values
100
FREQUENCY – MHz
1000
TPC 6. Small Signal Frequency Response for Various
Feedback Resistors, R F = RG
–6–
REV. D
AD8007/AD8008
10M
20pF
20pF AND
20⍀ SNUB
8
20pF AND
10⍀ SNUB
GAIN – dB
6
5
499⍀
4
499⍀
3
RSNUB
0pF
200⍀
49.9⍀
1
0
1
10
100
FREQUENCY – MHz
PHASE
10k
–90
1k
–150
–180
100
–210
10
–270
1
10k
1000
TPC 7. Small Signal Frequency Response for Capacitive
Load and Snub Resistor
3
–1
5
GAIN – dB
0
6
VS = +5V, –40ⴗC
VS = ⴞ5V, –40ⴗC
VS = ⴞ5V, +85ⴗC
VS = +5V, –40ⴗC
VS = ⴞ5V, –40ⴗC
3
–4
2
1
–6
0
–1
10
1000
100
FREQUENCY – MHz
1000
TPC 11. Small Signal Frequency Response over
Temperature, VS = +5 V, ± 5 V
TPC 8. Small Signal Frequency Response over
Temperature, VS = +5 V, ± 5 V
9
3
G = +2
VOUT = 2V p-p
8
2
G = +1 G = +2
1
7
6
0
GAIN – dB
–1
G = +10
–2
G = –1
–3
5
4
3
–4
2
–5
1
–6
0
–7
VS = +5V, +85ⴗC
4
–5
100
FREQUENCY – MHz
–330
1G 2G
G = +2
7
–7
10
100M
8
1
–3
10M
1M
FREQUENCY – Hz
9
VS = ⴞ5V, +85ⴗC
–2
100k
TPC 10. Transimpedance and Phase vs. Frequency
VS = +5V, +85ⴗC
G = +1
2
1
10
100
FREQUENCY – MHz
RL = 150⍀, VS = ⴞ5V, VO = 2V p-p
–1
10
1000
TPC 9. Large Signal Frequency Response for Various Gains
REV. D
0
–30
CLOAD
2
GAIN – dB
30
TRANSIMPEDANCE
100k
7
NORMALIZED GAIN – dB
90
1M
TRANSIMPEDANCE – ⍀
G = +2
9
PHASE – Degrees
10
RL = 1k⍀, VS = ⴞ5V, VO = 2V p-p
RL = 150⍀, VS = +5V, VO = 1V p-p
RL = 1k⍀, VS = +5V, VO = 1V p-p
100
FREQUENCY – MHz
1000
TPC 12. Large Signal Frequency Response for VS and R LOAD
–7–
AD8007/AD8008
–40
–40
G = ⴙ1
VS = 5V
VO = 1V p-p
–50
HD2, RL = 150⍀
–50
HD3, RL = 150⍀
DISTORTION – dBc
DISTORTION – dBc
HD2, RL = 1k⍀
–70
HD3, RL = 1k⍀
–80
–70
–90
–100
–100
–110
1
–40
10
FREQUENCY – MHz
1
100
100
10
FREQUENCY – MHz
TPC 16. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R L
–40
G = ⴙ1
VS = ⴞ5V
VO = 2V p-p
–50
G = ⴙ2
VS = ⴞ5V
VO = 2V p-p
–50
–60
–60
DISTORTION – dBc
DISTORTION – dBc
HD3, RL = 150⍀
HD3, RL = 1k⍀
TPC 13. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R L
HD2, RL = 150⍀
–70
HD2, RL = 1k⍀
–80
HD3, RL = 150⍀
HD2, RL = 1k⍀
–70
HD2, RL = 150⍀
–80
–90
–90
HD3, RL = 1k⍀
–100
1
–110
100
10
FREQUENCY – MHz
–30
100
HD3, VO = 4V p-p
–50
HD3, G = ⴙ10
–70
–80
HD3, G = ⴙ1
HD2, VO = 4V p-p
–60
–70
HD2, VO = 2V p-p
–80
–90
–90
HD2, G = ⴙ1
–100
10
FREQUENCY – MHz
G = +2
VS = 5V
RL = 150⍀
–40
DISTORTION – dBc
–60
1
–30
HD2, G = ⴙ10
–50
HD3, RL = 1k⍀
TPC 17. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R L
VS = ⴞ5V
VO = 2V p-p
RL = 150⍀
–40
HD3, RL = 150⍀
–100
TPC 14. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R L
DISTORTION – dBc
HD2, RL = 150⍀
–80
–90
–110
HD2, RL = 1k⍀
–60
–60
–110
G = ⴙ2
VS = 5V
VO = 1V p-p
HD3, VO = 2V p-p
–100
–110
–110
1
10
FREQUENCY – MHz
1
100
TPC 15. AD8007 Second and Third Harmonic Distortion
vs. Frequency and Gain
10
FREQUENCY – MHz
100
TPC 18. AD8007 Second and Third Harmonic Distortion
vs. Frequency and V OUT
–8–
REV. D
AD8007/AD8008
(VS = ⴞ5 V, RS = 200 ⍀, RF = 499 ⍀, RL = 150 ⍀, @ 25°C, unless otherwise noted.)
–40
–40
G=1
VS = 5V
VO = 1V p-p
–50
–60
–60
DISTORTION – dBc
DISTORTION – dBc
G=2
VS = 5V
VO = 1V p-p
–50
HD2, RL = 150⍀
–70
HD2, RL = 1k⍀
–80
HD2, RL = 150⍀
–70
HD2, RL = 1k⍀
–80
–90
–90
HD3, RL = 1k⍀
HD3, RL = 1k⍀
–100
–100
HD3, RL = 150⍀
HD3, RL = 150⍀
–110
1
10
–110
100
1
10
FREQUENCY – MHz
FREQUENCY – MHz
TPC 19. AD8008 Second and Third Harmonic
Distortion vs. Frequency and RL
TPC 22. AD8008 Second and Third Harmonic
Distortion vs. Frequency and RL
–40
–40
G=1
VS = 5V
VO = 1V p-p
–50
G=2
VS = 5V
VO = 2V p-p
–50
–60
HD2, RL = 1k⍀
–60
DISTORTION – dBc
DISTORTION – dBc
100
–70
HD2, RL = 150⍀
–80
HD2, RL = 1k⍀
–90
–70
HD2, RL = 150⍀
–80
–90
HD3, RL = 1k⍀
–100
–100
HD3, RL = 1k⍀
–110
1
HD3, RL = 150⍀
HD3, RL = 150⍀
10
FREQUENCY – MHz
–110
100
TPC 20. AD8008 Second and Third Harmonic
Distortion vs. Frequency and RL
G=2
RL = 150⍀
VS = 5V
–40
–50
–50
HD2, G = 10
DISTORTION – dBc
DISTORTION – dBc
100
–30
VS = 5V
VO = 2V p-p
RL = 150 ⍀
–40
–60
–70
–80
HD2, G = 1
–90
–60
HD2, VO = 4V p-p
–70
HD2, VO = 2V p-p
–80
–90
–100
HD3, G = 10
1
10
FREQUENCY – MHz
HD3, VO = 4V p-p
–100
HD3, G = 1
HD3, VO = 2V p-p
–110
100
TPC 21. AD8008 Second and Third Harmonic
Distortion vs. Frequency and Gain
REV. D
10
FREQUENCY – MHz
TPC 23. AD8008 Second and Third Harmonic
Distortion vs. Frequency and RL
–30
–110
1
1
10
FREQUENCY – MHz
TPC 24. AD8008 Second and Third Harmonic
Distortion vs. Frequency and VOUT
–9–
100
AD8007/AD8008
–60
–65
G = ⴙ2
VS = 5V
FO = 20MHz
–65
HD3, RL = 1k⍀
G = ⴙ2
VS = ⴞ5V
FO = 20MHz
–70
HD3, RL = 1k⍀
–75
HD2, RL = 150⍀
DISTORTION – dBc
DISTORTION – dBc
HD2, RL = 1k⍀
–70
HD3, RL = 150⍀
–75
–80
–80
–85
HD2, RL = 1k⍀
–90
HD3, RL = 150⍀
–95
HD2, RL = 150⍀
–100
–85
–105
–90
1
1.5
–110
2.5
2
1
3
4
VOUT – V p-p
2
VOUT – V p-p
44
44
G = +2
VS = ⴞ5V
VO = 2V p-p
RL = 1k⍀
42
G = ⴙ2
VS = 5V
VO = 2V p-p
RL = 1k⍀
43
THIRD ORDER INTERCEPT – dBm
43
THIRD ORDER INTERCEPT – dBm
6
TPC 28. AD8007 Second and Third Harmonic
Distortion vs. VOUT and RL
TPC 25. AD8007 Second and Third Harmonic
Distortion vs. VOUT and RL
41
40
39
38
37
36
42
41
40
39
38
37
36
35
5
10
15
20
25
30 35 40 45 50
FREQUENCY – MHz
55
60
65
35
70
10
15
20
25
30 35 40 45 50
FREQUENCY – MHz
55
60
65
70
–65
G = ⴙ2
VS = 5V
FO = 20MHz
–70
5
TPC 29. AD8008 Third Order Intercept vs. Frequency
TPC 26. AD8007 Third Order Intercept vs. Frequency
–65
5
HD2, RL = 1k⍀
–70
HD2, RL = 150⍀
HD2, RL = 150⍀
–75
HD2, RL = 1k⍀
–80
HD3, RL = 150⍀
–75
–85
HD3, RL = 1k⍀
–90
–80
HD3, RL = 150⍀
–95
HD3, RL = 1k⍀
–100
–85
G = ⴙ2
VS = 5V
FO = 20MHz
–105
–90
–110
1
1.5
2
2.5
VOUT – V p-p
1
2
3
4
VOUT – V p-p
5
6
TPC 30. AD8008 Second and Third Harmonic
Distortion vs. VOUT and RL
TPC 27. AD8008 Second and Third Harmonic
Distortion vs. VOUT and RL
–10–
REV. D
AD8007/AD8008
(VS = ⴞ5 V, RL = 150 ⍀, RS = 200 ⍀, RF = 499 ⍀, unless otherwise noted.)
1000
CURRENT NOISE – pA/ Hz
VOLTAGE NOISE – nV/ Hz
100
10
2.7nV/ Hz
1
10
10k
1k
FREQUENCY – Hz
100
100k
100
INVERTING CURRENT NOISE 22.5pA / Hz
10
1
10
1M
TPC 31. Input Voltage Noise vs. Frequency
NONINVERTING CURRENT NOISE 2.0pA/ Hz
1k
100
100k
10k
FREQUENCY – Hz
1M
10M
TPC 34. Input Current Noise vs. Frequency
1000
–20
G = ⴙ2
G = ⴙ2
R = 150⍀
VS = ⴞ5V
VM = 1V p-p
–30
100
CROSSTALK – dB
OUTPUT IMPEDANCE – ⍀
–40
10
1
SIDE B DRIVEN
–50
–60
–70
SIDE A DRIVEN
–80
0.1
–90
0.01
100k
–100
1M
10M
FREQUENCY – Hz
100M
1G
100k
1M
10M
FREQUENCY – Hz
100M
1G
TPC 35. AD8008 Crosstalk vs. Frequency (Output to Output)
TPC 32. Output Impedance vs. Frequency
20
0
VS = ⴞ5V, ⴙ5V
10
–10
0
–10
PSRR – dB
CMRR – dB
–20
–30
–40
–20
–30
+PSRR
–40
–50
–50
–60
–60
–70
100k
1M
10M
FREQUENCY – Hz
100M
–80
10k
1G
100k
10M
1M
FREQUENCY – Hz
100M
TPC 36. PSRR vs. Frequency
TPC 33. CMRR vs. Frequency
REV. D
–PSRR
–70
–11–
1G
AD8007/AD8008
RL = 150⍀, VS = ⴙ5V AND ⴞ5V
G = ⴙ1
G = +2
RL = 150⍀, VS = +5V AND 5V
RL = 1k⍀, VS = +5V AND 5V
RL = 1k⍀, VS = ⴙ5V AND ⴞ5V
50mV/DIV
50mV/DIV
0
20
30
TIME – ns
10
40
0
50
20
30
TIME – ns
40
50
TPC 40. Small Signal Transient Response for
RL = 150 Ω, 1 kΩ and VS = +5 V, ± 5 V
TPC 37. Small Signal Transient Response for
RL = 150 Ω, 1 kΩ and VS = +5 V, ± 5 V
G = +1
10
G = –1
RL = 150⍀
INPUT
RL = 1k⍀
OUTPUT
1V/DIV
1V/DIV
0
10
20
30
TIME – ns
40
0
50
20
30
TIME – ns
40
50
TPC 41. Large Signal Transient Response, G = –1,
RL = 150 Ω
TPC 38. Large Signal Transient Response for
RL = 150 Ω, 1 kΩ
G = ⴙ2
10
CL = 0pF
G = ⴙ2
CLOAD = 0pF
CL = 20pF
CLOAD = 10pF
CL = 20pF
RSNUB = 10⍀
CLOAD = 20pF
499⍀
499⍀
200⍀
RSNUB
–
+
CLOAD
49.9⍀
50mV/DIV
1V/DIV
0
10
20
30
TIME – ns
40
0
50
10
20
30
TIME – ns
40
50
TPC 42. Small Signal Transient Response: Effect of
Series Snub Resistor when Driving Capacitive Load
TPC 39. Large Signal Transient Response
for Capacitive Load = 0 pF, 10 pF, and 20 pF
–12–
REV. D
AD8007/AD8008
4
G = +10
VS = 5V
VIN = 0.75V
3
G = ⴙ2
ⴙVS
2
RL = 1k⍀
VOUT – V
1
RL = 150⍀
0
–1
OUTPUT (2V/DIV)
–2
INPUT (1V/DIV)
ⴚVS
–3
–4
0
100
200
300
TIME – ns
400
500
0
0.5
G = +2
SETTLING TIME – %
0.3
0.2
0.1
0
ⴚ0.1
18ns
ⴚ0.3
ⴚ0.4
0
5
10
15
20
25
TIME – ns
30
35
40
45
TPC 44. 0.1% Settling Time, 2 V Step
REV. D
600
800
1000
TPC 45. VOUT Swing vs. RLOAD, VS = ± 5 V, G = +10,
VIN = ± 0.75 V
0.4
ⴚ0.5
400
RL – ⍀
TPC 43. Output Overdrive Recovery, RL = 1 kΩ,
150 Ω, VIN = ± 2.5 V
ⴚ0.2
200
–13–
AD8007/AD8008
THEORY OF OPERATION
The AD8007 (single) and AD8008 (dual) are current feedback
amplifiers optimized for low distortion performance. A simplified
conceptual diagram of the AD8007 is shown in Figure 3. It closely
resembles a classic current feedback amplifier comprised of a
complementary emitter-follower input stage, a pair of signal mirrors, and a diamond output stage. However, in the case of the
AD8007/AD8008, several modifications have been made to greatly
improve the distortion performance over that of a classic current
feedback topology.
USING THE AD8007/AD8008
Supply Decoupling for Low Distortion
Decoupling for low distortion performance requires careful
consideration. The commonly adopted practice of returning the
high frequency supply decoupling capacitors to physically separate (and possibly distant) grounds can lead to degraded
even-order harmonic performance. This situation is shown in
Figure 4 using the AD8007 as an example. Note that for a sinusoidal input, each decoupling capacitor returns to its ground a
quasi-rectified current carrying high even-order harmonics.
RF
499⍀
+VS
M1
GND 1
– I3
I1 –
CJ1
+VS
Q1
D1
IDI
IN+
RG
499⍀
Q3
IDO
HiZ
IN–
OUT
D2
IN
Q2
10␮F
+
0.1␮F
Q5
+VS
RS
200⍀
AD8007
OUT
Q4
–VS
CJ2
–VS
Q6
10␮F
+
0.1␮F
I2 –
– I4
M2
GND 2
–VS
Figure 4. High Frequency Capacitors Returned
to Physically Separate Grounds (Not Recommended)
RF
RG
Figure 3. Simplified Schematic of AD8007
The signal mirrors have been replaced with low distortion, high
precision mirrors. They are shown as “M1” and “M2” in Figure 3.
Their primary function from a distortion standpoint is to greatly
reduce the effect of highly nonlinear distortion caused by capacitances CJ1 and CJ2. These capacitors represent the collector-to-base
capacitances of the mirrors’ output devices.
The decoupling scheme shown in Figure 5 is preferable. Here,
the two high frequency decoupling capacitors are first tied
together at a common node, and are then returned to the
ground plane through a single connection. By first adding the
two currents flowing through each high frequency decoupling
capacitor, one is ensuring that the current returned into the
ground plane is only at the fundamental frequency.
RF
499⍀
A voltage imbalance arises across the output stage, as measured
from the high impedance node “HiZ” to the output node
“Out.” This imbalance is a result of delivering high output
currents and is the primary cause of output distortion. Circuitry
is included to sense this output voltage imbalance and generate
a compensating current “IDO.” When injected into the circuit,
IDO reduces the distortion that would be generated at the output
stage. Similarly, the nonlinear voltage imbalance across the
input stage (measured from the noninverting to the inverting
input) is sensed, and a current “IDI” is injected to compensate
for input-generated distortion.
10␮F
+
RG
499⍀
IN
+VS
0.1␮F
RS
200⍀
AD8007
OUT
0.1␮F
–VS
10␮F
The design and layout are strictly top-to-bottom symmetric in
order to minimize the presence of even-order harmonics.
+
Figure 5. High Frequency Capacitors Returned
to Ground at a Single Point (Recommended)
Whenever physical layout considerations prevent the decoupling
scheme shown in Figure 5, the user can connect one of the high
frequency decoupling capacitors directly across the supplies and
connect the other high frequency decoupling capacitor to ground.
This is shown in Figure 6.
–14–
REV. D
AD8007/AD8008
RF
499⍀
Output Capacitance
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. There are two methods to
effectively minimize its effect:
10␮F
+
+VS
1. Put a small value resistor in series with the output to isolate
the load capacitance from the amplifier’s output stage.
(See TPC 7.)
C1
0.1␮F
RG
499⍀
IN
RS
200⍀
AD8007
2. Increase the phase margin by (a) increasing the amplifier’s
gain or (b) adding a pole by placing a capacitor in parallel
with the feedback resistor.
OUT
C2
0.1␮F
–VS
10␮F
Input-to-Output Coupling
To minimize capacitive coupling, the input and output signal
traces should not be parallel. This helps reduce unwanted positive feedback.
+
Figure 6. High Frequency Capacitors Connected
across the Supplies (Recommended)
External Components and Stability
The AD8007 and AD8008 are current feedback amplifiers and,
to a first order, the feedback resistor determines the bandwidth
and stability. The gain, load impedance, supply voltage, and
input impedances also have an effect.
Layout Considerations
The standard noninverting configuration with recommended power
supply bypassing is shown in Figure 6. The 0.1 µF high frequency decoupling capacitors should be X7R or NPO chip
components. Connect C2 from the +VS pin to the –VS pin. Connect C1 from the +VS pin to signal ground.
The length of the high frequency bypass capacitor leads is critical.
Parasitic inductance due to long leads will work against the low
impedance created by the bypass capacitor. The ground for the
load impedance should be at the same physical location as the
bypass capacitor grounds. For the larger value capacitors, which
are intended to be effective at lower frequencies, the current
return path distance is less critical.
LAYOUT AND GROUNDING CONSIDERATIONS
Grounding
A ground plane layer is important in densely packed PC boards
to minimize parasitic inductances. However, an understanding of
where the current flows in a circuit is critical to implementing
effective high speed circuit design. The length of the current path
is directly proportional to the magnitude of parasitic inductances and thus the high frequency impedance of the path. High
speed currents in an inductive ground return will create an
unwanted voltage noise. Broad ground plane areas will reduce
the parasitic inductance.
Input Capacitance
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance will reduce the input impedance at high frequencies, in turn increasing the amplifier’s gain,
causing peaking of the frequency response or even oscillations
if severe enough. It is recommended that the external passive components that are connected to the input pins be placed as close as
possible to the inputs to avoid parasitic capacitance. The ground
and power planes must be kept at a distance of at least 0.05 mm
from the input pins on all layers of the board.
REV. D
TPC 6 shows the effect of changing RF on bandwidth and peaking
for a gain of +2. Increasing RF will reduce peaking but also
reduce the bandwidth. TPC 1 shows that for a given RF, increasing
the gain will also reduce peaking and bandwidth. Table I shows
the recommended RF and RG values that optimize bandwidth with
minimal peaking.
Table I. Recommended Component Values
Gain
RF(Ω)
RG(Ω)
RS (Ω)
–1
+1
+2
+5
+10
499
499
499
499
499
499
NA
499
124
54.9
200
200
200
200
200
The load resistor will also affect bandwidth as shown in TPCs 2
and 5. A comparison between TPCs 2 and 5 also demonstrates
the effect of gain and supply voltage.
When driving loads with a capacitive component, stability is
improved by using a series snub resistor RSNUB at the output.
The frequency and pulse responses for various capacitive loads
are illustrated in TPCs 7 and 42, respectively.
For noninverting configurations, a resistor in series with the input,
RS, is needed to optimize stability for Gain = +1, as illustrated
in TPC 3. For larger noninverting gains, the effect of a series
resistor is reduced.
–15–
AD8007/AD8008
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
6.20 (0.2440)
5.80 (0.2284)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
SEATING
0.10
PLANE
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4.90
BSC
3.00
BSC
1
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
8ⴗ
0ⴗ
0.23
0.08
0.80
0.60
0.40
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
2.00 BSC
4
5
1.25 BSC
2.10 BSC
1
2
3
PIN 1
0.65 BSC
1.00
0.90
0.70
0.10 MAX
1.10 MAX
0.22
0.08
0.30
0.15
0.10 COPLANARITY
SEATING
PLANE
0.46
0.36
0.26
COMPLIANT TO JEDEC STANDARDS MO-203AA
–16–
REV. D
AD8007/AD8008
Revision History
Location
Page
6/03—Data Sheet changed from REV. C to REV. D
Change to Layout Considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Deleted Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Deleted EVALUATION BOARD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10/02—Data Sheet changed from REV. B to REV. C
CONNECTION DIAGRAMS captions updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ORDERING GUIDE updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9/02—Data Sheet changed from REV. A to REV. B.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8/02—Data Sheet changed from REV. 0 to REV. A.
Added AD8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Added SOIC-8 (RN) and MSOP-8 (RM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to MAXIMUM POWER DISSIPATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
New TPCs 19–24 and TPCs 27, 29, 30, and 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to EVALUATION BOARD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MSOP-8 (RM) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REV. D
–17–
–18–
–19–
–20–
C02866–0–6/03(D)