CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM
with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC)
Features
Functional Description
■
No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
■
Supports up to 133 MHz bus operations with zero wait states
❐ Data is transferred on every clock
■
Pin-compatible and functionally equivalent to ZBT™ devices
■
Internally self-timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow through operation
■
Byte write capability
■
3.3 V/2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
■
Clock enable (CEN) pin to enable clock and suspend operation
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Available in JEDEC-standard Pb-free 100-pin TQFP packages
■
Three chip enables for simple depth expansion
■
Automatic power-down feature available using ZZ mode or CE
deselect
■
Burst capability – linear or interleaved burst order
■
Low standby power
■
On chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are
3.3 V, 512K × 36/1M × 18 synchronous flow through burst SRAM
designed specifically to support unlimited true back-to-back
read/write operations with no wait state insertion. The
CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33
are
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by the two or four byte write
select (BWX) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Selection Guide
Description
133 MHz
Maximum access time
Maximum operating current
Cypress Semiconductor Corporation
Document Number: 001-97852 Rev. *F
•
198 Champion Court
•
100 MHz
Unit
6.5
8.5
ns
× 18
129
114
mA
× 36
149
134
mA
San Jose, CA 95134-1709
•
408-943-2600
Revised February 8, 2018
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Logic Block Diagram – CY7C1371KV33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
CE
C
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
S
E
N
S
E
ADV/LD
BW A
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW B
BW C
MEMORY
ARRAY
A
M
P
S
BW D
WE
INPUT
REGISTER
OE
CE1
CE2
CE3
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1371KVE33
ADDRESS
REGISTER
A0, A1, A
MODE
C
CLK
/CEN
A1
D1
A0
D0
Q1
Q0
A1'
A0'
BURST LOGIC
/CE
ADV or /LD
C
WRITE ADDRESS
REGISTER
ADV or /LD
WRITE
DRIVERS
/BWA
/BWB
/BWC
MEMORY
ARRAY
S
E
N
S
E
D
A
T
A
ECC
DECODER
A
M
P
S
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
/BWD
/WE
/OE
/CE1
CE2
/CE1
ZZ
READ
LOGIC
ECC
ENCODER
INPUT
REGISTER
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQS
DQPA
DQPB
DQPC
DQPD
E
E
SLEEP
CONTROL
Document Number: 001-97852 Rev. *F
Page 2 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Logic Block Diagram – CY7C1373KV33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 001-97852 Rev. *F
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
E
E
READ LOGIC
SLEEP
CONTROL
Page 3 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses .................................................. 9
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Truth Table for Read/Write ................................ 12
Partial Truth Table for Read/Write ................................ 12
Maximum Ratings ........................................................... 13
Operating Range ............................................................. 13
Neutron Soft Error Immunity ......................................... 13
Electrical Characteristics ............................................... 13
Document Number: 001-97852 Rev. *F
Capacitance .................................................................... 15
Thermal Resistance ........................................................ 15
AC Test Loads and Waveforms ..................................... 15
Switching Characteristics .............................................. 16
Switching Waveforms .................................................... 17
Ordering Information ...................................................... 20
Ordering Code Definitions ......................................... 20
Package Diagrams .......................................................... 21
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Document History Page ................................................. 23
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Page 4 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
A
81
A
82
A
83
A
84
ADV/LD
85
VSS
90
OE
VDD
91
86
CE3
92
CEN
BWA
93
87
BWB
94
WE
BWC
95
88
BWD
96
CLK
CE2
97
89
CE1
98
A
42
43
44
45
46
47
48
49
50
NC/72M
NC/36M
A
A
A
A
A
A
A
41
A0
40
37
A1
VSS
36
A
VDD
35
A
39
34
A
NC/144M
33
A
38
32
Document Number: 001-97852 Rev. *F
NC/288M
31
BYTE D
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
CY7C1371KV33/CY7C1371KVE33
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 5 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Configurations (continued)
Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
A
81
A
82
A
83
A
84
ADV/LD
85
OE
86
CEN
87
90
WE
VSS
91
88
VDD
92
CLK
CE3
93
89
BWB
BWA
94
NC
95
NC
CE2
97
96
CE1
98
A
42
43
44
45
46
47
48
49
50
NC/72M
NC/36M
A
A
A
A
A
A
A
41
VDD
37
A0
40
36
A1
VSS
35
A
39
34
A
NC/144M
33
A
38
32
A
Document Number: 001-97852 Rev. *F
NC/288M
31
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
CY7C1373KV33
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 6 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
synchronous A[1:0] are fed to the two-bit burst counter.
InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
BWA, BWB,
BWC, BWD synchronous edge of CLK.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the Clock signal is masked. While deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
ZZ
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Document Number: 001-97852 Rev. *F
Page 7 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Definitions (continued)
Name
I/O
Description
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:D] are placed in a tristate condition.The outputs are automatically tristated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
DQPX
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs.
synchronous
MODE
Input strap pin Mode input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
I/O power
supply
VSS
Ground
NC
–
Power supply for the I/O circuitry.
Ground for the device.
No connects. Not internally connected to the die. NC/(36M, 72M, 144M, 288M, 576M, 1G) are address
expansion pins and are not internally connected to the die.
Document Number: 001-97852 Rev. *F
Page 8 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Functional Overview
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 is a
synchronous flow through burst SRAM designed specifically to
eliminate wait states during write-read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133 MHz
device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are all asserted active
■
The write enable input signal WE is deasserted HIGH
■
ADV/LD is asserted LOW.
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output is tristated immediately.
Burst Read Accesses
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 has
an on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four reads without
reasserting the address inputs. ADV/LD must be driven LOW to
load a new address into the SRAM, as described in the Single
Document Number: 001-97852 Rev. *F
Read Accesses section above. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enable inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
type of access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1371KV33/CY7C1371KVE33/
CY7C1373KV33 provides byte write capability that is described
in the truth table. Asserting the write enable input (WE) with the
selected byte write select input selectively writes to only the
desired bytes. Bytes not selected during a byte write operation
remains unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1371KV33/CY7C1371KVE33/
CY7C1373KV33 is a common I/O device, data must not be
driven into the device while the outputs are active. The output
enable (OE) can be deasserted HIGH before presenting data to
the DQs and DQPX inputs. Doing so tristates the output drivers.
As a safety precaution, DQs and DQPX are automatically
tristated during the data portion of a write cycle, regardless of the
state of OE.
Burst Write Accesses
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 has
an on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in the Single Write
Accesses section above. When ADV/LD is driven HIGH on the
subsequent clock rise, the chip enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BWX inputs must be driven in each cycle of the burst
write, to write the correct bytes of data.
Page 9 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Sleep mode standby current
Test Conditions
ZZ > VDD– 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ active to sleep current
tRZZI
ZZ Inactive to exit sleep current
Document Number: 001-97852 Rev. *F
Min
Max
Unit
–
65
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 10 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Truth Table
The truth table for CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are as follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tristate
Deselect cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tristate
Deselect cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tristate
Continue deselect cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tristate
Read cycle (begin burst)
External
L
H
L
L
L
H
X
L
L
L->H Data out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tristate
Next
X
X
X
L
H
X
X
H
L
L->H
Tristate
External
L
H
L
L
L
L
L
X
L
L->H Data in (D)
Write cycle (continue burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data in (D)
NOP/write abort (begin burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tristate
Write abort (continue burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tristate
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Ignore clock edge (stall)
Sleep mode
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects
are asserted, see truth table for details.
2. Write is defined by BWX, and WE. See Truth Table for read/write.
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tristate when OE is inactive
or when the device is deselected, and DQs and DQPX = data when OE is active.
Document Number: 001-97852 Rev. *F
Page 11 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1371KV33/CY7C1371KVE33 follows. [8, 9, 10]
Function (CY7C1371KV33/CY7C1371KVE33)
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write no bytes written
L
H
H
H
H
Write byte A – (DQA and DQPA)
L
L
H
H
H
Write byte B – (DQB and DQPB)
L
H
L
H
H
Write byte C – (DQC and DQPC)
L
H
H
L
H
Write byte D – (DQD and DQPD)
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1373KV33 follows. [8, 9, 10]
Function (CY7C1373KV33)
WE
BWA
BWB
Read
H
X
X
Write - no bytes written
L
H
H
Write byte A – (DQA and DQPA)
L
L
H
Write byte B – (DQB and DQPB)
L
H
L
Write all bytes
L
L
L
Notes
8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one byte write select is active, BWX = valid signifies that the desired byte write selects
are asserted, see Truth Table on page 11 for details.
9. Write is defined by BWX, and WE. See Truth Table on page 11 for read/write.
10. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is based on which byte write is active.
Document Number: 001-97852 Rev. *F
Page 12 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Ambient
Temperature
Commercial
0 °C to +70 °C
Industrial
–40 °C to +85 °C
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................. > 2001 V
Latch up current ..................................................... > 200 mA
Range
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Neutron Soft Error Immunity
Parameter
Description
LSBU
(Device
without
ECC)
LSBU
(Device with
ECC)
LMBU
Logical
Single-Bit
Upsets
SEL
Test
Conditions Typ
25 °C
<5
Logical
Multi-Bit
Upsets
Single Event
Latch up
Max*
Unit
5
FIT/
Mb
0
0.01
FIT/
Mb
25 °C
0
0.01
FIT/
Mb
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [11, 12]
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage [11]
VIL
[11]
Test Conditions
IX
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
–
0.4
V
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
Input LOW Voltage
Min
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
VDD + 0.3
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input Current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Input Current of ZZ
Notes
11. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
12. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) of at least 200 ms. During this time VIH < VDD and VDDQ <VDD.
Document Number: 001-97852 Rev. *F
Page 13 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [11, 12]
Description
Test Conditions
IOZ
Output Leakage Current
GND VI VDDQ, Output Disabled
IDD
VDD Operating Supply
VDD = Max.,
IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE Power-down
Current – TTL Inputs
Max. VDD,
Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
Min
Max
Unit
–5
5
A
–
114
mA
100 MHz
× 18
× 36
–
134
133 MHz
× 18
–
129
× 36
–
149
× 18
–
75
× 36
–
80
× 18
–
75
× 36
–
80
100 MHz
133 MHz
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD,
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f=0
All speed
grades
× 18
–
65
× 36
–
70
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD,
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
100 MHz
× 18
–
75
× 36
–
80
× 18
–
75
Max. VDD,
Device Deselected,
VIN VIH or VIN VIL,
f=0
All speed
grades
Automatic CE Power-down
Current – TTL Inputs
Document Number: 001-97852 Rev. *F
133 MHz
× 36
–
80
× 18
–
65
× 36
–
70
mA
mA
mA
mA
Page 14 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Capacitance
Parameter
100-pin TQFP
Package
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test With Still Air (0 m/s)
methods and procedures for
With Air Flow (1 m/s)
measuring thermal impedance, per
EIA/JESD51.
With Air Flow (3 m/s)
37.95
C/W
33.19
C/W
30.44
C/W
24.07
C/W
8.36
C/W
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
Thermal Resistance
Parameter
JA
Description
Thermal resistance
(junction to ambient)
JB
Thermal resistance
(junction to board)
JC
Thermal resistance
(junction to case)
--
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1ns
1ns
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25 V
(a)
Document Number: 001-97852 Rev. *F
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1ns
1ns
(c)
Page 15 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
tPOWER
Description
VDD(typical) to the first access [15]
133 MHz
100 MHz
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
10
–
ns
tCH
Clock HIGH
2.1
–
2.5
–
ns
tCL
Clock LOW
2.1
–
2.5
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
–
8.5
ns
tDOH
Data output hold after CLK rise
2.0
–
2.0
–
ns
2.0
–
2.0
–
ns
–
4.0
–
5.0
ns
–
3.2
–
3.8
ns
0
–
0
–
ns
–
4.0
–
5.0
ns
[16, 17, 18]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [16, 17, 18]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[16, 17, 18]
OE HIGH to output high Z
[16, 17, 18]
Setup Times
tAS
Address setup before CLK rise
1.5
–
1.5
–
ns
tALS
ADV/LD setup before CLK rise
1.5
–
1.5
–
ns
tWES
WE, BWX setup before CLK rise
1.5
–
1.5
–
ns
tCENS
CEN setup before CLK rise
1.5
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.5
–
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.5
–
0.5
–
ns
tWEH
WE, BWX hold after CLK rise
0.5
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
0.5
–
ns
Hold Times
Notes
13. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
14. Test conditions shown in (a) of Figure 3 on page 15 unless otherwise noted.
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can
be initiated.
16. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 15. Transition is measured ±200 mV from steady-state voltage.
17. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z
prior to low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 001-97852 Rev. *F
Page 16 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Switching Waveforms
Figure 4. Read/Write Waveforms [19, 20, 21]
1
2
3
t CYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
A4
A3
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
19. For this waveform ZZ is tied LOW.
20. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-97852 Rev. *F
Page 17 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Switching Waveforms (continued)
Figure 5. NOP, STALL AND DESELECT Cycles [22, 23, 24]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 001-97852 Rev. *F
Page 18 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
26. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-97852 Rev. *F
Page 19 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit
us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Ordering Code
CY7C1371KV33-133AXC
Package
Diagram
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1373KV33-133AXI
Operating
Range
Commercial
Industrial
CY7C1371KVE33-133AXI
100
CY7C1371KV33-100AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1373KV33-100AXC
CY7C1371KV33-100AXI
Industrial
CY7C1371KVE33-100AXI
Ordering Code Definitions
CY
7
C
13XX KV E 33 - XXX XX
X X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A
A = 100-pin TQFP
Speed Grade: XXX = 100 or 133 MHz
33 = 3.3 V VDD
E = Device with ECC; blank = Device without ECC
Process Technology: K =65 nm
Part Identifier: 13XX = 1371 or 1373
1371 = FT, 512Kb × 36 (18Mb)
1373 = FT, 1Mb × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-97852 Rev. *F
Page 20 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-97852 Rev. *F
Page 21 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
CE
Chip Enable
°C
degree Celsius
CEN
Clock Enable
MHz
megahertz
EIA
Electronic Industries Alliance
µA
microampere
I/O
Input/Output
mA
milliampere
JEDEC
Joint Electron Devices Engineering Council
mm
millimeter
JTAG
Joint Test Action Group
ms
millisecond
LSB
Least Significant Bit
mV
millivolt
MSB
Most Significant Bit
nm
nanometer
NoBL
No Bus Latency
OE
Output Enable
SRAM
Static Random Access Memory
TAP
TCK
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
Test Access Port
V
volt
Test Clock
W
watt
TDI
Test Data Input
TMS
Test Mode Select
TDO
Test Data Output
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-97852 Rev. *F
Page 22 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Document History Page
Document Title: CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with
NoBL™ Architecture (With ECC)
Document Number: 001-97852
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*C
4983482
DEVM
10/23/2015
Changed status from Preliminary to Final.
*D
5085569
DEVM
01/14/2016
Post to external web.
*E
5333298
PRIT
07/01/2016
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device
without ECC) parameter.
Updated to new template.
*F
6063409
CNX
02/08/2018
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Document Number: 001-97852 Rev. *F
Page 23 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/clocks
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cypress.com/iot
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cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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Document Number: 001-97852 Rev. *F
Revised February 8, 2018
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
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