The MC74AC256/74ACT256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Clear and Enable inputs (see Function Table). In the addressable latch mode, data at the Data (D) inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held HIGH (inactive) while the address lines are changing. In the dual 1-of-4 decoding or demultiplexing mode (MR = E = LOW), addressed outputs will follow the level of the D inputs with all other outputs LOW. In the clear mode, all outputs are LOW and unaffected by the Address and Data inputs. • • • • • • • Combines Dual Demultiplexer and 8-Bit Latch Serial-to-Parallel Capability Output from Each Storage Bit Available Random (Addressable) Data Entry Easily Expandable Common Clear Input Useful as Dual 1-of-4 Active HIGH Decoder VCC 16 MR E 15 14 Db 13 Q3b 12 Q2b 11 Q1b 10 1 2 3 4 5 6 7 8 A1 Da Q0a Q1a Q2a Q3a GND N SUFFIX CASE 648-08 PLASTIC D SUFFIX CASE 751B-05 PLASTIC Q0b 9 A0 DUAL 4-BIT ADDRESSABLE LATCH LOGIC SYMBOL Db Da A0 E MR A1 Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b FACT DATA 5-1 MC74AC256 MC74ACT256 MODE SELECT-FUNCTION TABLE Inputs Operating Mode Outputs MR E D A0 A1 Q0 Q1 Q2 Q3 Master Reset L H X X X L L L L Demultiplex (Active HIGH Decoder when D = H) L L L L L L L L d d d d L H L H L L H H Q=d L L L L Q=d L L L L Q=d L L L L Q=d Store (Do Nothing) H H X X X q0 q1 q2 q3 Addressable Latch H H H H L L L L d d d d L H L H L L H H Q=d q0 q0 q0 q1 Q=d q1 q1 q2 q2 Q=d q2 q3 q3 q3 Q=d H = HIGH Voltage Level Steady State L = LOW Voltage Level Steady State X = Immaterial d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. LOGIC DIAGRAM E Da Q0a A0 Q1a A1 Q2a MR Db Q3a Q0b Q1b Q2b Q3b Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. MAXIMUM RATINGS* Symbol Parameter Value Unit –0.5 to +7.0 V DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Sink/Source Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C VCC DC Supply Voltage (Referenced to GND) Vin * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. FACT DATA 5-2 MC74AC256 MC74ACT256 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH IOL Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs tr, tf Min Unit V VCC VCC @ 3.0 V 150 VCC @ 4.5 V 40 VCC @ 5.5 V 25 VCC @ 4.5 V 10 VCC @ 5.5 V 8.0 V ns/V ns/V 140 °C 85 °C Output Current — High –24 mA Output Current — Low 24 mA –40 25 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = –40°C to +85°C Typ VIH VIL VOH 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC – 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC – 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.46 3.76 4.76 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 5.5 ±0.1 Maximum Low Level Output Voltage Maximum Input Leakage Current IOLD †Minimum Dynamic Output Current ICC Guaranteed Limits 3.0 4.5 5.5 IIN IOHD Conditions Minimum High Level Input Voltage 3.0 4.5 5.5 VOL Unit Maximum Quiescent Supply Current 3.0 4.5 5.5 0.002 0.001 0.001 IOUT = –50 µA V *VIN = VIL or VIH –12 mA IOH –24 mA –24 mA IOUT = 50 µA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA ±1.0 µA VI = VCC, GND 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. FACT DATA 5-3 MC74AC256 MC74ACT256 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Dn to Qn 3.3 5.0 2.0 2.0 9.0 6.5 14.5 10.0 1.5 1.5 17.0 11.5 ns 3-5 tPHL Propagation Delay Dn to Qn 3.3 5.0 2.0 2.0 9.0 6.0 13.5 9.5 1.5 1.5 16.0 11.0 ns 3-5 tPLH Propagation Delay E to Qn 3.3 5.0 2.0 2.0 10.5 7.0 15.0 10.5 1.5 1.5 17.5 12.5 ns 3-6 tPHL Propagation Delay E to Qn 3.3 5.0 2.0 2.0 8.0 7.5 12.5 9.0 1.5 1.5 15.0 11.0 ns 3-6 tPLH Propagation Delay Address to Qn 3.3 5.0 2.0 2.0 12.0 8.0 19.0 13.0 1.5 1.5 22.5 15.5 ns 3-6 tPHL Propagation Delay Address to Qn 3.3 5.0 2.0 2.0 10.0 7.0 16.0 11.0 1.5 1.5 19.0 13.0 ns 3-6 tPHL Propagation Delay MR to Q 3.3 5.0 2.0 2.0 8.0 6.0 12.0 9.0 1.5 1.5 13.5 10.0 ns 3-7 Unit Fig. No. * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) Typ 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to E 3.3 5.0 3.5 2.5 4.5 3.5 ns 3-9 th Hold Time, HIGH or LOW Dn to E 3.3 5.0 2.5 2.0 2.5 2.0 ns 3-9 ts Setup Time Address to E 3.3 5.0 7.0 4.0 9.0 6.0 ns 3-6 th Hold Time Address to E 3.3 5.0 2.0 2.0 2.0 2.0 ns 3-6 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-4 MC74AC256 MC74ACT256 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = –40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC – 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC – 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 3.86 4.86 3.76 4.76 0.1 0.1 0.1 0.1 4.5 5.5 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA ±0.1 ±1.0 µA VI = VCC, GND 1.5 mA VI = VCC – 2.1 V 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 V V IOUT = –50 µA *VIN = VIL or VIH –24 mA IOH –24 mA IOUT = 50 µA IIN Maximum Input Leakage Current 5.5 ∆ICCT Additional Max. ICC/Input 5.5 IOLD †Minimum Dynamic Output Current 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current 0.6 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. FACT DATA 5-5 MC74AC256 MC74ACT256 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Dn to Qn 5.0 2.0 6.5 11.5 1.5 13.0 ns 3-5 tPHL Propagation Delay Dn to Qn 5.0 2.0 7.0 11.0 1.5 12.5 ns 3-5 tPLH Propagation Delay E to Qn 5.0 2.0 8.0 12.0 1.5 14.0 ns 3-6 tPHL Propagation Delay E to Qn 5.0 2.0 6.5 10.5 1.5 12.5 ns 3-6 tPLH Propagation Delay Address to Qn 5.0 2.0 10.5 14.5 1.5 17.0 ns 3-6 tPHL Propagation Delay Address to Qn 5.0 2.0 9.0 12.5 1.5 14.5 ns 3-6 tPHL Propagation Delay MR to Q 5.0 2.0 7.0 10.5 1.5 11.5 ns 3-7 Unit Fig. No. * Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to E 5.0 3.5 4.5 ns 3-9 th Hold Time, HIGH or LOW Dn to E 5.0 2.5 2.5 ns 3-9 ts Setup Time Address to E 5.0 5.5 6.5 ns 3-6 th Hold Time Address to E 5.0 2.5 2.5 ns 3-6 * Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 30.0 pF VCC = 5.0 V FACT DATA 5-6 MC74AC256 MC74ACT256 OUTLINE DIMENSIONS N SUFFIX PLASTIC DIP PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M M DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A– 20 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X J D 0.010 (0.25) M T A B S S F R X 45 _ C –T– 18X G SEATING PLANE K T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0_ 7_ 0_ 7_ P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ FACT DATA 5-7 *MC74AC256/D* MC74AC256/D