DA9211 and DA9212 Company confidential Datasheet 1. General description DA9211 and DA9212 are PMUs optimised for the supply of CPUs, GPUs, and DDR memory rails in smartphones, tablets and other handheld applications. The fast transient response (10A/µs) and load regulation are optimised for the new generation of multi-core application processors. DA9212 integrates two dual-phase buck converters, each phase using a small external 0.47 µH inductor. Each buck is capable of delivering up to 6 A output current at an output voltage in the range 0.3 - 1.57 V. The input voltage range of 2.8 – 5.5 V makes it suited for a wide variety of low voltage systems, including all Li-Ion battery-powered applications. DA9211 operates as a single four-phase buck converter delivering up to 12 A output current. To guarantee the highest accuracy and to support multiple PCB routing scenarios without loss of performance, a remote sensing capability is implemented in both DA9211 and DA9212. The power devices are fully integrated, so no external FETs or Schottky diodes are needed. A programmable soft start-up can be enabled, which limits the inrush current from the input node and secures a slope-controlled activation of the rail. The Dynamic Voltage Control (DVC) supports adaptive adjustment of the supply voltage depending on the processor load, either via direct register writes through the communication interface (I2C or SPI compatible) or via an input pin. A voltage tracking functionality is implemented allowing the buck output voltage to be controlled by an analogue input signal. This feature, together with a digital clock input, allows complete control of the buck converter from external signals in the platform. DA9211 and DA9212 feature integrated over-temperature and over-current protection for increased system reliability without the need for external sensing components. The safety feature set is completed by a VDDIO under voltage lockout. The configurable I2C address selection via GPI allows multiple instances of DA9211 and DA9212 or both to be placed in the application sharing the same communication interface with different addresses. 2. Key features ■ ■ ■ ■ ■ ■ ■ ■ ■ 2.8 V to 5.5 V Input voltage 0.3 V to 1.57 V Output voltage 12 A Output Current (DA9211) 2x 6 A Output Current (DA9212) 3 MHz nominal Switching Frequency Max Inductor height 1.0 mm ±1 % Accuracy (static) ±3 % Accuracy (dynamic) ■ ■ ■ ■ ■ ■ ■ ■ Automatic Phase Shedding Integrated Power Switches Remote Sensing at Point of Load I2C/SPI compatible Interface Output Voltage Tracking Capability Adjustable Soft Start -40 to +85 ºC Temperature Range Package 42 WL-CSP 0.4 mm pitch Dynamic Voltage Control (DVC) Data sheet CFR0011-120-00 Rev 3 Version <3.0> 1 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 3. Applications ■ Smartphones, Mobile Phones and Ultra books ■ Portable Navigation Devices, TV and Media players ■ Tablet PCs, E-Book Readers and Car Infotainment 1µF VDD_B2 VDD_B1 VDD_A2 VSYS VDD_A1 4. System diagrams 4x 10µF FBAP IC_EN GPI0 GPI GPI1 GPI GPIO2 GPIO OTP MEMORY DIGITAL CORE REGISTER SPACE BIAS SUPERV OSC CTRL + DRIVE L/C/R PCB 4x 0.47µH nIRQ PoL 4x 22µF OUT VDDIO 2/4-WIRE INTERFACE DVS IN FBAN FBBP FBBN nCS/GPI4 GPIO IN SCL/SK SO/GPIO3 GPIO VSS_ANA SDA/SI 100nF Figure 1: DA9211 System diagram Data sheet CFR0011-120-00 Rev 3 Version <3.0> 2 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential 1µF VDD_B2 4x 10µF Buck A IC_EN GPI0 GPI GPI1 GPI GPIO2 VDD_B1 VDD_A2 VSYS VDD_A1 Datasheet GPIO DIGITAL CORE OTP MEMORY CTRL + DRIVE 2x 0.47µH L/C/R PCB PoL 2x 22µF BIAS SUPERV OSC REGISTER SPACE DVS DAC Buck B nIRQ FBAP OUT VDDIO 2/4-WIRE INTERFACE 100nF CTRL + DRIVE FBAN FBBP 2x 0.47µH L/C/R PCB PoL IN GPIO IN GPIO 2x 22µF VSS_ANA DVS DAC nCS/GPI4 SO/GPIO3 SCL/SK SDA/SI FBBN Figure 2: DA9212 System diagram Data sheet CFR0011-120-00 Rev 3 Version <3.0> 3 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Contents 1. General description ....................................................................................................................... 1 2. Key features ................................................................................................................................... 1 3. Applications ................................................................................................................................... 2 4. System diagrams ........................................................................................................................... 2 5. Revision history ............................................................................................................................ 7 6. Terms and definitions ................................................................................................................... 7 7. Ordering information .................................................................................................................... 8 8. Pin information .............................................................................................................................. 8 9. Absolute maximum ratings ........................................................................................................ 11 10. Recommended operating conditions ........................................................................................ 11 11. Electrical characteristics ............................................................................................................ 12 12. Typical Characteristics ............................................................................................................... 21 13. Functional description ................................................................................................................ 28 13.1 DC-DC Buck Converter ....................................................................................................... 32 13.1.1 Switching Frequency .............................................................................................. 32 13.1.2 Operation Modes and Phase Selection .................................................................. 33 13.1.3 Output Voltage Selection ........................................................................................ 33 13.1.4 Soft Start up ............................................................................................................ 34 13.1.5 Current Limit ........................................................................................................... 34 13.2 Ports Description ................................................................................................................. 35 13.2.1 VDDIO ..................................................................................................................... 35 13.2.2 IC_EN ..................................................................................................................... 35 13.2.3 nIRQ ........................................................................................................................ 35 13.2.4 GPIO Extender........................................................................................................ 36 13.3 Operating Modes ................................................................................................................. 38 13.3.1 ON Mode................................................................................................................. 38 13.3.2 OFF Mode ............................................................................................................... 39 13.4 Control Interfaces ................................................................................................................ 40 13.4.1 4-WIRE Communication ......................................................................................... 40 13.4.2 2-WIRE Communication ......................................................................................... 44 13.4.3 Details of the 2-WIRE control bus protocol ............................................................. 45 13.5 Internal Temperature Supervision ....................................................................................... 48 14. Register definitions ..................................................................................................................... 49 14.1 Register map ....................................................................................................................... 49 14.2 Register Definitions ............................................................................................................. 50 14.2.1 Register Page Control ............................................................................................ 50 14.2.2 Register Page 0 ...................................................................................................... 50 14.2.3 Register Page 1 ...................................................................................................... 57 Data sheet Version <3.0> <07-Jan-2015> CFR0011-120-00 Rev 3 4 of 74 © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 14.2.4 Register Page 2 ...................................................................................................... 64 15. Application Information .............................................................................................................. 71 15.1 Capacitor Selection ............................................................................................................. 71 15.2 Inductor Selection ............................................................................................................... 71 16. Package information ................................................................................................................... 73 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 5 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Figures Figure 1: DA9211 System diagram ....................................................................................................... 2 Figure 2: DA9212 System diagram ....................................................................................................... 3 Figure 4: Connection diagram ............................................................................................................... 8 Figure 5: 2-WIRE Bus Timing .............................................................................................................. 18 Figure 6: 4-WIRE Bus Timing .............................................................................................................. 19 Figure 32: Interface of DA9211/12 with DA9063 and the host processor ........................................... 28 Figure 33: Typical application of DA9211 ............................................................................................ 29 Figure 34: Typical application of DA9212 ............................................................................................ 31 Figure 35: Concept of control of the buck’s output voltage ................................................................. 34 Figure 36: GPIO principle of operation (example paths) ..................................................................... 38 Figure 37: Schematic of 4-WIRE and 2-WIRE Power Manager Bus .................................................. 41 Figure 38: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) ............. 42 Figure 39: 4-WIRE Host Write and Read Timing (nCS_POL= ‘0’, CPOL = ‘0’, CPHA = ‘1’) .............. 42 Figure 40: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) ............. 43 Figure 41: 4-WIRE Host Write and Read Ttiming (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) ............ 43 Figure 42: Timing of 2-WIRE START and STOP Condition ................................................................ 45 Figure 43: 2-WIRE Byte Write (SDA Line) .......................................................................................... 46 Figure 44: Examples of 2-WIRE Byte Read (SDA Line) ..................................................................... 46 Figure 45: Examples of 2-WIRE Page Read (SDA Line) .................................................................... 46 Figure 46: 2-WIRE Page Write (SDA Line) ......................................................................................... 47 Figure 47: 2-WIRE Repeated Write (SDA Line) .................................................................................. 47 Figure 49: DA9211/12 WL-CSP package outline drawing .................................................................. 73 Tables Table 1: Ordering information ................................................................................................................ 8 Table 2: Pin description ......................................................................................................................... 9 Table 3: Pin type definition .................................................................................................................. 10 Table 4: Absolute maximum ratings (Note 1) ...................................................................................... 11 Table 5: Recommended operating conditions (Note 1) ....................................................................... 11 Table 6: Buck Converters Characteristics ........................................................................................... 12 Table 7: IC Performance and Supervision .......................................................................................... 15 Table 8: Digital I/O Characteristics ...................................................................................................... 16 Table 9: 2-WIRE Control Bus Characteristics ..................................................................................... 17 Table 10: 4-WIRE Control Bus Characteristics ................................................................................... 19 Table 11: Graphs of Typical Characteristics ....................................................................................... 20 Table 12: Selection of the buck current limit from the coil parameters ............................................... 35 Table 13: 4-WIRE Clock Configurations .............................................................................................. 41 Table 14: 4-WIRE Interface Summary ................................................................................................ 44 Table 15: Over-temperature thresholds .............................................................................................. 48 Table 16: Register map ....................................................................................................................... 49 Table 17: Recommended capacitor types ........................................................................................... 71 Table 18: Recommended inductor types ............................................................................................. 72 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 6 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 5. Revision history Version Date Description 2.0 Feb 2014 Initial Release 2.1 July 2014 Updated transient line Updated UVLO electrical characteristics Swapped GPIO0 and GPIO1 Updated IC_EN electrical characteristics Update OSC_TUNE register Updated quiescent current in PFM 2.2 November 2014 Updated GPI0-4, SCL, SDA VIH and VIL specification Updated IC_EN description and timing relation to VDD_IO Updated use case 2-phases Update IQ according to NEROII-34 Fixed block diagrams assignment to DA9211 and DA9212 Added limitation on use of power good Removed force PFM mode selection Added minimum on time Updated load and line transient performances Updated quiescent current in PWM 3.0 January 2015 Added performance plots (to be done) Updated IQ Added Typical Characteristics Updated Application Information Added power dissipation 6. Terms and definitions AP CPU DDR DVC GPU IC OTP PCB PMIC POL Data sheet CFR0011-120-00 Rev 3 Application Processor Central Processing Unit Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory) Dynamic Voltage Control Graphic Processing Unit Integrated Circuit One Time Programmable memory Printed Circuit Board Power Management Integrated Circuit Point Of Load Version <3.0> 7 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 7. Ordering information The order number consists of the part number followed by a suffix indicating the packing method. For details, please consult the customer portal on the Dialog web site or your local sales representative. Table 1: Ordering information Part number Package Package description Package outline DA9211-xxUU2 42 WL-CSP T&R, 5000pcs Figure 49 DA9211-xxUU6 42 WL-CSP Waffle DA9212-xxUU2 42 WL-CSP T&R, 5000pcs DA9212-xxUU6 42 WL-CSP Waffle 8. Pin information A 1 2 3 4 5 6 7 VDD_A1 VDD_A1 SDA/ SI SCL/ SK GPI0/ TRK VDD_B1 VDD_B1 A DA9211/12 see balls through package B LX_A1 LX_A1 NC GPI1/ CLK_IN GPIO2 LX_B1 LX_B1 B High Power Signals C VSS_A1 VSS_A1 FBAP SO/ GPIO3 FBBP/ NC VSS_B1 VSS_B1 High Power Noisy Signals C Power Signals D VSS_A2 VSS_A2 FBAN nCS/ GPI4 FBBN/ NC VSS_B2 VSS_B2 Noisy Digital Signals D Quasi Static Digital Signals E LX_A2 LX_A2 VSS VSS_ANA VDDIO LX_B2 LX_B2 E F VDD_A2 VDD_A2 nIRQ VSYS IC_EN VDD_B2 VDD_B2 F 1 2 3 4 5 6 7 Sensitive Analog Signals 42 balls Figure 4: Connection diagram Data sheet CFR0011-120-00 Rev 3 Version <3.0> 8 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Table 2: Pin description Pin Name Signal Name Second function Type (See Table 3) Description B1, B2 LX_A1 AO Switching node for Buck A phase 1 E1, E2 LX_A2 AO Switching node for Buck A phase 2 B6, B7 LX_B1 AO Switching node for Buck B phase 1 E6, E7 LX_B2 AO Switching node for Buck B phase 2 A1, A2 VDD_A1 PS Supply voltage for Buck A phase 1 To be connected to VSYS F1, F2 VDD_A2 PS Supply voltage for Buck A phase 2 To be connected to VSYS A6, A7 VDD_B1 PS Supply voltage for Buck B phase 1 To be connected to VSYS F6, F7 VDD_B2 PS Supply voltage for Buck B phase 2 To be connected to VSYS F5 IC_EN DI Integrated Circuit (IC) Enable Signal F3 nIRQ DO Interrupt line towards the host E5 VDDIO PS I/O Voltage Rail C3 FBAP AI Positive sense node for the Buck A D3 FBAN AI Negative sense node for the Buck A C5 FBBP AI Positive sense node for the Buck B for DA9212 N/C AI For DA9211 FBBN AI Negative sense node for the Buck B for DA9212 N/C AI For DA9211 D5 A5 GPI0 TRK DI/AI General purpose input, input track B5 GPI1 CLK_IN DI General purpose input, digital clock input B4 GPIO2 DIO General purpose input/output A3 SDA SI DIO 2-WIRE data, 4-WIRE data input/output A4 SCL SK DI 2-WIRE clock, 4-WIRE clock D4 nCS GPI4 DI 4-WIRE chip select, general purpose input C4 SO GPIO3 DIO 4-WIRE data output, general purpose input/output B3 NC F4 VSYS PS E3 VSS VSS E4 VSS_ANA VSS Data sheet CFR0011-120-00 Rev 3 Leave floating Supply for IC and input for voltage supervision Version <3.0> 9 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Pin Name Signal Name C1, C2 VSS_A1, D1, D2 C6, C7 VSS_A2 VSS_B1 D6, D7 VSS_B2 Second function Type Description (See Table 3) VSS Connect together Table 3: Pin type definition Pin type Description Pin type Description DI Digital Input AI Analogue Input DO Digital Output AO Analogue Output DIO Digital Input/Output AIO Analogue Input/Output PS Power Supply VSS Ground Data sheet CFR0011-120-00 Rev 3 Version <3.0> 10 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 9. Absolute maximum ratings Table 4: Absolute maximum ratings (Note 1) Symbol Parameter Conditions Min Typ Max Unit TSTG Storage temperature -65 +165 °C TA_LIM Limiting ambient temperature -40 +85 °C VDD_LIM Limiting supply voltage -0.3 5.5 V VPIN Limiting voltage at all pins except above -0.3 VDD + 0.3 (max 5.5) V PTOT total power dissipation (Note 2) VESD_HBM Electrostatic discharge voltage derating factor above TA = 70°C: 23 mW/°C 1265 1610 Human Body Model mW 2 kV Note 1 Stresses beyond those listed under ‘Absolute maximum ratings’ may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2 Obtained from simulation on a 2S2P 4L JEDEC Board (EIA/JESD51-2). Influenced by PCB technology and layout 10. Recommended operating conditions Table 5: Recommended operating conditions (Note 1) Symbol Parameter VDD Supply voltage VDDIO Input/output supply voltage Conditions Min Max Unit 2.8 5.5 V 1.2 3.6 (Note 2) V Note 1 Within the specified limits, a life time of 10 years is guaranteed Note 2 VDDIO is not allowed to be higher than VDD Data sheet CFR0011-120-00 Rev 3 Version <3.0> 11 of 74 Typ <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 11. Electrical characteristics Table 6: Buck Converters Characteristics Unless otherwise noted, the following is valid for TA = -40 to +85 ºC, VDD = 2.8 V to 5.5 V, COUT = 22 μF /phase, local sensing Symbol Parameter Conditions Min Typ Max Unit 5.5 V VDD Supply voltage VDD_x = VSYS 2.8 COUT Output capacitance (per phase) Including voltage and 11 22 28.6 µF 23 47 61 µF 10 mΩ temperature coefficient ESRCOUT Equivalent series resistance (per phase) LPHASE047 Inductance (per phase) Including current and temperature dependence LPHASE022 Inductance (per phase) Including current and f > 100 kHz temperature dependence DCRLPHASE Inductor resistance VBUCK Buck output voltage (Note 1) VOACC Output voltage accuracy PWM mode 0.23 0.47 0.62 µH 0.11 0.22 0.29 µH 30 100 mΩ IO = 0 to IO_MAX 0.3 1.57 V Incl. static line/load reg and voltage ripple VBUCK ≥ 1 V -2.0 +2.0 % Incl. static line/load reg and voltage ripple ±20 mV VBUCK < 1 V VBUCK = 1 V VDD = 3.8 V no load -1.0 +1.0 % -0.5 +0.5 % +3 % VBUCK = 1 V VDD = 3.8 V no load TA = 27 ºC VTR_LOAD Load regulation transient voltage IO = 0 to 5 A, 10 A/µs 4-phase operation, PWM VBUCK ≥ 1 V 0.6 V ≤ VBUCK < 1 V -3 Note 2 -30 mV +30 mV IO = 0 to 5 A, 10 A/µs phase shedding, PWM VDD ≤ 4.2 V VBUCK ≥ 1 V 0.6 V ≤ VBUCK < 1 V Data sheet CFR0011-120-00 Rev 3 Version <3.0> 12 of 74 -3.5 -35 mV Note 2 +3.5 +35 mV % <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Symbol Parameter Conditions Min Typ Max Unit -3.5 -35 mV Note 2 +3.5 +35 mV % IO = 0 to 5 A, 10 A/µs auto mode, ph shedding COUT = 47 µF VBUCK ≥ 1 V 0.6 V ≤ VBUCK < 1 V VTR_LINE Line regulation transient voltage VDD = 3 to.3.6 V dt =10 µs 8 mV IO = IO(MAX)/2 RRS_MAX Maximum remote sensing resistance (Note 3) To sense connection at point of load 10 mΩ Maximum remote sensing inductance (Note 3) To sense connection at point of load 10 nH IO_MAX Maximum output current Per phase ILIM_MIN Minimum current limit BUCKA_ILIM per phase (programmable) BUCKB_ILIM = 0000 Maximum current limit BUCKA_ILIM per phase (programmable) BUCKB_ILIM = 1111 Quiescent current @ synchronous rectification mode Per phase No load LRS_MAX ILIM_MAX IQ_PWM 3000 mA -20% 2000 20% mA -20% 5000 20% mA 10 mA VDD = 3.7 V fSW Switching frequency 3 MHz tON_MIN minimum on time 20 ns tSTUP Start up time 50 (Note 4) µs BUCKA_UP_CTRL BUCKB_UP_CTRL = 011 RO_PD Output pull-down resistance For each phase at the LX node @0.5 V, (see BUCKx_PD_DIS) 150 200 Ω 1.57 V PFM Mode VBUCK_PFM IQ_PFM_A2 Buck output voltage in PFM DA9212 quiescent current Buck A enabled IQ_PFM_A4 DA9211 quiescent current Buck enabled Data sheet CFR0011-120-00 Rev 3 IO = 0 mA to IO_MAX No load VDD = 3.7 V No load VDD = 3.7 V Version <3.0> 13 of 74 0.3 56 µA 70 µA <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Symbol IQ_PFM_A2B2 Parameter DA9212 quiescent current Buck A enabled Buck B enabled Conditions Min No load VDD = 3.7 V Typ 104 Max Unit µA Note 1 Programmable in 10 mV increments Note 2 Additionally to the dc accuracy. The value is intended measured directly at C OUT(EXT). In case of remote sensing, parasitics of PCB and external components may affect this value. Note 3 (ca 13 cm) trace routed over a ground plane (approx 1.2 nH/cm) Note 4 Time from begin to end of the voltage ramp. Additional 10 µs typical delay, plus internal sync to the enable port Data sheet CFR0011-120-00 Rev 3 Version <3.0> 14 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Table 7: IC Performance and Supervision TA = -40 to +85 ºC Symbol Parameter IDD_OFF Off state supply current @VSYS,VDDx IDD_ON On state supply current @VSYS,VDDx Conditions Min IC_EN = 0 TA = 27 °C IC_EN = 1 Buck A/B off Typ Max Unit 0.1 1 µA 12 µA -50 mV Power good hysteresis voltage 50 mV VTH_UVLO_VDD Under voltage lockout threshold @ VDD 2.0 V VTH_UVLO_IO Under voltage lockout threshold @ VDDIO VHYS_UVLO_IO Under voltage lockout hysteresis @ VDDIO VTH_PG VHYS_PG TTH_WARN Power good threshold voltage TA = 27 °C referred to VBUCK 1.35 1.45 1.55 70 V mV Thermal warning threshold temperature 110 125 140 °C TTH_CRIT Thermal critical threshold temperature 125 140 155 ºC TTH_POR Thermal power on reset threshold temperature 135 150 165 °C fOSC Internal oscillator frequency -7% 6.0 +7% MHz Data sheet CFR0011-120-00 Rev 3 Version <3.0> 15 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Table 8: Digital I/O Characteristics TA = -40 to +85 ºC Symbol Parameter Conditions Min Typ Max Unit VIH_EN HIGH level input voltage @ pin IC_EN VIL_EN LOW level input voltage @ pin IC_EN tEN Enable time I/F operating 750 µs RO_PU_GPO Pull up resistor @ GPO VDDIO = 1.8 V VGPO = 0V 100 k RI_PD_GPI Pull down resistor @ GPI VDDIO = 1.8V VGPI = VDDIO 150 k GPI0-4, SCL, SDA, VLDOCORE mode (2-WIRE mode) HIGH level input voltage VDDIO mode GPI0-4, SCL, SDA, (2-WIRE mode) VLDOCORE mode VDDIO mode VIH VIL 0.7*VDDIO V 0.3*VDDIO V 1.75 0.7*VDDIO V 0.75 0.3*VDDIO V LOW level input voltage SK, nCS, SI VIH_4WIRE (4-WIRE Mode) HIGH level input voltage 0.7*VDDIO V SK, nCS, SI VIL_4WIRE VOH VOL1 (4-WIRE Mode) LOW level input voltage GPO2-3, SO (4-WIRE mode) HIGH level output voltage 0.3*VDDIO push-pull mode @1mA 0.8*VDDIO V V VDDIO ≥ 1.5 V GPO2-3, SDA (2-WIRE mode) SO (4-WIRE mode) 0.3 V 0.24 V 0.4 V 10 pF LOW level output voltage @IOL = 1 mA SDA (2-WIRE Mode) VOL3 VOL20 LOW level output voltage @IOL = 3 mA SDA (2-WIRE Mode) LOW level output voltage @IOL = 20 mA CLK, SDA CIN (2-WIRE Mode) input capacitance Data sheet CFR0011-120-00 Rev 3 2.5 Version <3.0> 16 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Symbol Parameter Conditions Min Typ Max Unit CLK, SDA tSP tfDA (2-WIRE Mode) spike suppression pulse width Fall time of SDA signal (2-WIRE Mode) Fast/Fast+ mode 0 50 High Speed mode 0 10 Fast @ Cb<550pF 20+0.1Cb 120 10 20 80 160 ns Max Unit HS @ 10<Cb<100pF HS @ Cb<400pF ns Table 9: 2-WIRE Control Bus Characteristics TA = -40 to +85 ºC Symbol Parameter tBUF Bus free time from STOP to START condition CB Bus line capacitive load Conditions Min Typ 0.5 µs 150 pF 1000 kHz Standard/Fast/Fast+ Mode fSCL Clock frequency @ pin SCL 0 (Note 1) tSU_STA START condition set-up time 0.26 µs tH_STA START condition hold time 0.26 µs tW_CL Clock LOW duration 0.5 µs tW_CH Clock HIGH duration 0.26 µs tR Rise time @ pin CLK and DATA Input requirement 1000 ns tF Fall time @ pin CLK and DATA Input requirement 300 ns tSU_D Data set-up time 50 ns tH_D Data hold time 0 ns High Speed Mode fSCL_HS Clock frequency @ pin SCL 0 (Note 1) tSU_STA_HS START condition set-up time 160 ns tH_STA_HS START condition hold time 160 ns tW_CL_HS Clock LOW duration 160 ns tW_CH_HS Clock HIGH duration 60 ns tR_HS Rise time @ pin CLK and DATA Data sheet CFR0011-120-00 Rev 3 Input requirement Version <3.0> 17 of 74 3400 160 kHz ns <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Symbol tF_HS Parameter Fall time @ pin CLK and DATA Conditions Min Input requirement Typ Max Unit 160 ns tSU_D_HS Data set-up time 10 ns tH_D_HS Data hold time 0 ns tSU_STO_HS STOP condition set-up time 160 ns Note 1 Minimum clock frequency is 10 kHz if 2WIRE_TO is enabled Figure 5: 2-WIRE Bus Timing Data sheet CFR0011-120-00 Rev 3 Version <3.0> 18 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Table 10: 4-WIRE Control Bus Characteristics TA = -40 to +85 ºC Symbol Parameter Label in plot Min Typ Max Unit 100 pF CB Bus line capacitive load tC Cycle time 1 70 ns tSU_CS Chip select setup time 2, from CS active to first SK edge 20 ns tH_CS Chip select hold time 3, from last SK edge to CS idle 20 ns tW_CL Clock LOW duration 4 0.4 x tC ns tW_CH Clock HIGH duration 5 0.4 x tC ns tSU_SI Data input setup time 6 10 ns tH_SI Data input hold time 7 10 ns tV_SO Data output valid time 8 tH_SO Data output hold time 9 6 ns tW_CS Chip select HIGH duration 10 20 ns 22 (2) tSU_CS (3) tH_CS ns (10) tW_CS 70% nCS 30% (5) tW_CH (4) tW_CL (1) tC 70% SK 30% (6) tSU_SI (7) tH_SI 70% SI 30% (8) tV_SO (9) tH_SO 70% 30% SO Figure 6: 4-WIRE Bus Timing Data sheet CFR0011-120-00 Rev 3 Version <3.0> 19 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Table 11: Graphs of Typical Characteristics Patameter Efficiency Start-up DVC Test Conditions Efficiency vs Output Current, VOUT = 1.0 V, 4 phases Figure 7 Efficiency vs Output Current, VOUT = 1.2 V, 4 phases Figure 8 Efficiency vs Output Current, VOUT = 0.9 V, 4 phases Figure 9 Efficiency vs Output Current, VOUT = 1.0 V, 2 phases Figure 10 Efficiency vs Output Current, VOUT = 1.2 V, 2 phases Figure 11 Efficiency vs Output Current, VOUT = 0.9 V, 2 phases Figure 12 Efficiency vs Input Voltage, IOUT = 100 mA Figure 13 Efficiency vs Input Voltage, IOUT = 2 A Figure 14 Efficiency vs Input Voltage, IOUT = 10 A Figure 15 no load, STARTUP_CTRL=000 (slowest), VDD=3.7 V, VOUT=1.0 V Figure 16 no load, STARTUP_CTRL=100 (default), VDD=3. 7 V, VOUT=1.0 V Figure 17 no load, STARTUP_CTRL=110 (fastest), VDD=3. 7 V, VOUT=1.0 V Figure 18 1 load, STARTUP_CTRL=000 (slowest), VDD=3. 7 V, VOUT=1.0 V Figure 19 1 load, STARTUP_CTRL=100 (default), VDD=3. 7 V, VOUT=1.0 V Figure 20 1 load, STARTUP_CTRL=110 (fastest), VDD=3. 7 V, VOUT=1.0 V Figure 21 Start up from IC_EN no load, STARTUP_CTRL=100 (default), VDD=3.7V, VOUT=1.0V Figure 22 DVC no load, slowest speed 2.5mV/μs, VDD=3.7V, VOUT 1.2V/0.8V DVC no load, default speed 10mV/μs, VDD=3.7V, VOUT 1.2V/0.8V DVC no load, fastest speed 20mV/μs, VDD=3.7V, VOUT 1.2V/0.8V Switching waveforms PWM, no load, VDD=3.7 V, VOUT=1.0 V Voltage and current ripple, PWM, no load, VDD=3.7 V, VOUT=1.0 V Load Transient response Figure Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 PFM, no load, VDD=3.7 V, VOUT=1.0 V Figure 28 PWM, 4-phases, 05A in 10 A/µs, VDD=3.7 V, VOUT=1.0 V Figure 29 PWM, 4-phases, 15A in 10 A/µs, VDD=3.7 V, VOUT=1.0 V Figure 30 Auto, 4-phases, 10mA5A in 10 A/µs, VDD=3.7 V, VOUT=1.0 V Figure 31 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 20 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 12. Typical Characteristics Figure 7 Figure 8 Figure 9 Figure 10 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 21 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Data sheet CFR0011-120-00 Rev 3 Figure 11 Figure 12 Figure 13 Figure 14 Version <3.0> 22 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Start up no load, STARTUP_CTRL=000 (slowest) VDD=3.7V, VOUT=1.0V Figure 15 Figure 16 Start up no load, Start up no load, STARTUP_CTRL=100 (default) STARTUP_CTRL=110 (fastest) VDD=3.7V, VOUT=1.0V VDD=3.7V, VOUT=1.0V Figure 17 Figure 18 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 23 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Start up 1 load, Start up 1 load, STARTUP_CTRL=000 (slowest) STARTUP_CTRL=100 (default) VDD=3.7V, VOUT=1.0V VDD=3.7V, VOUT=1.0V Figure 19 Figure 20 Start up 1 load, Start up from IC_EN no load, STARTUP_CTRL=110 (fastest) STARTUP_CTRL=100 (default) VDD=3.7V, VOUT=1.0V VDD=3.7V, VOUT=1.0V Figure 21 Figure 22 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 24 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet DVC no load, DVC no load, slowest speed 2.5mV/μs default speed 10mV/μs VDD=3.7V, VOUT 1.2V/0.8V VDD=3.7V, VOUT 1.2V/0.8V Figure 23 Figure 24 DVC no load, Switching waveforms, fastest speed 20mV/μs PWM, no load VDD=3.7V, VOUT 1.2V/0.8V VDD=3.7V, VOUT=1.0V Figure 25 Figure 26 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 25 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Voltage and current ripple, Switching waveforms, PWM, no load PFM, no load VDD=3.7V, VOUT=1.0V VDD=3.7V, VOUT=1.0V Figure 27 Figure 28 Transient Load , PWM, 4-phases Transient Load , PWM, 4-phases Data sheet CFR0011-120-00 Rev 3 05A in 10A/µs, 15A in 10A/µs, VDD=3.7 V, VOUT=1.0 V VDD=3.7 V, VOUT=1.0 V Figure 29 Figure 30 Version <3.0> 26 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Transient Load , Auto, 4-phases 10mA5A in 10A/µs, VDD=3.7 V, VOUT=1.0 V Figure 31 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 27 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 13. Functional description Flexible configurability and the availability of different control schemes make both DA9211 and DA9212 the ideal single/dual buck companion ICs to expand the existing capabilities of a master PMIC. Due to the advanced compatibility between both DA9211 and DA9212 and the DA9063, they offer several advantages when they are operated together. These advantages include: ● DA9211 and DA9212 can be enabled and controlled by DA9063 during the power up sequence, thanks to DA9063’s dedicated output signals during power-up, and compatible input controls in both DA9211 and DA9212. ● DA9211 and DA9212 can be used in a completely transparent way for the host processor and can share the same Control Interface (same SPI chip select or I2C address), thanks to the compatible registers map. DA9211 and DA9212 has a dedicated register space for configuration and control which doesn’t conflict with DA9063. ● DA9211 and DA9212 supports a Power-good configurable port for enhanced communication to the host processor and improved power-up sequencing. ● DA9211 and DA9212 can both share the same interrupt line with DA9063. In addition, the 2-WIRE / 4-WIRE interfaces allow DA9211 and DA9212 to fit to many standard PMU parts and power applications. Vdd nIRQ nSHUTDOWN SYS_EN nOFF nONKEY PWR_EN Host Processor PWR1_EN DA9063 LID OUT_32K GPIOs nRESET Control IF VCharger GPIO9 IC_EN Control IF GPIO2 (AC_OK) DA9211/12 nIRQ GPI1 (voltage set) GPI0 (enable) Figure 32: Interface of DA9211/12 with DA9063 and the host processor Data sheet CFR0011-120-00 Rev 3 Version <3.0> 28 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet As shown in Figure 32, a typical application case includes a host processor, a Main PMIC (for example, DA9063) and DA9211 or DA9212 used as companion IC for the high power core supply. The easiest way of controlling DA9211 and DA9212 is through the Control Interface. The master initiating the communication must always be the host processor that reads and writes to the main PMIC, and to the DA9211 and DA9212 registers. To poll the status of DA9211 or DA9212, the host processor must access the dedicated register area through the Control Interface. DA9211 and DA9212 can be additionally controlled by means of hardware inputs. CORE VDDIO DA9211 SCL SDA nIRQ VSEL (GPI1) EN (GPI0) LP_MODE DA9063 (PMIC) VIN VDD_A1 IC_EN GPIO9 (seq) VDD_A2 VDD_B1 VDD_B2 SENSE+ LX_A1 LX_A2 CPU / GPU / DDR VSYS LX_B1 VSS_ANA LX_B2 SENSEFBAP FBAN VDDIO I2C_ADDR_SEL (GPI4) AC_OK (GPIO2) Power Good (GPIO3) Vcharger Ext Supply Figure 33: Typical application of DA9211 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 29 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Figure 33 shows a typical use case of DA9211 for the supply of CPU, GPU, or DDR rails. The IC is enabled and disabled by the main PMIC via IC_EN port as part of its sequencer. Once the IC is enabled, the CORE application processor enables the buck converter with the EN1 signal and manages the output voltage selection with the VSEL signal. The VSEL signal can be shared between the main PMIC and the DA9211. Three GPI/GPIOs embedded in DA9211 are used in this case: ● GPIO2 signals the insertion of an external charger in the application (through interrupt to the host processor) ● GPIO3 indicates a power-good-condition, either to proceed with the power up sequence or to enable an external supply connected to the port ● GPI4 is used for the I2C interface address hardware selection Data sheet CFR0011-120-00 Rev 3 Version <3.0> 30 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet DA9212 CORE VDDIO SCL SDA nIRQ EN_A (GPI0) EN_B (GPI1) IC_EN VIN VDD_A1 VDD_A2 VDD_B1 SENSE+ CPU SENSE+ GPU LX_A1 VDD_B2 LX_A2 SENSEVSYS FBAP FBAN VSS_ANA LX_B1 LX_B2 SENSEFBBP FBBN VDDIO I2C_ADDR_SEL (GPI4) Figure 34: Typical application of DA9212 Figure 34 shows a typical use case of DA9212 for the simultaneous supply of a CPU and a GPU rail. The CORE application processor enables and disables the IC, the CPU and the GPU individually via dedicated ports on DA9212. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 31 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 13.1 DC-DC Buck Converter DA9211 is a four-phase 12 A high efficiency synchronous step-down DVC regulator, operating at a high frequency of typically 3 MHz. It supplies an output voltage of typically 1.0 V for a CPU rail, configurable in the range 0.3 – 1.57 V, with high accuracy in steps of 10 mV. DA9212 contains two buck converters, Buck A and Buck B, each capable of delivering 6 A To improve the accuracy of the delivered voltage, each buck converter is able to support a differential sensing of the configured voltage directly at the point of load via dedicated positive and negative sense pins. Both Buck A and Buck B have two voltage registers each. One defines the normal output voltage, while the other offers an alternative retention voltage. In this way different application power modes can easily be supported. The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. When a buck is enabled, its output voltage is monitored and a power-good signal indicates that the buck output voltage has reached a level higher than the VTH(PG) threshold. The power-good is lost when the voltage drops below VTH(PG) - VHYS(PG), which is the level at which the signal is de-asserted. The power good signalling should not be used in conjunction with fast start up rates, configured in BUCKx_UP_CTRL register fields and can be individually masked during DVC transitions using the PGA_DVC_MASK and PGB_DVC_MASK bits. For each of the buck converters the status of the power-good indicator can be read back via I2C from the PWRGOOD_A and PWRGOOD_B status bits. It can be also individually assigned to either GPIO2 or GPIO3 using BUCKA_PG_SEL and BUCKB_PG_SEL. For correct functionality, the GPIO ports need to be configured as output. An I2C write in GPIOx_MODE can overwrite the internal configuration so that a new update will be automatically done only when the internal power-good indicator changes status. The buck converters are capable of supporting DVC transitions that occur: ● When the active and selected A-voltage or B-voltage is updated to a new target value. ● When the voltage selection is changed from the A-voltage to the B-voltage (or B-voltage to the A-voltage) using VBUCKA_SEL and VBUCKB_SEL. The DVC controller operates in Pulse Width Modulation (PWM) mode with synchronous rectification. When the host processor changes the output voltage, the voltage transition of each buck converter can be individually signalled with a READY signal routed to either GPIO2 or GPIO3. The port has to be configured as GPO and selected for the functionality via READYA_CONF or READYB_CONF. In contrast to the power-good signal, the READY only informs the host processor about the completion of the digital DVC ramp without confirming that the target voltage has actually been reached. The slew rate of the DVC transition is individually programmed for each buck converter at 10mV per (4, 2, 1 or 0.5 µs) via control bit SLEW_RATE_A and SLEW_RATE_B. The typical supply current is in the order of 8 mA per phase (quiescent current and charge/discharge current) and drops to <1 µA when the buck is turned off. When the buck is disabled, a pull-down resistor (typically 150 Ω) for each phase is activated depending of the value stored in register bits BUCKA_PD_DIS and BUCKB_PD_DIS. Phases disabled using PHASE_SEL_A and PHASE_SEL_B will not have any pull-down. The pull-down resistor is always disabled at all phases when DA9211 and DA9212 are OFF. 13.1.1 Switching Frequency The switching frequency is chosen to be high enough to allow the use of a small 0.47 µH inductor (see a complete list of coils in the Application Information section (see section 15). The buck Data sheet CFR0011-120-00 Rev 3 Version <3.0> 32 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet switching frequency can be tuned using register bit OSC_TUNE. The internal 6 MHz oscillator frequency is tuned in steps of 180 kHz. This impacts the buck converter frequency in steps of 90 kHz and helps to mitigate possible disturbances to other HF systems in the application. 13.1.2 Operation Modes and Phase Selection The buck converters can operate in synchronous PWM mode and PFM mode. The operating mode is selected using register bits BUCKA_MODE and BUCKB_MODE. An automatic phase shedding can be enabled for each buck converter in PWM mode via PH_SH_EN_A, PH_SH_EN_B, thereby automatically reducing or increasing the number of active phases depending on the output load current. For DA9212 the phase shedding will automatically change between 1-phase and 2-phase operation at a typical current of 1.3 A. For DA9211 the phase shedding will automatically change between 1-phase and 4-phase operation at a typical current of 1.6 A. The PHASE_SEL_A and PHASE_SEL_B register fields limit the maximum number of active phases under any conditions. If the automatic operation mode is selected on BUCKA_MODE or BUCKB_MODE, the buck converters will automatically change between synchronous PWM mode and PFM depending on the load current. This improves the efficiency of the converters across the whole range of output load currents. 13.1.3 Output Voltage Selection The switching converter can be configured using either a 2-WIRE or a 4-WIRE interface. For security reasons, the re-programming of registers that can cause damage when wrongly programmed (for example, the voltage settings) can be disabled by asserting the control V_LOCK. When V_LOCK is asserted, reprogramming the registers 0xD0 to 0x14F from control interfaces is disabled. For each buck converter two output voltages can be pre-configured inside registers VBUCKA_A and VBUCKB_A, and registers VBUCKA_B and VBUCKB_B. The output voltage can be selected by either toggling register bits VBUCKA_SEL and VBUCKB_SEL or by re-programming the selected voltage control register. Both changes will result into ramped voltage transitions, during which the READY signal is asserted. After being enabled, the buck converter will by default use the register settings in VBUCKA_A and VBUCKB_A unless the output voltage selection is configured via the GPI port. If “00” has been selected in BUCKA_MODE or BUCKB_MODE, A-/B- voltage selection registers VBUCKx_x control the operation of the PWM and PFM modes. Regardless of the values programmed in the VBUCKx_A and VBUCKx_B registers, the registers VBUCKA_MAX, VBUCKB_MAX will individually limit the output voltage that can be set for each of the buck converters . The buck converter provides an optional hardware enable/disable via selectable GPI, and configured via control register bits BUCKA_GPI and BUCKB_GPI. A change of the output voltage from the state of a GPI is enabled via control register bits VBUCKA_GPI and VBUCKB_GPI. After detecting a rising or falling edge at the related GPIs, DA9211 and DA9212 will configure the buck converters according to their status. In addition to selecting between the A/B voltages, a track mode can be activated for Buck A to set the output voltage. In the DA9211, the track mode is applied to the 4-phase buck converter. This feature can be enabled on GPI0 via GPI0_PIN. The output voltage will be configured to follow the value applied at a selected GPI pin. The voltage applied at GPI0 must be in the same range as the nominal output voltage selectable for the buck rail (see VBUCKA_A and VBUCKA_B registers). In Track Mode, only single ended remote sensing is possible. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 33 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet In Track Mode, the content of the VBUCKA_SEL bit is ignored, as well as VBUCKA_A and VBUCKA_B bits. They will become active again once the voltage track mode is disabled. The GPI0 does not generate any event in this case. Figure 35: Concept of control of the buck’s output voltage 13.1.4 Soft Start up To limit in-rush current from VSYS, the buck converters can perform a soft-start after being enabled. The start-up behaviour is a compromise between acceptable inrush current from the battery and turn-on time. In DA9211 and DA9212, different ramp times can be individually configured for each buck converter on register BUCKA_UP_CTRL and BUCKB_UP_CTRL. Rates higher than 20 mV/µs may produce overshoot during the start-up phase, so they should be considered carefully. A ramped power-down can be selected on register bits BUCKA_DOWN_CTRL and BUCKB_DOWN_CTRL. When no ramp is selected, the output node will be discharged only by the pull-down resistor, if enabled via BUCKA_PD_DIS and BUCKB_PD_DIS. 13.1.5 Current Limit The integrated current limit is meant to protect DA9211 and DA9212’s power stages and the external coil from excessive current. The bucks’ current limit should be configured to be at least 40% higher than the required maximum continuous output current (see table below). When reaching the current limit, each buck converter generates an event and an interrupt to the host processor unless the interrupt has been masked using the OCx_MASK controls. These OCA_MASK and OCB_MASK control bits can be used to mask the generation of over-current events during DVC transitions. An extra masking time as defined in OCx_MASK will be automatically added to the DVC interval after the DVC has finished in order to ensure that the possible high current levels needed for DVC do not influence the event generation. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 34 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Table 12: Selection of the buck current limit from the coil parameters Min ISAT (mA) Frequency (MHz) Buck current limit (mA) Average current (mA) 5060 3 4600 3300 4180 3 3800 2700 3080 3 2800 2000 1760 3 1600 1100 13.2 Ports Description This section describes the functionality of each input / output port. 13.2.1 VDDIO VDDIO is an independent IO supply rail input to DA9211 and DA9212 that can be assigned to the power manager interface and to the GPIOs (see control PM_IF_V and GPI_V). The rail assignment determines the IO voltage levels and logical thresholds (see also the Digital I/O Characteristics in Table 8). An integrated under voltage lockout circuit for the VDDIO prevents internal errors by disabling the I2C communication when the voltage drops below VULO_IO. In that case the buck converters are also disabled and can not be re-enabled (even via input port) until the VDDIO under-voltage condition has been resolved. At the exit of the VDDIO under voltage condition an event E_UVLO_IO is generated and the nIRQ line is driven active if the event is not masked. The VDDIO under-voltage circuit monitors voltages relative to a nominal voltage of 1.8V. If a different rail voltage is being used, the under-voltage circuit can be disabled via UVLO_IO_DIS. Note that the maximum speed at 4-WIRE interface is only available if the selected supply rail is greater than 1.6 V. 13.2.2 IC_EN IC_EN is a general enable signal for DA9211 and DA9212, turning on and off the internal circuitry (for example, the reference, the digital core, etc). Correct control of this port has a direct impact on the quiescent current of the whole application. A low level of IC_EN allows the device to reach the minimum quiescent current. The voltage at this pin is continuously sensed by a dedicated analogue circuit. The host processor will be allowed to start the communication with DA9211 and DA9212 through the Control Interface and, for example to turn on the buck converters, a delay time of tEN after assertion of the IC_EN pin. If the bucks are enabled via OTP (see BUCKA_EN and BUCKB_EN controls), they will start up automatically after assertion of IC_EN. The IC_EN signal shall be asserted and deasserted only when the VDD_IO supply is available and its level is above the undervoltage threshold level VTH_UVLO_IO. 13.2.3 nIRQ The nIRQ port indicates that an interrupt-causing event has occurred and that the event/status information is available in the related registers. The nIRQ is an output signal that can either be Data sheet CFR0011-120-00 Rev 3 Version <3.0> 35 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet push-pull or open drain (selected via IRQ_TYPE). If an active high IRQ signal is required, it can be achieved by asserting control IRQ_LEVEL (recommended for push-pull mode). Examples of this type of information can be critical temperature and voltage, fault conditions, status changes at GPI ports, and so forth. The event registers hold information about the events that have occurred. Events are triggered by a status change at the monitored signals. When an event bit is set, the nIRQ signal is asserted unless this interrupt is masked by a bit in the IRQ mask register. The nIRQ will not be released until all event registers with asserted bits have been read and cleared. New events that occur during reading an event register are held until the event register has been cleared, ensuring that the host processor does not miss them. 13.2.4 GPIO Extender DA9211 and DA9212 includes a GPIO extender that offers up to five 5 V-tolerant general purpose input/output ports. Each port is ontrolled via registers from the host processor. The GPIO3 and GPI4 ports are pin-shared with the 4-WIRE Control Interface. For instance, if GPIO3_PIN = 01, GPI4_PIN = 01 (Interface selected), the GPIO3 and GPI4 ports will be exclusively dedicated to output and chip-select signaling for 4-WIRE purposes. If the alternative function is selected, all GPIOs configuration as per registers 0x58 to 0x5A and 0x145 will be ignored. GPIs are supplied from the internal rail VDDCORE or VDDIO (selected via GPI_V) and can be configured to be active high or active low (selected via GPIOx_TYPE). The input signals can be debounced or directly change the state of the assigned status register GPIx to high or low, according to the setting of GPIOx_MODE. The debouncing time is configurable via control DEBOUNCE (10 ms default). When ever the status has changed to its configured active state (edge sensitive), the assigned event register is set and the nIRQ signal is asserted (unless this nIRQ is masked, see also Figure 36). Whenever DA9211 and DA9212 is enabled and enters ON mode (also when enabled changing the setting of GPIOx_PIN) the GPI status bits are initiated towards their configured passive state. This ensures that already active signals are detected, and that they create an event immediately after the GPI comparators are enabled. The buck enable signal (BUCKx_EN) can be controlled directly via a GPI, if so configured in the BUCKA_GPI and BUCKB_GPI registers. If it is required that GPI ports do not generate an event when configured for the HW control of the switching regulator, the relative mask bit should be set. GPIs can alternatively be selected to toggle the VBUCKA_SEL and VBUCKB_SEL from rising and falling edges at this inputs. Apart from changing the regulator output voltage this also provides hardware control of the regulator mode (normal/low power mode) from the settings of Error! eference source not found., Error! Reference source not found., Error! Reference source not found., and Error! Reference source not found. (enabled if BUCKA_MODE or BUCKB_MODE = ‘00’). All GPI ports have the additional option of activating a 100 kΩ pull-down resistor via GPIOx_PUPD, which ensures a well defined level in case the input is not actively driven. If enabled via ADDR_SEL_CONF, the I2C address selection can be assigned to a specific GPI. An active voltage level at the selected GPI configures the slave address of DA9211 and DA9212 to IF_BASE_ADDR1 while a passive voltage level configures the slave address to IF_BASE_ADDR2. If no GPI is selected then the IF_BASE_ADDR1 is automatically used. If defined as an output, GPIOs can be configured to be open-drain or push-pull. If configured as push-pull, the supply rail is VDDIO. By disabling the internal 120 kΩ pull-up resistor in open-drain mode, the GPO can also be supplied from an external rail. The output state will be assigned as configured by the GPIO register bit GPIOx_MODE. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 36 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet A specific power-good port for each of the buck converters can be configured via BUCKA_PG_SEL and BUCKB_PG_SEL. The respective port must be configured as GPO for correct operation. If assigned to the same GPO, it is necessary that the power-good indicators for Buck A and Buck B are both active (supply voltages in range) to assert the overall power-good. The signal will be released as soon as one of the single power-good signals is not active (that is, at least one supply is out of range). The power good signalling should not be used in conjunction with fast start up rates, configured in BUCKx_UP_CTRL register fields. Whenever the GPIO unit is off (POR or OFF Mode) all ports are configured as open drain active high (pass device switched off, high impedance state). When leaving POR the pull-up or pull-down resistors will be configured from register GPIOx_PUPD. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 37 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Interrupt mask: M_GPI0 Track Mode Input Reference Buffer GPIO0_TYPE: Active high/low Buck GPI0_MODE: Debounce on/off Status register Event register Debounce GPI NOR GPI0 GPIO0_PUPD Reserved E_GPI0 Rising or Falling edge GPI0_PIN nIRQ Reset NOR Reserved Buck HW control Event register write 100kΩ Regulator configure ... BUCK_ EN VBUCK_SEL VDD_IO Interrupt mask: M_GPI3 4-WIRE SO GPIO3_TYPE: Active high/low GPIO3_MODE: Debounce on/off Status register Event register Interface NOR GPI3 E_GPI3 Rising or Falling edge Debounce GPI Reset GPIO3_PIN Event register write GPIO3_PUPD VDD_IO GPIO3_PUPD 100kΩ 120kΩ GPO (Open drain) READY_EN READY signal asserted during DVC VDD_IO GPO3_MODE: 0 or 1 GPO (Push-pull) Figure 36: GPIO principle of operation (example paths) 13.3 Operating Modes 13.3.1 ON Mode DA9211 and DA9212 is in ON Mode when the IC_EN port is higher than EN_ON and the supply voltage is higher than VTH(UVLO)(VDD). Once enabled, the host processor can start the communication with DA9211 and DA9212 via Control Interface after the tEN delay needed for internal circuit start up. If BUCKA_EN or BUCKB_EN is asserted when DA9211 and DA9212 is in ON Mode the power up of the related buck converter is initiated. If the bucks are controlled via GPI, the level of the controlling ports is checked when entering ON mode, so that an active level will immediately have effect on the Data sheet CFR0011-120-00 Rev 3 Version <3.0> 38 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet buck. If BUCKA_EN or BUCKB_EN are not asserted and all controlling GPI ports are inactive, the buck converter will stay off with the output pull-down resistor enabled/disabled according to the setting of BUCKA_PD_DIS and BUCKB_PD_DIS. 13.3.2 OFF Mode DA9211 and DA9212 is in OFF Mode when the IC_EN port is lower than EN_OFF. In OFF Mode, the bucks are always disabled and the output pull-down resistors are disabled independently of BUCKA_PD_DIS and BUCKB_PD_DIS. All I/O ports of DA9211 and DA9212 are configured as high impedance. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 39 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 13.4 Control Interfaces All the features of DA9211 and DA9212 can be controlled by SW through a serial control interfaces. The communication is selectable to be either a 2-WIRE (I2C compliant) or a 4-WIRE connection (SPI compliant) via control IF_TYPE, which will be selected during the initial OTP read. If 4-WIRE is selected, the GPIO3 and GPI4 are automatically configured as interface pins. Data is shifted into or out of DA9211 and DA9212 under the control of the host processor, which also provides the serial clock. In a normal application case the interface is only configured once from OTP values, which are loaded during the initial start-up of DA9211 and DA9212. DA9211 and DA9212 reacts only on read/write commands where the transmitted register address (using the actual page bits as a MSB address range extensions) is within 0x50 to 0x67, 0xD0 to DF, 0x140 to 0x14F and (read only) 0x200 to 0x27F. Host access to registers outside these ranges will be ignored. This means there will be no acknowledge after receiving the register address in 2-WIRE Mode, and SO stays HI-Z in 4-WIRE Mode. During debug and production modes write access is available to page 4 (0x200 to 0x27F). DA9211 and DA9212 will react only on write commands where the transmitted register address is 0x00, 0x80, 0x100 to0x106. The host processor must read the content of those registers before writing, thereby changing only the bit fields that are not marked as reserved (the content of the read back comes from the compatible PMIC, for example DA9063). If the STAND_ALONE bit is asserted (OTP bit), DA9211 and DA9212 will also react to read commands. 13.4.1 4-WIRE Communication In 4-WIRE Mode the interface uses a chip-select line (nCS/nSS), a clock line (SK), data input (SI) and data output line (SO). The DA9211 and DA9212 register map is split into four pages that each contain up to 128 registers. The register at address zero on each page is used as a page control register. The default active page after turn-on includes registers 0x50 to 0x6F. Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting bit REVERT. Unless the REVERT bit was asserted after modifying the active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. All registers outside the DA9211 and DA9212 range are write only, that is, the DA9211 and DA9212 will not answer to a read command and the data bus is tri-state (they are implicitly directed to DA9063). In particular the information contained in registers 0x105 and 0x106 is used by DA9211 and DA9212 to configure the control interface. They must be the same as the main PMIC (DA9063), so that a write to those registers configures both the main PMIC and DA9211 and DA9212 at the same time. The default OTP settings also need to be identical for a correct operation of the system. The 4-WIRE interface features a half-duplex operation, that is, data can be transmitted and received within a single 16-bit frame at enhanced clock speed (up to 14 MHz). It operates at the clock frequencies provided by the host. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 40 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet VDDIO VDDIO VDDIO SK Host SO processor SI VDDIO SK PMIC SI (slave) SO nCS/nSS nCS/nSS nCS/nSS Host processor VDDIO SK PMIC Peripheral SI device SCL SDA VDDIO 4-WIRE interface 2-WIRE interface SK SI Slave device SO nCS/nSS SCL SDA Peripheral device Figure 37: Schematic of 4-WIRE and 2-WIRE Power Manager Bus A transmission begins when initiated by the host. Reading and writing is accomplished by the use of an 8-bit command, which is sent by the host prior to the exchanged 8-bit data. The byte from the host begins shifting in on the SI pin under the control of the serial clock SK provided from the host. The first seven bits specify the register address (0x01 to 0x07) that will be written or read by the host. The register address is automatically decoded after receiving the seventh address bit. The command word ends with an R/W bit, which together with the control bit R/W_POL specifies the direction of the following data exchange. During register writing the host continues sending out data during the following eight SK clocks. For reading, the host stops transmitting and the 8-bit register is clocked out of DA9211 and DA9212 during the consecutive eight SK clocks of the frame. Address and data are transmitted with MSB first. The polarity (active state) of nCS is defined by control bit nCS_POL. nCS resets the interface when inactive and it has to be released between successive cycles. The SO output from DA9211 and DA9212 is normally in high-impedance state and active only during the second half of read cycles. A pull-up or pull-down resistor may be needed at the SO line if a floating logic signal can cause unintended current consumption inside other circuits. Table 13: 4-WIRE Clock Configurations Configurations CPHA clock polarity CPOL clock phase Output data is updated at SK edge Input data is registered at SK edge 0 (idle low) 0 Falling Rising 0 (idle low) 1 Rising Falling 1 (idle high) 0 Rising Falling 1 (idle high) 1 Falling Rising DA9211 and DA9212’s 4-WIRE interface offers two further configuration bits. Clock polarity (CPOL) and clock phase (CPHA) define when the interface will latch the serial data bits. CPOL determines whether SK idles high (CPOL = 1) or low (CPOL = 0). CPHA determines on which SK edge data is shifted in and out. With CPOL = 0 and CPHA = 0, DA9211 and DA9212 latch data on the SK rising edge. If the CPHA is set to 1 the data is latched on the SK falling edge. CPOL and CPHA states allow four different combinations of clock polarity and phase. Each setting is incompatible with the other three. The host and DA9211 and DA9212 must be set to the same CPOL and CPHA states to communicate with each other. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 41 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 4-WIRE WRITE nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 SO 4-WIRE READ nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn HI-Z SO D7 latch data Figure 38: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) 4-WIRE WRITE nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 SO 4-WIRE READ nCS SK SI A6 SO A5 A4 A3 A2 A1 A0 R/Wn HI-Z D7 latch data Figure 39: 4-WIRE Host Write and Read Timing (nCS_POL= ‘0’, CPOL = ‘0’, CPHA = ‘1’) Data sheet CFR0011-120-00 Rev 3 Version <3.0> 42 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 4-WIRE WRITE nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 SO 4-WIRE READ nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn HI-Z SO D7 latch data Figure 40: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) 4-WIRE WRITE nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 SO 4-WIRE READ nCS SK SI A6 SO A5 A4 A3 A2 A1 A0 R/Wn HI-Z D7 latch data Figure 41: 4-WIRE Host Write and Read Ttiming (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) Data sheet CFR0011-120-00 Rev 3 Version <3.0> 43 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Table 14: 4-WIRE Interface Summary Parameters nCS Chip select Signal Lines SI Serial input data SO Serial output data SK Master out Slave in Master in Slave out Transmission clock Interface Push-pull with tristate Supply voltage Selected from VDDIO 1.6 V to 3.3 V Data rate Effective read/write data Up to 7 Mbps Half-duplex MSB first 16 bit cycles 7-bit address, 1 bit read/write, 8-bit data CPOL Clock polarity CPHA nCS_POL Clock phase nCS is active low/high Transmission Configuration Note that reading the same register at high clock rates directly after writing it does not guarantee a correct value. It is recommended to keep a delay of one frame until re-accessing a register that has just been written (for example, by writing/reading another register address in between). 13.4.2 2-WIRE Communication The IF_TYPE bit in the INTERFACE2 register can be used to configure the DA9211 and DA9212 control interface as a 2-WIRE serial data interface. In this case the GPIO3 and GPI4 are free for regular input/output functions. DA9211 and DA9212 has a configurable device write address (default: 0xD0) and a configurable device read address (default: 0xD1). See control IF_BASE_ADDR1 for details of configurable addresses. The ADDR_SEL_CONF bit is used to configure the device address as IF_BASE_ADDR1 or IF_BASE_ADDR2 depending on the voltage level applied at a configurable GPI port (see GPIO Extender). The SK port functions as the 2-WIRE clock and the SI port carries all the power manager bi-directional 2-WIRE data. The 2-WIRE interface is open-drain supporting multiple devices on a single line. The bus lines have to be pulled HIGH by external pull-up resistors (in the 2 kΩ to 20 kΩ range). The attached devices only drive the bus lines LOW by connecting them to ground. As a result two devices cannot conflict if they drive the bus simultaneously. In standard/fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be determined by the application and does not have any relation to the DA9211 and DA9212 internal clock signals. DA9211 and DA9212 will follow the host clock speed within the described limitations, and does not initiate any clock arbitration or slow down. An automatic interface reset can be triggered using control 2WIRE_TO if the clock signal stops to toggle for more than 35 ms. The interface supports operation compatible to Standard, Fast, Fast-Plus and High Speed mode of the I2C-bus specification Rev 4. Operation in high speed mode at 3.4 MHz requires mode changing in order to set spike suppression and slope control characteristics to be compatible with the I2C-bus specification. The high speed mode can be enabled on a transfer by transfer basis by sending the master code (0000 1XXX) at the begin of the transfer. DA9211 and DA9212 do not make use of clock stretching, and deliver read data without additional delay up to 3.4 MHz. Alternatively, PM_IF_HSM configures the interface to use high speed mode continuously. In this case, the master code is not required at the beginning of every transfer. This reduces the communication overhead on the bus but limits the slaves attachable to the bus to compatible devices. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 44 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet The communication on the 2-WIRE bus always takes place between two devices, one acting as the master and the other as the slave. The DA9211 and DA9212 will only operate as a SLAVE. In contrast to the 4-WIRE mode, the 2-WIRE interface has direct access to two pages of the register map (up to 256 addresses). The register at address zero on each page is used as a page control register (with the 2-WIRE bus ignoring the LSB of control REG_PAGE). Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting control REVERT. Unless REVERT was asserted after modifying the active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. In 2-WIRE operation DA9211 and DA9212 offer an alternative way to access register page 2 and page 3. It removes the need for preceeding page selection writes by incrementing the device write/read address by one (default 0xD2/0xD3) for any direct access of page 2 and page 3 (page 0 and 1 access requires the basic write/read device address with the MSB of REG_PAGE to be ‘0’). 13.4.3 Details of the 2-WIRE control bus protocol All data is transmitted across the 2-WIRE bus in groups of eight bits. To send a bit the SDA line is driven towards the intended state while the SCL is LOW (a low on SDA indicates a zero bit). Once the SDA has settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the SDA bit into the receiver’s shift register. A two-byte serial protocol is used containing one byte for address and one byte data. Data and address transfer are transmitted MSB first for both read and write operations. All transmissions begin with the START condition from the master while the bus is in IDLE state (the bus is free). It is initiated by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the high state). SCL SDA Figure 42: Timing of 2-WIRE START and STOP Condition The 2-WIRE bus is monitored by DA9211 and DA9212 for a valid SLAVE address whenever the interface is enabled. It responds immediately when it receives its own slave address. The acknowledge is done by pulling the SDA line low during the following clock cycle (white blocks marked with ‘A’ in Figure 43 to Figure 47). The protocol for a register write from master to slave consists of a start condition, a slave address with read/write bit and the 8-bit register address followed by eight bits of data terminated by a STOP condition. DA9211 and DA9212 respond to all bytes with Acknowledge. This is illustrated in Figure 43. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 45 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet S SLAVEadr 7-bits W A REGadr 1-bit A DATA 8-bits Master to Slave P A 8-bits Slave to Master S = START condition P = STOP condition A = Acknowledge (low) W = Write (low) Figure 43: 2-WIRE Byte Write (SDA Line) When the host reads data from a register it first has to write to DA9211 and DA9212 with the target register address and then read from DA9211 and DA9212 with a Repeated START or alternatively a second START condition. After receiving the data, the host sends No Acknowledge and terminates the transmission with a STOP condition. This is illustrated in Figure 44. S SLAVEadr W A 7-bits S 1-bit SLAVEadr W A 7-bits 1-bit REGadr A Sr SLAVEadr 8-bits REGadr A P S 8-bits Master to Slave R A A P 8-bits SLAVEadr 7-bits * DATA 1-bit 7-bits R A 1-bit * DATA A P 8-bits Slave to Master S = START condition Sr = Repeated START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 44: Examples of 2-WIRE Byte Read (SDA Line) Consecutive (page) read out mode is initiated from the master by sending an Acknowledge instead of Not acknowledge after receipt of the data word. The 2-WIRE control block then increments the address pointer to the next 2-WIRE address and sends the data to the master. This enables an unlimited read of data bytes until the master sends a Not acknowledge directly after the receipt of data, followed by a subsequent STOP condition. If a non-existent 2-WIRE address is read out, the DA9211 and DA9212 will return code zero. This is illustrated in Figure 45. S SLAVEadr W A 7-bits 1 bit S SLAVEadr W 7-bits REGadr A Sr SLAVEadr R A 8-bits A REGadr 7-bits S A P Master to Slave S = START condition Sr = Repeat START condition P = STOP condition 8-bits SLAVEadr R A 7-bits 8-bits 1-bit 1-bit DATA 1-bit A DATA A 8-bits DATA * DATA A P 8-bits A 8-bits DATA * A P 8-bits Slave to Master A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 45: Examples of 2-WIRE Page Read (SDA Line) Note that the slave address after the Repeated START condition must be the same as the previous slave address. Consecutive (page) write mode is supported if the Master sends several data bytes following a slave register address. The 2-WIRE control block then increments the address pointer to the next 2-WIRE address, stores the received data and sends an Acknowledge until the master sends the STOP condition. This is illustrated in Figure 46. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 46 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet S SLAVEadr W A 7-bits 1 bit REGadr A 8-bits Master to Slave DATA 8-bits A 1-bit DATA A 8-bits DATA A 8-bits ………. A P Repeated writes Slave to Master S = START condition Sr = Repeat START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 46: 2-WIRE Page Write (SDA Line) Via control WRITE_MODE an alternate write mode can be configured. Register addresses and data are sent in alternation like in Figure 47 to support host repeated write operations that access several non consecutive registers. Data will be stored at the previously received register address. An update of WRITE_MODE can not be done without interruption within a transmission frame. Thus, if not previously selected or not set as OTP default, the activation of Repeated Write must be done with a regular write on WRITE_MODE followed by a stop condition. The next frame after a start condition can be written in Repeated Write. S SLAVEadr W A 7-bits 1 bit REGadr 8-bits Master to Slave A DATA 8-bits A REGadr 1-bit 8-bits A DATA 8-bits A ………. A P Repeated writes Slave to Master S = START condition Sr = Repeat START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 47: 2-WIRE Repeated Write (SDA Line) If a new START or STOP condition occurs within a message, the bus will return to IDLE-mode. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 47 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 13.5 Internal Temperature Supervision To protect DA9211 and DA9212 from damage due to excessive power dissipation, the internal temperature is continuously monitored. There are three temperature thresholds, Table 15: Over-temperature thresholds Temperature threshold Typical temperature setting Interrupt event Status bit Masking bit TEMP_WARN 125 °C E_TEMP_WARN TEMP_WARN M_TEMP_WARN TEMP_CRIT 140 °C E_TEMP_CRIT TEMP_CRIT M_TEMP_CRIT TEMP_POR 150 °C When the junction temperature reaches the TEMP_WARN threshold, DA9211 and DA9212 will assert the bit TEMP_WARN and will generate the event E_TEMP_WARN. If not masked using bit M_TEMP_WARN, the output port nIRQ will be asserted. The status bit TEMP_WARN will remain asserted as long as the junction temperature remains higher than TEMP_WARN. When the junction temperature increases further to TEMP_CRIT, DA9211 and DA9212 will immediately disable the buck converter, assert the bit TEMP_CRIT, and will generate the event E_TEMP_CRIT. If not masked via bit M_TEMP_CRIT, the output port nIRQ will be asserted. The status bit TEMP_CRIT will remain asserted as long as the junction temperature remains higher than TEMP_CRIT. The buck converter will be kept disabled as long as the junction temperature is above TEMP_CRIT. It will not be automatically re-enabled even after the temperature drops below the valid threshold (even if the controlling GPI is asserted). A direct write into BUCKA_EN or BUCKB_EN, or a toggling of the controlling GPI, is needed to enable the buck converter. Whenever the junction temperature exceeds TEMP_POR, a power on reset to the digital core is immediately asserted, which will stops all functionalities of DA9211 and DA9212. This is needed to prevent possible permanent damage in the case of a rapid temperature increase. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 48 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 14. Register definitions 14.1 Register map Table 16: Register map All bits loaded from OTP are marked in bold A ddr F unc t io n 7 6 5 0x00 P A GE_CON REVERT WRITE_M ODE Reserved 4 3 2 1 0 0x50 STA TUS_A Reserved Reserved Reserved GP I4 GP I3 GP I2 GP I1 GP I0 0x51 STA TUS_B Reserved Reserved OV_CURR_B OV_CURR_A TEM P _CRIT TEM P _WA RN P WRGOOD_B P WRGOOD_A 0x52 EVENT_A Reserved E_UVLO_IO Reserved E_GP I4 E_GP I3 E_GP I2 E_GP I1 E_GP I0 0x53 EVENT_B Reserved Reserved E_OV_CURR_B E_OV_CURR_A E_TEM P _CRIT E_TEM P _WA RN E_P WRGOODB E_P WRGOOD_A 0x54 M A SK_A Reserved M _ UV LO _ IO Reserved M _ G P I4 M _ G P I3 M _ G P I2 M _ G P I1 M _ G P I0 Reserved M _ O V _ C UR R _ B M _ O V _ C UR R _ A M _ T E M P _ C R IT M _ T E M P _ WA R N M _ P WR G O O D _ B M _ P WR G O O D _ A Register Page 0 0x55 M A SK_B Reserved 0x56 CONTROL_A V _ LO C K 0x57 Reserved Reserved S LE W_ R A T E _ B Reserved REG_P A GE Reserved S LE W_ R A T E _ A Reserved Reserved D E B O UN C IN G Reserved Reserved Reserved Reserved 0x58 GP IO0-1 G P I1_ M O D E G P I1_ T Y P E G P I1_ P IN G P I0 _ M O D E G P I0 _ T Y P E G P I0 _ P IN 0x59 GP IO2-3 G P IO 3 _ M O D E G P IO 3 _ T Y P E G P IO 3 _ P IN G P IO 2 _ M O D E G P IO 2 _ T Y P E G P IO 2 _ P IN 0x5A GP IO4 Reserved Reserved G P I4 _ M O D E G P I4 _ T Y P E 0x5B Reserved Reserved Reserved 0x5C Reserved Reserved Reserved 0x5D B UCKA _CONT Reserved 0x5E B UCKB _CONT Reserved 0x80 P A GE_CON REVERT 0xD0 B UCK_ILIM Reserved Reserved G P I4 _ P IN Reserved Reserved Reserved Reserved Reserved Reserved V B UC KA _ G P I V B UC KA _ S E L B UC KA _ P D _ D IS B UC KA _ G P I B UC KA _ E N V B UC KB _ G P I V B UC KB _ S E L B UC KB _ P D _ D IS B UC KB _ G P I B UC KB _ E N Reserved Reserved Reserved Reserved Reserved Register Page 1 WRITE_M ODE Reserved REG_P A GE B UC KB _ ILIM B UC KA _ ILIM B UC KA _ D O WN _ C T R L B UC KA _ UP _ C T R L B UC KA _ M O D E 0xD1 B UCKA _CONF 0xD2 B UCKB _CONF 0xD3 B UCK_CONF Reserved Reserved Reserved P H _SH _EN _B P H _SH _EN _A P H A S E _ S E L_ B 0xD4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0xD5 VB UCKA _M A X Reserved V B UC KA _ M A X 0xD6 VB UCKB _M A X Reserved V B UC KB _ M A X 0xD7 VB UCKA _A Reserved V B UC KA _ A 0xD8 VB UCKB _B Reserved V B UC KA _ B V B UC KB _ A B UC KB _ D O WN _ C T R L B UC KB _ UP _ C T R L 0xD9 VB UCKB _A Reserved 0xDA VB UCKB _B Reserved 0x100 P A GE_CON REVERT WRITE_M ODE Reserved Reserved Reserved B UC KB _ M O D E P H A S E _ S E L_ A Reserved V B UC KB _ B Register Page 2 REG_P A GE 0x101 OTP _CONT Reserved Reserved Reserved Reserved P C_DONE OTP _A P P S_RD Reserved OTP _TIM 0x102 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x103 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x104 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x105 INTERFA CE R / W_ P O L CP HA C P OL nC S _ P O L 0x106 INTERFA CE2 IF _ T Y P E P M _ IF _ H S M P M _ IF _ F M P P M _ IF _ V Reserved Reserved Reserved Reserved 0x140 OTP _CONT2 O T P _ C O N F _ LO C K O T P _ A P P S _ LO C K Reserved Reserved Reserved Reserved Reserved Reserved IF _ B A S E _ A D D R 1 0x141 OTP _A DDR OTP _A DDR 0x142 OTP _DA TA OTP _DA TA 0x143 CONFIG_A Reserved Reserved Reserved 0x144 CONFIG_B UV LO _ IO _ D IS P GB _D VC _M A SK P GA _D VC _M A SK 0x145 CONFIG_C Reserved Reserved Reserved 0x146 CONFIG_D 0x147 CONFIG_E 0x148 CONFIG_F Data sheet CFR0011-120-00 Rev 3 B UC KB _ P G _ S E L S T A N D _ A LO N E 2 WIR E _ T O B UC KA _ P G _ S E L S LA V E _ S E L Reserved G P I_ V Reserved OC B _M A SK G P I4 _ P UP D Reserved IF _ B A S E _ A D D R 2 49 of 74 IR Q _ T Y P E IR Q _ LE V E L G P I1_ P UP D G P I0 _ P UP D OC A _M A SK G P IO 3 _ P UP D G P IO 2 _ P UP D R EA D YB _C ON F Reserved R EA D YA _C ON F O S C _ T UN E Reserved Reserved Version <3.0> Reserved Reserved A D D R _ S E L_ C O N F <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 14.2 Register Definitions 14.2.1 Register Page Control Register Bit Type Label Def Description 0x00 PAGE_CON 7 R/W REVERT 0 Resets REG_PAGE to 000 after read/write access has finished 6 R/W WRITE_MODE 0 2-WIRE multiple write mode (Note 1) 0: Page Write Mode 1: Repeated Write Mode 5:3 R/W (reserved) 000 000: Selects Register 0x01 to 0x3F 3:0 R/W REG_PAGE 000 001: Selects Register 0x81 to 0xCF 010: Selects Register 0x101 to 0x1CF >010: Reserved for production and test Note 1 14.2.2 Not used for 4-WIRE-IF Register Page 0 14.2.2.1 System Control and Event The STATUS registers report the current value of the various signals at the time that it is read out. Register Bit Type Label Def 0x50 STATUS_A 7:5 R (reserved) 000 4 R GPI4 0 GPI4 level 3 R GPI3 0 GPI3 level 2 R GPI2 0 GPI2 level 1 R GPI1 0 GPI1 level 0 R GPI0 0 GPI0 level Register Bit Type Label Def Description 0x51 7:6 R (reserved) 00 STATUS_B 5 R OV_CURR_B 0 Asserted as long as the current limit for Buck B is hit 4 R OV_CURR_A 0 Asserted as long as the current limit for Buck A is hit 3 R TEMP_CRIT 0 Asserted as long as the thermal shutdown threshold is reached 2 R TEMP_WARN 0 Asserted as long as the thermal warning threshold is reached 1 R PWRGOOD_B 0 Asserted as long as the Buck B output voltage is in range Data sheet CFR0011-120-00 Rev 3 Description Version <3.0> 50 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def Description 0 R PWRGOOD_A 0 Asserted as long as the Buck A output voltage is in range The EVENT registers hold information about events that have occurred in DA9211 and DA9212. Events are triggered by a change in the status register which contains the status of monitored signals. When an EVENT bit is set in the event register, the IRQ signal is asserted unless the event is masked by a bit in the mask register. The IRQ triggering event register will be cleared from the host by writing back its read value. New events occurring during clearing will be delayed before they are passed to the event register, ensuring that the host controller does not miss them. Register Bit Type Label Def 0x52 EVENT_A 7 R (reserved) 0 6 R E_UVLO_IO 0 5 R (reserved) 0 4 R E_GPI4 0 GPI4 event according to active state setting 3 R E_GPI3 0 GPI3 event according to active state setting 2 R E_GPI2 0 GPI2 event according to active state setting 1 R E_GPI1 0 GPI1 event according to active state setting 0 R E_GPI0 0 GPI0 event according to active state setting Register Bit Type Label Def Description 0x53 EVENT_B 7:6 R (reserved) 00 5 R E_OV_CURR_B 0 OV_CURR Buck B caused event 4 R E_OV_CURR_A 0 OV_CURR Buck A caused event 3 R E_TEMP_CRIT 0 TEMP_CRIT caused event 2 R E_TEMP_WARN 0 TEMP_WARN caused event 1 R E_PWRGOOD_B 0 PWRGOOD loss at Buck B caused event 0 R E_PWRGOOD_A 0 PWRGOOD loss at Buck A caused event Data sheet CFR0011-120-00 Rev 3 Description UVLO_IO caused the event Version <3.0> 51 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def 0x54 7 R/W (reserved) 0 MASK_A 6 R/W M_UVLO_IO 0 5 R/W (reserved) 0 4 R/W M_GPI4 0 Masks nIRQ interrupt at GPI4 3 R/W M_GPI3 0 Masks nIRQ interrupt at GPI3 2 R/W M_GPI2 0 Masks nIRQ interrupt at GPI2 1 R/W M_GPI1 0 Masks nIRQ interrupt at GPI1 0 R/W M_GPI0 0 Masks nIRQ interrupt at GPI0 Register Bit Type Label Def Description 0x55 7:6 R/W (reserved) 00 MASK_B 5 R/W M_OV_CURR_B 0 OV_CURR Buck B caused event 4 R/W M_OV_CURR_A 0 OV_CURR Buck A caused event 3 R/W M_TEMP_CRIT 0 TEMP_CRIT caused event 2 R/W M_TEMP_WARN 0 TEMP_WARN caused event 1 R/W M_PWRGOOD_B 0 PWRGOOD Buck B caused event 0 R/W M_PWRGOOD_A 0 PWRGOOD Buck A caused event Data sheet CFR0011-120-00 Rev 3 Description Mask UVLO_IO caused nIRQ Version <3.0> 52 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def Description 0x56 7 R/W V_LOCK 0 0: Allows host writes into registers 0xD0 to 0x14F 1: Disables register 0xD0 to 0x14F reprogramming from control interfaces 6:5 R/W SLEW_RATE_B 10 Buck B DVC slewing is executed at CONTROL_A 00: 10mV every 4.0 µs 01: 10mV every 2.0 µs 10: 10mV every 1.0 µs 11: 10mV every 0.5 µs 4:3 R/W SLEW_RATE_A 10 Buck A DVC slewing is executed at 00: 10mV every 4.0 µs 01: 10mV every 2.0 µs 10: 10mV every 1.0 µs 11: 10mV every 0.5 µs 0:2 R/W DEBOUNCE 011 Input signals debounce time: 000: no debounce time 001: 0.1 ms 010: 1.0 ms 011: 10 ms 100: 50 ms 101: 250 ms 110: 500 ms 111: 1000 ms 14.2.2.2 GPIO Control Register Bit Type Label Def 0x58 GPI0-1 7 R/W GPI1_MODE 0 6 R/W GPI1_TYPE 1 5:4 R/W GPI1_PIN 00 Description 0: GPI: debouncing off 1: GPI: debouncing on 0: GPI: active low 1: GPI: active high PIN assigned to: 00: GPI >00: Reserved 3 R/W GPI0_MODE 0 2 R/W GPI0_TYPE 1 1:0 R/W GPI0_PIN 00 0: GPI: debouncing off 1: GPI: debouncing on 0: GPI: active low 1: GPI: active high PIN assigned to: 00: GPI 01: Track enable 1x: Reserved Data sheet CFR0011-120-00 Rev 3 Version <3.0> 53 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register 0x59 GPIO2-3 Bit Type Label Def 7 R/W GPIO3_MODE 0 6 R/W GPIO3_TYPE 1 Description 0: GPI: debouncing off GPO: Sets output to passive level 1: GPI: debouncing on GPO: Sets output to active level 0: GPI/GPO: active low 1: GPI/GPO: active high PIN assigned to: 00: GPI 5:4 R/W GPIO3_PIN 00 01: Reserved 10: GPO (Open drain) 11: GPO (Push-pull) 3 R/W GPIO2_MODE 0 2 R/W GPIO2_TYPE 1 0: GPI: debouncing off GPO: Sets output to passive level 1: GPI: debouncing on GPO: Sets output to active level 0: GPI/GPO: active low 1: GPI/GPO: active high PIN assigned to: 00: GPI 1:0 R/W GPIO2_PIN 00 01: Reserved 10: GPO (Open drain) 11: GPO (Push-pull) Register Bit Type Label Def 0x5A GPI4 7:4 R/W (reserved) 0000 3 R/W GPI4_MODE 0 2 R/W GPI4_TYPE 1 1:0 Data sheet CFR0011-120-00 Rev 3 R/W GPI4_PIN 00 Description 0: GPI: debouncing off 1: GPI: debouncing on 0: GPI: active low 1: GPI: active high PIN assigned to: 00: GPI 01: Reserved 1x: Reserved Version <3.0> 54 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 14.2.2.3 Regulators Control Register Bit Type Label Def 0x5D BUCKA_CON T 7 R/W (reserved) 0 Description Selects the GPI that specifies the target voltage of VBUCKA. This is VBUCKA_A on active to passive transition, VBUCKA_B on passive to active transition. 6:5 R/W VBUCKA_GPI 00 Active high/low is controlled by GPIx_TYPE. 00: Not controlled by GPIO 01: GPIO1 controlled 10: GPIO2 controlled 11: GPIO4 controlled 4 R/W VBUCKA_SEL 0 Buck A voltage is selected from (ramping): 0: VBUCKA_A 1: VBUCKA_B 3 2:1 R/W R/W BUCKA_PD_DIS BUCKA_GPI 0 00 0: Enable pull-down resistor of Buck A when the buck is disabled 1: Disable pull-down resistor of Buck A when the buck is disabled GPIO enables the Buck A on passive to active state transition, disables the Buck A on active to passive state transition 00: Not controlled by GPIO 01: GPIO0 controlled 10: GPIO1 controlled 11: GPIO3 controlled 0 R/W BUCKA_EN 0 Register Bit Type Label Def 0x5E BUCKB_CON T 7 R/W (reserved) 0 6:5 R/W VBUCKB_GPI 00 0: Buck A disabled 1: Buck A enabled Description Selects the GPI that specifies the target voltage of VBUCKB. This is VBUCKB_A on active to passive transition, VBUCKB_B on passive to active transition. Active high/low is controlled by GPIx_TYPE. 00: Not controlled by GPIO 01: GPIO1 controlled 10: GPIO2 controlled 11: GPIO4 controlled 4 R/W VBUCKB_SEL 0 Buck A voltage is selected from (ramping): 0: VBUCKB_A 1: VBUCKB_B Data sheet CFR0011-120-00 Rev 3 Version <3.0> 55 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit 3 2:1 Type R/W R/W Label Def BUCKB_PD_DIS BUCKB_GPI 0 00 Description 0: Enable pull-down resistor of Buck B when the buck is disabled 1: Disable pull-down resistor of Buck B when the buck is disabled GPIO enables the Buck B on passive to active state transition, disables the Buck B on active to passive state transition 00: Not controlled by GPIO 01: GPIO0 controlled 10: GPIO1 controlled 11: GPIO3 controlled 0 Data sheet CFR0011-120-00 Rev 3 R/W BUCKB_EN 0 0: Buck B disabled 1: Buck B enabled Version <3.0> 56 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 14.2.3 Register Page 1 Register Bit Type Label Def Description 0x80 PAGE_CON 7 R/W REVERT 0 Resets REG_PAGE to 000 after read/write access has finished 6 R/W WRITE_MODE 0 2-WIRE multiple write mode 0: Page Write Mode 1: Repeated Write Mode 5:3 R/W (reserved) 000 000: Selects Register 0x01 to 0x3F 3:0 R/W REG_PAGE 000 001: Selects Register 0x81 to 0xCF 010: Selects Register 0x101 to 0x1CF >010: Reserved for production and test 14.2.3.1 Register Regulators Settings Bit Type Label Def 0xD0 BUCK_ILIM Description Current limit per phase: 0000: 2000 mA 0001: 2200 mA 0010: 2400 mA 7:4 R/W BUCKB_ILIM 1001 continuing through… 1001: 3800 mA to… 1110: 4800 mA 1111: 5000 mA Current limit per phase: 0000: 2000 mA 0001: 2200 mA 0010: 2400 mA 3:0 R/W BUCKA_ILIM 1001 continuing through… 1001: 3800 mA to… 1110: 4800 mA 1111: 5000 mA Data sheet CFR0011-120-00 Rev 3 Version <3.0> 57 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def Description 0xD1 Buck A voltage ramping during power down BUCKA_CON F 000: 1.25 mV/µs 001: 2.5 mV/µs 7:5 R/W BUCKA_DOWN_ CTRL 111 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs 101: 30 mV/µs 110: 40 mV/µs 111: no ramped power down Buck A voltage ramping during start up 000: 1.25 mV/µs 001: 2.5 mV/µs 010: 5 mV/µs 4:2 R/W BUCKA_UP_CTR L 100 011: 10 mV/µs 100: 20 mV/µs (Note 1) 101: 30 mV/µs 110: 40 mV/µs 111: target voltage applied immediately (no soft start) 1:0 R/W BUCKA_MODE 10 00: Reserved 01: Reserved 10: Buck A always operates in PWM mode 11: Automatic mode Note 1 Settings higher than 20 mV/µs may cause significant overshoot Data sheet CFR0011-120-00 Rev 3 Version <3.0> 58 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def Description 0xD2 Buck B voltage ramping during power down BUCKB_CON F 000: 1.25 mV/µs 001: 2.5 mV/µs 7:5 R/W BUCKB_DOWN_ CTRL 111 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs 101: 30 mV/µs 110: 40 mV/µs 111: no ramped power down Buck B voltage ramping during start up 000: 1.25 mV/µs 001: 2.5 mV/µs 010: 5 mV/µs 4:2 R/W BUCKB_UP_CTR L 100 011: 10 mV/µs 100: 20 mV/µs (Note 1) 101: 30 mV/µs 110: 40 mV/µs 111: target voltage applied immediately (no soft start) 1:0 R/W BUCKB_MODE 10 00: Reserved 01: Reserved 10: Buck B always operates in PWM mode 11: Automatic mode Note 1 Settings higher than 20mV/µs may cause significant overshoot Data sheet CFR0011-120-00 Rev 3 Version <3.0> 59 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def 0xD3 7:5 R/W (reserved) 000 4 R/W PH_SH_EN_B 1 Enable current dependant phase shedding in PWM for Buck B 3 R/W PH_SH_EN_A 1 Enable current dependant phase shedding in PWM for Buck A 2 R/W PHASE_SEL_B 1 BUCK_CONF Description Phase selection for Buck B in PWM 1:0 R/W PHASE_SEL_A 11 Register Bit Type Label Def 0xD5 VBUCKA_MA X 7 R/W (reserved) 0 0: 1 phase is selected 1: 2 phases are selected Phase selection for Buck A in PWM mode. Settings >01 apply only for DA9211 otherwise the number of phases is limited to max 2 00: 1 phase is selected 01: 2 phases are selected 10: 3 phases are selected (uneven 0/90/180 phase shift) 11: 4 phases are selected Description Sets the maximum voltage allowed for Buck A (OTP programmed, access only in test mode) 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R VBUCKA_MAX 0x7F Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Data sheet CFR0011-120-00 Rev 3 Version <3.0> 60 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def 0xD6 7 R/W (reserved) 0 VBUCKB_MA X Description Sets the maximum voltage allowed for Buck B (OTP programmed, access only in test mode) 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R VBUCKB_MAX 0x7F Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label Def 0xD7 VBUCKA_A 7 R/W (reserved) 0 Description 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R/W VBUCKA_A 0x46 Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Data sheet CFR0011-120-00 Rev 3 Version <3.0> 61 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def 0xD8 7 R/W (reserved) 0 VBUCKA_B Description 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R/W VBUCKA_B 0x46 Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label Def 0xD9 7 R/W (reserved) 0 VBUCKB_A Description 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R/W VBUCKB_A 0x46 Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Data sheet CFR0011-120-00 Rev 3 Version <3.0> 62 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def 0xDA 7 R/W (reserved) 0 VBUCKB_B Description 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R/W VBUCKB_B 0x46 Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Data sheet CFR0011-120-00 Rev 3 Version <3.0> 63 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 14.2.4 Register Page 2 Register Bit Type Label Def Description 0x100 PAGE_CON 7 R/W REVERT 0 Resets REG_PAGE to 000 after read/write access has finished 6 R/W WRITE_MODE 0 2-WIRE multiple write mode 0: Page Write Mode 1: Repeated Write Mode 5:3 R/W (reserved) 000 000: Selects Register 0x01 to 0x3F 3:0 R/W REG_PAGE 000 001: Selects Register 0x81 to 0xCF 010: Selects Register 0x101 to 0x1CF >010: Reserved for production and test 14.2.4.1 Interface and OTP Settings (shared with DA9063) Register Bit Type Label Def 0x101 OTP_CONT 7:4 R/W (reserved) 0000 Description 3 R/W PC_DONE 0 Asserted from Power Commander software after the emulated OTP read has finished, automatically cleared when leaving emulated OTP read 2 R/W OTP_APPS_RD 0 Reads on assertion application specific registers 0x105, 0x106, 0x143 to 0x149 and OTP_APPS_LOCK) from OTP 1 R/W (reserved) 0 0 R/W OTP_TIM 0 OTP read timing: Data sheet CFR0011-120-00 Rev 3 0: normal read 1: marginal read (for OTP fuse verification) Version <3.0> 64 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def Description 1101 4 MSB of 2-WIRE control interfaces base address XXXX0000 11010000 = 0xD0 write address of PM 2-WIRE interface (page 0 and 1) 11010001 = 0xD1 read address of PM 2-WIRE interface (page 0 and 1) 11010010 = 0xD2 write address of PM-2-WIRE interface (page 2 and 3) 11010011 = 0xD3 read address of PM-2-WIRE interface (page 2 and 3) Code ‘0000’ is reserved for unprogrammed OTP (triggers start-up with hardware default interface address) 0x105 INTERFACE 7:4 R/W IF_BASE_ADDR1 3 R/W R/W_POL 1 4-WIRE: Read/Write bit polarity 0: Host indicates reading access via R/W bit = ‘0’ 1: Host indicates reading access via R/W bit = ‘1’ 2 R/W CPHA 0 4-WIRE interface clock phase (see Table 13) 1 R/W CPOL 0 4-WIRE interface clock polarity 0: SK is low during idle 1: SK is high during idle 0 Data sheet CFR0011-120-00 Rev 3 R/W nCS_POL 1 4-WIRE chip select polarity 0: nCS is low active 1: nCS is high active Version <3.0> 65 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit 0x106 Type R/W Label Def Description IF_TYPE 1 0: Power manager interface is 4-WIRE. Automatically configures GPIO3 and GPI4 as interface signals. The GPIO configuration is overruled. 1: Power manager interface is 2-WIRE Er or! INTERFACE2 7 Bookma rk not defined. 14.2.4.2 Register 6 R/W PM_IF_HSM 0 Enables continuous high speed mode on 2-WIRE interface if asserted (no master code reguired) 5 R/W PM_IF_FMP 0 Enables 2-WIRE interface operating with fast mode+ timings if asserted 4 R/W PM_IF_V 0 0:3 R/W (reserved) 0000 0: Power manager interface in 2-WIRE mode is supplied from VDDCORE (4-WIRE always from VDDIO) 1: Power manager interface in 2-WIRE mode is supplied from VDDIO (4-WIRE always from VDDIO) OTP Fusing Registers Bit Type Label Def Description 0 0: Registers 0x54 to 0x5E and 0xD0 to 0xDA are not locked for OTP programming (should be selected for unmarked evaluation samples) 0x140 OTP_CONT2 7 R/W OTP_CONF_LOC K 1: Registers 0x54 to 0x5E and 0xD0 to 0xDA are locked in OTP (no further fusing possible) 6 R/W OTP_APPS_LOC K 0 0: Registers 0x105, 0x106, 0x143 to 0x149 are not locked for OTP programming (should be selected for unmarked evaluation samples) 1: Registers 0x105, 0x106, 0x143 to 0x149 are locked in OTP (no further fusing possible) 5:0 R/W (reserved) 0000 00 Register Bit Type Label Def Description 0x141 OTP_ADDR 7:0 R/W OTP_ADDR 0x00 OTP Array address Register Bit Type Label Def Description 0x142 OTP_DATA 7:0 R/W OTP_DATA 0x00 OTP read/write data OTP_DATA written to OTP_ADDR selects the IC and accepts unlock sequence (1 + 3 bytes) Data sheet CFR0011-120-00 Rev 3 Version <3.0> 66 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 14.2.4.3 Application Configuration Settings Register Bit Type Label Def 0x143 CONFIG_A 7:5 R/W (reserved) 000 4 R/W 2WIRE_TO 1 3 R/W GPI_V 0 Description Enables automatic reset of 2-WIRE interface if the clock stays low for >35 ms 0: Disabled 1: Enabled GPIs are supplied from: 0: VDDCORE 1: VDDIO 2 R/W (reserved) 0 nIRQ output port is: 1 R/W IRQ_TYPE 1 0 R/W IRQ_LEVEL 0 0: Push-pull 1: Open drain (requires external pull-up resistor) nIRQ output port is: 0: Active low 1: Active high Data sheet CFR0011-120-00 Rev 3 Version <3.0> 67 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def Description 7 R/W UVLO_IO_DIS 0 Disable the UVLO for the VDDIO rail and its comparator (suggested for rail voltages different to 1.8 V and to save quiescent current) 0x144 CONFIG_B 6 R/W PGB_DVC_MAS K 0 Power-good configuration for Buck B 0: Power-good signal not masked during DVC transitions 1: Power-good signal masked during DVC transitions (keep previous status) 5 R/W PGA_DVC_MAS K 0 Power-good configuration for Buck A 0: Power-good signal not masked during DVC transitions 1: Power-good signal masked during DVC transitions (keep previous status) Over Current configuration for Buck B 00: Event generation due to over current hit is always active during DVC transitions of the Buck converter 4:3 R/W OCB_MASK 00 01: Event generation due to over current hit is masked during DVC transitions of the buck converter + 2 µs extra masking at the end 10: Event generation due to over current hit is masked during DVC transitions of the buck converter + 10 µs extra masking at the end 11: Event generation due to over current hit is masked during DVC transitions of the buck converter + 50 µs extra masking at the end Over Current configuration for Buck A 00: Event generation due to over current hit is always active during DVC transitions of the buck converter 2:1 R/W OCA_MASK 00 01: Event generation due to over current hit is masked during DVC transitions of the buck converter + 2 µs extra masking at the end 10: Event generation due to over current hit is masked during DVC transitions of the buck converter + 10 µs extra masking at the end 11: Event generation due to over current hit is masked during DVC transitions of the buck converter + 50 µs extra masking at the end 0 Data sheet CFR0011-120-00 Rev 3 R/W (reserved) 0 Version <3.0> 68 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def 0x145 7:5 R/W (reserved) 000 4 R/W GPI4_PUPD 0 CONFIG_C 3 R/W GPIO3_PUPD 0 Description 0: GPI: pull-down resistor disabled 1: GPI: pull-down resistor enabled 0: GPI: pull-down resistor disabled GPO (open drain): pull up resistor disabled (external pull-up resistor) 1: GPI: pull-down resistor enabled GPO (open drain): pull up resistor 2 R/W GPIO2_PUPD 0 0: GPI: pull-down resistor disabled GPO (open drain): pull up resistor disabled (external pull-up resistor) 1: GPI: pull-down resistor enabled GPO (open drain): pull up resistor enabled Register 1 R/W GPI1_PUPD 0 0: GPI: pull-down resistor disabled 1: GPI: pull-down resistor enabled 0 R/W GPI0_PUPD 0 0: GPI: pull-down resistor disabled 1: GPI: pull-down resistor enabled Bit Type Label Def Description 0x146 Selection of the PG signal for Buck B CONFIG_D 00: none 01: GPO2 7:6 R/W BUCKB_PG_SEL 00 10: GPO3 11: reserved Selection of the PG signal for Buck A 00: none 5:4 R/W BUCKA_PG_SEL 00 01: GPO2 10: GPO3 11: reserved Selection of the READY signal for Buck B 00: none 3:2 R/W READYB_CONF 00 01: GPO2 10: GPO3 11: reserved Selection of the READY signal for Buck A 1:0 R/W READYA_CONF 00 00: none 01: GPO2 10: GPO3 11: reserved Data sheet CFR0011-120-00 Rev 3 Version <3.0> 69 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Register Bit Type Label Def Description 0: DA9211 and DA9212 is used as companion IC to DA9063 or DA9063-compliant 0x147 CONFIG_E 7 R/W STAND_ALONE 0 6 R/W (reserved) 0 5:3 R/W (reserved) 000 1: DA9211 and DA9212 is stand alone or as companion IC with another PMU not DA9063-compliant Tune the main 6 MHz oscillator frequency: 000: no tune Register 2:0 R/W OSC_TUNE 000 Bit Type Label Def 0x148 001: +180 kHz 010: +360 kHz 011: +540 kHz 100: +720 kHz 101: 900 kHz 110: 1080 kHz 111: 1260 kHz Description If a second I2C address is to be selected on ADR_SEL_CONF, this field configures the second address. CONFIG_F 7:4 R/W IF_BASE_ADDR2 1101 4 MSB of 2-WIRE control interfaces base address XXXX0000 11010000 = 0xD0 write address of PM 2-WIRE interface (page 0 and 1) 11010001 = 0xD1 read address of PM 2-WIRE interface (page 0 and 1) 11010010 = 0xD2 write address of PM-2-WIRE interface (page 2 and 3) 11010011 = 0xD3 read address of PM-2-WIRE interface (page 2 and 3) Code ‘0000’ is reserved for unprogrammed OTP (triggers start-up with hardware default interface address) 3:2 1 R R/W (reserved) 00 ADDR_SEL_CON F Selects the GPI for the alternative I2C address selection: 00: none 00 01: GPI0 10: GPI1 11: GPI4 Data sheet CFR0011-120-00 Rev 3 Version <3.0> 70 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 15. Application Information The following recommended components are examples selected from requirements of a typical application. 15.1 Capacitor Selection Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias characteristic has to be taken into account. Table 17: Recommended capacitor types Application Value Size VOUT output bypass 4x 22 µF 0402 X5R +/-15% +/-20% 4V Semco CL05A226MR5NZNC 4x 10 µF 0402 X5R +/-15% +/-20% 10 V 4x 10 µF 0603 X5R +/-15% +/-20% 6.3 V 1x 1 µF 0402 X5R +/-15% +/-10% 10 V 1x 100 nF 01005 X5R +/-15% ±10% 6.3 V Semco CL05A106MP5NUNC Murata GRM188R60J106ME84 Murata GRM155R61A105KE15# Semco CL02A104KQ2NNN VDDx bypass VSYS bypass VDDIO bypass Temp Char Tol V-Rate Type 15.2 Inductor Selection Inductors should be selected based upon the following parameters: ● Rated max. current: usually a coil provides two current limits: The Isat specifies the maximum current at which the inductance drops by 30% of the nominal value. The Imax is defined by the maximum power dissipation and is applied to the effective current. ● DC resistance: critical for the converter efficiency and should therefore be minimised. ● Inductance: given by converter electrical characteristics; 0.47uH for each DA9211 and DA9212 phase. Data sheet CFR0011-120-00 Rev 3 Version <3.0> 71 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Table 18: Recommended inductor types Applicatio n Value Size BUCK 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 4x 0.47 µH 2.0x1.6x 1.0 mm 2.0x1.6x 1.2 mm 2.5x2.0x 1.0 mm 2.5x2.0x 1.2 mm 2.0x1.6x 1.0 mm 2.5x2.0x 1.0 mm 2.0x1.6x 1.0mm 2.5x2.0x 1.0mm 2.5x2.0x 1.2mm 2.5x2.0x 1.2mm 2.0x2.0x 1.2mm 2.5x2.0x 1.2mm 2.0x1.6x 1.0mm 4x4x1.2 mm Data sheet CFR0011-120-00 Rev 3 Imax(dc) Isat Tol 3.6 A 4.1 A +/-20% 3.8 A 4.2 A +/-30% 3.6 A 3.9 A +/-20% 4.4 A 4.7 A +/-20% 2.7 A 3.5 A +/-20% 2.8 A 4.5 A +/-20% 2.7 A 3.56 A +/-20% 3.5 A 4.5 A +/-20% 4.5 A 5.0 A +/-20% 3.7 A 3.9 A +/-20% 2.8 A 4.2 A +/-30% 3.9 A 4.8 A +/-20% 3.2 A 3.6 A +/-20% 8.7 A 6.7 A +/-20% Version <3.0> 72 of 74 DC res 32 mΩ 40 mΩ 35 mΩ 29 mΩ 38 mΩ 34 mΩ 38 mΩ 34 mΩ 23 mΩ 25 mΩ 30 mΩ 30 mΩ 32 mΩ 14 mΩ Type TOKO DFE201610PH-R47M TOKO DFE201612C 1286AS-H-R47M TOKO DFE252010C 1269AS-H-R47M TOKO DFE252012C 1239AS-H-R47M TDK TFM201610A R47M TDK TFM252010A R47M Cyntec PIFE20161T Cyntec PIFE25201T Cyntec PIFE25201B Cyntec PST25201B Taiyo Yuden MDMK2020T R47M Taiyo Yuden MAMK2520T R47M Murata LQM2MPNR47MGH Coilcraft XFL4012471ME <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet 16. Package information Figure 49: DA9211/12 WL-CSP package outline drawing Data sheet CFR0011-120-00 Rev 3 Version <3.0> 73 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH DA9211 and DA9212 Company confidential Datasheet Disclaimer Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any information source outside of Dialog Semiconductor. Dialog Semiconductor reserves the right to change without notice the information published in this document, including without limitation the specification and the design of the related semiconductor products, software and applications. Applications, software, and semiconductor products described in this document are for illustrative purposes only. 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Phone: +31 73 640 88 22 Taiwan Dialog Semiconductor Taiwan Phone: +886 226 580 388 Korea Dialog Semiconductor Korea Phone: +82 2 569 2301 Email: [email protected] Web site: www.dialog-semiconductor.com Data sheet CFR0011-120-00 Rev 3 Version <3.0> 74 of 74 <07-Jan-2015> © 2015 Dialog Semiconductor GmbH