M65667SP
Picture-in-Picture Signal Processing
REJ03F0186-0201
Rev.2.01
Mar 31, 2008
Description
The M65667SP is a NTSC PIP (Picture in Picture) signal processing LSI, whose sub and main-picture inputs are
composite and Y/C separated signals, respectively. The built-in field memory (96 Kbit RAM), V-chip data slicer and
analog circuitries lead the PIP system low cost and small size.
Features
•
•
•
•
•
•
Built-in 96 Kbit field memory (sub-picture data storage)
Internal V-chip data slicer (for sub-picture)
Pin compatible with M65617SP
Vertical filter for sub-picture (Y signal)
Single sub-picture (selectable picture size: 1/9, 1/16)
Sub-picture processing specification (1/9 size / 1/16 size)
Quantization bits
Y, B-Y, R-Y: 6 bits
Horizontal sampling 171 pixels (Y), 28.5 pixels (B-Y, R-Y)
Vertical lines
69/52 lines
• Frame (sub-picture) on/off
• Built-in analog circuits
Two 8-bit A/D converters (main and sub-picture signals)
Two 8-bit D/A converters (Y and C sub-picture signals)
Sync-tip-clamp, VCXO, Analog switch, etc.
• I2C BUS control (parallel/serial control)
PIP on/off, Sub-picture size (1/9 or 1/16), Frame on/off (programmable luma level), PIP position (4 corners fixed
position), Picture freeze, Y delay adjustment, Chroma level, Tint, Black level, Contrast, etc.
Application
NTSC color TV
Recommended Operating Condition
Supply voltage range …………………………… 3.1 to 3.5 V
Operating frequency …………………………… 14.32 MHz
Operating temperature ………………………… –20 to 75°C
Input voltage (CMOS interface) "H" …………… Vdd ± 0.7 to Vdd V
"L" …………… 0 to Vdd ± 0.3 V
Output current (output buffer) ………………… 4 mA (Max)
Output load capacitance ………………………
20 pF (Max) Note2
Circuit current ………………………………… 160 mA
Notes: 1. Connect a 0.1 µF or larger capacitor between Vdd and Vss pins.
2. Include pin capacitance (7 pF)
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 1 of 11
M65667SP
Block Diagram
SCK
CSYNC (s)
/TEST1
BGP (s)
/TEST0
Yin
Y-PlP
Sync tip
clamp
Cin
Vdd/Vss
15
For test
3
DATA
CLK
ACK
Vin (s)
3
Vrt (m)
Vrb (m)
Bias
C-PlP
RAM (1H)
V-chip
data slicer
I2C
I/F
Y
Delay
Luma
clamp
Y
A/D
8 bit
Sync tip
clamp
Bias
6
Back porch
clamp
Y/C SEP
(LPF, BPF)
Sync
sep
2
Phase
select
HD
C
Demod
Tint
B-Y
6
R-Y
6
SWMG
/TEST7
2
HPLL
Yout-sub
Y
B-Y
R-Y
4 fsc
Delay
D/A
8 bit
Delay
Delay
Cout-sub
Encode
MIX
D/A
8 bit
Vrt (m)
Vrb (m)
fsc
Y
6 B-Y
Timing gen
(Memory
cont)
RAM
96 Kbits
VD
/CSYNC
/TEST6
6 R-Y
HD
/TEST5
Level
detect
ADJ-Csub
Vin (m)
LPF
&MPY
6
Demux
(I C)
ADJ-Ysub
Bias
A/D
8 bit
FILTER
BIAS
Phase
detect
Burst data
sampling
4 fsc
Lock/Free-run
via I2C
2
RESET
MCK
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 2 of 11
Y-PlPin
Vert-filter
&
MUX
Timing gen
(Decode)
AFC
C-PlPin
BGP (m)
/TEST2
fsc
/TEST3
SWM
/TEST4
VCXO
driver
VCXO in
VCXO
VCXO out
M65667SP
Pin Arrangement
M65667SP
AVss3 (vcxo) 1
52 AVssf (ana)
VCXO out 2
51 Cin
VCXO in 3
50 TESTEN
FILTER 4
49 Yin
BIAS 5
48 TEST9
AVdd3 (vcxo) 6
47 Y-PIP
AVdd2 (m) 7
46 TEST8
Vin (m) 8
45 C-PIP
Vrt (m) 9
44 AVdd4 (da)
Vrb (m) 10
43 C-PIPin
AVss2 (m) 11
AVdd1 (s) 12
42 AVss4 (da)
41 Y-PIPin
Vin (s) 13
40 ADJ-Ysub
Vrt (s) 14
39 Yout-sub
38 ADJ-Csub
Vrb (s) 15
AVss1 (s) 16
RESET 17
37 Cout-sub
36 DVss3
DVss1 18
35 DVdd3
DVdd1 19
34 LOCK/TEST7
33 VD/CSYNC/TEST6
BGP (s)/TEST0 20
32 HD/TEST5
SCK 21
31 SWM/TEST4
CSYNC (s)/TEST1 22
30 MCK
ACK 23
29 fsc/TEST3
DATA 24
28 BGP (m)/TEST2
CLK 25
27 DVdd2 (ram)
DVss2 (ram) 26
(Top view)
Outline: PRDP0052BA-A (52P4B)
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 3 of 11
M65667SP
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
AVss3 (vcxo)
VCXO out
VCXO in
FILTER
BIAS
AVdd3 (vcxo)
AVdd2 (m)
Vin (m)
Vrt (m)
Vrb (m)
AVss2 (m)
AVdd1 (s)
Vin (s)
Vrt (s)
Vrb (s)
AVss1 (s)
RESET
I/O
GND
O
I
I
O
Vdd
Vdd
I
O
O
GND
Vdd
I
O
O
GND
I
Function
Connects to analog GND
VCXO output signal
VCXO input signal
Filter
Bias
Connect to analog power supply
Connect to analog power supply
Chroma signal input (main-picture)
A/D Vref+ (main-picture)
A/D Vref– (main-picture)
Connect to analog GND
Connect to analog power supply
Composite video signal input (sub-picture)
A/D Vref+ (sub-picture)
A/D Vref– (sub-picture)
Connect to analog GND
Power on reset input signal ("L" reset)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DVss1
DVdd1
BGP (s) /TEST0
SCK
CSYNC (s) /TEST1
ACK
DATA
CLK
DVss2 (ram)
DVdd2 (ram)
BGP (m) /TEST2
fsc/TEST3
MCK
SWM/TEST4
HD/TEST5
VD/CSYNC/TEST6
SWMG/TEST7
DVdd3
GND
Vdd
(I/) O
I
I (/O)
O
I
I
GND
Vdd
(I/) O
I (/O)
I
(I/) O
I (/O)
I (/O)
I (/O)
Vdd
Connect to digital GND
Connect to digital power supply
For test
For test (connect to digital GND)
For test (connect to digital GND)
I2C bus-data/Acknowledge output signal
I2C bus-data input signal
I2C bus-clock input signal
Connect to digital GND
Connect to digital power supply
For test
For test (pull down to digital GND by resistor 15 kΩ)
For test (connect to digital GND)
For test
Horizontal sync input signal (Positive going edge is used)
Vertical sync input signal (active "H")
Enable input signal to display sub picture ("H" enable)
Connect to digital power supply
36
37
38
39
40
41
42
43
44
45
DVss3
Cout-sub
ADJ-Csub
Yout-sub
ADJ-Ysub
Y-PIPin
AVss4 (da)
C-PIPin
AVdd4 (da)
C-PIP
GND
O
I
O
I
I
GND
I
Vdd
O
Connect to digital GND
D/A output signal (Chroma signal of sub-picture)
D/A adjust for chroma signal (sub-picture)
D/A output signal (Luma signal of sub-picture)
D/A adjust for luma signal (sub-picture)
PIP luma signal re-input
Connects to analog GND
PIP chroma signal re-input
Connect to analog power supply
PIP chroma signal output
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 4 of 11
Remarks
100 kΩ to Vdd,
10 µF to GND
Non connect
Connect to GND
Pull down 15 kΩ
Non connect
Pull down 15 kΩ
Connect to GND
Non connect
Pull up 15 kΩ
M65667SP
Pin Description (cont.)
Pin
No.
46
47
48
49
50
51
52
Name
TEST8
Y-PIP
TEST9
Yin
TESTEN
Cin
AVssf (ana)
I/O
I
O
I
I
I
I
Vss
Function
For test (connect to analog GND)
PIP luma signal output
For test (connect to analog GND)
Luma input signal (main-picture)
For test (connect to analog GND)
Chroma input signal (main-picture)
Connect to analog GND
Remarks
Pull up 15 kΩ
Connect to GND
Connect to GND
Absolute Maximum Ratings
(Vss = 0 V)
Limits
Item
Symbol
Min
Max
Unit
Supply voltage (3.3 V)
VDD3
–0.3
4.6
V
Input voltage
Output voltage
VI
VO
–0.3
–0.3
VDD3 + 0.3
VDD3 + 0.3
V
V
IO
—
IOL = 20
IOH = –26
1400
75
125
mA
Output current
Note1
Power dissipation
Operating temperature
Storage temperature
Note:
Pd
Topr
Tstg
—
–20
–50
1. Output current per output terminal. But Pd limits all current.
Thermal Derating
(Maximum Rating)
Power Dissipation Pd (mW)
2000
1600
1490
1200
800
400
0
0
25
50
75
100
Ambient Temperature Ta (°C)
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 5 of 11
125
mW
°C
°C
M65667SP
DC Characteristics
(Ta = 25°C, unless otherwise noted, Vss = 0 V)
Item
Symbol
Input voltage
(CMOS interface)
Min
Limits
Typ
Max
Unit
—
—
—
—
—
—
—
—
—
—
—
—
—
7
7
7
0.81
3.6
1.65
2.4
1.2
0.05
—
—
–4
1
1
1
1
15
15
15
V
V
V
V
V
V
V
mA
mA
µA
µA
µA
µA
pF
pF
pF
—
140
mA
L
H
–
+
VIL
VIH
VT–
VT+
Hysteresis
L
H
L
H
L
H
L
H
Input pin capacitance
Output pin capacitance
Bidirectional pin capacitance
VH
VOL
VOH
IOL
IOH
IIL
IIH
IOZL
IOZH
CI
CO
CIO
0
2.52
0.5
1.4
0.3
—
3.25
4
—
–1
–1
–1
–1
—
—
—
Operating current
3.3 V supply
IDD
—
Input voltage schmitt
trigger
(CMOS interface)
Output voltage
Output current
Input current
Output leakage current
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 6 of 11
Test Conditions
VDD = 2.7 V
VDD = 3.6 V
VDD = 3.3V
VDD = 3.3 V, |IO| < 1 µA
VDD = 3.0 V, VOL = 0.4 V
VDD = 3.0 V, VOH = 2.6 V
VDD = 3.6 V, VI = 0 V
VDD = 3.6 V, VI = 3.6 V
VDD = 3.6 V, VO = 0 V
VDD = 3.6 V, VO = 3.6 V
f = 1 MHz, VDD = 0 V
M65667SP
PIP TV System Block Diagram
(BASIC)
Composite
video signal
Y/C
Separation
Y
Y
M65667SP
Y
C
C
C
BLPLL
B-LD
Y/C separated
video signal
Y
C
CV
+
PIP signal
processing
Y
Video
signal
processing
Deflection
unit
Yoke
C
HD
VD
Driving Method and Operating Specification for Serial Interface Data
(1) Serial data transmission completion and start
A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the
serial transmission and makes the bus free.
A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the
following CLK and DATA inputs.
(2) Serial data transmission
The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively.
One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter
one is for acknowledge detection. (In reading state, ACK is "H" under these two conditions;
1. The coincidence of two address data for the address data transmission.
2. The completion of 8-bit setting data transfer. In writing state, ACK is "H" with the address coincidence and
ACK is "L" for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data).
For address/data transmission, DATA must change while CLK is "L". (The data change while CLK is "H" or the
simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from
the completion/start of serial data transfer.)
After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited.
(3) The byte format of data transmission (The sequence of data transmission)
1. The byte format during data setting to M65667SP are shown as follows.
In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred.
Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively.
Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are
written into the address resister whose address is increased one in initially transferred internal register address.
(The next address of 7Fh, it returns to 00h.)
2. The byte format during data reading from M65667SP are shown as follows.
Before data reading from M65667SP, whose internal address need to be set by the data reading/transmitting.
After the data reading/transmitting, the operation of "serial data transmission completion and start" (described in
(1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data
are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this
operation, the setting data also are written into the address register whose address is increased one in initially
transferred internal register address. (The next address of 7Fh, it returns to 00h.)
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 7 of 11
M65667SP
The Examples of Serial Byte Transmission Format
(1) The writing operation of the setting data (AAh) into M65667SP internal address of 00h
Confirmation
of bus free
(DATA = 'H')
Transmission
activation
Yes
S
24h
A
00h
A
AAh
A D E
No
S: Operation of serial transmission start
A: Acknowledge detection
D: Dummy clock feed for the release of
acknowledge output state
E: Operation of serial transmission completion
is applied
on CLK for the
release of
output state
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65667SP internal address of 04h to 06h
Transmission
activation
Confirmation
of bus free
(DATA = 'H')
Yes
S
24h
A
04h
A
FFh
A
80h
A
EEh
A D E
No
is applied
on CLK for the
release of
output state
(3) The reading operation of the setting data from M65667SP internal address of 00h
Transmission
activation
Confirmation
of bus free
(DATA = 'H')
Yes
S
24h
A
00h
A D E S
25h
A
$$h
A
No
A: Bus free operation by the master (micro processor)
is applied
on CLK for the
release of
output state
(4) The reading operation of the setting data from M65667SP internal address of 04h to 06h
Transmission
activation
Confirmation
of bus free
(DATA = 'H')
Yes
S
24h
A
04h
A D E S
25h
A
$$h
A
No
is applied
on CLK for the
release of
output state
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 8 of 11
A: Output L operation by the master (micro processor)
$$h
A
$$h A
M65667SP
Timing Diagram
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(1)
CLK
DATA
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
ACK
Detec.
Bit7
(MSB)
ACK
_Acknowledge
ACK
_Readout data
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 9 of 11
Bit7
(MSB)
M65667SP
104 F
10 µF
104 F
360 Ω
150 pF
49
48
47
46
Horizontal sync input signal (main-picture)
Dig
104 F
45
44
43
42
103 F
10 F
+
15
kΩ
50
Dig
103 F
103 F
51
Vertical sync input signal (main-picture)
Ana.
Ana.
52
Sub-picture displaying on/off
PIP Chroma signal output
470 Ω
68 pF
Ana.
+
PIP Luma signal output
Luma signal input (main-picture)
Ana.
104 F
41
40
39
38
103 F
15 kΩ
37
36
35
34
33
32
31
30
29
28
27
16
17
18
19
20
21
22
23
24
25
26
103 F
+
Chroma input signal (main-picture)
Application Example
10 µF
M65667SP
6
7
470
kΩ
3.3 µF
104 F
10 µF
Ana.
Analog +3.3 V
power supply
12
13
14
15
103 F 103 F
103 F 103 F
10 µF
Ana.
Dig 5 V
+
103 F
104 F
Ana.
100 kΩ
103 F
103 F
Ana.
Digital GND
11
10 µF
+
Digital +3.3 V
power supply
10
104 F
100 kΩ
103 F
2 kΩ
51 Ω
330 Ω
9
10 µF
Dig 5 V
12 kΩ
14 pF
8
47 kΩ
5
12 kΩ
4
47 kΩ
3
+
2
+
1
Dig
Analog GND
+
560 Ω
100 Ω
10 kΩ
100 Ω
10 kΩ
100 Ω
SCL
Composite video
input signal
(sub-picture)
330 Ω
SDA
SYNC SEP
Circuit
(Optional)
I2C BUS Clock
input signal
I2C BUS DATA
input/output
signal
Note:
Separate Y/C signals by using LC-tank circuit or LPF, BPF for Y/C signals level adjust.
And then mix both signals for sub-picture input video signal.
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 10 of 11
M65667SP
Package Dimensions
RENESAS Code
PRDP0052BA-A
Previous Code
52P4B
MASS[Typ.]
5.1g
27
1
26
c
*1
E
52
e1
JEITA Package Code
P-SDIP52-13x45.85-1.78
*2
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
D
A
A2
L
A1
Reference
Symbol
SEATING PLANE
*3
e
b3
bp
*3 b
2
e1
D
E
A
A1
A2
bp
b2
b3
c
e
L
REJ03F0186-0201 Rev.2.01 Mar 31, 2008
Page 11 of 11
Dimension in Millimeters
Min
14.94
45.65
12.85
Nom
15.24
45.85
13.0
Max
15.54
16.05
13.15
5.5
0.51
0.4
0.65
0.9
0.22
0°
1.528
3.0
3.8
0.5 0.6
0.75 1.05
1.0 1.3
0.27 0.34
15°
1.778 2.028
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
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