MOTOROLA DSP56002PV80 24-bit digital signal processor Datasheet

MOTOROLA
Order this document by:
DSP56002/D, Rev. 3
SEMICONDUCTOR TECHNICAL DATA
DSP56002
24-BIT DIGITAL SIGNAL PROCESSOR
The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an
efficient 24-bit DSP core, program and data memories, various peripherals, and support
circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs.
The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI),
parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip
Emulation (OnCE™) port. This combination of features, illustrated in Figure 1, makes the
DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital
signal processing.
1
6
24-bit
Timer/
Event
Counter
Sync.
Serial
(SSI)
or I/O
3
Serial
Comm.
(SCI)
or I/O
XAB
YAB
External
Data
Bus
Switch
PDB
XDB
YDB
Interrupt
Control
Clock
Gen.
Program
Decode
Controller
Program
Address
Generator
Y Data
Memory
256 × 24 RAM
256 × 24 ROM
(sine)
External
Address
Bus
Switch
GDB
OnCE™
Port
7
X Data
Memory
256 × 24 RAM
256 × 24 ROM
(A-law/ µ-law)
PAB
Internal
Data
Bus
Switch
PLL
Program
Memory
512 × 24 RAM
64 × 24 ROM
(boot)
Host
Interface
(HI)
or I/O
Address
Generation
Unit
24-bit
56000 DSP
Core
16-bit Bus
24-bit Bus
15
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
Bus
Control
Address
16
Data
24
Control
10
Program Control Unit
4
3
IRQ
AA0604
Figure 1 DSP56002 Block Diagram
©1996 MOTOROLA, INC.
SECTION 1
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SECTION 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SECTION 3
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
SECTION 4
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
SECTION 5
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
FOR TECHNICAL ASSISTANCE:
Telephone:
1 (800) 521-6274
Email:
[email protected]
Internet:
http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
“asserted”
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
“deasserted”
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Examples:
Note:
ii
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
DSP56002/D, Rev. 3
MOTOROLA
DSP56002
Features
FEATURES
Digital Signal Processing Core
•
Efficient 24-bit DSP56000 core
•
Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at
80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz
•
Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS
at 66 MHz
•
Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks
•
Highly parallel instruction set with unique DSP addressing modes
•
Two 56-bit accumulators including extension bits
•
Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
•
Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles
•
56-bit addition/subtraction in 1 instruction cycle
•
Fractional and integer arithmetic with support for multiprecision arithmetic
•
Hardware support for block-floating point FFT
•
Hardware nested DO loops
•
Zero-overhead fast interrupts (2 instruction cycles)
•
Four 24-bit internal data buses and three 16-bit internal address buses for
maximum information transfer on-chip
•
On-chip Harvard architecture permitting simultaneous accesses to program
and two data memories
•
512 × 24-bit on-chip Program RAM and 64 × 24-bit bootstrap ROM
•
Two 256 × 24-bit on-chip data RAMs
•
Two 256 × 24-bit on-chip data ROMs containing sine, A-law, and µ-law tables
•
External memory expansion with 16-bit address and 24-bit data buses
•
Bootstrap loading from external data bus, Host Interface, or Serial
Communications Interface
Memory
MOTOROLA
DSP56002/D, Rev. 3
iii
Features
Peripheral and Support Circuits
•
Byte-wide host interface (HI) with Direct Memory Access (DMA) support (or
fifteen Port B GPIO lines)
•
SSI support:
–
Supports serial devices with one or more industry-standard codecs, other
DSPs, microprocessors, and Motorola-SPI-compliant peripherals
–
Asynchronous or synchronous transmit and receive sections with separate
or shared internal/external clocks and frame syncs
–
Network mode using frame sync and up to 32 software-selectable time
slots
–
8-bit, 12-bit, 16-bit, and 24-bit data word lengths
•
SCI for full duplex asynchronous communications (or three additional Port C
GPIO lines)
•
One 24-bit timer/event counter (or one additional GPIO line)
•
Double-buffered peripherals
•
Up to twenty-five General Purpose Input/Output (GPIO) pins
•
One non-maskable and two maskable external interrupt/mode control pins
•
On-Chip Emulation (OnCE) port for unobtrusive, processor speedindependent debugging
•
Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer
for the DSP core clock with a wide input frequency range (12.2 KHz to 80
MHz)
Miscellaneous Features
iv
•
Power-saving Wait and Stop modes
•
Fully static, HCMOS design for specified operating frequency down to dc
•
Three packages available:
–
132-pin Plastic Quad Flat Pack (PQFP); 1.1 × 1.1 × 0.19 inches
–
144-pin Thin Quad Flat Pack (TQFP); 20 × 20 × 1.5 mm
–
132-pin Ceramic Pin Grid Array (PGA); 1.36 × 1.35 × 0.125 inches
DSP56002/D, Rev. 3
MOTOROLA
DSP56002
Product Documentation
PRODUCT DOCUMENTATION
The three documents listed in the following table are required for a complete description of the
DSP56002 and are necessary to design properly with the part. Documentation is available from
one of the following locations (see back cover for detailed information):
•
A local Motorola distributor
•
A Motorola semiconductor sales office
•
A Motorola Literature Distribution Center
•
The World Wide Web (WWW)
Table 1 DSP56002 Documentation
Name
Description
Order Number
DSP56000
Family Manual
Detailed description of the DSP56000 family
processor core and instruction set
DSP56KFAMUM/AD
DSP56002
User’s Manual
Detailed functional description of the DSP56002
memory configuration, operation, and register
programming
DSP56002UM/AD
DSP56002
Technical Data
DSP56002 features list and physical, electrical, timing,
and package specifications
DSP56002/D
MOTOROLA
DSP56002/D, Rev. 3
v
Product Documentation
vi
DSP56002/D, Rev. 3
MOTOROLA
SECTION
1
SIGNAL/PIN DESCRIPTIONS
INTRODUCTION
DSP56002 signals are organized into twelve functional groups, as summarized in
Table 1-1.
Table 1-1 Signal Functional Group Allocations
Number
of
Signals
Detailed
Description
Power (VCCX)
16
Table 1-2
Ground (GNDX)
24
Table 1-3
PLL and Clock
7
Table 1-4
Address Bus
16
Table 1-5
24
Table 1-6
Bus Control
10
Table 1-7
Interrupt and Mode Control
4
Table 1-8
15
Table 1-9
3
Table 1-10
Synchronous Serial Interface (SSI) Port
6
Table 1-11
Timer/Event Counter or General Purpose Input/Output (GPIO)
1
Table 1-12
On-Chip Emulation (OnCE) Port
4
Table 1-13
Functional Group
Port A1
Data Bus
Port B2
Host Interface (HI) Port
Serial Communications Interface (SCI) Port
Note:
1.
2.
3.
Port C3
Port A signals define the External Memory Interface port.
Port B signals are the HI signals multiplexed on the external pins with the GPIO signals.
Port C signals are the SCI and SSI signals multiplexed on the external pins with the GPIO signals.
Figure 1-1 is a diagram of DSP56002 signals by functional group.
MOTOROLA
DSP56002/D, Rev. 3
1-1
Signal/Pin Descriptions
Introduction
DSP56002
VCCP
VCCCK
VCCQ
VCCA
VCCD
VCCC
VCCH
VCCS
GNDP
GNDCK
GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
4
3
3
2
4
5
6
4
2
EXTAL
XTAL
CKOUT
CKP
PCAP
PINIT
PLOCK
A0–A15
D0–D23
PS
DS
X/Y
BS
BR
BG
BN
WT
RD
WR
Note:
Power Inputs:
PLL
Clock Output
Internal Logic
Address Bus
Data Bus
Bus Control
HI
SSI/SCI
Grounds:
PLL
Clock
Internal Logic
Address Bus
Data Bus
Bus Control
HI
SSI/SCI
Interrupt
Port B
Host
Interface
(HI) Port1
H0–H7
HA0–HA2
HR/W
HEN
HREQ
HACK
PB0–PB7
PB8–PB10
PB11
PB12
PB13
PB14
Port C
Synchronous
Serial
Interface (SSI)
Port2
24
8
3
Serial
Communications
Interface (SCI)
Port2
PLL and
Clock
16
MODA
MODB
MODC
RESET
Interrupt/
Mode
Control
IRQA
IRQB
NMI
3
RXD
TXD
SCLK
PC0
PC1
PC2
SC0–SC2
SCK
SRD
STD
PC3–PC5
PC6
PC7
PC8
External
Address Bus
External
Data Bus
External
Bus
Control
Timer/
Event Counter
TIO
Status
OnCE
Port
DSCK
DSI
DSO
DR
OS1
OS0
1. The Host Interface port signals are multiplexed with the Port B GPIO signals (PB0–PB15).
2. The SCI and SSI signals are multiplexed with the Port C GPIO signals (PC0–PC8).
3. Power and Ground lines are indicated for the 144-pin TQFP package.
AA1081G
Figure 1-1 Signals Identified by Functional Group
1-2
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
Power
POWER
Table 1-2 Power
Power Names
Description
VCCP
Analog PLL Circuit Power—This line is dedicated to the analog PLL circuits
and must remain noise-free to ensure stable PLL frequency and performance.
Ensure that the input voltage to this line is well-regulated and uses an extremely
low impedance path to tie to the VCC power rail. Use a 0.1 µF capacitor and a
0.01 µF capacitor located as close as possible to the chip package to connect
between the VCCP line and the GNDP line.
VCCCK
Clock Output Power—This line supplies a quiet power source for the CKOUT
output. Ensure that the input voltage to this line is well-regulated and uses an
extremely low impedance path to tie to the VCC power rail. Use a 0.1 µF bypass
capacitor located as close as possible to the chip package to connect between the
VCCCK line and the GNDCK line.
VCCQ (4)
Oscillator Power—These lines supply a quiet power source to the oscillator
circuits and the mode control and interrupt lines. Ensure that the input voltage
to this line is well-regulated and uses an extremely low impedance path to tie to
the VCC power rail. Use a 0.1 µF bypass capacitor located as close as possible to
the chip package to connect between the VCCQ lines and the GNDQ lines.
VCCA (3)
Address Bus Power—These lines supply power to the address bus.
VCCD (3)
Data Bus Power—These lines supply power to the data bus.
VCCC
Bus Control Power—This line supplies power to the bus control logic.
VCCH (2)
Host Interface Power—These lines supply power to the Host Interface logic.
VCCS
Serial Interface Power—This line supplies power to the serial interface logic
(SCI and SSI).
MOTOROLA
DSP56002/D, Rev. 3
1-3
Signal/Pin Descriptions
Ground
GROUND
Table 1-3 Ground
Ground Names
Description
GNDP
Analog PLL Circuit Ground—This line supplies a dedicated quiet ground
connection for the analog PLL circuits and must remain relatively noise-free to
ensure stable PLL frequency and performance. Ensure that this line connects
through an extremely low impedance path to ground. Use a 0.1 µF capacitor and
a 0.01 µF capacitor located as close as possible to the chip package to connect
between the VCCP line and the GNDP line.
GNDCK
Clock Output Ground—This line supplies a quiet ground connection for the
CKOUT output. Ensure that this line connects through an extremely low
impedance path to ground. Use a 0.1 µF bypass capacitor located as close as
possible to the chip package to connect between the VCCCK line and the GNDCK
line.
GNDQ (4)
Oscillator Ground—These lines supply a quiet ground connection for the
oscillator circuits and the mode control and interrupt lines. Ensure that this line
connects through an extremely low impedance path to ground. Use a 0.1 µF
bypass capacitor located as close as possible to the chip package to connect
between the VCCQ line and the GNDQ line.
GNDA (5)
Address Bus Ground—These lines connect system ground to the address bus.
GNDD (6)
Data Bus Ground—These lines connect system ground to the data bus.
GNDC
Bus Control Ground—This line connects ground to the bus control logic.
GNDΗ (4)
Host Interface Ground—These lines supply ground connections for the Host
Interface logic.
GNDS (2)
Serial Interface Ground—These lines supply ground connections for the serial
interface logic (SCI and SSI).
1-4
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
PLL and Clock
PLL AND CLOCK
Table 1-4 PLL and Clock Signals
Signal
Type
State
during
Reset
Input
Input
External Clock/Crystal Input—This input connects the internal
oscillator input to an external crystal or to an external oscillator.
XTAL
Output
Chipdriven
Crystal Output—This output connects the internal crystal oscillator
output to an external crystal. If an external oscillator is used, XTAL
should be left unconnected.
CKOUT
Output
Chipdriven
PLL Output Clock—When the PLL is enabled and locked, this
signal provides a 50% duty cycle output clock signal synchronized
to the internal processor clock.
Signal
Name
EXTAL
Signal Description
When the PLL is enabled and the Multiplication Factor is less than
or equal to 4, then CKOUT is synchronized to EXTAL.
When the PLL is disabled, the output clock at CKOUT is derived
from, and has the same frequency and duty cycle as, EXTAL.
Note:
CKP
PCAP
For information about using the PLL Multiplication Factor,
see the DSP56002 User’s Manual.
Input
Input
PLL Output Clock Polarity Control—The value of this signal at
reset defines the polarity of the CKOUT output relative to EXTAL. If
CKP is pulled low by connecting through a resistor to ground,
CKOUT and EXTAL have the same polarity. Pulling CKP high by
connecting it through a resistor to VCC causes CKOUT and EXTAL
to be inverse polarities. The polarity of CKOUT is latched at the end
of reset; therefore, any changes to CKP after deassertion of RESET
do not affect CKOUT polarity.
Input/
Output
Indeterminate
PLL Capacitor—This signal is used to connect the required external
filter capacitor to the PLL filter. Connect one end of the capacitor to
PCAP and the other to VCCP. The value of the capacitor is specified
in Section 2 of this data sheet.
MOTOROLA
DSP56002/D, Rev. 3
1-5
Signal/Pin Descriptions
PLL and Clock
Table 1-4 PLL and Clock Signals (Continued)
Signal
Name
PINIT
Signal
Type
State
during
Reset
Input
Input
Signal Description
PLL Initialization Source—The value of this signal at reset defines
the value written into the PLL Enable (PEN) bit in the PLL control
register.
If PINIT is pulled high during reset, the PEN bit is written as a 1,
enabling the PLL and causing the DSP internal clocks to be derived
from the PLL VCO.
If PINIT is pulled low during reset, the PEN bit is written as a 0,
disabling the PLL and causing DSP internal clocks to be derived
from the clock connected to EXTAL.
PEN is written only at the deassertion of RESET and; therefore, the
value of PINIT is ignored after that time.
PLOCK
Output
Indeterminate
Phase and Frequency Lock—This output is generated by an
internal Phase Detector circuit. This circuit drives the output high
when:
• the PLL is disabled (the output clock is EXTAL and is
therefore in phase with itself), or
• the PLL is enabled and is locked onto the proper phase
(based on the CKP value) and frequency of EXTAL.
The circuit drives the output low (deasserted) whenever the PLL is
enabled, but has not locked onto the proper phase and frequency.
Note:
1-6
PLOCK is a reliable indicator of the PLL lock state only after
the chip has exited the Reset state. During hardware reset,
the PLOCK state is determined by PINIT and the current
PLL lock condition.
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
Address Bus
ADDRESS BUS
Table 1-5 Address Bus Signals
Signal
Names
Signal
Type
A0–A15
Output
State
during
Reset
Signal Description
Tri-stated Address Bus—These signals specify the address for external
program and data memory accesses. If there is no external bus
activity, A0–A15 remain at their previous values to reduce
power consumption. A0–A15 are tri-stated when the bus grant
signal is asserted.
DATA BUS
Table 1-6 Data Bus Signals
Signal
Names
D0–D23
MOTOROLA
Signal
Type
Input/
Output
State
during
Reset
Signal Description
Tri-stated Data Bus—These signals provide the bidirectional data bus for
external program and data memory accesses. D0–D23 are tristated when the BG or RESET signal is asserted.
DSP56002/D, Rev. 3
1-7
Signal/Pin Descriptions
Bus Control
BUS CONTROL
Table 1-7 Bus Control Signals
State
during
Reset
Signal
Name
Signal
Type
PS
Output Tri-stated
Program Memory Select—PS is asserted low for external program
memory access. PS is tri-stated when the BG or RESET signal is
asserted.
DS
Output Tri-stated
Data Memory Select—DS is asserted low for external data memory
access. DS is tri-stated when the BG or RESET signal is asserted.
X/Y
Output Tri-stated
X/Y External Memory Select—This output is driven low during
external Y data memory accesses. It is also driven low during external
exception vector fetches when operating in the Development mode.
X/Y is tri-stated when the BG or RESET signal is asserted.
BS
Output Pulled
high
Bus Select—BS is asserted when the DSP accesses the external bus,
and it acts as an early indication of imminent external bus access by
the DSP56002. It may also be used with the bus wait input WT to
generate wait states. BS is pulled high when the BG or RESET signal is
asserted.
BR
Input
Input
Signal Description
Bus Request—When the Bus Request input (BR) is asserted, it allows
an external device, such as another processor or DMA controller, to
become the master of the external address and data buses. While the
bus is released, the DSP may continue internal operations using
internal memory spaces. When BR is deasserted, the DSP56002 is the
bus master.When BR is asserted, the DSP56002 will release Port A,
including A0–A15, D0–D23, and the bus control signals (PS, DS, X/Y,
RD, WR, and BS) by placing them in the high-impedance state after
execution of the current instruction has been completed.
Note:
BG
1-8
Output Pulled
high
To prevent erroneous operation, pull up the BR signal when it
is not in use.
Bus Grant—When this output is asserted, it grants an external
device’s request for access to the external bus. This output is
deasserted during hardware reset.
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
Bus Control
Table 1-7 Bus Control Signals (Continued)
State
during
Reset
Signal
Name
Signal
Type
BN
Output Pulled
low
Signal Description
Bus Not Required—The BN signal is asserted whenever the chip
requires mastership of the external bus. During instruction cycles
where the external bus is not required, BN is deasserted. If the BN
signal is asserted when the DSP is not the bus master, processing has
stopped and the chip is waiting to acquire bus ownership. An external
arbiter may use this signal to help determine when to return bus
ownership to the DSP.
Note:
WT
Input
Input
The BN signal cannot be used as an early indication of
imminent external bus access because it is valid later than the
other bus control signals BS and WT.
Bus Wait—An external device may insert wait states by asserting WT
during external bus cycles.
Note:
To prevent erroneous operation, pull up the WT signal when
it is not in use.
WR
Output Tri-stated
Write Enable—WR is asserted low during external memory write
cycles. WR is tri-stated when the BG or RESET signal is asserted.
RD
Output Tri-stated
Read Enable—RD is asserted low during external memory read
cycles. RD is tri-stated when the BG or RESET signal is asserted.
MOTOROLA
DSP56002/D, Rev. 3
1-9
Signal/Pin Descriptions
Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
Table 1-8 Interrupt and Mode Control Signals
Signal Name
Signal
Type
MODA/IRQA
Input
State
during
Reset
Input
Signal Description
Mode Select A/External Interrupt Request A—This input has
two functions:
1. to select the initial chip operating mode, and
2.
after synchronization, to allow an external device to
request a DSP interrupt.
MODA is read and internally latched in the DSP when the
processor exits the Reset state. MODA, MODB, and MODC
select the initial chip operating mode. Several clock cycles
(depending on PLL stabilization time) after leaving the Reset
state, the MODA signal changes to external interrupt request
IRQA. The chip operating mode can be changed by software
after reset. The IRQA input is a synchronized external
interrupt request that indicates that an external device is
requesting service. It may be programmed to be level-sensitive
or negative-edge-sensitive. If level-sensitive triggering is
selected, an external pull up resistor is required for wired-OR
operation. If the processor is in the Stop state and IRQA is
asserted, the processor will exit the Stop state.
MODB/IRQB
Input
Input
Mode Select B/External Interrupt Request B—This input has
two functions:
1. to select the initial chip operating mode, and
2.
after internal synchronization, to allow an external
device to request a DSP interrupt.
MODB is read and internally latched in the DSP when the
processor exits the Reset state. MODA, MODB, and MODC
select the initial chip operating mode. Several clock cycles
(depending on PLL stabilization time) after leaving the Reset
state, the MODB signal changes to external interrupt request
IRQB. After reset, the chip operating mode can be changed by
software. The IRQB input is an external interrupt request that
indicates that an external device is requesting service. It may
be programmed to be level-sensitive or negative-edgetriggered. If level-sensitive triggering is selected, an external
pull up resistor is required for wired-OR operation.
1-10
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
Interrupt and Mode Control
Table 1-8 Interrupt and Mode Control Signals (Continued)
Signal Name
MODC/NMI
Signal
Type
Input
State
during
Reset
Input
Signal Description
Mode Select C/Non-maskable Interrupt Request—This input
has two functions:
1. to select the initial chip operating mode, and
2.
after internal synchronization, to allow an external
device to request a non-maskable DSP interrupt.
MODC is read and internally latched in the DSP when the
processor exits the Reset state. MODA, MODB, and MODC
select the initial chip operating mode. Several clock cycles
(depending on PLL stabilization time) after leaving the Reset
state, the MODC signal changes to the nonmaskable external
interrupt request NMI. After reset, the chip operating mode
can be changed by software. The NMI input is an external
interrupt request that indicates that an external device is
requesting service. It may be programmed to be level-sensitive
or negative-edge-triggered. If level-sensitive triggering is
selected, an external pull up resistor is required for wired-OR
operation.
RESET
MOTOROLA
Input
Input
Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the DSP is initialized and placed
in the Reset state. A Schmitt trigger input is used for noise
immunity. When the RESET signal is deasserted, the initial
chip operating mode is latched from the MODA, MODB, and
MODC signals. The internal reset signal is deasserted
synchronous with the internal clocks. In addition, the PINIT
pin is sampled and written into the PEN bit of the PLL Control
Register and the CKP pin is sampled to determine the polarity
of the CKOUT signal.
DSP56002/D, Rev. 3
1-11
Signal/Pin Descriptions
Host Interface (HI) Port
HOST INTERFACE (HI) PORT
Table 1-9 HI Signals
Signal
Name
H0–H7
Signal
Type
State
during
Reset
Signal Description
Input Tri-stated Host Data Bus (H0–H7)—This data bus transfers data between
or
the host processor and the DSP56002.
Output
When configured as a Host Interface port, the H0–H7signals are
tri-stated as long as HEN is deasserted. The signals are inputs
unless HR/W is high and HEN is asserted, in which case H0–H7
become outputs, allowing the host processor to read the
DSP56002 data. H0–H7 become outputs when HACK is asserted
during HREQ assertion.
Port B GPIO 0–7 (PB0–PB7)—These signals are General Purpose
I/O signals (PB0–PB7) when the Host Interface is not selected.
PB0–PB7
After reset, the default state for these signals is GPIO input.
HA0–HA2
Input
PB8–PB10
Input
or
Output
Tri-stated Host Address 0—Host Address 2 (HA0–HA2)—These inputs
provide the address selection for each Host Interface register.
Port B GPIO 8–10 (PB8–PB10)—These signals are General
Purpose I/O signals (PB8–PB10) when the Host Interface is not
selected.
After reset, the default state for these signals is GPIO input.
HR/W
PB11
Input
Input
or
Output
Tri-stated Host Read/Write—This input selects the direction of data
transfer for each host processor access. If HR/W is high and HEN
is asserted, H0–H7 are outputs and DSP data is transferred to the
host processor. If HR/W is low and HEN is asserted, H0–H7 are
inputs and host data is transferred to the DSP. HR/W must be
stable when HEN is asserted.
Port B GPIO 11 (PB11)—This signal is a General Purpose I/O
signal called PB11 when the Host Interface is not being used.
After reset, the default state for this signal is GPIO input.
1-12
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
Host Interface (HI) Port
Table 1-9 HI Signals (Continued)
Signal
Name
Signal
Type
HEN
Input
PB12
Input
or
Output
State
during
Reset
Signal Description
Tri-stated Host Enable—This input enables a data transfer on the host data
bus. When HEN is asserted and HR/W is high, H0–H7 become
outputs and the host processor may read DSP56002/L002 data.
When HEN is asserted and HR/W is low, H0–H7 become
inputs. Host data is latched inside the DSP on the rising edge of
HEN. Normally, a chip select signal derived from host address
decoding and an enable strobe are used to generate HEN.
Port B GPIO 12 (PB12)—This signal is a General Purpose I/O
signal called PB12 when the Host Interface is not being used.
After reset, the default state for this signal is GPIO input.
HREQ
Open Tri-stated Host Request—This signal is used by the Host Interface to
drain
request service from the host processor, DMA controller, or a
Output
simple external controller.
Note:
PB13
Input
or
Output
HREQ should always be pulled high when it is not in
use.
Port B GPIO 13 (PB13)—This signal is a General Purpose (not
open-drain) I/O signal (PB13) when the Host Interface is not
selected.
After reset, the default state for this signal is GPIO input.
HACK
Input
Tri-stated Host Acknowledge—This input has two functions. It provides a
host acknowledge handshake signal for DMA transfers and it
receives a host interrupt acknowledge compatible with MC68000
family processors.
Note:
PB14
Input
or
Output
HACK should always be pulled high when it is not in
use.
Port B GPIO 14 (PB14)—This signal is a General Purpose I/O
signal (PB14) when the Host Interface is not selected.
After reset, the default state for this signal is GPIO input.
MOTOROLA
DSP56002/D, Rev. 3
1-13
Signal/Pin Descriptions
Serial Communications Interface Port
SERIAL COMMUNICATIONS INTERFACE PORT
Table 1-10 Serial Communications Interface (SCI+) Signals
Signal Name
Signal
Type
RXD
Input
PC0
Input
or
Output
State
during
Reset
Signal Description
Tri-stated Receive Data (RXD)—This input receives byte-oriented data and
transfers the data to the SCI receive shift register. Input data can be
sampled on either the positive edge or on the negative edge of the
receive clock, depending on how the SCI control register is
programmed.
Port C GPIO 0 (PC0)—This signal is a GPIO signal called PC0
when the SCI RXD function is not being used.
After reset, the default state is GPIO input.
TXD
Output Tri-stated Transmit Data (TXD)—This output transmits serial data from
the SCI transmit shift register. In the default configuration, the
data changes on the positive clock edge and is valid on the
negative clock edge. The user can reverse this clock polarity by
programming the SCI control register appropriately.
PC1
Input
or
Output
Port C GPIO 1 (PC1)—This signal is a GPIO signal called PC1
when the SCI TXD function is not being used.
After reset, the default state is GPIO input.
SCLK
PC2
Input Tri-stated SCI Clock (SCLK)—This signal provides an input or output
or
clock from which the receive or transmit baud rate is derived in
Output
the Asynchronous mode, and from which data is transferred in
the Synchronous mode. The direction and function of the signal
is defined by the RCM bit in the SCI+ Clock Control Register
(SCCR).
Port C GPIO 2 (PC2)—This signal is a GPIO signal called PC2
when the SCI SCLK function is not being used.
After reset, the default state is GPIO input.
1-14
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
Synchronous Serial Interface Port
SYNCHRONOUS SERIAL INTERFACE PORT
Table 1-11 Synchronous Serial Interface (SSI) Signals
Signal Name
SC0
Signal
Type
State
during
Reset
Input Trior
stated
Output
Signal Description
Serial Clock 0 (SC0)—This signal’s function is determined by
whether the SCLK is in Synchronous or Asynchronous mode.
•
•
PC3
In Synchronous mode, this signal is used as a serial I/O
flag.
In Asynchronous mode, this signal receives clock I/O.
Port C GPIO 3 (PC3)—This signal is a GPIO signal called PC3
when the SSI SC0 function is not being used.
After reset, the default state is GPIO input.
SC1
Input Trior
stated
Output
Serial Clock 1 (SC1)—The SSI uses this bidirectional signal to
control flag or frame synchronization. This signal’s function is
determined by whether the SCLK is in Synchronous or
Asynchronous mode.
•
•
In Asynchronous mode, this signal is frame sync I/O.
For Synchronous mode with continuous clock, this
signal is a serial I/O flag and operates like the SC0.
SC0 and SC1 are independent serial I/O flags but may be used
together for multiple serial device selection.
Port C GPIO 4 (PC4)—This signal is a GPIO signal called PC4
when the SSI SC1 function is not being used.
PC4
After reset, the default state is GPIO input.
SC2
PC5
Input Trior
stated
Output
Serial Clock 2 (SC2)—The SSI uses this bidirectional signal to
control frame synchronization only. As with SC0 and SC1, its
function is defined by the SSI operating mode.
Port C GPIO 5 (PC5)—This signal is a GPIO signal called PC5
when the SSI SC1 function is not being used.
After reset, the default state is GPIO input.
MOTOROLA
DSP56002/D, Rev. 3
1-15
Signal/Pin Descriptions
Synchronous Serial Interface Port
Table 1-11 Synchronous Serial Interface (SSI) Signals (Continued)
Signal Name
SCK
Signal
Type
State
during
Reset
Input Trior
stated
Output
Signal Description
SSI Serial Receive Clock—This bidirectional signal provides the
serial bit rate clock for the SSI when only one clock is being used.
Port C GPIO 6 (PC6)—This signal is a GPIO signal called PC6
when the SSI function is not being used.
PC6
After reset, the default state is GPIO input.
SRD
Input
PC7
Input
or
Output
Tristated
SSI Receive Data—This input signal receives serial data and
transfers the data to the SSI Receive Shift Register.
Port C GPIO 7 (PC7)—This signal is a GPIO signal called PC7
when the SSI SRD function is not being used.
After reset, the default state is GPIO input.
STD
Output Tristated
SSI Transmit Data (STD)—This output signal transmits serial
data from the SSI Transmitter Shift Register.
PC8
Input
or
Output
Port C GPIO 8 (PC8)—This signal is a GPIO signal called PC8
when the SSI STD function is not being used.
After reset, the default state is GPIO input.
1-16
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
Timers
TIMERS
Table 1-12 Timer Signals
Signal Name
TIO
Signal
Type
State
during
Reset
Input Trior
stated
Output
Signal Description
Timer Input/Output—The TIO signal provides an interface to the
timer/event counter module. When the module functions as an
external event counter or is used to measure external pulse width/
signal period, the TIO is an input. When the module functions as a
timer, the TIO is an output, and the signal on the TIO signal is
the timer pulse.
When not used by the timer module, the TIO can be
programmed through the Timer Control/Status Register
(TCSR) to be a General Purpose I/O signal.
TIO is effectively disconnected upon leaving reset.
MOTOROLA
DSP56002/D, Rev. 3
1-17
Signal/Pin Descriptions
On-Chip Emulation Port
On-CHIP EMULATION PORT
Table 1-13 On-Chip Emulation (OnCE) Signals
Signal Name
DSI/OS0
Signal
Type
Input
or
Output
State
during
Reset
Signal Description
Low
Debug Serial Input/Chip Status 0—Serial data or commands
Output are provided to the OnCE controller through the DSI/OS0 signal
when it is an input. The data received on the DSI signal will be
recognized only when the DSP has entered the Debug mode of
operation. Data is latched on the falling edge of the DSCK serial
clock. Data is always shifted into the OnCE serial port Most
Significant Bit (MSB) first. When the DSI/OS0 signal is an
output, it works in conjunction with the OS1 signal to provide
chip status information. The DSI/OS0 signal is an output when
the processor is not in Debug mode. When switching from
output to input, the signal is tri-stated.
Note:
DSCK/OS1
Input
or
Output
Connect an external pull-down resistor to this signal.
Low
Debug Serial Clock/Chip Status 1—The DSCK/OS1 signal
Output supplies the serial clock to the OnCE when it is an input. The
serial clock provides pulses required to shift data into and out of
the OnCE serial port. (Data is clocked into the OnCE on the
falling edge and is clocked out of the OnCE serial port on the
rising edge.) The debug serial clock frequency must be no
greater than 1/8 of the processor clock frequency. When
switching from input to output, the signal is tri-stated.
When it is an output, this signal works with the OS0 signal to
provide information about the chip status. The DSCK/OS1 signal
is an output when the chip is not in Debug mode.
Note:
1-18
Connect an external pull-down resistor to this signal.
DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions
On-Chip Emulation Port
Table 1-13 On-Chip Emulation (OnCE) Signals (Continued)
Signal Name
Signal
Type
DSO
Output
State
during
Reset
Pulled
high
Signal Description
Debug Serial Output—Data contained in one of the OnCE
controller registers is provided through the DSO output signal,
as specified by the last command received from the external
command controller. Data is always shifted out the OnCE serial
port Most Significant Bit (MSB) first. Data is clocked out of the
OnCE serial port on the rising edge of DSCK.
The DSO signal also provides acknowledge pulses to the
external command controller. When the chip enters the Debug
mode, the DSO signal will be pulsed low to indicate
(acknowledge) that the OnCE is waiting for commands. After
the OnCE receives a read command, the DSO signal will be
pulsed low to indicate that the requested data is available and
the OnCE serial port is ready to receive clocks in order to deliver
the data. After the OnCE receives a write command, the DSO
signal will be pulsed low to indicate that the OnCE serial port is
ready to receive the data to be written; after the data is written,
another acknowledge pulse will be provided.
Note:
DR
Input
Input
Debug Request—The debug request input (DR) allows the user
to enter the Debug mode of operation from the external
command controller. When DR is asserted, it causes the DSP to
finish the current instruction being executed, save the instruction
pipeline information, enter the Debug mode, and wait for
commands to be entered from the DSI line. While in Debug
mode, the DR signal lets the user reset the OnCE controller by
asserting it and deasserting it after receiving acknowledge. It
may be necessary to reset the OnCE controller in cases where
synchronization between the OnCE controller and external
circuitry is lost. DR must be deasserted after the OnCE responds
with an acknowledge on the DSO signal and before sending the
first OnCE command. Asserting DR will cause the chip to exit
the Stop or Wait state. Having DR asserted during the
deassertion of RESET will cause the DSP to enter Debug mode.
Note:
MOTOROLA
Connect an external pull-up resistor to this signal.
Connect an external pull-up resistor to this signal.
DSP56002/D, Rev. 3
1-19
Signal/Pin Descriptions
On-Chip Emulation Port
1-20
DSP56002/D, Rev. 3
MOTOROLA
SECTION
2
SPECIFICATIONS
GENERAL CHARACTERISTICS
The DSP56002 is fabricated in high-density HCMOS with TTL compatible inputs and
outputs.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GND or VCC).
Note: In the calculation of timing requirements, adding a maximum value of one
specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum
specification is calculated using the worst case for the same parameters in the
opposite direction. Therefore, a “maximum” value for a specification will
never occur in the same device that has a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that
can never exist.
MOTOROLA
DSP56002/D, Rev. 3
2-1
Specifications
Thermal characteristics
Table 2-1 Absolute Maximum Ratings (GND = 0 V)
Rating
Symbol
Value
Unit
Supply Voltage
VCC
–0.3 to +7.0
V
All Input Voltages
VIN
(GND – 0.5) to (VCC + 0.5)
V
Current Drain per Pin excluding VCC and GND
I
10
mA
Operating Temperature Range
TJ
–40 to +105
°C
Tstg
–55 to +150
°C
Storage Temperature
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
Symbol
PQFP
Value3
TQFP
Value3
TQFP
Value4
PGA
Value3
Unit
Junction-to-ambient
thermal resistance1
RθJA or θJA
50
48
40.6
22
˚C/W
Junction-to-case
thermal resistance2
RθJC or θJC
12.4
10.8
—
6.5
˚C/W
ΨJT
4.0
0.16
—
N/A
˚C/W
Characteristic
Thermal
characterization
parameter
Notes:
1.
2.
3.
4.
2-2
Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided
Printed Circuit Board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and
Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111)
Measurements were made with the parts installed on thermal test boards meeting the specification
EIA/JEDECSI-3.
Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88,
with the exception that the cold plate temperature is used for the case temperature.
These are measured values. See note 1 for test board conditions.
These are measured values; testing is not complete. Values were measured on a non-standard fourlayer thermal test board (two internal planes) at one watt in a horizontal configuration.
DSP56002/D, Rev. 3
MOTOROLA
Specifications
DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
Characteristics
Supply Voltage
Input High Voltage
•EXTAL
•RESET
• MODA, MODB, MODC
• All other inputs
Input Low Voltage
• EXTAL
• MODA, MODB, MODC
• All other inputs
Input Leakage Current
EXTAL, RESET, MODA/IRQA, MODB/IRQB,
MODC/NMI, DR, BR, WT, CKP, PINIT, MCBG,
MCBCLR, MCCLK, D20IN
Tri-state (Off–state) Input Current (@ 2.4 V/0.4 V)
Output High Voltage (IOH = –0.4 mA)
Output Low Voltage (IOL = 3.0 mA)
HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA
Internal Supply Current at 40 MHz1
• In Wait mode2
• In Stop mode2
Internal Supply Current at 66 MHz1
• In Wait mode2
• In Stop mode2
Internal Supply Current at 80 MHz1
• In Wait mode2
• In Stop mode2
PLL Supply Current3
• 40 MHz
• 66 MHz
• 80 MHz
CKOUT Supply Current4
• 40 MHz
• 66 MHz
• 80 MHz
Input Capacitance5
Notes:
1.
2.
3.
4.
5.
Symbol
Min
Typ
Max
Units
VCC
4.5
5.0
5.5
V
VIHC
VIHR
VIHM
VIH
4.0
2.5
3.5
2.0
—
—
—
—
VCC
VCC
VCC
VCC
V
V
V
V
VILC
VILM
VIL
IIN
–0.5
–0.5
–0.5
–1
—
—
—
—
0.6
2.0
0.8
1
V
V
V
µA
ITSI
VOH
VOL
–10
2.4
—
—
—
—
10
—
0.4
µA
V
V
ICCI
ICCW
ICCS
ICCI
ICCW
ICCS
ICCI
ICCW
ICCS
—
—
—
—
—
—
—
—
—
90
12
2
95
15
2
115
18
2
105
20
95
130
25
95
160
30
95
mA
mA
µA
mA
mA
µA
mA
mA
µA
—
—
—
1.0
1.1
1.2
1.5
1.5
1.8
mA
mA
mA
—
—
—
—
14
28
34
10
20
35
42
—
mA
mA
mA
pF
CIN
Section 4 Design Considerations describes how to calculate the external supply current.
In order to obtain these results all inputs must be terminated (i.e., not allowed to float).
Values are given for PLL enabled.
Values are given for CKOUT enabled.
Periodically sampled and not 100% tested
MOTOROLA
DSP56002/D, Rev. 3
2-3
Specifications
AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
The timing waveforms in the AC Electrical Characteristics are tested with a VIL
maximum of 0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET,
MODA, MODB, and MODC. These pins are tested using the input levels set forth in
the DC Electrical Characteristics. AC timing specifications that are referenced to a
device input signal are measured in production with respect to the 50% point of the
respective input signal’s transition. DSP56002 output levels are measured with the
production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V,
respectively.
Pulse Width
Low
VIH
Input
Signal
90%
50%
10%
Midpoint1
VIL
Fall Time
Note:
High
Rise Time
The midpoint is VIL + (VIH – VIL)/2.
AA0179
Figure 2-1 Signal Measurement Reference
2-4
DSP56002/D, Rev. 3
MOTOROLA
Specifications
Internal Clocks
INTERNAL CLOCKS
For each occurrence of TH, TL, TC or ICYC, substitute with the numbers in Table 2-4.
DF and MF are PLL division and multiplication factors set in registers.
Table 2-4 Internal Clocks
Characteristics
Symbol
Internal Operation Frequency
f
Internal Clock High Period
• With PLL disabled
• With PLL enabled and MF ≤ 4
TH
• With PLL enabled and MF > 4
Internal Clock Low Period
• With PLL disabled
• With PLL enabled and MF ≤ 4
TL
• With PLL enabled and MF > 4
Internal Clock Cycle Time
Instruction Cycle Time
MOTOROLA
DSP56002/D, Rev. 3
Expression
ETH
(Min) 0.48 × TC
(Max) 0.52 × TC
(Min) 0.467 × TC
(Max) 0.533 × TC
ETL
(Min) 0.48 × TC
(Max) 0.52 × TC
(Min) 0.467 × TC
(Max) 0.533 × TC
TC
ETC × DF/MF
ICYC
2 × TC
2-5
Specifications
External Clock (EXTAL Pin)
EXTERNAL CLOCK (EXTAL PIN)
The DSP56002 system clock may be derived from the on-chip crystal oscillator as
shown in Figure 2-2, or it may be externally supplied. An externally supplied square
wave voltage source should be connected to EXTAL, leaving XTAL physically
unconnected to the board or socket. The rise and fall times of this external clock
should be 4 ns maximum.
EXTAL
XTAL EXTAL
R
XTAL
R1
R2
C1
XTAL1
C
C
C2
Fundamental Frequency
Crystal Oscillator
1. The suggested crystal source is
ICM, # 433163 - 4.00
(4 MHz fundamental, 20 pf load) or
# 436163 - 30.00
(30 MHz fundamental, 20 pf load).
2. To reduce system cost, a ceramic
resonator may be used instead of
the crystal. Suggested source:
Murata-Erie #CST4.00MGW040
(4 MHz with built-in load
capacitors)
C3
3rd Overtone
Crystal Oscillator
Suggested Component Values
R = 680 kΩ ± 10%
C = 20 pf ± 20%
Note:
XTAL1*
L1
Suggested Component Values
R1 = 470 kΩ ± 10%
R2 = 330 Ω ± 10%
C1 = 0.1 µf ± 20%
C2 = 26 pf ± 20%
C3 = 20 pf ± 10%
L1 = 2.37 µH ± 10%
XTAL = 40 MHz, AT cut, 20 pf load,
50 Ω max series resistance
Note:
1. *3rd overtone crystal.
2. The suggested crystal source is ICM,
# 471163 - 40.00 (40 MHz 3rd overtone,
20 pf load).
3. R2 limits crystal current.
4. Reference Benjamin Parzen, The Design
of Crystal and Other Harmonic
Oscillators, John Wiley & Sons, 1983.
AA0211
Figure 2-2 Crystal Oscillator Circuits
2-6
DSP56002/D, Rev. 3
MOTOROLA
Specifications
External Clock (EXTAL Pin)
VIHC
Midpoint
VILC
EXTAL
ETH
ETL
1
2
3
ETC
4
NOTE: The midpoint is VILC + 0.5 (VIHC – VILC).
AA0360
Figure 2-3 External Clock Timing
Table 2-5 Clock Operation
40 MHz
Num
Characteristics
Frequency of Operation
(EXTAL Pin)
1
2
3
4
Note:
Clock Input High
• With PLL disabled
(46.7% – 53.3% duty cycle)
• With PLL enabled
(42.5% – 57.5% duty cycle)
66 MHz
80 MHz
Symbol
Ef
ETH
Unit
Min
Max
Min
Max
Min
Max
0
40
0
66
0
80
11.7
∞
7.09
∞
5.8
∞
5.3
235.5 µs
5.8
∞
5.3
235.5 µs
10.5 235.5 µs 6.36 235.5 µs
MHz
ns
Clock Input Low
• With PLL disabled
(46.7% – 53.3% duty cycle)
• With PLL enabled
(42.5% – 57.5% duty cycle)
ETL
Clock Cycle Time
• With PLL disabled
• With PLL enabled
ETC
25
25
∞
15.15
∞
12.5
∞
409.6 µs 15.15 409.6 µs 12.5 409.6 µs
ns
ICYC
50
50
∞
30.3
∞
819.2 µs 30.3 819.2 µs
ns
Instruction Cycle Time =
ICYC = 2TC
• With PLL disabled
• With PLL enabled
11.7
∞
7.09
∞
10.5 235.5 µs 6.36 235.5 µs
25
25
∞
819.2 µs
ns
External Clock Input High and External Clock Input Low are measured at 50% of the input
transition.
MOTOROLA
DSP56002/D, Rev. 3
2-7
Specifications
Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 2-6 Phase Lock Loop (PLL) Characteristics
Characteristics
VCO frequency when PLL
enabled1,2,3
PLL external capacitor4
(PCAP pin to VCCP)
Notes:
1.
2.
3.
4.
Expression
Min
Max
Unit
MF × Ef
10
f
MHz
MF × Cpcap
@ MF ≤ 4
@ MF > 4
MF × 340
MF × 380
MF × 480
MF × 970
pF
pF
The E in ETH, ETL, and ETC means external.
MF is the PCTL Multiplication Factor bits (MF0–MF11).
The maximum VCO frequency is limited to the internal operation frequency.
Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF = 1.
The recommended value for Cpcap is: 400 pF for MF ≤ 4 and 540 pF for MF > 4.
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
CL = 50 pF + 2 TTL loads
WS = number of Wait States (0–15) programmed into the external bus access using BCR
1 Wait State = TC
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies)
Num
9
10
11
12
13
Characteristics
Min
Max
Unit
—
26
ns
75000TC
25TC
2500TC
—
—
—
ns
ns
ns
Delay from Asynchronous RESET Deassertion to First
External Address Output (Internal Reset Deassertion)
8TC
9TC + 20
ns
Synchronous Reset Setup Time from RESET Deassertion to
first CKOUT transition
8.5
TC
ns
Synchronous Reset Delay Time from the first CKOUT
transition to the First External Address Output
8TC
8TC + 6
ns
Delay from RESET Assertion to Address High Impedance
(periodically sampled and not 100% tested).
Minimum Stabilization Duration
• Internal Oscillator PLL Disabled1
• External clock PLL Disabled2
• External clock PLL Enabled2
14
Mode Select Setup Time
21
—
ns
15
Mode Select Hold Time
0
—
ns
16
Minimum Edge-Triggered Interrupt Request Assertion
Width
13
—
ns
2-8
DSP56002/D, Rev. 3
MOTOROLA
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)
Num
Characteristics
Min
Max
Unit
13
—
ns
Delay from IRQA, IRQB, NMI Assertion to External Memory
Access Address Out Valid
• Caused by First Interrupt Instruction Fetch
• Caused by First Interrupt Instruction Execution
5TC + TH
9TC + TH
—
—
ns
ns
Delay from IRQA, IRQB, NMI Assertion to General Purpose
Transfer Output Valid caused by First Interrupt Instruction
Execution
11TC + TH
—
ns
—
2 TC + TL +
(TC × WS) – 23
ns
—
2TC +
(TC × WS) – 21
ns
16a Minimum Edge-Triggered Interrupt Request Deassertion
Width
17
18
19
Delay from Address Output Valid caused by First Interrupt
Instruction Execute to Interrupt Request
Deassertion for Level Sensitive Fast Interrupts3
20
Delay from RD Assertion to Interrupt Request
Deassertion for Level Sensitive Fast Interrupts3
21
Delay from WR Assertion to Interrupt Request Deassertion
for Level Sensitive Fast Interrupts3
• WS = 0
• WS > 0
—
—
2TC – 21
TC + TL +
(TC × WS) – 21
ns
ns
Delay from General-Purpose Output Valid to Interrupt
Request Deassertion for Level Sensitive Fast Interrupts3
—If Second Interrupt Instruction is:
• Single Cycle
• Two Cycles
—
—
TL – 31
2TC + TL – 31
ns
ns
Synchronous Interrupt Setup Time from IRQA, IRQB, NMI
Assertion to the second CKOUT transition
10
TC
ns
Synchronous Interrupt Delay Time from the second CKOUT
transition to the First External Address Output Valid caused
by the First Instruction Fetch after coming out of Wait State
13TC + TH
13TC + TH + 6
ns
22
23
24
25
Duration for IRQA Assertion to Recover from Stop State
12
—
ns
26
Delay from IRQA Assertion to Fetch of First Interrupt
Instruction (when exiting ‘Stop’)1
• Internal Crystal Oscillator Clock, OMR bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
65548TC
20TC
13TC
—
—
—
ns
ns
ns
Duration of Level Sensitive IRQA Assertion to ensure
interrupt service (when exiting ‘Stop’)1
• Internal Crystal Oscillator Clock, OMR bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17 = 1
65534TC + TL
6TC + TL
12
—
—
—
ns
ns
ns
27
MOTOROLA
DSP56002/D, Rev. 3
2-9
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)
Num
28
Characteristics
Delay from Level Sensitive IRQA Assertion to Fetch of First
Interrupt Instruction (when exiting ‘Stop’) 1
• Internal Crystal Oscillator Clock, OMR bit 6 = 0
• Stable External Clock, OMR bit 6 = 1
• Stable External Clock, PCTL bit 17= 1
Notes:
1.
2.
3.
Min
Max
Unit
65548TC
20TC
13TC
—
—
—
ns
ns
ns
A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:
• after power-on reset, and
• when recovering from Stop mode.
During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period
varies, a delay of 75,000 × TC is typically allowed to assure that the oscillator is stable before executing
programs.
Circuit stabilization delay is required during reset when using an external clock in two cases:
• after power-on reset, and
• when recovering from Stop mode.
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through
22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edgetriggered mode is recommended when using fast interrupt. Long interrupts are recommended when
using Level-sensitive mode.
VIHR
RESET
10
11
9
A0–A15
First Fetch
AA0356
Figure 2-4 Reset Timing
CKOUT
12
RESET
13
A0-A15,
DS, PS
X/Y
AA0357
Figure 2-5 Synchronous Reset Timing
2-10
DSP56002/D, Rev. 3
MOTOROLA
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
VIHR
RESET
14
15
VIHM
MODA, MODB
MODC
VILM
VIH
VIL
IRQA, IRQB,
NMI
AA0358
Figure 2-6 Operating Mode Select Timing
First Interrupt Instruction Execution/Fetch
A0–A15
RD
20
WR
21
IRQA
IRQB
NMI
17
19
a) First Interrupt Instruction Execution
General
Purpose
I/O
18
22
IRQA
IRQB
NMI
b) General Purpose I/O
AA0359
Figure 2-7 External Level-Sensitive Fast Interrupt Timing
MOTOROLA
DSP56002/D, Rev. 3
2-11
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
IRQA, IRQB
NMI
16
IRQA, IRQB
NMI
16A
AA0361
Figure 2-8 External Interrupt Timing (Negative Edge-Triggered)
T0, T2
CKOUT
T1, T3
23
IRQA, IRQB
NMI
24
A0–A15,
DS, PS
X/Y
AA0362
Figure 2-9 Synchronous Interrupt from Wait State Timing
25
IRQA
26
A0–A15,
DS, PS
X/Y
First Instruction Fetch
AA0363
Figure 2-10 Recovery from Stop State Using IRQA
27
IRQA
28
A0–A15,
DS, PS
X/Y
First IRQA Interrupt
Instruction Fetch
AA0364
Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service
2-12
DSP56002/D, Rev. 3
MOTOROLA
Specifications
Host I/O (HI) Timing
HOST I/O (HI) TIMING
CL = 50 pF + 2 TTL loads
Note: Active low lines should be “pulled up” in a manner consistent with the ac and
dc specifications.
Table 2-8 Host I/O Timing (All Frequencies)
Num
Min
Max
Unit
HEN/HACK Assertion Width1
• CVR, ICR, ISR, RXL Read
• IVR, RXH/M Read
• Write
TC + 31
26
13
—
—
—
ns
32
HEN/HACK Deassertion Width1
• Between Two TXL Writes2
• Between Two CVR, ICR, ISR, RXL Reads3
13
2TC + 31
2TC + 31
—
—
—
ns
ns
ns
33
Host Data Input Setup Time Before HEN/HACK
Deassertion
4
—
ns
34
Host Data Input Hold Time After HEN/HACK
Deassertion
3
—
ns
35
HEN/HACK Assertion to Output Data
Active from High Impedance
0
—
ns
36
HEN/HACK Assertion to Output Data Valid
—
26
ns
37
HEN/HACK Deassertion to Output Data High
Impedance5
—
18
ns
38
Output Data Hold Time After HEN/HACK
Deassertion6
2.5
—
ns
39
HR/W Low Setup Time Before HEN Assertion
0
—
ns
40
HR/W Low Hold Time After HEN Deassertion
3
—
ns
41
HR/W High Setup Time to HEN Assertion
0
—
ns
42
HR/W High Hold Time After HEN/HACK
Deassertion
3
—
ns
43
HA0–HA2 Setup Time Before HEN Assertion
0
—
ns
44
HA0–HA2 Hold Time After HEN Deassertion
3
—
ns
45
DMA HACK Assertion to HREQ Deassertion4
3
45
ns
46
DMA HACK Deassertion to HREQ Assertion4,5
• For DMA RXL Read
• For DMA TXL Write
• All other cases
TL + TC + TH
TL + TC
0
—
—
—
ns
ns
ns
31
Characteristics
MOTOROLA
DSP56002/D, Rev. 3
2-13
Specifications
Host I/O (HI) Timing
Table 2-8 Host I/O Timing (Continued)(All Frequencies) (Continued)
Num
Characteristics
Min
Max
Unit
47
Delay from HEN Deassertion to HREQ
Assertion for RXL Read4,5
TL + TC + TH
—
ns
48
Delay from HEN Deassertion to HREQ
Assertion for TXL Write4,5
TL + TC
—
ns
49
Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write 4,5
3
58
ns
Notes:
1.
2.
3.
4.
5.
6.
See Host Port Considerations in Section 4.
This timing must be adhered to only if two consecutive writes to the TXL are executed without polling
TXDE or HREQ.
This timing must be adhered to only if two consecutive reads from one of these registers are executed
without polling the corresponding status bits or HREQ
HREQ is pulled up by a 1 kΩ resistor.
Specifications are periodically sampled and not 100% tested.
May decrease to 0 ns for future versions.
HREQ
(Output)
31
32
HACK
(Input)
41
42
HR/W
(Input)
36
35
H0–H7
(Output)
37
38
Data Valid
AA1084
Figure 2-12 Host Interrupt Vector Register (IVR) Read
2-14
DSP56002/D, Rev. 3
MOTOROLA
Specifications
Host I/O (HI) Timing
HREQ
(Output)
49
RXH
Read
HEN
(Input)
47
RXM
Read
RXL
Read
32
31
43
44
HA2–HA0
(Input)
Address Valid
Address Valid
Address Valid
41
42
HR/W
(Input)
36
37
35
38
H0–H7
(Output)
Data
Valid
Data
Valid
Data
Valid
AA1113
Figure 2-13 Host Read Cycle (Non-DMA Mode)
HREQ
(Output)
49
TXH
Write
HEN
(Input)
TXM
Write
TXL
Write
32
31
43
HA2–HA0
(Input)
48
44
Address Valid
39
Address Valid
Address Valid
40
HR/W
(Input)
34
33
H0–H7
(Output)
Data
Valid
Data
Valid
Data
Valid
AA1114
Figure 2-14 Host Write Cycle (Non-DMA Mode)
MOTOROLA
DSP56002/D, Rev. 3
2-15
Specifications
Host I/O (HI) Timing
HREQ
(Output)
45
46
31
32
46
RXH
Read
HACK
(Input)
RXM
Read
36
46
RXL
Read
37
35
38
Data
Valid
H0–H7
(Output)
Data
Valid
Data
Valid
AA1115
Figure 2-15 Host DMA Read Cycle
HREQ
(Output)
45
46
31
32
46
TXH
Write
HACK
(Input)
TXM
Write
33
H0–H7
(Output)
46
TXL
Write
34
Data
Valid
Data
Valid
Data
Valid
AA1116
Figure 2-16 Host DMA Write Cycle
2-16
DSP56002/D, Rev. 3
MOTOROLA
Specifications
Serial Communication Interface (SCI) Timing
SERIAL COMMUNICATION INTERFACE (SCI) TIMING
CL = 50 pF + 2 TTL loads
tSCC = Synchronous Clock Cycle Time (For internal clock, tSCC is determined by the SCI Clock
Control Register and TC.) The minimum tSCC value is 8 × TC.
Table 2-9 SCI Synchronous Mode Timing (All Frequencies)
Num
Characteristics
Min
Max
Unit
8TC
—
ns
55
Synchronous Clock Cycle—tSCC
56
Clock Low Period
tSCC/2 – 10.5
—
ns
57
Clock High Period
tSCC/2 – 10.5
—
ns
58
< intentionally blank >
—
—
—
59
Output Data Setup to Clock Falling Edge
(Internal Clock)
tSCC/4 + TL – 26
—
ns
60
Output Data Hold After Clock Rising Edge
(Internal Clock)
tSCC/4 – TL – 8
—
ns
61
Input Data Setup Time Before Clock
Rising Edge (Internal Clock)
tSCC/4 + TL + 23
—
ns
62
Input Data Not Valid Before Clock Rising
Edge (Internal Clock)
—
tSCC/4 + TL – 5.5
ns
63
Clock Falling Edge to Output Data Valid
(External Clock)
—
32.5
ns
64
Output Data Hold After Clock Rising Edge
(External Clock)
TC + 3
—
ns
65
Input Data Setup Time Before Clock
Rising Edge (External Clock)
16
—
ns
66
Input Data Hold Time After Clock Rising
Edge (External Clock)
21
—
ns
Table 2-10 SCI Asynchronous Mode Timing—1X Clock
Num
Characteristics
Min
Max
Unit
64TC
—
ns
67
Asynchronous Clock Cycle—tACC
68
Clock Low Period
tACC/2 – 11
—
ns
69
Clock High Period
tACC/2 – 11
—
ns
70
< intentionally blank >
—
—
—
71
Output Data Setup to Clock Rising Edge (Internal
Clock)
tACC/2 – 51
—
ns
72
Output Data Hold After Clock Rising Edge
(Internal Clock)
tACC/2 – 51
—
ns
MOTOROLA
DSP56002/D, Rev. 3
2-17
Specifications
Serial Communication Interface (SCI) Timing
55
57
56
RCLK
TCLK
(Output)
59
60
TXD
Data Valid
61
62
Data
Valid
RXD
a) Internal Clock
55
57
56
RCLK
TCLK
(Input)
63
64
TXD
Data Valid
65
66
RXD
Data Valid
b) External Clock
AA0388
Figure 2-17 SCI Synchronous Mode Timing
67
69
68
1X TCLK
(Output)
72
71
TXD
Note:
Data Valid
In the wire-OR mode, TXD can be pulled up by 1 kΩ.
AA0389
Figure 2-18 SCI Asynchronous Mode Timing
2-18
DSP56002/D, Rev. 3
MOTOROLA
Specifications
Synchronous Serial Interface (SSI) Timing
SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING
CL = 50 pF + 2 TTL loads
tSSICC = SSI clock cycle time
TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) = Receive Frame Sync
i ck = Internal Clock
x ck = External Clock
g ck = Gated Clock
i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that
STD and SRD are two different clocks)
i ck s = Internal Clock, Synchronous Mode (Synchronous implies that
STD and SRD are the same clock)
bl = bit length
wl = word length
Table 2-11 SSI Timing
40 MHZ or 66 MHz
Num
80 MHz
Characteristics
Min
Max
Min
Max
Case
Unit
80
Clock Cycle–tSSICC1
4TC
3TC
—
—
4TC
3TC
—
—
i ck
x ck
ns
81
Clock High Period
tSSICC/2 – 10.8
TC + TL
—
—
TC + 5
TC + 5
—
—
i ck
x ck
ns
82
Clock Low Period
tSSICC/2 – 10.8
TC + TL
—
—
TC + 5
TC + 5
—
—
i ck
x ck
ns
84
RXC Rising Edge to
FSR Out (bl) High
—
—
40.8
25.8
—
—
30
25.8
x ck
i ck a
ns
85
RXC Rising Edge to
FSR Out (bl) Low
—
—
35.8
25.8
—
—
30
25.8
x ck
i ck a
ns
86
RXC Rising Edge to
FSR Out (wl) High
—
—
35.8
20.8
—
—
30
20.8
x ck
i ck a
ns
87
RXC Rising Edge to
FSR Out (wl) Low
—
—
35.8
20.8
—
—
30
20.8
x ck
i ck a
ns
88
Data In Setup Time
Before RXC (SCK in
Synchronous Mode)
Falling Edge
3.3
15.8
13
—
—
—
3.3
15.8
13
—
—
—
x ck
i ck a
i ck s
ns
MOTOROLA
DSP56002/D, Rev. 3
2-19
Specifications
Synchronous Serial Interface (SSI) Timing
Table 2-11 SSI Timing (Continued)
40 MHZ or 66 MHz
Num
80 MHz
Characteristics
Min
Max
Min
Max
Case
Unit
89
Data In Hold Time
After RXC Falling
Edge
18
3.3
—
—
18
3.3
—
—
x ck
i ck
ns
90
FSR Input (bl) High
Before RXC Falling
Edge
0.8
17.4
—
—
0.8
17.4
—
—
x ck
i ck a
ns
91
FSR Input (wl) High
Before RXC Falling
Edge
3.3
18.3
—
—
3.3
18.3
—
—
x ck
i ck a
ns
92
FSR Input Hold
Time After RXC
Falling Edge
18.3
3.3
—
—
18.3
3.3
—
—
x ck
i ck
ns
93
Flags Input Setup
Before RXC Falling
Edge
0.8
16.7
—
—
0.8
16.7
—
—
x ck
i ck s
ns
94
Flags Input Hold
Time After RXC
Falling Edge
18.3
3.3
—
—
18.3
3.3
—
—
x ck
i ck s
ns
95
TXC Rising Edge to
FST Out (bl) High
—
—
31.6
15.8
—
—
30
15.8
x ck
i ck
ns
96
TXC Rising Edge to
FST Out (bl) Low
—
—
33.3
18.3
—
—
30
18.3
x ck
i ck
ns
97
TXC Rising Edge to
FST Out (wl) High
—
—
30.8
18.3
—
—
30
18.3
x ck
i ck
ns
98
TXC Rising Edge to
FST Out (wl) Low
—
—
33.3
18.3
—
—
30
18.3
x ck
i ck
ns
99
TXC Rising Edge to
Data Out Enable
from High
Impedance
—
33.3 +
TH
20.8
—
30
x ck
ns
—
20.8
i ck
TXC Rising Edge to
Data Out Valid
—
—
30
x ck
—
33.3 +
TH
22.4
—
22.4
i ck
—
—
35.8
20.8
—
—
30
20.8
x ck
i ck
100
101
2-20
TXC Rising Edge to
Data Out High
Impedance 2
—
DSP56002/D, Rev. 3
ns
ns
MOTOROLA
Specifications
Synchronous Serial Interface (SSI) Timing
Table 2-11 SSI Timing (Continued)
40 MHZ or 66 MHz
Num
80 MHz
Characteristics
Min
Max
Min
Max
Case
Unit
101A
TXC Falling Edge to
Data Out High
Impedance 2
—
TC + TH
—
TC + TH
g ck
ns
102
FST Input (bl) Setup
Time Before TXC
Falling Edge
0.8
18.3
0.8
18.3
—
x ck
i ck
ns
—
103
FST Input (wl) to
Data Out Enable
from High
Impedance
—
30.8
—
30.8
104
FST Input (wl)
Setup Time Before
TXC Falling Edge
0.8
20.0
—
—
0.8
20.0
—
—
x ck
i ck
ns
105
FST Input Hold
Time After TXC
Falling Edge
18.3
3.3
—
—
18.3
3.3
—
—
x ck
i ck
ns
106
Flag Output Valid
After TXC Rising
Edge
—
—
32.5
20.8
—
—
30
20.8
x ck
i ck
ns
Notes:
1.
2.
ns
For internal clock, External Clock Cycle is defined by Icyc and SSI control register.
Periodically sampled and not 100% tested
MOTOROLA
DSP56002/D, Rev. 3
2-21
Specifications
Synchronous Serial Interface (SSI) Timing
80
TXC
(Input/
Output)
81
82
95
96
FST (Bit)
Out
97
98
FST (Word)
Out
100
101A
100
99
101
Data Out
First Bit
Last Bit
102
105
FST (Bit) In
103
104
105
FST (Word)
In
106
See Note
Flags Out
Note:
In the Network mode, output flag transitions can occur at the start of each time slot within the
frame. In the Normal mode, the output flag state is asserted for the entire frame period.
AA0390
Figure 2-19 SSI Transmitter Timing
2-22
DSP56002/D, Rev. 3
MOTOROLA
Specifications
Synchronous Serial Interface (SSI) Timing
80
81
82
RXC
(Input/Output)
84
85
FSR (Bit)
Out
86
87
FSR (Word)
Out
88
Data In
89
First Bit
Last Bit
90
92
FSR (Bit)
In
91
92
FSR (Word)
In
93
94
Flags In
AA0391
Figure 2-20 SSI Receiver Timing
MOTOROLA
DSP56002/D, Rev. 3
2-23
Specifications
External Bus Asynchronous Timing
EXTERNAL BUS ASYNCHRONOUS TIMING
CL = 50 pF + 2 TTL loads
WS = Number of Wait States (0 to 15), as determined by BCR register
Capacitance Derating: The DSP56002 External Bus Timing Specifications are designed and
tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive
capability of the External Bus pins (A0–A15, D0–D23, PS, DS, RD, WR, X/Y, EXTP) derates
linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C
pins (HI, SCI, SSI, and Timer) derate linearly at 1 ns per 5 pF of additional capacitance from 50
pF to 250 pF of loading. Active low lines should be “pulled up” in a manner consistent with the
AC and DC specifications.
Table 2-12 External Bus Asynchronous Timing
40 MHz
No.
80 MHz
Unit
Min
115 Delay from BR
Assertion to BG
Assertion
• With no
2TC +
external access
TH
from the DSP
• During external TC + TH
read or write
access
• During external TC + TH
read-modifywrite access
• During Stop
∞
mode—
external bus
will not be
released and
BG will not go
low
• During Wait
TH
mode
116 Delay from BR
Deassertion to BG
Deassertion
2-24
66 MHz
Characteristics
2TC
Max
Min
Max
Min
Max
4TC + TH + 14
2TC +
TH
4TC + TH + 14
2TC +
TH
4TC + TH + 14
ns
4TC + TH + TC + TH 4TC + TH + TC + TH 4TC + TH +
(TC × WS) + 14
(TC × WS) + 14
(TC × WS) + 14
ns
6TC + TH + TC + TH 6TC + TH + TC + TH 6TC + TH +
ns
(2TC × WS) +14
(2TC × WS) +14
(2TC × WS) +14
14
∞
14
∞
14
ns
TC + TH + 15
TH
TC + TH + 15
TH
TC + TH + 15
ns
4TC + 12.5
2TC
4TC + 12.5
2TC
4TC + 12.5
ns
DSP56002/D, Rev. 3
MOTOROLA
Specifications
External Bus Asynchronous Timing
Table 2-12 External Bus Asynchronous Timing (Continued)
40 MHz
No.
66 MHz
80 MHz
Characteristics
Unit
Min
117 BG Deassertion
Duration
• During Wait
TC – 5.5
mode
• All other cases 2TC +
TH – 5.5
Max
Min
Max
Min
Max
—
TC – 5.5
—
TC – 5.5
—
ns
—
2TC +
TH – 5.5
—
2TC +
TH – 5.5
—
ns
118 Delay from Address,
Data, and Control Bus
High Impedance to BG
Assertion
0
—
0
—
0
—
ns
119 Delay from BG
Deassertion to Address
and Control Bus
Enabled
0
TH
0
TH
0
TH
ns
TL – 6
TC – 6
—
—
TL – 4.5
TC – 4.5
—
—
TL – 4.5
TC – 4.5
—
—
ns
ns
TC – 4
WS ×
TC + TL
—
—
TC – 4
WS ×
TC + TL
—
—
TC – 2
WS ×
TC + TL
—
—
ns
ns
TH – 6
—
TH – 4
—
TH – 4
—
ns
TH – 4
0
—
—
TH – 4
0
—
—
TH – 4
0
—
—
ns
ns
TH – 7
TH – 2.5
TH – 5
TH – 1.5
TH – 5
TH – 1.5
ns
TL – 0.8
WS ×
TC + TL
– 0.8
—
—
TL – 0.4
WS ×
TC + TL
– 0.4
—
—
TL – 0.5
WS ×
TC + TL
– 0.5
—
—
ns
ns
120 Address Valid to
WR Assertion
• WS = 0
• WS > 0
121 WR Assertion Width
• WS = 0
• WS > 0
122 WR Deassertion to
Address Not Valid
123 WR Assertion to Data
Out Active From High
Impedance
• WS = 0
• WS > 0
124 Data Out Hold Time
from WR Deassertion
(the maximum
specification is
periodically sampled,
and not 100% tested)
125 Data Out Setup Time
to WR Deassertion
• WS = 0
• WS > 0
MOTOROLA
DSP56002/D, Rev. 3
2-25
Specifications
External Bus Asynchronous Timing
Table 2-12 External Bus Asynchronous Timing (Continued)
40 MHz
No.
66 MHz
80 MHz
Characteristics
Unit
Min
Max
Min
Max
Min
Max
TH
—
TH – 1
—
TH
—
ns
TC +
TL – 6
((WS +
1) ×
TC) +
TL – 6
—
TC +
TL – 6
((WS +
1) ×
TC) +
TL – 6
—
TC +
TL – 6
((WS +
1) ×
TC) +
TL – 6
—
ns
—
ns
0
—
0
—
0
—
ns
TC – 4
((WS +
1) ×
TC) – 4
—
—
TC – 4
((WS +
1) ×
TC) – 4
—
—
TC – 4
((WS +
1) ×
TC) – 4
—
—
ns
ns
—
—
TC + TL – 9.5
((WS+1) × TC) +
TL – 9.5
—
—
TC + TL – 7
((WS+1) × TC) +
TL – 7
—
—
TC + TL – 6
((WS+1) × TC)
+ TL – 6
ns
ns
TL – 4.5
—
TL – 4.5
—
TL – 4.5
—
ns
—
—
TC – 7.5
((WS+1) × TC) –
7.5
—
—
TC – 5.5
((WS+1) × TC) –
5.5
—
—
133 WR Deassertion to
RD Assertion
TC – 7
—
TC – 5
—
TC – 5
—
ns
134 RD Deassertion to
RD Assertion
TC – 4
—
TC – 2.5
—
TC – 2.5
—
ns
TC – 4
TC +
TH – 4
—
—
TC – 3
TC +
TH – 3
—
—
TC – 3
TC +
TH – 3
—
—
ns
ns
126 RD Deassertion to
Address Not Valid
127 Address Valid to RD
Deassertion
• WS = 0
•
WS > 0
128 Input Data Hold Time
to RD Deassertion
129 RD Assertion Width
• WS = 0
• WS > 0
130 Address Valid to Input
Data Valid
• WS = 0
• WS > 0
131 Address Valid to
RD Assertion
132 RD Assertion to Input
Data Valid
• WS = 0
• WS > 0
135 WR Deassertion to
WR Assertion
• WS = 0
• WS > 0
2-26
—
—
DSP56002/D, Rev. 3
TC – 5.5
ns
((WS+1) × TC) – ns
5.5
MOTOROLA
Specifications
External Bus Asynchronous Timing
Table 2-12 External Bus Asynchronous Timing (Continued)
40 MHz
No.
66 MHz
80 MHz
Characteristics
136 RD Deassertion to
WR Assertion
• WS = 0
• WS > 0
Unit
Min
Max
Min
Max
Min
Max
TC – 4
TC +
TH – 4
—
—
TC – 2.5
TC +
TH – 2.5
—
—
TC – 2.5
TC +
TH – 2.5
—
—
ns
ns
BR
115
116
BG
117
119
118
A0–A15, PS
DS, X/Y,
RD, WR
D0–D23
AA0392
Figure 2-21 Bus Request / Bus Grant Timing
MOTOROLA
DSP56002/D, Rev. 3
2-27
Specifications
External Bus Asynchronous Timing
A0–A15, DS,
PS, X/Y
(See Note)
126
127
131
129
134
RD
120
135
122
121
133
136
WR
132
123
130
125
D0–D23
Note:
128
124
Data Out
Data
In
During Read-Modify-Write instructions, the address lines do not change state.
AA0393
Figure 2-22 External Bus Asynchronous Timing
2-28
DSP56002/D, Rev. 3
MOTOROLA
Specifications
External Bus Synchronous Timing
EXTERNAL BUS SYNCHRONOUS TIMING
CL = 50 pF + 2 TTL loads
Capacitance Derating: The DSP56002 external bus timing specifications are designed and tested
at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive
capability of the external bus pins (A0–A15, D0–D23, PS, DS, RD, WR, X/Y) derates linearly at 1
ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI,
SCI, SSI, and Timer) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250
pF of loading. Active-low lines should be “pulled up” in a manner consistent with the ac and dc
specifications.
Table 2-13 External Bus Synchronous Timing
40 MHz
Num
66 MHz
80 MHz
Characteristics
Unit
Min
Max
Min
Max
Min
Max
First CKOUT transition to Address Valid
Second CKOUT transition to WR
Assertion1
• WS = 0
• WS > 0
—
6.2
—
5
—
5
—
—
4.4
TH + 4.4
—
—
4
TH + 4
—
—
4
TH + 4
142
Second CKOUT transition to WR
Deassertion
1.3
9.1
1
5
1
5
ns
143
Second CKOUT transition to RD
Assertion
—
3.9
—
3.9
—
3.9
ns
144
Second CKOUT transition to RD
Deassertion
0
3.4
–3
3
–3
3
ns
145
First CKOUT transition to Data-Out Valid
—
5.4
—
4.5
—
4.5
ns
146
First CKOUT transition to Data-Out
Invalid3
0
—
0
—
0
—
ns
147
Data-In Valid to second CKOUT transition
(Setup)
3.4
—
3.4
—
3.4
—
ns
148
Second CKOUT transition to Data-In
Invalid (Hold)
0
—
0
—
0
—
ns
149
First CKOUT transition to Address
Invalid3
0
—
0
—
0
—
ns
140
141
Notes:
1.
2.
3.
4.
5.
ns
ns
ns
AC timing specifications which are referenced to a device input signal are measured in production
with respect to the 50% point of the respective input signal’s transition.
WS are wait state values specified in the BCR.
First CKOUT transition to data-out invalid (specification # T146) and first CKOUT transition to
address invalid (specification # T149) indicate the time after which data/address are no longer
guaranteed to be valid.
Timings are given from CKOUT midpoint to VOL or VOH of the corresponding pin(s).
First CKOUT transition is a falling edge of CKOUT for CKP = 0.
MOTOROLA
DSP56002/D, Rev. 3
2-29
Specifications
External Bus Synchronous Timing
T0
T1
T2
T3
T0
T1
T2
T3
T0
CKOUT
A0–A15
DS, PS
X/Y
140
143
144
149
RD
141
142
WR
147
D0–D23
Data Out
145
148
Data In
146
BN
171
172
EXTAL
170
Note:
During Read-Modify-Write Instructions, the address lines do not change states.
AA0395
Figure 2-23 Synchronous Bus Timing
2-30
DSP56002/D, Rev. 3
MOTOROLA
Specifications
External Bus Synchronous Timing
Table 2-14 Bus Strobe/Wait Timing
40 MHz
No.
66 MHz
80 MHz
Characteristics
Unit
Min
Max
Min
Max
Min
Max
150 First CKOUT transition
to BS Assertion
—
5.6
—
5.6
—
5.6
ns
151 WT Assertion to first
CKOUT transition
(setup time)
5.3
—
5.3
—
5.3
—
ns
152 First CKOUT transition
to WT Deassertion for
Minimum Timing
0
TC – 7.9
0
TC – 7.9
0
TC – 6
ns
153 WT Deassertion to first
CKOUT transition for
Maximum Timing
(2 wait states)
7.9
—
7.9
—
6
—
ns
154 Second CKOUT
transition to BS
Deassertion
—
5.2
—
5.2
—
5.2
ns
155 BS Assertion to Address
Valid
0
2.4
0
2.4
0
2.4
ns
156 BS Assertion to WT
Assertion1
0
TC – 10.9
0
TC – 10.9
0
TC – 8.8
ns
157 BS Assertion to WT
Deassertion1,3
(WS–1) × WS × TC –
TC
13.5
158 WT Deassertion to BS
Deassertion
TC + TL +
3.3
2×
TC+TL+
7.8
TC + TL +
3.3
2×
TC+TL+
7.8
159 Minimum BS
Deassertion Width for
Consecutive External
Accesses
TH – 1
—
TH – 1
TH – 4.6
—
161 Data-In Valid to RD
Deassertion (Set Up)
3.4
162 BR Assertion to second
CKOUT transition for
Minimum Timing
9.5
160 BS Deassertion to
Address Invalid2
MOTOROLA
(WS–1) × WS × TC –
TC
13.5
(WS–1) × WS × TC –
TC
10.9
ns
TC + TL +
3.3
2×
TC+TL+
7.8
ns
—
TH – 1
—
ns
TH – 4.6
—
TH – 4.6
—
ns
—
3.4
—
3.4
—
ns
TC
9.5
TC
9.5
TC
ns
DSP56002/D, Rev. 3
2-31
Specifications
External Bus Synchronous Timing
Table 2-14 Bus Strobe/Wait Timing (Continued)
40 MHz
No.
66 MHz
80 MHz
Characteristics
Unit
Min
Max
Min
Max
Min
Max
163 BR Deassertion to
second CKOUT
transition for
Minimum Timing
8
TC
8
TC
8
TC
ns
164 First CKOUT transition
to BG Assertion
—
8.8
—
8.8
—
8.8
ns
165 First CKOUT transition
to BG Deassertion
—
5.3
—
5.3
—
5.3
ns
170 EXTAL to CKOUT with
PLL Disabled
EXTAL to CKOUT5 with
PLL Enabled and
MF < 5
3
9.7
3
9.7
3
9.7
ns
0.3
3.7
0.3
3.7
0.3
3.7
ns
171 Second CKOUT
transition to BN
Assertion
—
5.7
—
5.7
—
5.7
ns
172 Second CKOUT
transition to BN
Deassertion
—
5
—
5
—
5
ns
Notes:
1.
2.
3.
4.
5.
2-32
If wait states are also inserted using the BCR and if the number of wait states is greater than 2, then
specification numbers T156 and T157 can be increased accordingly.
BS deassertion to address invalid indicates the time after which the address are no longer guaranteed to
be valid.
The minimum number of wait states when using BS/WT is two (2).
For read-modify-write instructions, the address lines will not change states between the read and the
write cycle. However, BS will deassert before asserting again for the write cycle. If wait states are
desired for each of the read and write cycle, the WT pin must be asserted once for each cycle.
When EXTAL frequency is less than 33 MHz, then timing T170 is not guaranteed for a period of 1000 ×
TC after PLOCK assertion following the events below:
• when enabling the PLL operation by software,
• when changing the Multiplication Factor,
• when recovering from the Stop state if the PLL was turned off and it is supposed to turn, on
• when exiting the Stop state.
DSP56002/D, Rev. 3
MOTOROLA
Specifications
External Bus Synchronous Timing
T2
Tw
T2
T3
T0
T1
T2
Tw
T2
T3
T0
T1
CKOUT
162
164
163
165
BR
BG
AA0396
Figure 2-24 Synchronous Bus Request / Bus Grant Timing
MOTOROLA
DSP56002/D, Rev. 3
2-33
Specifications
External Bus Synchronous Timing
T0
T1
T2
Tw
T2
Tw
T2
T3
T0
CKOUT
140
149
A0–A15,
PS, DS,
X/Y
150
154
BS
152
151
153
WT
143
144
RD
147
148
Data In
D0–D23
141
142
WR
145
D0–D23
Note:
146
Data Out
During Read-Modify-Write instructions, the address lines do not change state.
However, BS will deassert before asserting again for the write cycle.
AA0397
Figure 2-25 Synchronous BS / WT Timings
2-34
DSP56002/D, Rev. 3
MOTOROLA
Specifications
External Bus Synchronous Timing
A0–A15,
PS, DS,
X/Y
155
160
BS
157
158
156
158
WT
131
126
RD
161
D0–D23
128
Data In
120
122
WR
123
D0–D23
Note:
125
124
Data Out
During Read-Modify-Write instructions, the address lines do not change state.
However, BS will deassert before asserting again for the write cycle.
AA0398
Figure 2-26 Asynchronous BS / WT Timings
MOTOROLA
DSP56002/D, Rev. 3
2-35
Specifications
OnCE Port Timing
OnCE PORT TIMING
CL = 50 pF + 2 TTL loads
Table 2-15 OnCE Port Timing
Num
Characteristics
Min
Max
Unit
230
DSCK Low
40
—
ns
231
DSCK High
40
—
ns
232
DSCK Cycle Time
200
—
ns
233
DR Asserted to DSO (ACK) Asserted
5TC
—
ns
234
DSCK High to DSO Valid
—
42
ns
235
DSCK High to DSO Invalid
3
—
ns
236
DSI Valid to DSCK Low (Setup)
15
—
ns
237
DSCK Low to DSI Invalid (Hold)
3
—
ns
238
Last DSCK Low to OS0–OS1, ACK Active
3TC + TL
—
ns
239
DSO (ACK) Asserted to First DSCK High
2TC
—
ns
240
DSO (ACK) Assertion Width
4TC + TH – 3
5TC + 7
ns
241
DSO (ACK) Asserted to OS0–OS1 High Impedance2
—
0
ns
242
OS0–OS1 Valid to second CKOUT transition
TC – 21
—
ns
243
Second CKOUT transition to OS0–OS1 Invalid
0
—
ns
244
Last DSCK Low of Read Register to First DSCK
High of Next Command
7TC + 10
—
ns
245
Last DSCK Low to DSO Invalid (Hold)
3
—
ns
246
DR Assertion to second CKOUT transition for Wake
Up from Wait state
12
TC
ns
247
Second CKOUT transition to DSO after Wake Up
from Wait state
17TC
—
ns
248
DR Assertion Width
• To recover from Wait state
• To recover from Wait state and enter Debug
mode
15
13TC + 15
12TC – 15
—
ns
17TC
—
ns
15
15
15
65548TC + TL
20TC + TL
13TC + TL
ns
ns
ns
249
250A
2-36
DR Assertion to DSO (ACK) Valid (enter Debug
mode) After Asynchronous Recovery from Wait State
DR Assertion Width to Recover from Stop state1
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17= 1
DSP56002/D, Rev. 3
MOTOROLA
Specifications
OnCE Port Timing
Table 2-15 OnCE Port Timing
Num
250B
251
Notes:
Characteristics
Min
Max
Unit
DR Assertion Width to Recover from Stop state and
enter Debug mode1
• Stable External Clock,OMR Bit 6 = 0
• Stable External Clock,OMR Bit 6 = 1
• Stable External Clock,PCTL Bit 17= 1
65549TC + TL
21TC + TL
14TC + TL
—
—
—
ns
ns
ns
DR Assertion to DSO (ACK) Valid (enter Debug
mode) after recovery from Stop state1
• Stable External Clock, OMR Bit 6 = 0
• Stable External Clock, OMR Bit 6 = 1
• Stable External Clock, PCTL Bit 17= 1
65553TC + TL
25TC + TL
18TC + TL
—
—
—
ns
ns
ns
1.
2.
A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:
• after power-on Reset, and
• when recovering from Stop mode.
During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period
varies, a delay of 75,000 × TC is typically allowed to assure that the oscillator is stable before executing
programs. While it is possible to set OMR bit 6 = 1 when using the internal crystal oscillator, it is not
recommended and these specifications do not guarantee timings for that case.
The maximum specified is periodically sampled and not 100% tested.
230
DSCK
(Input)
231
232
AA0399
Figure 2-27 OnCE Serial Clock Timing
DR
(Input)
233
DSO
(Output)
(ACK)
AA0400
Figure 2-28 OnCE Acknowledge Timing
MOTOROLA
DSP56002/D, Rev. 3
2-37
Specifications
OnCE Port Timing
DSCK
(Input)
(OS1)
(Last)
DSO
(Output)
(ACK)
236
237
238
DSI
(Input)
(OS0)
(See Note)
Note:
High Impedance, external pull-down resistor
AA0501
Figure 2-29 OnCE Data I/O To Status Timing
DSCK
(Input)
(Last)
234
235
245
(See Note)
DSO
(Output)
Note:
High Impedance, external pull-down resistor
AA0502
Figure 2-30 OnCE Read Timing
239
OS1
(Output)
(See Note)
241
(DSCK Input)
240
DSO
(Output)
(DSO Output)
(DSI Input)
OS0
(Output)
241
(See Note) 236
237
Note:
High Impedance, external pull-down resistor
AA0503
Figure 2-31 OnCE Data I/O To Status Timing
2-38
DSP56002/D, Rev. 3
MOTOROLA
Specifications
OnCE Port Timing
CKOUT
242
243
OS0–OS1
(Output)
(See Note)
Note:
High Impedance, external pull-down resistor
AA0504
Figure 2-32 OnCE CKOUT To Status Timing
DSCK
(Input)
(Next Command)
244
AA0505
Figure 2-33 OnCE Read Register to Next Command Timing
CKOUT
T0, T2
T1, T3
248
DR
(Input)
246
247
DSO
(Output)
AA0506
Figure 2-34 Synchronous Recovery from Wait State
248
DR
(Input)
249
DSO
(Output)
AA0507
Figure 2-35 Asynchronous Recovery from Wait State
MOTOROLA
DSP56002/D, Rev. 3
2-39
Specifications
OnCE Port Timing
250
DR
(Input)
251
DSO
(Output)
AA0508
Figure 2-36 Asynchronous Recovery from Stop State
2-40
DSP56002/D, Rev. 3
MOTOROLA
Specifications
Timer Timing
TIMER TIMING
CL = 50 pF + 2 TTL loads
Table 2-16 Timer Timing
Num
Characteristics
Min
Max
Unit
2TC + 7
—
ns
2TC + 7
—
ns
10
TC
ns
5TC + TH
—
ns
260
261
TIO Low
TIO High
262
Synchronous Timer Setup Time from TIO (input)
Assertion to CKOUT Rising Edge
263
Synchronous Timer Delay Time from CKOUT Rising Edge
to the External Memory Access Address Out Valid Caused
by First Interrupt Instruction Execution
264
CKOUT Rising Edge to TIO (output) Assertion
0
8
ns
265
CKOUT Rising Edge to TIO (output) Deassertion
0
8
ns
266
CKOUT Rising Edge to TIO (General Purpose Output)
0
8
ns
TIO
260
261
AA0509
Figure 2-37 TIO Timer Event Input
CKOUT
TIO (Input)
262
ADDRESS
263
First Interrupt Instruction Execution
AA0510
Figure 2-38 Timer Interrupt Generation
MOTOROLA
DSP56002/D, Rev. 3
2-41
Specifications
Timer Timing
CKOUT
TIO (Output)
264
265
AA0511
Figure 2-39 External Pulse Generation
fetch the instruction MOVE X0,X:(R0); X0 contains the new value of TIO
; and R0 contains the address of TCSR
266
CKOUT
A0–A15
PS, DS
EXTP, X/Y
TIO (Output)
AA0512
Figure 2-40 GPIO Output Timing
2-42
DSP56002/D, Rev. 3
MOTOROLA
SECTION
3
PACKAGING
PIN-OUT AND PACKAGE INFORMATION
This sections provides information about the available packages for this product,
including diagrams of the package pinouts and tables describing how the signals
described in Section 1 are allocated for each package.
The DSP56002 is available in three package types:
MOTOROLA
•
132-pin Plastic Quad Flat Pack (PQFP)
•
144-pin Thin Quad Flat Pack (TQFP)
•
132-pin Ceramic Pin Grid Array (PGA)
DSP56002/D, Rev. 3
3-1
Packaging
Pin-out and Package Information
PQFP Package Description
18
Orientation Mark
(Chamfered Edge)
(Top View)
51
84
GNDD
D21
D20
VCCD
D19
D18
GNDD
D17
D16
D15
D14
GNDD
D13
D12
VCCD
D11
D10
GNDD
GNDQ
VCCQ
D9
D8
D7
D6
GNDD
D5
D4
VCCD
D3
D2
GNDD
D1
D0
DR
DSO
DSI/OS0
BS
X/Y
GNDA
DS
VCCA
PS
A0
A1
GNDA
A2
A3
A4
VCCQ
GNDQ
A5
VCCA
GNDA
A6
A7
A8
A9
GNDA
A10
A11
A12
VCCA
A13
GNDA
A14
A15
H4/PB4
H3/PB3
VCCH
H2/PB2
GNDH
H1/PB1
H0/PB0
RXD/PC0
TXD/PC1
GNDS
SCLK/PC2
SC0/PC3
VCCS
SCK/PC6
SC2/PC5
STD/PC8
GNDS
SC1/PC4
GNDQ
VCCQ
SRD/PC7
TIO
NC
BN
WT
BG
BR
VCCC
WR
RD
GNDC
NC
DSCK/OS1
117
1
H5/PB5
GNDH
H6/PB6
H7/PB7
HREQ/PB13
HR/W/PB11
GNDH
HEN/PB12
VCCH
HACK/PB14
HA0/PB8
HA1/PB9
GNDH
HA2/PB10
GNDQ
VCCQ
EXTAL
XTAL
PINIT
PLOCK
GNDP
PCAP
VCCP
CKP
RESET
VCCCK
CKOUT
GNDCK
MODA/IRQA
MODB/IRQB
MODC/NMI
D23
D22
Top and bottom views of the PQFP package are shown in Figure 3-1 and Figure 3-2
with their pin-outs.
Note:
1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.
2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
3. To simplify locating the pins, each fifth pin is shaded in the illustration.
AA0611
Figure 3-1 Top View of the 132-pin Plastic Quad Flat Pack (PQFP) Package
3-2
DSP56002/D, Rev. 3
MOTOROLA
Packaging
D22
D23
MODC/NMI
MODB/IRQB
MODA/IRQA
GNDCK
CKOUT
VCCCK
RESET
CKP
VCCP
PCAP
GNDP
PLOCK
PINIT
XTAL
EXTAL
VCCQ
GNDQ
HA2/PB10
GNDH
HA1/PB9
HA0/PB8
HACK/PB14
VCCH
HEN/PB12
GNDH
HR/W/PB11
HREQ/PB13
H7/PB7
H6/PB6
GNDH
H5/PB5
Pin-out and Package Information
117
1
18
Orientation Mark
(Chamfered Edge
on Top Side)
51
(Bottom View)
84
H4/PB4
H3/PB3
VCCH
H2/PB2
GNDH
H1/PB1
H0/PB0
RXD/PC0
TXD/PC1
GNDS
SCLK/PC2
SC0/PC3
VCCS
SCK/PC6
SC2/PC5
STD/PC8
GNDS
SC1/PC4
GNDQ
VCCQ
SRD/PC7
TIO
NC
BN
WT
BG
BR
VCCC
WR
RD
GNDC
NC
DSCK/OS1
A15
A14
GNDA
A13
VCCA
A12
A11
A10
GNDA
A9
A8
A7
A6
GNDA
VCCA
A5
GNDQ
VCCQ
A4
A3
A2
GNDA
A1
A0
PS
VCCA
DS
GNDA
X/Y
BS
DSI/OS0
DSO
DR
GNDD
D21
D20
VCCD
D19
D18
GNDD
D17
D16
D15
D14
GNDD
D13
D12
VCCD
D11
D10
GNDD
GNDQ
VCCQ
D9
D8
D7
D6
GNDD
D5
D4
VCCD
D3
D2
GNDD
D1
D0
Note:
1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.
2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
3. To simplify locating the pins, each fifth pin is shaded in the illustration.
AA0612
Figure 3-2 Bottom View of the 132-pin Plastic Quad Flat Pack (PQFP) Package
MOTOROLA
DSP56002/D, Rev. 3
3-3
Packaging
Pin-out and Package Information
The DSP56002 signals that may be programmed as General Purpose I/O are listed
with their primary function in Table 3-9.
Table 3-1 DSP56002 General Purpose I/O Pin Identification in PQFP Package
3-4
Pin Number
Primary Function
Port
GPIO ID
24
H0
B
PB0
23
H1
PB1
21
H2
PB2
19
H3
PB3
18
H4
PB4
17
H5
PB5
15
H6
PB6
14
H7
PB7
7
HA0
PB8
6
HA1
PB9
4
HA2
PB10
12
HR/W
PB11
10
HEN
PB12
13
HREQ
PB13
8
HACK
PB14
25
RXD
26
TXD
PC1
28
SCLK
PC2
29
SC0
PC3
35
SC1
PC4
32
SC2
PC5
31
SCK
PC6
38
SRD
PC7
33
STD
PC8
39
TIO
No port assigned
DSP56002/D, Rev. 3
C
PC0
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-2 DSP56002 Signal Identification by PQFP Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
EXTAL
26
TXD/PC1
51
DR
2
VCCQ
27
GNDS
52
DSO
3
GNDQ
28
SCLK/PC2
53
DSI/OS0
4
HA2/PB10
29
SC0/PC3
54
BS
5
GNDH
30
VCCS
55
X/Y
6
HA1/PB9
31
SCK/PC6
56
GNDA
7
HA0/PB8
32
SC2/PC5
57
DS
8
HACK/PB14
33
STD/PC8
58
VCCA
9
VCCH
34
GNDS
59
PS
10
HEN/PB12
35
SC1/PC4
60
A0
11
GNDH
36
GNDQ
61
A1
12
HR/W/PB11
37
VCCQ
62
GNDA
13
HREQ/PB13
38
SRD/PC7
63
A2
14
H7/PB7
39
TIO*
64
A3
15
H6/PB6
40
NC
65
A4
16
GNDH
41
BN
66
VCCQ
17
H5/PB5
42
WT
67
GNDQ
18
H4/PB4
43
BG
68
A5
19
H3/PB3
44
BR
69
VCCA
20
VCCH
45
VCCC
70
GNDA
21
H2/PB2
46
WR
71
A6
22
GNDH
47
RD
72
A7
23
H1/PB1
48
GNDC
73
A8
24
H0/PB0
49
NC
74
A9
25
RXD/PC0
50
DSCK/OS1
75
GNDA
MOTOROLA
DSP56002/D, Rev. 3
3-5
Packaging
Pin-out and Package Information
Table 3-2 DSP56002 Signal Identification by PQFP Pin Number (Continued)
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
76
A10
95
D8
114
D20
77
A11
96
D9
115
D21
78
A12
97
VCCQ
116
GNDD
79
VCCA
98
GNDQ
117
D22
80
A13
99
GNDD
118
D23
81
GNDA
100
D10
119
MODC/NMI
82
A14
101
D11
120
MODB/IRQB
83
A15
102
VCCD
121
MODA/IRQA
84
D0
103
D12
122
GNDCK
85
D1
104
D13
123
CKOUT
86
GNDD
105
GNDD
124
VCCCK
87
D2
106
D14
125
RESET
88
D3
107
D15
126
CKP
89
VCCD
108
D16
127
VCCP
90
D4
109
D17
128
PCAP
91
D5
110
GNDD
129
GNDP
92
GNDD
111
D18
130
PLOCK
93
D6
112
D19
131
PINIT
94
D7
113
VCCD
132
XTAL
Note:
1.
2.
3-6
“NC” are No Connection pins that are reserved for possible future enhancements.
Do not connect these pins to any power, ground, signal traces, or vias.
An OVERBAR indicates the signal is asserted when the voltage = ground (active
low).
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-3 DSP56002 PQFP Pin Identification by Signal Name
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
A0
60
D3
114
DSO
52
A1
61
D4
116
EXTAL
1
A2
63
D5
117
GNDA
56
A3
64
D6
119
GNDA
62
A4
65
D7
94
GNDA
70
A5
68
D8
95
GNDA
75
A6
71
D9
96
GNDA
81
A7
72
D10
100
GNDC
48
A8
73
D11
101
GNDCK
122
A9
74
D12
103
GNDD
86
A10
76
D13
104
GNDD
92
A11
77
D14
106
GNDD
99
A12
78
D15
107
GNDD
105
A13
80
D16
108
GNDD
110
A14
82
D17
109
GNDD
116
A15
83
D18
111
GNDH
5
BG
43
D19
112
GNDH
11
BN
41
D20
114
GNDH
16
BR
44
D21
115
GNDH
22
BS
54
D22
117
GNDP
129
CKOUT
123
D23
118
GNDQ
3
CKP
126
DR
51
GNDQ
36
D0
84
DS
57
GNDQ
67
D1
85
DSCK
50
GNDQ
98
D2
87
DSI
53
GNDS
27
MOTOROLA
DSP56002/D, Rev. 3
3-7
Packaging
Pin-out and Package Information
Table 3-3 DSP56002 PQFP Pin Identification by Signal Name (Continued)
3-8
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
GNDS
34
PB1
23
PLOCK
130
H0
24
PB2
21
PS
59
H1
23
PB3
19
RD
47
H2
21
PB4
18
RESET
125
H3
19
PB5
17
RXD
25
H4
18
PB6
15
SC0
29
H5
17
PB7
14
SC1
35
H6
15
PB8
7
SC2
32
H7
14
PB9
6
SCK
31
HA0
7
PB10
4
SCLK
28
HA1
6
PB11
12
SRD
38
HA2
4
PB12
10
STD
33
HACK
8
PB13
13
TIO
39
HEN
10
PB14
8
TXD
26
HR/W
12
PC0
25
VCCA
58
HREQ
13
PC1
26
VCCA
69
IRQA
121
PC2
28
VCCA
79
IRQB
120
PC3
29
VCCC
45
MODA
121
PC4
35
VCCCK
124
MODB
120
PC5
32
VCCD
89
MODC
119
PC6
31
VCCD
102
NMI
119
PC7
38
VCCD
113
OS0
53
PC8
33
VCCH
9
OS1
50
PCAP
128
VCCH
20
PB0
24
PINIT
131
VCCP
127
VCCQ
2
VCCS
30
XTAL
132
VCCQ
37
WR
46
nc
40
VCCQ
66
WT
42
nc
49
VCCQ
97
X/Y
55
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
Power and ground pins have special considerations for noise immunity.
See Section 4 Design Considerations.
Table 3-4 DSP56002 Power Supply Pins in PQFP Package
Pin Number
Power Supply
Circuit Supplied
58
69
VCCA
79
Address
Bus
Buffers
56
62
70
GNDA
75
81
45
VCCC
48
GNDC
124
VCCCK
122
GNDCK
Bus Control
Buffers
Clock
89
102
VCCD
113
86
92
99
GNDD
Data
Bus
Buffers
105
110
116
9
20
VCCH
5
11
16
GNDH
Host
Interface
Buffers
22
MOTOROLA
DSP56002/D, Rev. 3
3-9
Packaging
Pin-out and Package Information
Table 3-4 DSP56002 Power Supply Pins in PQFP Package (Continued)
Pin Number
Power Supply
Circuit Supplied
2
37
66
VCCQ
97
Internal Logic
3
36
67
GNDQ
98
127
VCCP
129
GNDP
30
VCCS
27
34
3-10
GNDS
DSP56002/D, Rev. 3
PLL
Serial Port
MOTOROLA
Packaging
Pin-out and Package Information
A
128X
A1
AC AC
S
G
X
X=L, M, OR N
S1
J
J1
1
N
17
VIEW AB
117
18
116
CL
VIEW AB
B1
V1
PIN 1
IDENT
M
P
B
V
BASE
METAL
AA
L
E
P1
(D)
AA
50
84
E1
D2
51
83
0.016 H L-M N
0.010 T L-M N
0.012 H L-M N
0.002 N
0.002 L-M
4X
2X
PLATING
SECTION AC-AC
4X 33 TIPS
4X
2X
0.004 T
C C2
132X
SEATING
PLANE
C1
T
132X D1
0.008 M T L-M N
R R1
H
K1
GAGE
PLANE
U
K
132X D
W
θ
0.008 M T L-M N
SECTION AA-AA
CASE 831A-02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1982.
2. DIMENSIONS IN INCHES.
3. DIMENSIONS A, B, J, AND P DO NOT
INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION
FOR DIMENSIONS A AND B IS 0.007,
FOR DIMENSIONS J AND P IS 0.010.
4. DATUM PLANE H IS LOCATED AT THE
UNDERSIDE OF LEADS WHERE
LEADS EXIT PACKAGE BODY.
5. DATUMS L, M, AND N TO BE
DETERMINED WHERE CENTER
LEADS EXIT PACKAGE BODY AT
DATUM H.
6. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE,
DATUM T.
7. DIMENSIONS A, B, J, AND P TO BE
DETERMINED AT DATUM PLANE H.
8. DIMENSION F DOES NOT INCLUDE
DAMBAR PROTRUSIONS. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
LEAD WIDTH TO EXCEED 0.019.
DIM
A
A1
B
B1
C
C1
C2
D
D1
D2
E
E1
F
G
J
J1
K
K1
P
P1
R1
S
S1
U
V
V1
W
θ
INCHES
MIN
MAX
1.100 BSC
0.550 BSC
1.100 BSC
0.550 BSC
0.160 0.180
0.020 0.040
0.135 0.145
0.008 0.012
0.012 0.016
0.008 0.011
0.006 0.008
0.005 0.007
0.014 0.014
0.025 BSC
0.950 BSC
0.475 BSC
0.034 0.044
0.010 BSC
0.950 BSC
0.475 BSC
0.013 REF
1.080 BSC
0.540 BSC
0.025 REF
1.080 BSC
0.540 BSC
0.006 0.008
0°
8°
Figure 3-3 132-Pin Plastic Quad Flat Pack (PQFP) Mechanical Information
MOTOROLA
DSP56002/D, Rev. 3
3-11
Packaging
Pin-out and Package Information
TQFP Package Description
109
(Top View)
Orientation Mark
1
37
NC
DSCK/OS1
NC
GNDC
RD
WR
VCCC
BR
BG
WT
BN
NC
TIO
SRD/PC7
VCCQ
GNDQ
SC1/PC4
NC
GNDS
STD/PC8
SC2/PC5
SCK/PC6
VCCS
SC0/PC3
SCLK/PC2
GNDS
TXD/PC1
RXD/PC0
H0/PB0
H1/PB1
GNDH
H2/PB2
VCCH
H3/PB3
H4/PB4
NC
NC
D22
D23
MODC/NMI
MODB/IRQB
MODA/IRQA
GNDCK
CKOUT
VCCCK
RESET
CKP
VCCP
PCAP
GNDP
PLOCK
PINIT
XTAL
NC
EXTAL
VCCQ
GNDQ
HA2/PB10
GNDH
HA1/PB9
HA0/PB8
HACK/PB14
VCCH
HEN/PB12
GNDH
HR/W/PB11
HREQ/PB13
H7/PB7
H6/PB6
GNDH
H5/PB5
NC
NC
D0
D1
GNDD
D2
D3
VCCD
D4
D5
GNDD
D6
D7
D8
D9
VCCQ
GNDQ
GNDD
D10
NC
D11
VCCD
D12
D13
GNDD
D14
D15
D16
D17
GNDD
D18
D19
VCCD
D20
D21
GNDD
NC
73
NC
A15
A14
GNDA
A13
VCCA
A12
A11
A10
GNDA
A9
A8
A7
A6
GNDA
VCCA
A5
NC
GNDQ
VCCQ
A4
A3
A2
GNDA
A1
A0
PS
VCCA
DS
GNDA
X/Y
BS
DSI/OS0
DSO
DR
NC
Top and bottom views of the TQFP package are shown in Figure 3-4 and Figure 3-5
with their pin-outs.
Note:
1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.
2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
3. To simplify locating the pins, each fifth pin is shaded in the illustration.
AA0613
Figure 3-4 Top View of the 144-pin Thin Quad Flat Pack (TQFP) Package
3-12
DSP56002/D, Rev. 3
MOTOROLA
Packaging
109
(Bottom View)
Orientation Mark
(on Top Side)
1
37
NC
D0
D1
GNDD
D2
D3
VCCD
D4
D5
GNDD
D6
D7
D8
D9
VCCQ
GNDQ
GNDD
D10
NC
D11
VCCD
D12
D13
GNDD
D14
D15
D16
D17
GNDD
D18
D19
VCCD
D20
D21
GNDD
NC
NC
H5/PB5
GNDH
H6/PB6
H7/PB7
HREQ/PB13
HR/W/PB11
GNDH
HEN/PB12
VCCH
HACK/PB14
HA0/PB8
HA1/PB9
GNDH
HA2/PB10
GNDQ
VCCQ
EXTAL
NC
XTAL
PINIT
PLOCK
GNDP
PCAP
VCCP
CKP
RESET
VCCCK
CKOUT
GNDCK
MODA/IRQA
MODB/IRQB
MODC/NMI
D23
D22
NC
NC
DSCK/OS1
NC
GNDC
RD
WR
VCCC
BR
BG
WT
BN
NC
TIO
SRD/PC7
VCCQ
GNDQ
SC1/PC4
NC
GNDS
STD/PC8
SC2/PC5
SCK/PC6
VCCS
SC0/PC3
SCLK/PC2
GNDS
TXD/PC1
RXD/PC0
H0/PB0
H1/PB1
GNDH
H2/PB2
VCCH
H3/PB3
H4/PB4
NC
73
NC
DR
DSO
DSI/OS0
BS
X/Y
GNDA
DS
VCCA
PS
A0
A1
GNDA
A2
A3
A4
VCCQ
GNDQ
NC
A5
VCCA
GNDA
A6
A7
A8
A9
GNDA
A10
A11
A12
VCCA
A13
GNDA
A14
A15
NC
Pin-out and Package Information
Note:
1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.
2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
3. To simplify locating the pins, each fifth pin is shaded in the illustration.
AA0614
Figure 3-5 Bottom View of the144-pin Thin Quad Flat Pack (TQFP) Package
MOTOROLA
DSP56002/D, Rev. 3
3-13
Packaging
Pin-out and Package Information
The DSP56002 signals that may be programmed as General Purpose I/O are listed
with their primary function in Table 3-9.
Table 3-5 DSP56002 General Purpose I/O Pin Identification in TQFP Package
3-14
Pin Number
Primary Function
Port
GPIO ID
44
H0
B
PB0
43
H1
PB1
41
H2
PB2
39
H3
PB3
38
H4
PB4
35
H5
PB5
33
H6
PB6
32
H7
PB7
25
HA0
PB8
24
HA1
PB9
22
HA2
PB10
30
HR/W
PB11
28
HEN
PB12
31
HREQ
PB13
26
HACK
PB14
45
RXD
46
TXD
PC1
48
SCLK
PC2
49
SC0
PC3
56
SC1
PC4
52
SC2
PC5
51
SCK
PC6
59
SRD
PC7
53
STD
PC8
60
TIO
No port assigned
DSP56002/D, Rev. 3
C
PC0
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-6 DSP56002 Signal Identification by TQFP Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
NC
26
HACK/PB14
51
SCK/PC6
2
D22
27
VCCH
52
SC2/PC5
3
D23
28
HEN/PB12
53
STD/PC8
4
MODC/NMI
29
GNDH
54
GNDS
5
MODB/IRQB
30
HR/W/PB11
55
NC
6
MODA/IRQA
31
HREQ/PB13
56
SC1/PC4
7
GNDCK
32
H7/PB7
57
GNDQ
8
CKOUT
33
H6/PB6
58
VCCQ
9
VCCCK
34
GNDH
59
SRD/PC7
10
RESET
35
H5/PB5
60
TIO
11
CKP
36
NC
61
NC
12
VCCP
37
NC
62
BN
13
PCAP
38
H4/PB4
63
WT
14
GNDP
39
H3/PB3
64
BG
15
PLOCK
40
VCCH
65
BR
16
PINIT
41
H2/PB2
66
VCCC
17
XTAL
42
GNDH
67
WR
18
NC
43
H1/PB1
68
RD
19
EXTAL
44
H0/PB0
69
GNDC
20
VCCQ
45
RXD/PC0
70
NC
21
GNDQ
46
TXD/PC1
71
DSCK/OS1
22
HA2/PB10
47
GNDS
72
NC
23
GNDH
48
SCLK/PC2
73
NC
24
HA1/PB9
49
SC0/PC3
74
DR
25
HA0/PB8
50
VCCS
75
DSO
MOTOROLA
DSP56002/D, Rev. 3
3-15
Packaging
Pin-out and Package Information
Table 3-6 DSP56002 Signal Identification by TQFP Pin Number (Continued)
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
76
DSI/OS0
99
GNDA
122
D9
77
BS
100
A10
123
VCCQ
78
X/Y
101
A11
124
GNDQ
79
GNDA
102
A12
125
GNDD
80
DS
103
VCCA
126
D10
81
VCCA
104
A13
127
NC
82
PS
105
GNDA
128
D11
83
A0
106
A14
129
VCCD
84
A1
107
A15
130
D12
85
GNDA
108
NC
131
D13
86
A2
109
NC
132
GNDD
87
A3
110
D0
133
D14
88
A4
111
D1
134
D15
89
VCCQ
112
GNDD
135
D16
90
GNDQ
113
D2
136
D17
91
NC
114
D3
137
GNDD
92
A5
115
VCCD
138
D18
93
VCCA
116
D4
139
D19
94
GNDA
117
D5
140
VCCD
95
A6
118
GNDD
141
D20
96
A7
119
D6
142
D21
97
A8
120
D7
143
GNDD
98
A9
121
D8
144
NC
Note:
1.
2.
3-16
“NC” are No Connection pins that are reserved for possible future enhancements.
Do not connect these pins to any power, ground, signal traces, or vias.
An OVERBAR indicates the signal is asserted when the voltage = ground (active
low).
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-7 DSP56002 TQFP Pin Identification by Signal Name
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
A0
83
D3
114
DSO
75
A1
84
D4
116
EXTAL
19
A2
86
D5
117
GNDA
79
A3
87
D6
119
GNDA
85
A4
88
D7
120
GNDA
94
A5
92
D8
121
GNDA
99
A6
95
D9
122
GNDA
105
A7
96
D10
126
GNDC
69
A8
97
D11
128
GNDCK
7
A9
98
D12
130
GNDD
112
A10
100
D13
131
GNDD
118
A11
101
D14
133
GNDD
125
A12
102
D15
134
GNDD
132
A13
104
D16
135
GNDD
137
A14
106
D17
136
GNDD
143
A15
107
D18
138
GNDH
23
BG
64
D19
139
GNDH
29
BN
62
D20
141
GNDH
34
BR
65
D21
142
GNDH
42
BS
77
D22
2
GNDP
14
CKOUT
8
D23
3
GNDQ
21
CKP
11
DR
74
GNDQ
57
D0
110
DS
80
GNDQ
90
D1
111
DSCK
71
GNDQ
124
D2
113
DSI
76
GNDS
47
MOTOROLA
DSP56002/D, Rev. 3
3-17
Packaging
Pin-out and Package Information
Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued)
3-18
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
GNDS
54
PB1
43
PLOCK
15
H0
44
PB2
41
PS
82
H1
43
PB3
39
RD
68
H2
41
PB4
38
RESET
10
H3
39
PB5
35
RXD
45
H4
38
PB6
33
SC0
49
H5
35
PB7
32
SC1
56
H6
33
PB8
25
SC2
52
H7
32
PB9
24
SCK
51
HA0
25
PB10
22
SCLK
48
HA1
24
PB11
30
SRD
59
HA2
22
PB12
28
STD
53
HACK
26
PB13
31
TIO
60
HEN
28
PB14
26
TXD
46
HR/W
30
PC0
45
VCCA
81
HREQ
31
PC1
46
VCCA
93
IRQA
6
PC2
48
VCCA
103
IRQB
5
PC3
49
VCCC
66
MODA
6
PC4
56
VCCCK
9
MODB
5
PC5
52
VCCD
115
MODC
4
PC6
51
VCCD
129
NMI
4
PC7
59
VCCD
140
OS0
76
PC8
53
VCCH
27
OS1
71
PCAP
13
VCCH
40
PB0
44
PINIT
16
VCCP
12
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued)
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
VCCQ
20
XTAL
17
nc
72
VCCQ
58
nc
70
nc
73
VCCQ
89
nc
1
nc
91
VCCQ
123
nc
18
nc
108
VCCS
50
nc
36
nc
109
WR
67
nc
37
nc
127
WT
63
nc
55
nc
144
X/Y
78
nc
61
MOTOROLA
DSP56002/D, Rev. 3
3-19
Packaging
Pin-out and Package Information
Power and ground pins have special considerations for noise immunity. See the
section Design Considerations.
Table 3-8 DSP56002 Power Supply Pins in TQFP Package
Pin Number
Power Supply
Circuit Supplied
81
93
VCCA
103
Address
Bus
Buffers
79
85
94
GNDA
99
105
66
VCCC
69
GNDC
9
VCCCK
7
GNDCK
115
129
Bus Control
Buffers
Clock
VCCD
140
112
118
125
GNDD
Data
Bus
Buffers
132
137
143
27
40
VCCH
23
29
34
GNDH
Host
Interface
Buffers
42
3-20
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-8 DSP56002 Power Supply Pins in TQFP Package (Continued)
Pin Number
Power Supply
Circuit Supplied
20
58
89
VCCQ
123
Internal Logic
21
57
90
GNDQ
124
12
VCCP
14
GNDP
50
VCCS
47
54
MOTOROLA
GNDS
DSP56002/D, Rev. 3
PLL
Serial Port
3-21
Packaging
Pin-out and Package Information
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 36 TIPS
144
109
108
1
4X
J1
P
J1
M
L
CL
B
V
140X
B1 V1
VIEW Y
36
VIEW Y
73
NOTES:
9. DIMENSIONS AND TOLERANCING PER ASME
Y14.5, 1994.
10.DIMENSIONS IN MILLIMETERS.
11.DATUMS L, M AND N TO BE DETERMINED AT
THE SEATING PLANE, DATUM T.
12.DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
13.DIMENSIONS A AND B DO NOT INCULDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE H.
14.DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLED DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.35.
72
37
N
A1
S1
A
S
VIEW AB
C
0.1 T
θ2
144X
SEATING
PLANE
θ2
T
PLATING
J
F
AA
C2
— 0.05
R2
θ
R1
D
0.08
M
0.25
BASE
METAL
GAGE PLANE
T L-M N
SECTION J1-J1
(ROTATED 90)
144 PL
(K)
C1
E
(Y)
VIEW AB
X
X=L, M OR N
G
θ1
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
θ
θ1
θ2
MILLIMETERS
MIN
MAX
20.00 BSC
10.00 BSC
20.00 BSC
10.00 BSC
1.40
1.60
0.05
0.15
1.35
1.45
0.17
0.27
0.45
0.75
0.17
0.23
0.50 BSC
0.09
0.20
0.50 REF
0.25 BSC
0.13
0.20
0.13
0.20
22.00 BSC
11.00 BSC
22.00 BSC
11.00 BSC
0.25 REF
1.00 REF
0.09
0.16
0°
0°
7°
11°
13°
(Z)
CASE 918-03
ISSUE C
Figure 3-6 144-pin Thin Plastic Quad Flat Pack (TQFP) Mechanical Information
3-22
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
PGA Package Description
Top and bottom views of the PGA package are shown in Figure 3-7 and Figure 3-8
with their pin-outs.
Orientation
Mark
1
2
3
4
5
6
7
8
9
10
11
12
13
GNDQ
VCCQ
GNDQ
VCCQ
GNDQ
VCCQ
GNDQ
VCCQ
HA2
HACK
H6
GNDH
GNDH
GNDD
VCCCK RESET
CKP
VCCP
PCAP
PLOCK
XTAL
HA1
HEN
H7
H5
VCCH
VCCD
MODB/ MODA/ GNDCK CKOUT GNDP
IRQA
IRQB
PINIT
EXTAL
HA0
HREQ
H2
RXD
GNDH
HR/W
H4
H1
TXD
VCCH
H3
H0
SCLK
GNDH
A
B
C
D
GNDD
D20
D21
D23
GNDD
D18
D19
D22
D15
D16
D17
SC0
SCK
SC2
D14
D13
D12
STD
SC1
SRD
D11
D10
D9
TIO
NC
BN
VCCD
D8
D7
A15
RD
WR
WT
GNDS
GNDD
D6
D5
A14
A11
A0
X/Y
DR
BG
VCCS
GNDD
D4
D3
A13
A10
A8
A6
A3
A1
DS
DSO
BR
GNDS
VCCD
D2
D1
A12
A9
A7
A5
A4
A2
PS
DSI/OS0
NC
VCCC
GNDD
D0
GNDA
VCCA
GNDA
GNDA
VCCA
GNDA
VCCA
GNDA
BS
DSCK/
OS1
GNDC
MODC/
NMI
E
F
G
H
Top View
J
K
L
M
N
Note:
1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.
2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
AA0615
Figure 3-7 Top View of the 132-pin Ceramic (RC) 13 ×13 Pin Grid Array Package
MOTOROLA
DSP56002/D, Rev. 3
3-23
Packaging
Pin-out and Package Information
Orientation Mark
(on Top Side)
13
12
11
10
9
8
7
6
5
4
3
2
1
GNDH
GNDH
H6
HACK
HA2
VCCQ
GNDQ
VCCQ
GNDQ
VCCQ
GNDQ
VCCQ
GNDQ
VCCH
H5
H7
HEN
HA1
XTAL
PLOCK
PCAP
VCCP
CKP
RESET VCCCK
GNDD
GNDH
RXD
H2
HREQ
HA0
EXTAL
PINIT
GNDP
CKOUT GNDCK MODA/ MODB/
IRQA
IRQB
VCCD
VCCH
TXD
H1
H4
HR/W
GNDH
SCLK
H0
H3
SC2
SCK
SRD
A
B
C
D
D23
D21
D20
GNDD
D22
D19
D18
GNDD
SC0
D17
D16
D15
SC1
STD
D12
D13
D14
BN
NC
TIO
D9
D10
D11
GNDS
WT
WR
RD
A15
D7
D8
VCCD
VCCS
BG
DR
X/Y
A0
A11
A14
D5
D6
GNDD
GNDS
BR
DSO
DS
A1
A3
A6
A8
A10
A13
D3
D4
GNDD
VCCC
NC
DSI/OS0
PS
A2
A4
A5
A7
A9
A12
D1
D2
VCCD
GNDC
DSCK/
OS1
BS
GNDA
VCCA
GNDA
VCCA
GNDA
GNDA
VCCA
GNDA
D0
GNDD
MODC/
NMI
E
F
G
H
Bottom View
J
K
L
M
N
Note:
1. “NC” are No Connection pins that are reserved for possible future enhancements. Do not
connect these pins to any power, ground, signal traces, or vias.
2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
AA0616
Figure 3-8 Bottom View of the 132-pin Ceramic (RC) 13 ×13 Pin Grid Array Package
3-24
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
The DSP56008 signals that may be programmed as General Purpose I/O are listed
with their primary function in Table 3-9.
Table 3-9 DSP56002 General Purpose I/O Pin Identification in PGA Package
MOTOROLA
Pin Number
Primary Function
Port
GPIO ID
E11
H0
B
PB0
D11
H1
PB1
C11
H2
PB2
E10
H3
PB3
D10
H4
PB4
B12
H5
PB5
A11
H6
PB6
B11
H7
PB7
C9
HA0
PB8
B9
HA1
PB9
A9
HA2
PB10
D9
HR/W
PB11
B10
HEN
PB12
C10
HREQ
PB13
A10
HACK
PB14
C12
RXD
D12
TXD
PC1
E12
SCLK
PC2
F11
SC0
PC3
G12
SC1
PC4
F13
SC2
PC5
F12
SCK
PC6
G13
SRD
PC7
G11
STD
PC8
H11
TIO
No port assigned
DSP56002/D, Rev. 3
C
PC0
3-25
Packaging
Pin-out and Package Information
Table 3-10 DSP56002 Signal Identification by PGA Pin Number
3-26
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
A1
GNDQ
B13
VCCH
E2
D18
A2
VCCQ
C1
VCCD
E3
D19
A3
GNDQ
C2
MODB/IRQB
E4
D22
A4
VCCQ
C3
MODA/IRQA
E10
H3/PB3
A5
GNDQ
C4
GNDCK
E11
H0/PB0
A6
VCCQ
C5
CKOUT
E12
SCLK/PC2
A7
GNDQ
C6
GNDP
E13
GNDH
A8
VCCQ
C7
PINIT
F1
D15
A9
HA2/PB10
C8
EXTAL
F2
D16
A10
HACK/PB14
C9
HA0/PB8
F3
D17
A11
H6/PB6
C10
HREQ/PB13
F11
SC0/PC3
A12
GNDH
C11
H2/PB2
F12
SCK/PC6
A13
GNDH
C12
RXD/PC0
F13
SC2/PC5
B1
GNDD
C13
GNDH
G1
D14
B2
VCCCK
D1
GNDD
G2
D13
B3
RESET
D2
D20
G3
D12
B4
CKP
D3
D21
G11
STD/PC8
B5
VCCP
D4
D23
G12
SC1/PC4
B6
PCAP
D5
MODC/NMI
G13
SRD/PC7
B7
PLOCK
D9
HR/W/PB11
H1
D11
B8
XTAL
D10
H4/PB4
H2
D10
B9
HA1/PB9
D11
H1/PB1
H3
D9
B10
HEN/PB12
D12
TXD/PC1
H11
TIO*
B11
H7/PB7
D13
VCCH
H12
NC
B12
H5/PB5
E1
GNDD
H13
BN
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-10 DSP56002 Signal Identification by PGA Pin Number (Continued)
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
J1
VCCD
L2
D4
M8
A4
J2
D8
L3
D3
M9
A2
J3
D7
L4
A13
M10
PS
J4
A15
L5
A10
M11
DSI/OS0
J10
RD
L6
A8
M12
NC
J11
WR
L7
A6
M13
VCCC
J12
WT
L8
A3
N1
GNDD
J13
GNDS
L9
A1
N2
D0
K1
GNDD
L10
DS
N3
GNDA
K2
D6
L11
DSO
N4
VCCA
K3
D5
L12
BR
N5
GNDA
K4
A14
L13
GNDS
N6
GNDA
K5
A11
M1
VCCD
N7
VCCA
K9
A0
M2
D2
N8
GNDA
K10
X/Y
M3
D1
N9
VCCA
K11
DR
M4
A12
N10
GNDA
K12
BG
M5
A9
N11
BS
K13
VCCS
M6
A7
N12
DSCK/OS1
L1
GNDD
M7
A5
N13
GNDC
Note:
1.
2.
MOTOROLA
NC” are No Connection pins that are reserved for possible future enhancements.
Do not connect these pins to any power, ground, signal traces, or vias.
An OVERBAR indicates the signal is asserted when the voltage = ground (active
low).
DSP56002/D, Rev. 3
3-27
Packaging
Pin-out and Package Information
Table 3-11 DSP56002 PGA Pin Identification by Signal Name
3-28
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
A0
K9
D3
L3
DSO
L11
A1
L9
D4
L2
EXTAL
C8
A2
M9
D5
K3
GNDA
N10
A3
L8
D6
K2
GNDA
N8
A4
M8
D7
J3
GNDA
N6
A5
M7
D8
J2
GNDA
N5
A6
L7
D9
H3
GNDA
N3
A7
M6
D10
H2
GNDC
N13
A8
L6
D11
H1
GNDCK
C4
A9
M5
D12
G3
GNDD
N1
A10
L5
D13
G2
GNDD
L1
A11
K5
D14
G1
GNDD
K1
A12
M4
D15
F1
GNDD
E1
A13
L4
D16
F2
GNDD
D1
A14
K4
D17
F3
GNDD
B1
A15
J4
D18
E2
GNDH
A12
BG
K12
D19
E3
GNDH
A13
BN
H13
D20
D2
GNDH
C13
BR
L12
D21
D3
GNDH
E13
BS
N11
D22
E4
GNDP
C6
CKOUT
C5
D23
D4
GNDQ
A1
CKP
B4
DR
K11
GNDQ
A2
D0
N2
DS
L10
GNDQ
A5
D1
M3
DSCK
N12
GNDQ
A7
D2
M2
DSI
M11
GNDS
J13
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-11 DSP56002 PGA Pin Identification by Signal Name (Continued)
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
GNDS
L13
PB5
B12
SCK
F12
H0
E11
PB6
A11
SCLK
E12
H1
D11
PB7
B11
SRD
G13
H2
C11
PB8
C9
STD
G11
H3
E10
PB9
B9
TIO
H11
H4
D10
PB10
A9
TXD
D12
H5
B12
PB11
D9
VCCA
N9
H6
A11
PB12
B10
VCCA
N7
H7
B11
PB13
C10
VCCA
N4
HA0
C9
PB14
A10
VCCC
M13
HA1
B9
PC0
C12
VCCCK
B2
HA2
A9
PC1
D12
VCCD
M1
HACK
A10
PC2
E12
VCCD
J1
HEN
B10
PC3
F11
VCCD
C1
HR/W
D9
PC4
G12
VCCH
B13
HREQ
C10
PC5
F13
VCCH
D13
IRQA
C3
PC6
F12
VCCP
B5
IRQB
C2
PC7
G13
VCCQ
A2
MODA
C3
PC8
G11
VCCQ
A4
MODB
C2
PCAP
B6
VCCQ
A6
MODC
D5
PINIT
C7
VCCQ
A8
NMI
D5
PLOCK
B7
VCCS
K13
OS0
M11
PS
M10
WR
J11
OS1
N12
RD
J10
WT
J12
PB0
E11
RESET
B3
X/Y
K10
PB1
D11
RXD
C12
XTAL
B8
PB2
C11
SC0
F11
nc
H12
PB3
E10
SC1
G12
nc
M12
PB4
D10
SC2
F13
MOTOROLA
DSP56002/D, Rev. 3
3-29
Packaging
Pin-out and Package Information
Power and ground pins have special considerations for noise immunity. See the
section Design Considerations.
Table 3-12 DSP56002 Power Supply Pins in PGA Package
Pin Number
Power Supply
Circuit Supplied
N9
N7
VCCA
N4
Address
Bus
Buffers
N10
N8
N6
GNDA
N5
N3
M13
VCCC
N13
GNDC
B2
VCCCK
C4
GNDCK
M1
J1
Bus Control
Buffers
Clock
VCCD
C1
N1
L1
K1
GNDD
Data
Bus
Buffers
E1
D1
B1
B13
D13
VCCH
A12
A13
C13
GNDH
Host
Interface
Buffers
E13
3-30
DSP56002/D, Rev. 3
MOTOROLA
Packaging
Pin-out and Package Information
Table 3-12 DSP56002 Power Supply Pins in PGA Package (Continued)
Pin Number
Power Supply
Circuit Supplied
A8
A6
VCCQ
A4
A2
Internal Logic
A1
A2
GNDQ
A5
A7
B5
VCCP
C6
GNDP
K13
VCCS
J13
PLL
Serial Port
GNDS
L13
-TK
-A-
G
N
M
L
K
J
H
G
F
E
D
C
B
A
G
NOTES:
1.
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2.
2. CONTROLLING DIMENSION: INCH.
DIM
A
B
C
D
G
K
INCHES
MIN
MAX
1.340
1.380
1.340
1.380
0.100
0.150
0.017
0.022
0.100 BSC
0.170
0.195
1 2 3 4 5 6 7 8 9 10 11 12 13
-BC
D 132 PL
0.005 M T A S B S
CASE 789B-01
ISSUE O
Figure 3-9 132-pin Ceramic Pin Grid Array (PGA) Package Mechanical Information
MOTOROLA
DSP56002/D, Rev. 3
3-31
Packaging
Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information regarding DSP56002 packaging is available by
facsimile through Motorola's Mfax™ system. Call the following number to obtain
information by facsimile:
(602) 244-6591
The Mfax automated system requests the following information:
•
The receiving facsimile telephone number including area code or country
code
•
The caller’s Personal Identification Number (PIN)
Note: For first time callers, the system provides instructions for setting up a PIN,
which requires entry of a name and telephone number.
•
The type of information requested:
–
Instructions for using the system
–
A literature order form
–
Specific part technical information or data sheets
–
Other information described by the system messages
A total of three documents may be ordered per call.
The DSP56002 132-pin PQFP package mechanical drawing is referenced as 831A-02.
The reference number for the 144-pin TQFP package is 918-03. The reference number
for the 132-pin ceramic PGA package is 789B-01.
3-32
DSP56002/D, Rev. 3
MOTOROLA
SECTION
4
DESIGN CONSIDERATIONS
HEAT DISSIPATION
An estimation of the chip junction temperature, TJ, in °C can be obtained from the
equation:
Equation 1: T J = T A + ( P D × R θJA )
Where:
TA = ambient temperature ˚C
RθJA = package junction-to-ambient thermal resistance ˚C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:
Equation 2: R θJA = R θJC + R θCA
Where:
RθJA = package junction-to-ambient thermal resistance ˚C/W
RθJC = package junction-to-case thermal resistance ˚C/W
RθCA = package case-to-ambient thermal resistance ˚C/W
RθJC is device-related and cannot be influenced by the user. The user controls the
thermal environment to change the case-to-ambient thermal resistance, RθCA. For
example, the user can change the air flow around the device, add a heat sink, change
the mounting arrangement on the Printed Circuit Board, or otherwise change the
thermal dissipation capability of the area surrounding the device on a Printed Circuit
Board. This model is most useful for ceramic packages with heat sinks; some 90% of
the heat flow is dissipated through the case to the heat sink and out to the ambient
environment. For ceramic packages, in situations where the heat flow is split between
a path to the case and an alternate path through the Printed Circuit Board, analysis of
the device thermal performance may need the additional modeling capability of a
system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature
of the Printed Circuit Board to which the package is mounted. Again, if the
MOTOROLA
DSP56002/D, Rev. 3
4-1
Design Considerations
Heat Dissipation
estimations obtained from RθJA do not satisfactorily answer whether the thermal
performance is adequate, a system level model may be appropriate.
A complicating factor is the existence of three common ways for determining the
junction-to-case thermal resistance in plastic packages:
•
To minimize temperature variation across the surface, the thermal resistance
is measured from the junction to the outside surface of the package (case)
closest to the chip mounting area when that surface has a proper heat sink.
•
To define a value approximately equal to a junction-to-board thermal
resistance, the thermal resistance is measured from the junction to where the
leads are attached to the case.
•
If the temperature of the package case (TT) as determined by a thermocouple,
the thermal resistance is computed using the value obtained by the equation
(TJ – TT)/PD.
As noted above, the junction-to-case thermal resistances quoted in this data sheet are
determined using the first definition. From a practical standpoint, that value is also
suitable for determining the junction temperature from a case thermocouple reading
in forced convection environments. In natural convection, using the junction-to-case
thermal resistance to estimate junction temperature from a thermocouple reading on
the case of the package will estimate a junction temperature slightly hotter than
actual temperature. Hence, the new thermal metric, Thermal Characterization
Parameter or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better
estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the
sensor to the surface and to errors caused by heat loss to the sensor. The
recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
Note: Table 2-2 Thermal Characteristics on page 2-2 contains the package thermal
values for this chip.
4-2
DSP56002/D, Rev. 3
MOTOROLA
Design Considerations
Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Use the following list of recommendations to assure correct DSP operation:
MOTOROLA
•
Provide a low-impedance path from the board power supply to each VCC pin
on the DSP, and from the board ground to each GND pin.
•
Use at least four 0.1 µF bypass capacitors positioned as close as possible to the
four sides of the package to connect the VCC power source to GND.
•
Ensure that capacitor leads and associated printed circuit traces that connect
to the chip VCC and GND pins are less than 0.5 inch per capacitor lead.
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for
VCC and GND.
•
Because the DSP output signals have fast rise and fall times, PCB trace lengths
should be minimal. This recommendation particularly applies to the address
and data buses as well as the RD, WR, IRQA, IRQB, NMI, HEN, and HACK
pins.
•
Consider all device loads as well as parasitic capacitance due to PCB traces
when calculating capacitance. This is especially critical in systems with higher
capacitive loads that could create higher transient currents in the VCC and
GND circuits.
•
All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
•
Take special care to minimize noise levels on the PLL supply pins (both VCC
and GND).
DSP56002/D, Rev. 3
4-3
Design Considerations
Power Consumption
POWER CONSUMPTION
Power dissipation is a key issue in portable DSP applications. The following describes
some factors which affect current consumption. Current consumption is described by
the formula:
Equation 3: I = C × V × f
where:
C = node/pin capacitance
V = voltage swing
f = frequency of node/pin toggle
For example, for an address pin loaded with a 50 pF capacitance and operating at 5.5
V with a 40 MHz clock, toggling at its maximum possible rate (which is 10 MHz), the
current consumption is:
Equation 4: I = 50 × 10 –12 × 5.5 × 10 × 10 6 = 2.75mA
The maximum internal current value (ICCI-max), reflects the maximum ICC expected
when running the code given below. This represents “typical” internal activity, and is
included as a point of reference. Some applications may consume more or less current
depending on the code used. The typical internal current value (ICCI-typ) reflects
what is typically seen when running the given code.
The following steps are recommended for applications requiring very low current
consumption:
1. Minimize external memory accesses; use internal memory accesses instead.
2. Minimize the number of pins that are switching.
3. Minimize the capacitive load on the pins.
4. Connect the unused inputs to pull-up or pull-down resistors.
4-4
DSP56002/D, Rev. 3
MOTOROLA
Design Considerations
Power Consumption
Current consumption test code:
TP1
MOTOROLA
org
jmp
org
movep
move
move
move
move
nop
rep
move
rep
mov
clr
move
rep
mac
move
jmp
nop
jmp
p:RESET
MAIN
p:MAIN
#$180000,x:$FFFD
#0,r0
#0,r4
#$00FF, m0
#$00FF, m4
#256
r0,x:(r0)+
#256
r4,y:(r4)+
a
l:(r0)+,a
#30
x0,y0,a x:(r0)+,x0 y:(r4)+,y0
a,p:(r5)
TP1
MAIN
DSP56002/D, Rev. 3
4-5
Design Considerations
Host Port Considerations
HOST PORT CONSIDERATIONS
Careful synchronization is required when reading multibit registers that are written
by another asynchronous system. This is a common problem when two
asynchronous systems are connected. The situation exists in the host interface. The
following paragraphs present considerations for proper operation.
Host Programming Considerations
UNSYNCHRONIZED READING OF RECEIVE BYTE REGISTERS
When reading receive byte registers (RXH, RXM, and RXL) the host programmer
should use interrupts or poll the RXDF flag that indicates that data is available. This
assures that the data in the receive byte registers will be stable.
OVERWRITING TRANSMIT BYTE REGISTERS
The host programmer should not write to the transmit byte registers (TXH, TXM, and
TXL) unless the TXDE bit is set indicating that the transmit byte registers are empty.
This guarantees that the transmit byte registers will transfer valid data to the HRX
register.
SYNCHRONIZATION OF STATUS BITS FROM DSP TO HOST
HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared
from inside the DSP and read by the host processor. The host can read these status
bits very quickly without regard to the clock rate used by the DSP, but the possibility
exists that the state of the bit could be changing during the read operation. This is
generally not a system problem, since the bit will be read correctly in the next pass of
any host polling routine.
Note: Refer to DSP56002 User’s Manual sections describing the I/O Interface and
Host/DMA Interface Programming Model for descriptions of these status
bits.
OVERWRITING THE HOST VECTOR
The Host programmer should change the Host Vector register only when the Host
Command bit (HC) is clear. This change guarantees that the DSP interrupt control
logic will receive a stable vector.
4-6
DSP56002/D, Rev. 3
MOTOROLA
Design Considerations
Host Port Considerations
CANCELLING A PENDING HOST COMMAND EXCEPTION
The host processor may elect to clear the HC bit to cancel the Host Command
Exception request at any time before it is recognized by the DSP. Because the host
does not know exactly when the exception will be recognized (due to exception
processing synchronization and pipeline delays), the DSP may execute the Host
Command Exception after the HC bit is cleared. For these reasons, the HV bits must
not be changed at the same time the HC bit is cleared.
VARIANCE IN THE HI TIMING
HI timing may vary during initial startup during the time after reset before the PLL
locks. Therefore, before a host attempt to load (i.e., bootstrap) the DSP, the host
should first make sure that the HI port programming has been completed. The
following steps can be used to ensure that the programming is complete:
1. Set the INIT bit in the ICR
2. Poll the INIT bit until it is cleared.
3. Read the ISR.
An alternate method is:
1. Write the TREQ/RREQ together with INIT.
2. Poll INIT, ISR, and the HREQ pin.
DSP Programming Considerations
SYNCHRONIZATION OF STATUS BITS FROM HOST TO DSP
DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host
processor side of the interface. These bits are individually synchronized to the DSP
clock.
Note: Refer to DSP56002 User’s Manual sections describing the I/O Interface and
Host/DMA Interface Programming Model for descriptions of these status
bits.
READING HF0 AND HF1 AS AN ENCODED PAIR
A potential problem exists when reading status bits HF0 and HF1 as an encoded pair
(i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small
probability exists that the DSP will read the status bits synchronized during
transition. The solution to this potential problem is to read the HF0 and HF1 bits
twice and check for consensus.
MOTOROLA
DSP56002/D, Rev. 3
4-7
Design Considerations
Package Compatibility
PACKAGE COMPATIBILITY
The PQFP and TQFP packages are designed so that a single Printed Circuit Board
(PCB) can accommodate either package. The two package pinouts are similarly
sequenced. Proper orientation of each package with the smaller TQFP footprint
inside the PQFP footprint allow connection of PCB traces to either package. For
example, the D0 pin is near the corner of both the PQFP package (pin 84) and the
TQFP package (pin 109), and is adjacent to D1 on both packages.
Note: Some “no connect” pins in the TQFP pin sequence are excluded from the
PQFP pin sequence.
4-8
DSP56002/D, Rev. 3
MOTOROLA
SECTION
5
ORDERING INFORMATION
DSP56002 ordering information in the table below lists the pertinent information
needed to place an order. Consult a Motorola Semiconductor sales office or
authorized distributor to determine availability and to order parts.
Table 5-1 DSP56002 Ordering Information
Part
Supply
Voltage
Package Type
Plastic Quad Flat Pack
(PQFP)
DSP56002
MOTOROLA
5V
Pin Count
132
Plastic Thin Quad Flat
Pack (TQFP)
144
Ceramic Pin Grid Array
132
DSP56002/D, Rev. 3
Frequency
(MHz)
Order Number
40
DSP56002FC40
66
DSP56002FC66
80
DSP56002FC80
40
DSP56002PV40
66
DSP56002PV66
80
DSP56002PV80
40
DSP56002RC40
5-1
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any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may
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