IS61LV256 32K x 8 LOW VOLTAGE CMOS STATIC RAM FEATURES High-speed access times: -- 8, 10, 12, 15, 20 ns Automatic power-down when chip is deselected CMOS low power operation -- 345 mW (max.) operating -- 7 mW (max.) CMOS standby TTL compatible interface levels Single 3.3V power supply Fully static operation: no clock or refresh required Three-state outputs DESCRIPTION The 1+51 IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256 is available in the JEDEC standard 28-pin, 300mil SOJ and the 8*13.4mm TSOP-1 package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 256 X 1024 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. SR004-0D 1 IS61LV256 PIN CONFIGURATION PIN CONFIGURATION 28-Pin SOJ 8x13.4mm TSOP-1 A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE A0-A14 Address Inputs Mode CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Not Selected (Power-down) Output Disabled Read Write Vcc Power GND Ground WE CE OE I/O Operation Vcc Current X H X High-Z ISB, ISB H H L L L L H L X High-Z DOUT DIN ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TBIAS Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Temperature Under Bias TSTG PD IOUT Storage Temperature Power Dissipation DC Output Current Com. Ind. Value 0.5 to +4.6 0.5 to +4.6 10 to +85 45 to +90 65 to +150 1 ±20 Unit V V °C °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Circuit Solution Inc. SR004-0D IS61LV256 OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C Industrial 40°C to +85°C Speed 8, 10, 12 15, 20 All VCC 3.3V, +10%, 5% 3.3V ± 10% 3.3V + 10%, 5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = 4.0 mA 2.4 V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage 0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VCC Com. Ind. 1 5 1 5 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. 1 5 1 5 µA Notes: 1. VIL (min.) = 0.3V (DC); VIL (min.) = 2.0V (pulse width ≤ 2.0 ns). VIH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns). 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 ns -10 ns -12 ns -15 ns -20 ns Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Com. Ind. 120 130 110 120 100 110 90 100 80 90 mA VCC = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. 25 30 25 30 25 30 25 30 25 30 mA VCC = Max., CE ≤ VCC 0.2V, VIN > VCC 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. 2 5 2 5 2 5 2 5 2 5 mA Sym. Parameter Test Conditions ICC Vcc Dynamic Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX ISB TTL Standby Current (TTL Inputs) ISB CMOS Standby Current (CMOS Inputs) Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 5 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. Integrated Circuit Solution Inc. SR004-0D 3 IS61LV256 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -8 ns Parameter Min. Max. -10 ns -12 ns -15 ns -20 ns Min. Max. Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 8 10 12 15 20 ns tAA Address Access Time 8 10 12 15 20 ns tOHA Output Hold Time 2 2 2 2 2 ns tACE CE Access Time 8 10 12 15 20 ns tDOE OE Access Time 4 5 6 7 8 ns tLZOE OE to Low-Z Output 0 0 0 0 0 ns tHZOE OE to High-Z Output 4 5 5 6 6 ns CE to Low-Z Output 3 3 3 3 3 ns tHZCE CE to High-Z Output 4 5 6 7 7 ns tPU! CE to Power-Up 0 0 0 0 0 ns tPD CE to Power-Down 8 10 12 15 20 ns tLZCE " Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 Ω 3.3V 3.3V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. 4 319 Ω 353 Ω 5 pF Including jig and scope 353 Ω Figure 2. Integrated Circuit Solution Inc. SR004-0D IS61LV256 AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t ACE t HZCE t LZCE DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Circuit Solution Inc. SR004-0D 5 IS61LV256 WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol -8 ns Parameter Min. Max. -10 ns -12 ns -15 ns -20 ns Min. Max. Min. Max. Min. Max. Min. Max. Unit tWC Write Cycle Time 8 10 12 15 20 ns tSCE CE to Write End 7 8 8 10 12 ns tAW Address Setup Time to Write End 7 8 8 10 12 ns tHA Address Hold from Write End 0 0 0 0 0 ns tSA Address Setup Time 0 0 0 0 0 ns tPWE1 WE Pulse Width(OE High) 7 10 12 15 20 ns tPWE2 WE Pulse Width(OE Low) 6.5 7 8 10 12 ns tSD Data Setup to Write End 4.5 5 6 7 10 ns tHD Data Hold from Write End 0 0 0 0 0 ns ! tHZWE WE LOW to High-Z Output 3.5 4 6 7 7 ns tLZWE ! WE HIGH to Low-Z Output 0 0 0 0 0 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN 6 t HD DATAIN VALID Integrated Circuit Solution Inc. SR004-0D IS61LV256 WRITE CYCLE NO. 2(WE Controlled, OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. Integrated Circuit Solution Inc. SR004-0D 7 IS61LV256 ORDERING INFORMATION Commercial Range: 0°C to +70°C ORDERING INFORMATION Industrial Range: 40°C to +85°C Speed (ns) Order Part No. Package Speed (ns) Order Part No. Package 8 IS61LV256-8T IS61LV256-8J 8*13.4mm TSOP-1 300mil SOJ 8 IS61LV256-8TI IS61LV256-8JI 8*13.4mm TSOP-1 300mil SOJ 10 IS61LV256-10T IS61LV256-10J 8*13.4mm TSOP-1 300mil SOJ 10 IS61LV256-10TI IS61LV256-10JI 8*13.4mm TSOP-1 300mil SOJ 12 IS61LV256-12T IS61LV256-12J 8*13.4mm TSOP-1 300mil SOJ 12 IS61LV256-12TI IS61LV256-12JI 8*13.4mm TSOP-1 300mil SOJ 15 IS61LV256-15T IS61LV256-15J 8*13.4mm TSOP-1 300mil SOJ 15 IS61LV256-15TI IS61LV256-15JI 8*13.4mm TSOP-1 300mil SOJ 20 IS61LV256-15T IS61LV256-20J 8*13.4mm TSOP-1 300mil SOJ 20 IS61LV256-20TI IS61LV256-20JI 8*13.4mm TSOP-1 300mil SOJ Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 8 Integrated Circuit Solution Inc. SR004-0D