ISSI IS62LV256L 32K x 8 LOW VOLTAGE CMOS STATIC RAM ® APRIL 1999 FEATURES • High-speed access time: 15, 20, 25 ns • Automatic power-down when chip is deselected • CMOS low power operation — 255 mW (max.) operating — 0.18 mW (max.) CMOS standby • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three-state outputs DESCRIPTION The ISSI IS62LV256L is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV256L is available in the JEDEC standard 28-pin SOJ and the 450-mil TSOP package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 256 X 1024 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. SR033-1A 04/27/99 1 ISSI IS62LV256L PIN CONFIGURATION PIN CONFIGURATION 28-Pin SOJ 28-Pin TSOP A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 CE OE WE OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 Mode Chip Enable Input Not Selected (Power-down) Output Disabled Read Write Write Enable Input I/O0-I/O7 Input/Output Vcc Power GND Ground A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE Address Inputs Output Enable Input 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 ® WE CE OE I/O Operation Vcc Current X H X High-Z ISB1, ISB2 H H L L L L H L X High-Z DOUT DIN ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +4.6 –55 to +125 –65 to +150 0.5 20 Unit V °C °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. SR033-1A 04/27/99 ISSI IS62LV256L ® OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V +10% 3.3V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VCC Com. Ind. –2 –5 2 5 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. –2 –5 2 5 µA Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -15 ns Min. Max. Test Conditions -20 ns Min. Max. -25 ns Min. Max. Unit ICC1 Vcc Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = 0 Com. Ind. — — 1 2 — — 1 2 — — 1 2 mA ICC2 Vcc Dynamic Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. — — 70 80 — — 60 70 — — 50 60 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. — — 3 5 — — 3 5 — — 3 5 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., Com. Ind. — — 80 100 — — 80 100 CE ≤ VCC – 0.2V, — 80 — 100 µA VIN > VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 5 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. Integrated Silicon Solution, Inc. SR033-1A 04/27/99 3 ISSI IS62LV256L ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -15 ns Min. Max. Parameter -20 ns Min. Max. -25 ns Min. Max. Unit tRC Read Cycle Time 15 — 20 — 25 — ns tAA Address Access Time — 15 — 20 — 25 ns tOHA Output Hold Time 2 — 2 — 2 — ns — 15 — 20 — 25 ns — 7 — 8 — 9 ns 0 — 0 — 0 — ns — 8 — 9 — 10 ns 3 — 3 — 3 — ns — 6 — 9 — 10 ns 0 — 0 — 0 — ns — 15 — 18 — 20 ns tACE tDOE tLZOE (2) tHZOE tLZCE (2) (2) tHZCE(2) tPU (3) tPD (3) CE Access Time OE Access Time OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 635 Ω 3.3V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. 4 635 Ω 3.3V 702 Ω 5 pF Including jig and scope 702 Ω Figure 2. Integrated Silicon Solution, Inc. SR033-1A 04/27/99 ISSI IS62LV256L ® AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tLZOE CE tACE tLZCE DOUT HIGH-Z tHZCE DATA VALID tPU SUPPLY CURRENT tHZOE tPD 50% ICC 50% ISB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. SR033-1A 04/27/99 5 ISSI IS62LV256L ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol -15 ns Min. Max. Parameter -20 ns Min. Max. -25 ns Min. Max. Unit tWC Write Cycle Time 15 — 20 — 25 — ns tSCE CE to Write End 10 — 13 — 15 — ns tAW Address Setup Time to Write End 10 — 15 — 20 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns Address Setup Time 0 — 0 — 0 — ns WE Pulse Width 10 — 13 — 15 — ns tSD Data Setup to Write End 8 — 10 — 12 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns — 7 — 8 — 10 ns 0 — 0 — 0 — ns tSA tPWE (4) tHZWE(2) tLZWE (2) WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ADDRESS tHA tSCE CE tAW tPWE WE tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN 6 tHD DATA-IN VALID Integrated Silicon Solution, Inc. SR033-1A 04/27/99 ISSI IS62LV256L ® WRITE CYCLE NO. 2 (CE Controlled)(1,2) tWC ADDRESS tSA tHA tSCE CE tAW tPWE WE tHZWE DOUT DATA UNDEFINED tLZWE HIGH-Z tHD tSD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. ORDERING INFORMATION Commercial Range: 0°C to +70°C ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Speed (ns) Order Part No. Package Order Part No. Package 15 IS62LV256L-15T IS62LV256L-15J 450-mil TSOP 300-mil Plastic SOJ 15 IS62LV256L-15TI IS62LV256L-15JI 450-mil TSOP 300-mil Plastic SOJ 20 IS62LV256L-20T IS62LV256L-20J 450-mil TSOP 300-mil Plastic SOJ 20 IS62LV256L-20TI IS62LV256L-20JI 450-mil TSOP 300-mil Plastic SOJ 25 IS62LV256L-25T IS62LV256L-25J 450-mil TSOP 300-mil Plastic SOJ 25 IS62LV256L-25TI IS62LV256L-25JI 450-mil TSOP 300-mil Plastic SOJ ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com Integrated Silicon Solution, Inc. SR033-1A 04/27/99 7