TI LMD18200T 3a, 55v h-bridge Datasheet

LMD18200
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SNVS091F – DECEMBER 1999 – REVISED APRIL 2013
LMD18200 3A, 55V H-Bridge
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FEATURES
APPLICATIONS
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Delivers Up to 3A Continuous Output
Operates at Supply Voltages Up to 55V
Low RDS(ON) Typically 0.33Ω per Switch at 3A
TTL and CMOS Compatible Inputs
No “Shoot-Through” Current
Thermal Warning Flag Output at 145°C
Thermal Shutdown (Outputs Off) at 170°C
Internal Clamp Diodes
Shorted Load Protection
Internal Charge Pump with External Bootstrap
Capability
DC and Stepper Motor Drives
Position and Velocity Servomechanisms
Factory Automation Robots
Numerically Controlled Machinery
Computer Printers and Plotters
DESCRIPTION
The LMD18200 is a 3A H-Bridge designed for motion
control applications. The device is built using a multitechnology process which combines bipolar and
CMOS control circuitry with DMOS power devices on
the same monolithic structure. Ideal for driving DC
and stepper motors; the LMD18200 accommodates
peak output currents up to 6A. An innovative circuit
which facilitates low-loss sensing of the output current
has been implemented.
Functional Diagram
Figure 1. Functional Block Diagram of LMD18200
1
2
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LMD18200
SNVS091F – DECEMBER 1999 – REVISED APRIL 2013
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Connection Diagram
Figure 2. 11-Lead TO-220 Package
Top View
See Package NDJ0011B
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Total Supply Voltage (VS, Pin 6)
60V
Voltage at Pins 3, 4, 5, 8 and 9
Voltage at Bootstrap Pins
12V
(Pins 1 and 11)
VOUT +16V
Peak Output Current (200 ms)
Power Dissipation
6A
(3)
Continuous Output Current
3A
(4)
25W
Power Dissipation (TA = 25°C, Free Air)
3W
Junction Temperature, TJ(max)
ESD Susceptibility
150°C
(5)
1500V
−40°C to +150°C
Storage Temperature, TSTG
Lead Temperature (Soldering, 10 sec.)
(1)
300°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its rated operating conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
See Application Information for details regarding current limiting.
The maximum power dissipation must be derated at elevated temperatures and is a function of TJ(max), θJA, and TA. The maximum
allowable power dissipation at any temperature is PD(max) = (TJ(max) − TA)/θJA, or the number given in the Absolute Ratings, whichever is
lower. The typical thermal resistance from junction to case (θJC) is 1.0°C/W and from junction to ambient (θJA) is 30°C/W. For ensured
operation TJ(max) = 125°C.
Human-body model, 100 pF discharged through a 1.5 kΩ resistor. Except Bootstrap pins (pins 1 and 11) which are protected to 1000V
of ESD.
(2)
(3)
(4)
(5)
Operating Ratings
(1)
−40°C to +125°C
Junction Temperature, TJ
VS Supply Voltage
(1)
+12V to +55V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its rated operating conditions.
Electrical Characteristics
(1)
The following specifications apply for VS = 42V, unless otherwise specified. Boldface limits apply over the entire operating
temperature range, −40°C ≤ TJ ≤ +125°C, all other limits are for TA = TJ = 25°C.
Typ
Limit
Units
RDS(ON)
Symbol
Switch ON Resistance
Parameter
Output Current = 3A
Conditions
(2)
0.33
0.40/0.6
Ω (max)
RDS(ON)
Switch ON Resistance
Output Current = 6A
(2)
0.38
0.45/0.6
Ω (max)
(2)
1.2
1.5
V (max)
VCLAMP
Clamp Diode Forward Drop
Clamp Current = 3A
VIL
Logic Low Input Voltage
Pins 3, 4, 5
IIL
Logic Low Input Current
VIN = −0.1V, Pins = 3, 4, 5
VIH
Logic High Input Voltage
Pins 3, 4, 5
IIH
Logic High Input Current
Current Sense Output
Current Sense Linearity
(1)
(2)
(3)
(4)
VIN = 12V, Pins = 3, 4, 5
IOUT = 1A
(3)
1A ≤ IOUT ≤ 3A
377
(4)
±6
−0.1
V (min)
0.8
V (max)
−10
μA (max)
2
V (min)
12
V (max)
10
μA (max)
325/300
μA (min)
425/450
μA (max)
±9
%
All limits are 100% production tested at 25°C. Temperature extreme limits are ensured via correlation using accepted SQC (Statistical
Quality Control) methods. All limits are used to calculate AOQL, (Average Outgoing Quality Level).
Output currents are pulsed (tW < 2 ms, Duty Cycle < 5%).
Selections for tighter tolerance are available. Contact factory.
Regulation is calculated relative to the current sense output value with a 1A load.
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Electrical Characteristics (1) (continued)
The following specifications apply for VS = 42V, unless otherwise specified. Boldface limits apply over the entire operating
temperature range, −40°C ≤ TJ ≤ +125°C, all other limits are for TA = TJ = 25°C.
Symbol
Parameter
Conditions
Typ
Limit
Units
9
V (min)
11
V (max)
Undervoltage Lockout
Outputs turn OFF
TJW
Warning Flag Temperature
Pin 9 ≤ 0.8V, IL = 2 mA
145
VF(ON)
Flag Output Saturation Voltage
TJ = TJW, IL = 2 mA
0.15
IF(OFF)
Flag Output Leakage
VF = 12V
0.2
TJSD
Shutdown Temperature
Outputs Turn OFF
170
IS
Quiescent Supply Current
All Logic Inputs Low
13
tDon
Output Turn-On Delay Time
Sourcing Outputs, IOUT = 3A
300
ns
Sinking Outputs, IOUT = 3A
300
ns
ton
Output Turn-On Switching Time
100
ns
Sinking Outputs, IOUT = 3A
80
ns
Sourcing Outputs, IOUT = 3A
200
ns
Sinking Outputs, IOUT = 3A
200
ns
Sourcing Outputs, IOUT = 3A
75
ns
Sinking Outputs, IOUT = 3A
70
ns
toff
Output Turn-Off Delay Times
Output Turn-Off Switching Times
V
10
μA (max)
25
mA (max)
°C
Bootstrap Capacitor = 10 nF
Sourcing Outputs, IOUT = 3A
tDoff
°C
Bootstrap Capacitor = 10 nF
tpw
Minimum Input Pulse Width
Pins 3, 4 and 5
1
μs
tcpr
Charge Pump Rise Time
No Bootstrap Capacitor
20
μs
4
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Typical Performance Characteristics
VSAT vs Flag Current
RDS(ON) vs Temperature
Figure 3.
Figure 4.
RDS(ON) vs Supply Voltage
Supply Current vs Supply Voltage
Figure 5.
Figure 6.
Supply Current vs Frequency (VS = 42V)
Supply Current vs Temperature (VS = 42V)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
6
Current Sense Output vs Load Current
Current Sense
Operating Region
Figure 9.
Figure 10.
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TEST CIRCUIT
Switching Time Definitions
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Pinout Description
(See Test Circuit)
Pin 1, BOOTSTRAP 1 Input: Bootstrap capacitor pin for half H-bridge number 1. The recommended capacitor
(10 nF) is connected between pins 1 and 2.
Pin 2, OUTPUT 1: Half H-bridge number 1 output.
Pin 3, DIRECTION Input: See Logic Truth Table. This input controls the direction of current flow between
OUTPUT 1 and OUTPUT 2 (pins 2 and 10) and, therefore, the direction of rotation of a motor load.
Pin 4, BRAKE Input: See Logic Truth Table. This input is used to brake a motor by effectively shorting its
terminals. When braking is desired, this input is taken to a logic high level and it is also necessary to apply logic
high to PWM input, pin 5. The drivers that short the motor are determined by the logic level at the DIRECTION
input (Pin 3): with Pin 3 logic high, both current sourcing output transistors are ON; with Pin 3 logic low, both
current sinking output transistors are ON. All output transistors can be turned OFF by applying a logic high to Pin
4 and a logic low to PWM input Pin 5; in this case only a small bias current (approximately −1.5 mA) exists at
each output pin.
Pin 5, PWM Input: See Logic Truth Table. How this input (and DIRECTION input, Pin 3) is used is determined
by the format of the PWM Signal.
Pin 6, VS Power Supply
Pin 7, GROUND Connection: This pin is the ground return, and is internally connected to the mounting tab.
Pin 8, CURRENT SENSE Output: This pin provides the sourcing current sensing output signal, which is typically
377 μA/A.
Pin 9, THERMAL FLAG Output: This pin provides the thermal warning flag output signal. Pin 9 becomes activelow at 145°C (junction temperature). However the chip will not shut itself down until 170°C is reached at the
junction.
Pin 10, OUTPUT 2: Half H-bridge number 2 output.
Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin for Half H-bridge number 2. The recommended capacitor
(10 nF) is connected between pins 10 and 11.
Logic Truth Table
8
PWM
Dir
Brake
H
H
L
Source 1, Sink 2
Active Output Drivers
H
L
L
Sink 1, Source 2
L
X
L
Source 1, Source 2
H
H
H
Source 1, Source 2
H
L
H
Sink 1, Sink 2
L
X
H
NONE
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APPLICATION INFORMATION
TYPES OF PWM SIGNALS
The LMD18200 readily interfaces with different forms of PWM signals. Use of the part with two of the more
popular forms of PWM is described in the following paragraphs.
Simple, locked anti-phase PWM consists of a single, variable duty-cycle signal in which is encoded both
direction and amplitude information (see Figure 11). A 50% duty-cycle PWM signal represents zero drive, since
the net value of voltage (integrated over one period) delivered to the load is zero. For the LMD18200, the PWM
signal drives the direction input (pin 3) and the PWM input (pin 5) is tied to logic high.
Figure 11. Locked Anti-Phase PWM Control
Sign/magnitude PWM consists of separate direction (sign) and amplitude (magnitude) signals (see Figure 12).
The (absolute) magnitude signal is duty-cycle modulated, and the absence of a pulse signal (a continuous logic
low level) represents zero drive. Current delivered to the load is proportional to pulse width. For the LMD18200,
the DIRECTION input (pin 3) is driven by the sign signal and the PWM input (pin 5) is driven by the magnitude
signal.
Figure 12. Sign/Magnitude PWM Control
SIGNAL TRANSITION REQUIREMENTS
To ensure proper internal logic performance, it is good practice to avoid aligning the falling and rising edges of
input signals. A delay of at least 1 µsec should be incorporated between transitions of the Direction, Brake,
and/or PWM input signals. A conservative approach is be sure there is at least 500ns delay between the end of
the first transition and the beginning of the second transition. See Figure 13.
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Figure 13. Transitions in Brake, Direction, or PWM Must Be Separated By At Least 1 µsec
USING THE CURRENT SENSE OUTPUT
The CURRENT SENSE output (pin 8) has a sensitivity of 377 μA per ampere of output current. For optimal
accuracy and linearity of this signal, the value of voltage generating resistor between pin 8 and ground should be
chosen to limit the maximum voltage developed at pin 8 to 5V, or less. The maximum voltage compliance is 12V.
It should be noted that the recirculating currents (free wheeling currents) are ignored by the current sense
circuitry. Therefore, only the currents in the upper sourcing outputs are sensed.
USING THE THERMAL WARNING FLAG
The THERMAL FLAG output (pin 9) is an open collector transistor. This permits a wired OR connection of
thermal warning flag outputs from multiple LMD18200's, and allows the user to set the logic high level of the
output signal swing to match system requirements. This output typically drives the interrupt input of a system
controller. The interrupt service routine would then be designed to take appropriate steps, such as reducing load
currents or initiating an orderly system shutdown. The maximum voltage compliance on the flag pin is 12V.
SUPPLY BYPASSING
During switching transitions the levels of fast current changes experienced may cause troublesome voltage
transients across system stray inductance.
It is normally necessary to bypass the supply rail with a high quality capacitor(s) connected as close as possible
to the VS Power Supply (Pin 6) and GROUND (Pin 7). A 1 μF high-frequency ceramic capacitor is recommended.
Care should be taken to limit the transients on the supply pin below the Absolute Maximum Rating of the device.
When operating the chip at supply voltages above 40V a voltage suppressor (transorb) such as P6KE62A is
recommended from supply to ground. Typically the ceramic capacitor can be eliminated in the presence of the
voltage suppressor. Note that when driving high load currents a greater amount of supply bypass capacitance (in
general at least 100 μF per Amp of load current) is required to absorb the recirculating currents of the inductive
loads.
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CURRENT LIMITING
Current limiting protection circuitry has been incorporated into the design of the LMD18200. With any power
device it is important to consider the effects of the substantial surge currents through the device that may occur
as a result of shorted loads. The protection circuitry monitors this increase in current (the threshold is set to
approximately 10 Amps) and shuts off the power device as quickly as possible in the event of an overload
condition. In a typical motor driving application the most common overload faults are caused by shorted motor
windings and locked rotors. Under these conditions the inductance of the motor (as well as any series inductance
in the VCC supply line) serves to reduce the magnitude of a current surge to a safe level for the LMD18200. Once
the device is shut down, the control circuitry will periodically try to turn the power device back on. This feature
allows the immediate return to normal operation in the event that the fault condition has been removed. While the
fault remains however, the device will cycle in and out of thermal shutdown. This can create voltage transients on
the VCC supply line and therefore proper supply bypassing techniques are required.
The most severe condition for any power device is a direct, hard-wired (“screwdriver”) long term short from an
output to ground. This condition can generate a surge of current through the power device on the order of 15
Amps and require the die and package to dissipate up to 500 Watts of power for the short time required for the
protection circuitry to shut off the power device. This energy can be destructive, particularly at higher operating
voltages (>30V) so some precautions are in order. Proper heat sink design is essential and it is normally
necessary to heat sink the VCC supply pin (pin 6) with 1 square inch of copper on the PCB.
INTERNAL CHARGE PUMP AND USE OF BOOTSTRAP CAPACITORS
To turn on the high-side (sourcing) DMOS power devices, the gate of each device must be driven approximately
8V more positive than the supply voltage. To achieve this an internal charge pump is used to provide the gate
drive voltage. As shown in Figure 14, an internal capacitor is alternately switched to ground and charged to about
14V, then switched to V supply thereby providing a gate drive voltage greater than V supply. This switching
action is controlled by a continuously running internal 300 kHz oscillator. The rise time of this drive voltage is
typically 20 μs which is suitable for operating frequencies up to 1 kHz.
Figure 14. Internal Charge Pump Circuitry
For higher switching frequencies, the LMD18200 provides for the use of external bootstrap capacitors. The
bootstrap principle is in essence a second charge pump whereby a large value capacitor is used which has
enough energy to quickly charge the parasitic gate input capacitance of the power device resulting in much faster
rise times. The switching action is accomplished by the power switches themselves Figure 15. External 10 nF
capacitors, connected from the outputs to the bootstrap pins of each high-side switch provide typically less than
100 ns rise times allowing switching frequencies up to 500 kHz.
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Figure 15. Bootstrap Circuitry
INTERNAL PROTECTION DIODES
A major consideration when switching current through inductive loads is protection of the switching power
devices from the large voltage transients that occur. Each of the four switches in the LMD18200 have a built-in
protection diode to clamp transient voltages exceeding the positive supply or ground to a safe diode voltage drop
across the switch.
The reverse recovery characteristics of these diodes, once the transient has subsided, is important. These
diodes must come out of conduction quickly and the power switches must be able to conduct the additional
reverse recovery current of the diodes. The reverse recovery time of the diodes protecting the sourcing power
devices is typically only 70 ns with a reverse recovery current of 1A when tested with a full 6A of forward current
through the diode. For the sinking devices the recovery time is typically 100 ns with 4A of reverse current under
the same conditions.
TYPICAL APPLICATIONS
FIXED OFF-TIME CONTROL
This circuit controls the current through the motor by applying an average voltage equal to zero to the motor
terminals for a fixed period of time, whenever the current through the motor exceeds the commanded current.
This action causes the motor current to vary slightly about an externally controlled average level. The duration of
the Off-period is adjusted by the resistor and capacitor combination of the LM555. In this circuit the
Sign/Magnitude mode of operation is implemented (see TYPES OF PWM SIGNALS).
12
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Figure 16. Fixed Off-Time Control
Figure 17. Switching Waveforms
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TORQUE REGULATION
Locked Anti-Phase Control of a brushed DC motor. Current sense output of the LMD18200 provides load
sensing. The LM3524D is a general purpose PWM controller. The relationship of peak motor current to
adjustment voltage is shown in Figure 19.
Figure 18. Locked Anti-Phase Control Regulates Torque
Figure 19. Peak Motor Current
vs Adjustment Voltage
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VELOCITY REGULATION
Utilizes tachometer output from the motor to sense motor speed for a locked anti-phase control loop. The
relationship of motor speed to the speed adjustment control voltage is shown in Figure 21.
Figure 20. Regulate Velocity with Tachometer Feedback
Figure 21. Motor Speed vs
Control Voltage
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REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
LMD18200T
NRND
TO-220
NDJ
11
20
TBD
Call TI
Call TI
LMD18200T/LF14
ACTIVE
TO-220
NDJ
11
23
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
LMD18200T/NOPB
ACTIVE
TO-220
NDJ
11
20
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
LMD18200T
P+
LMD18200T
P+
-40 to 125
LMD18200T
P+
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
NDJ0011B
TA11B (Rev B)
www.ti.com
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