LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 2.0 Issue Date Sep.5.2006 Apr.12.2007 Jun.23.2007 Rev. 2.3 Description Initial Issue Revised PACKAGE OUTLINE DIMENSION (TSOP II) Revised ICC and ISB1 Revised TEST CONDITION of ISB1/IDR Added E and I grade Revised ABSOLUTE MAXIMUN RATINGS Adding PKG type : 36-ball 6mm x 8mm TFBGA Revised TEST CONDITION of ICC Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Revised PACKAGE OUTLINE DIMENSION in page 9/10/12 Rev. 2.4 Revised Aug.30.2010 Rev. 2.6 ORDERING INFORMATION in page 14/15/16/17/18/19 Correct ORDERING INFORMATION Typo. Added “*Not recommended for new design.” in ORDERING INFORMATION. Rev. 2.7 Revised ISB1 & ICC Revised IDR in DATA RETENTION CHARACTERISTICS Deleted -15/25ns Spec. Deleted E grade Deleted PKG type : 32-pin TSOP I & 32-pin sTSOP & 36-ball TFBGA Deleted WRITE CYCLE Notes : 1. WE#,CE# must be high during all address transitions. In page 8. Deleted -10/12ns Spec. Rev. 2.1 Rev. 2.2 Rev. 2.5 Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 Mar.31.2008 Apr.17.2009 May.7.2010 May.20.2015 Dec.27.2016 Apr.19.2017 LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 FEATURES GENERAL DESCRIPTION Fast access time : 20ns Very low power consumption: Operating current (Normal version): 50mA (TYP.) Standby current: 0.5mA (TYP. for 20ns) 20µ A (TYP. for LL version) Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.) Green package available Package : 44-pin 400 mil TSOP II The LY61L5128 is a 4,194,304-bit low power CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY61L5128 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The LY61L5128 operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY61L5128 LY61L5128(I) LY61L5128(LL) LY61L5128(LLI) Operating Temperature 0 ~ 70℃ -40 ~ 85℃ 0 ~ 70℃ -40 ~ 85℃ VCC Range Speed 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 20ns 20ns 20ns 20ns Power Dissipation Standby(ISB1,TYP.) Operating(ICC,TYP.) 0.5mA 50mA 0.5mA 50mA 20µA 50mA 20µA 50mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A18 DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# WE# OE# CONTROL CIRCUIT 512Kx8 MEMORY ARRAY SYMBOL DESCRIPTION A0 - A18 Address Inputs DQ0 - DQ7 Data Inputs/Outputs CE# Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection COLUMN I/O Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 PIN CONFIGURATION 1 44 NC NC 2 43 NC A4 3 42 NC A3 4 41 A5 A2 5 40 A6 A1 6 39 A7 A0 7 38 A8 CE# 8 37 OE# DQ0 9 36 DQ7 DQ1 10 35 DQ6 Vcc 11 34 Vss Vss 12 33 Vcc DQ2 13 32 DQ5 DQ3 14 31 DQ4 WE# 15 30 A9 A18 16 29 A10 A17 17 28 A11 A16 18 27 A12 A15 19 26 A13 A14 20 25 NC NC 21 24 NC NC 22 23 NC LY61L5128 XXXXXXXX XXXXXXXX NC TSOP II ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H L L L OE# X H L X WE# X H H L I/O OPERATION High-Z High-Z DOUT DIN H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 SUPPLY CURRENT ISB1 ICC ICC ICC LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC Input High Voltage VIH*1 Input Low Voltage VIL*2 Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -4mA Output Low Voltage VOL IOL = 8mA Cycle time = MIN. Average Operating ICC CE# = VIL , II/O = 0mA, Power supply Current others at VIH or VIL 20 Standby Power CE# ≧ VCC - 0.2V, ISB1 Supply Current others at 0.2V or VCC - 0.2V 20LL MIN. 3.0 2.2 - 0.3 -1 TYP. *4 MAX. 3.3 3.6 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.4 - - 0.4 V V - 50 80 mA - 0.5 20 5*5 100*6 mA µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ 5. 1mA for special request 6. 50µ A for special request CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX. 8 10 Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 UNIT pF pF LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH LY61L5128-20 MIN. MAX. 20 20 20 8 4 0 8 8 3 - UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* LY61L5128-20 MIN. MAX. 20 16 16 0 11 0 9 0 5 9 UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 High-Z LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW tAS tWP tWR WE# tWHZ Dout tOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.A write occurs during the overlap of a low CE#, low WE#. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V 20 VCC = 2.0V, CE# ≧ VCC - 0.2V Data Retention Current IDR Others at 0.2V or VCC - 0.2V 20LL Chip Disable to Data tCDR See Data Retention Waveforms (below) Retention Time Recovery Time tR tRC* = Read Cycle Time MIN. 2.0 - TYP. 0.5 10 MAX. 3.6 1 50 UNIT V mA µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≧ 2.0V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 0o 3o 6o DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 0o 3o 6o Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 LY61L5128 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 ORDERING INFORMATION Package Type Access Time Power Type (Speed)(ns) 44-pin (400mil) 20 Temperature Packing Range(℃) Type Normal Power 0℃~70℃ TSOP II -40℃~85℃ 20 Ultra 0℃~70℃ Low Power -40℃~85℃ Tray LY61L5128ML-20 Tape Reel LY61L5128ML-20T Tray LY61L5128ML-20I Tape Reel LY61L5128ML-20IT Tray LY61L5128ML-20LL Tape Reel LY61L5128ML-20LLT Tray LY61L5128ML-20LLI Tape Reel LY61L5128ML-20LLIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 Lyontek Item No. LY61L5128 Rev. 2.7 512K X 8 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11