e ADVANCED LINEAR DEVICES, INC. TM EPAD EN ® AB LE D ALD8100XX/ALD9100XX FAMILY of SUPERCAPACITOR AUTO BALANCING (SAB™) MOSFET ARRAYS GENERAL DESCRIPTION SAB MOSFET ADVANTAGES The ALD8100xx/ALD9100xx family of Supercapacitor Auto Balancing MOSFET Arrays, or SAB™ MOSFETs, are designed to address voltage and leakage current balancing of supercapacitors connected in series. Supercapacitors, also known as ultracapacitors or supercaps, connected in series can be balanced with single or multiple ALD8100xx/ALD9100xx packages. These SAB MOSFETs are built with ALD production proven EPAD® MOSFET technology. The ALD8100xx/ALD9100xx family of SAB MOSFETs are designed for automatic supercapacitor balancing. They are replacements for many other passive or active supercapacitor balancing methods where cost, board space, efficiency, simplicity and power dissipation are important design considerations. For example, in applications where supercapacitors require minimum long-term power dissipation (internal leakage currents) as a primary goal, ALD8100xx/ ALD9100xx SAB MOSFETs are simpler and more effective in performing the leakage balancing function, using significantly less board space and contributing no additional charge loss beyond the supercapacitor’s own leakages. Other common methods of charge SAB MOSFETs have unique electrical characteristics for superior active continuous leakage current regulation and self-balancing of stacked series-connected supercapacitors while dissipating near zero leakage currents, practically eliminating extra power consumption. For many applications, SAB MOSFET automatic charge balancing offers a simple, economical and effective method to balance and regulate supercapacitor voltages. With SAB MOSFETs, each supercapacitor in a series-connected stack is continuously monitored and automatically controlled for precise, effective balancing of its voltage and leakage current. PIN CONFIGURATIONS The SAB MOSFET regulates the voltage across a supercapacitor cell by increasing its drain current exponentially across the supercapacitor when its voltage increases, and by decreasing its drain current exponentially across the supercapacitor when its voltage decreases. When a supercapacitor cell is charged to a voltage less than 90% of the desired voltage limit, the SAB MOSFET across the supercap is turned off and there is zero leakage current contribution from the SAB MOSFET. On the other hand, when the voltage across the supercapacitor is over the desired voltage limit, the SAB MOSFET is turned on to increase its drain currents to keep the supercapacitor voltage from rising. Simultaneously, the voltages and leakages of other supercapacitors in the series stack are lowered to result in a near zero net increase in leakage current. The ALD8100xx/ALD9100xx SAB MOSFET family offers a selection of different threshold devices for various supercapacitor maximum operating voltage values and desired leakage balancing characteristics as well as different temperature range environments. A list of the available ALD part numbers can be found in the tables on pages 6 and 7 of this document. For individual datasheets and specifications, please visit www.aldinc.com under “SAB MOSFET”. ALD8100xx IC* 1 DN1 2 M2 GN1 3 SN1 4 V- V- V- 5 DN4 6 M4 M3 GN4 7 SN4 8 V- V- IC* 15 DN2 14 GN2 13 SN2 12 V+ 11 DN3 10 GN3 9 SN3 SCL PACKAGES SUPERCAPACITORS Supercapacitors are typically rated with a nominal recommended working voltage established for long life at their maximum rated operating temperature. When a supercapacitor cell voltage exceeds its rated voltage for a prolonged time period, it experiences reduced lifetime and eventual rupture and catastrophic failure. To prevent such an occurrence, in most applications having two or more supercapacitors connected in series, a means of automatically monitoring and adjusting charge-balancing at their maximum operating voltages is required. This is due to different internal leakage currents in each specific cell. The supercapacitor’s leakage current is a variable function of many parameters such as aging, initial leakage current at zero input voltage, material and construction of the supercapactor, its chemistry composition, its leakage as a function of the charging voltage and the charging current and temperature, operating temperature range, and the rate of change of many of these parameters. Supercapacitor balancing must correct for these changing effects automatically, with minimal added leakage currents or power consumption. ©2014 Advanced Linear Devices, Inc., Vers. 2.0 M1 16 www.aldinc.com ALD9100xx IC* 1 V- 8 V+ GN1 2 7 GN2 DN1 3 6 DN2 SN1 4 5 SN2, VSAL PACKAGES *IC pins are internally connected, connect to V- 1 of 17 ALD8100XX/ALD9100XX FAMILY GENERAL DESCRIPTION (cont.) balancing generally contribute additional continuous power dissipation due to linear currents at all supercapacitor voltage levels, whereas SAB MOSFET leakages decrease exponentially with decreased supercapacitor voltages. In many cases, the additional leakage charge loss is near zero. UNDERSTANDING SUPERCAPACITOR AUTO BALANCING USING SAB™ MOSFETS The principle behind the SAB MOSFET in balancing supercapacitors is simple. It is based on the natural threshold characteristics of a MOSFET device. The threshold voltage of a MOSFET is the voltage at which a MOSFET turns on and starts to conduct a current. The drain current of the MOSFET, at or below its threshold voltage, is an exponential function of its gate voltage. Hence, for small changes in the MOSFET’s gate voltage, its drainsource on-current can vary greatly, by orders of magnitude. ALD’s SAB MOSFETs are designed to take advantage of this fundamental device characteristic. SAB MOSFETs are connected in the Vt mode, meaning that the Gate-to-Source and the Drain-to-Source terminals of each MOSFET are always connected. In this mode VGS is always equal to VDS and when this joint terminal is connected across a supercapacitor, it is also referred to as an Input Voltage, VIN. Each SAB MOSFET has a well defined Drain-to-Source Current, IDS(ON), for different values of VIN Voltages. This current is also referred to as the Output Current, IOUT, of the SAB MOSFET. SAB MOSFETs can be connected in parallel or in series, to suit the desired leakage current characteristics, in order to charge-balance an array of supercapacitors connected in series. The array of combined SAB MOSFETs and supercapacitors would be automatically self-regulating with various leakage mismatches and environmental temperature changes. The SAB MOSFETs can also be used entirely in the subthreshold mode, meaning the SAB MOSFET is used at min., nominal and max. operating voltages in voltage ranges below its specified threshold voltage. With the ALD8100xx/ALD9100xx family, the threshold voltage Vt of an SAB MOSFET is defined as its drain-gate source voltage at a drain-source ON current, IDS(ON) = 1µA, when its gate and drain terminals are connected together (VGS = VDS). This voltage is specified as xx, where the threshold voltage is in 0.10V increments. Two examples are: the ALD810025 features a precise threshold voltage of Vt = 2.500V at IDS(ON) = 1µA and the AL ºD810017 has Vt = 1.700V at IDS(ON) = 1µA. As all ALD8100xx/ALD9100xx devices operate similarly, with linear voltage shifts, an ALD810025 is used as an illustration of its characteristics. At voltages below its threshold voltage, the ALD810025 rapidly turns off at a rate of approximately one decade of current per 104mV of voltage drop. Hence, at VIN = 2.396V, the ALD810025 IOUT is 0.1µA. At VIN = 2.292V, its IOUT becomes 0.01µA. When VIN drops further to 2.188V, its IOUT becomes 0.001µA. It should be apparent that at VIN ≤ 2.10V, the ALD810025 IOUT ≤ 0.00014µA, which is near zero when compared to 1µA at VIN = 2.50V. At VIN below 1.9V, the SAB MOSFET Output Current, IOUT, goes to essentially zero (~70pA). The IOUT ≤ 0.00014µA is controlled and repeatable for different units from various production batches. This exponential relationship between the SAB MOSFET’s VIN and IOUT can be an important consideration in replacing certain supercapacitor charge balancing applications currently using fixed resistors, operational amplifier circuits or other forms of charge balancing. These other conventional charge-balancing methods continue to dissipate a significant amount of current, even after the voltage across the supercapacitors has dropped, because the cur- rent dissipated is a linear function, rather than an exponential function, of the supercapacitor voltage (I = V/R). For supercapacitor series stacks with more than two cells, the challenge of leakage balancing becomes even more onerous. With most other passive or active circuits that offer charge balancing, active power is still being consumed even if the supercapacitor voltage falls much below its operating voltage. For a four-cell supercapacitor stack, for example, this translates into a 2.0V x 4 ~= 8.0V power supply for an IC charge-balancing circuit. As the number of cells increase, adding components to the charge balancing circuit, increased circuit complexity and power dissipation becomes a greater challenge. A supercapacitor stack using the SAB MOSFET charge-balancing method, on the other hand, would not cause extra power dissipation when the number of cells increase. This method provides an exponentially decreasing amount of charge loss with time, and helps preserve, by far, the greatest amount of charge on each of the supercapacitors. If VIN of the ALD810025 is greater than its Vt threshold voltage, its Output Current, IOUT, behavior has the opposite near-exponential effect. At VIN = 2.60V, for example, the ALD810025 IOUT increases tenfold to 10µA. Similarly, IOUT becomes 100µA at a VIN of 2.74V, and 300µA at VIN of 2.84V. (See Table 1.) As IOUT changes rapidly with the applied VIN, the SAB MOSFET device acts like a voltage limiting regulator with self-adjusting current levels. When the SAB MOSFET is connected across a supercapacitor cell, the total leakage current equals the two in combination automatically compensate and correct for each other. Consider the case when two supercapacitor cells are connected in series, each with an SAB MOSFET connected across it, charged by a power supply to a voltage equal to 2 x VS. If the top supercapacitor has a higher internal leakage current than the bottom supercapacitor, the voltage VS(top) across it tends to drop lower than that of the bottom supercapacitor. The SAB MOSFET IOUT across the top supercapacitor, sensing this voltage drop, drops off rapidly. Meanwhile, the bottom supercapacitor VS(bottom) voltage tends to rise, as VS(bottom) = (2 x VS) - VS(top). This tendency for the voltage rise also increases VIN voltage of the SAB MOSFET across the bottom supercapacitor. This increased VIN voltage would cause the IOUT of the bottom SAB MOSFET to increase rapidly as well. The excess leakage current of the top supercapacitor would now leak across the bottom SAB MOSFET, reducing the voltage rise tendency of the lower supercapacitor. With this automatic self-regulating mechanism, the top supercapacitor voltage tends to rise while the bottom supercapacitor voltage tends to drop, creating simultaneously opposing actions to the supercapacitor leakage currents. With appropriate design and selection of a specific SAB MOSFET device for a given pair of supercapacitors, it is now possible to regulate and balance two series-connected supercapacitors with essentially no extra leakage current, since the SAB MOSFET only conducts the difference in leakage current between the two supercapacitors. Likewise, the case of the bottom supercapacitor having a higher leakage current than that of the top supercapacitor works in similar fashion, where the bottom supercapacitor voltage tends to drop, compensated by the tendency of the top supercap voltage to drop as well, effected by the top SAB MOSFET. This SAB MOSFET charge balancing scheme also works with four, eight or more supercapacitors in series by using an equivalent number of SAB MOSFETs in multiple package(s). Ambient temperature increases cause supercapacitor leakage currents to increase. The SAB MOSFET threshold voltage is reduced ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 2 of 17 ALD8100XX/ALD9100XX FAMILY GENERAL DESCRIPTION (cont.) with temperature increase, which causes its IOUT to increase with temperature as well. This current increase compensates for the leakage current increase within the supercapacitor, reducing the overall supercapacitor temperature leakage effect and preserving charge balancing effectiveness. This temperature compensation assumes that all supercapacitors and SAB MOSFETs operate in the same temperature environments. The proess of selecting SAB MOSFETs to match specific models of supercapacitors begins by analyzing the parameters and the requirements of a given set of supercapacitors: 1) For better leakage current matching results, pick the same make and model of supercapacitors to be connected in a series. If possible, select supercapacitors from the same production batch. (Note: SAB MOSFETs are precisely set at the factory and specified such that their unit-to-unit variation is not a concern.) SAB MOSFET LIMITATIONS 2) Determine the max. leakage current of each supercapacitor. During supercapacitor charging, consideration must be paid to limit the rate of charging so that excessive voltage and current does not build up across any two pins of the SAB MOSFETs, even momentarily, to exceed their absolute maximum ratings in voltage, operating current, and power dissipation. In most cases though, this is not an issue, as other design constraints elsewhere limit the rate of charging or discharging of the supercapacitors. For many applications, no further action, other than checking the voltage and current excursions, or including a simple current-limiting charging resistor, is necessary. 3) Determine the desired nominal operating voltage of the supercapacitor. 4) Determine the maximum operating voltage rating of the supercapacitor. 5) Calculate or measure the maximum leakage current of the supercapacitor at its maximum rated operating voltage. 6) Determine the operating temperature range of the supercapacitor. For each SAB MOSFET, its V+ pin must be connected to the most positive voltage and its V- and IC pins to the most negative voltage within the package. SAB MOSFETs have numerous pins required for its manufacturing process, which must be connected to the supercapacitors when in use, for proper circuit operation. Multiple packages can be cascaded for higher system voltages as long as absolute maximum ratings are observed for each individual package. Note that each Drain pin of a SAB MOSFET has an internal reverse biased diode to its Source pin, which can become forwardbiased if the Drain voltage should become negative relative to its Source voltage. This forward-biased diode clamps the Drain voltage to limit the negative voltage relative to its Source voltage, and is limited to a 80mA max. rated current between any two pins. 7) Determine any additional level of operating leakage current in the system. Next, determine the normalized IOUT of an SAB MOSFET at a preselected VIN operating voltage. For example, the ALD810025 has a rated Drain Current of 1µA at applied VIN of 2.50V. If the desired normalized IOUT is 0.01µA, then the ALD810025 would give a bias VIN voltage of approximately 2.3V at that current, which produces an equivalent ON resistance of 2.3V/0.01µA ~= 230MΩ (using the rule of thumb: one decade of IOUT change per 0.10V of VIN change). Each Gate pin also has a reverse biased diode to V-. When forward biased, the maximum diode current must be within the absolute maximum ratings. All other pins must have voltages within V+ and V- voltage limits. Standard ESD protection facilities and handling procedures for static sensitive devices must also be followed before the SAB MOSFETs are installed. Once the SAB MOSFET is permanently connected to the supercapacitors, ESD concerns are relieved because any extraneous electrostatic charge would be absorbed by the supercapacitor and would not cause exessive voltage increase. FIGURE 1 V+ RSRC + + VIN1 VC1 EXTENDED TEMPERATURE RANGE OPERATION - IOUT1 SAB MOSFETs are built with solid state integrated circuit tehcnology. They are available for operation over a wide temperature range, with appropriate derating, screening and packaging. Standard commercial grade devices are rated for operation at 0°C to +70°C. Industrial temperature range (“I” suffix) units are rated for -40°C to +85°C. Custom versions are also available for military temperature ranges (“M” suffix), -55°C to +125°C. + MATCHING SAB™ MOSFETS TO SUPERCAPACITORS Figure 1 shows a basic connection diagram of two SAB MOSFETs connected across two supercapacitors, powered by a V+ power supply with an external (or internal) resistor, with basic equations of SAB MOSFET and supercapacitor voltages and currents. IC1 + VIN2 - VSUPPLY VC2 IOUT2 IC2 - Basic Equations: V+ = VC1 + VC2 + RSRC (IC1 + IOUT1) V+ = VC1 + VC2 + RSRC (IC2 + IOUT2) VC1 = VIN1 VC2 = VIN2 IC1 + IOUT1 = IC2 + IOUT2 VSUPPLY = VC1 + VC2 ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 3 of 17 ALD8100XX/ALD9100XX FAMILY GENERAL DESCRIPTION (cont.) CHOOSING A SPECIFIC SAB MOSFET In choosing SAB MOSFETs for a specific application, go to the SAB MOSFET selection table, (Table 1 for ALD8100xx devices, Table 2 for ALD9100xx devices) where each SAB MOSFET Part Number and its respective parameters are listed. First, select an SAB MOSFET IOUT Current horizontally across the top row of the Table(s). Next, look down that column to the row that contains the maximum desired VIN voltage. The appropriate ALD part number is in the first column of that row. The part number of an SAB MOSFET references its rated threshold voltage, but that is not necessarily the desired operating voltage where the auto-balancing supercapacitor operates. Generally, the recommended maximum supercapacitor IOUT auto-balancing for the ALD8100xx/ALD9100xx family is about 1mA. When supercapacitor leakage current exceeds 1mA, the effectiveness of the SAB MOSFET auto-balancing gradually diminishes and there is additional leakage current contribution from the SAB MOSFET itself as its VIN increases. Please contact [email protected] for more information or technical assistance. A DESIGN EXAMPLE A single 5V power supply using two 2.7V rated supercapacitors connected in series and a single ALD810026 SAB MOSFET array package (using two of the four devices in the package). For a supercapacitor with: 1) max. operating voltage = 2.70V and 2) max. leakage current = 10µA at 70°C. 3) At 2.50V, the supercapacitor max. leakage current = 2.5µA at 25°C. Next, pick ALD810026, a SAB MOSFET with Vt = 2.60V. For this device, at VIN = 2.60V, the nominal IOUT = 1µA. See Table 1, at VIN = 2.50V, IOUT ~= 0.1µA. At a nominal VIN of 2.50V, the additional leakage current contribution by the ALD810026 is therefore ~= 0.1µA. The total leakage current for the supercapacitor and the SAB MOSFET = 2.5µA + 0.1µA ~= 2.6µA @ 2.50V operating voltage. When operating voltage becomes 2.40V, additional ALD810026 leakage current contribution decreases to about 0.01µA. At VIN of 2.70V across the ALD810026 SAB MOSFET, IOUT = 10µA. 10µA is also the max. leakage current design margin, the difference between top and bottom supercapacitor leakage currents that can be compensated. If a higher max. leakage current margin is desired, then SAB MOSFET selection may need to go to the next SAB MOSFET part down in Table 1, which is ALD810025. For ALD810025 operating at a max. rated voltage of 2.70V, the max. leakage current margin is ~= 50µA. For this device, IOUT at 2.50V is ~= 1µA, which is the average current consumption for the series-connected stack. The total current for the supercapacitor and the SAB MOSFET is = 2.5µA + 1µA ~= 3.5µA @ 2.50V operating voltage. Because an SAB MOSFET is always active and always in “on” mode, there is no circuit switching or sleep mode involved. This may become an important factor when the time interval between the supercap discharging or recharging, and other events happening in the application, is long, unknown or variable. The circuit operation is also greatly simplified. In real life situations, the actual circuit behavior is a little different, further reducing overall leakage currents from both supercapacitors and SAB MOSFETs, due to the automatic compensation for differ- ent leakage currents from the supercapacitors by themselves and in combination with the SAB MOSFETs. Take an example of two supercapacitors in series, assuming that the top supercapacitor is leaking 10µA and the bottom one is leaking 4µA (both at the rated 2.7V max.) while the power supply remains at 5V DC. The actual voltage across the top supercapacitor tends to be less than 2.5V (50% of 5.0V), due to its higher internal leakage current, and results in a lowered current level than 10µA because the current tends to be lower at less than 2.7V. As the total voltage across both supercapacitors is still 5.0V, each supercapacitor would experience a lowered voltage than its maximum rated voltage of 2.7V, thereby resulting in reduced overall leakage currents in each of the two supercapacitors. These leakage currents are then further regulated by the SAB MOSFETs connected across each of the supercapacitors. The end result is a compensated condition where, for example, the top supercapacitor has V IN of ~2.4V across it and the bottom supercapacitor has VIN of ~2.6V. The excess leakage current of the top supercapacitor is bypassed across the bottom SAB MOSFET. Meanwhile the top SAB MOSFET, with ~2.4V across it, is biased to conduct very little IOUT. Note also that the top supercapacitor is now biased at ~2.4V and, therefore, would experience less current leakage than when it is at 2.7V. The key point here is that this process of leakage current balancing is fully automatic and works for a variety of supercapacitors, each with its own different leakage current characteristic profile. A second factor to note is that with ~2.4V and ~2.6V across the two supercapacitors, as in this example, the actual current level difference between the top and the bottom SAB MOSFETs is at about a 100:1 ratio (~2 orders of magnitude). The net additional leakage current contributed by the ALD810026 in the design example above would, therefore, be approximately 0.01µA. In this case, leakage currents between the two supercapacitors can be at a ratio of 100:1 and still experience charge balancing and voltage regulation. If a range of supercapacitor leakge currents can be determined or selected for a particular model of supercapacitor across different production batches, then a SAB MOSFET part can be specified that further minimizes any SAB leakage currents and still maintains balanced supercapacitor voltages within a narrow range. The dynamic response of a SAB MOSFET circuit is very fast, and the typical response time is determined by the RC time constant of the equivalent ON resistance value RON of the SAB MOSFET and the capacitance value C of the supercapacitor. In many cases the RON value is small initially, responding rapidly to a large voltage transient by having a smaller RONC time constant. As the voltages settle down, the equivalent RON increases. As these RON and C values can become very large, it can take a long time for the voltages across the supercaps to settle down to steady state levels. The direction of the voltage movements across the supercapacitor, however, can indicate that the supercapacitor voltages are moving away from the voltage limits. A HIGH LEAKAGE CURRENT DESIGN EXAMPLE A nominal 12V DC power supply connects across a supercapacitor series stack consisting of six 2.0V supercapacitor cells. Each cell has a nominal operating voltage of 2.0V and is rated at 2.5V max. Maximum voltage across the stack is 13.92V, which results in a per-cell voltage of 2.32V. The max. leakage current for the supercapacitor is rated at 1mA at 2.5V. Next, we choose a maximum acceptable supercapacitor in-balance stack voltage of 2.42V, which allows for temperature and aging effects, among other factors. When we look down the column of 1000µA (1mA) in Table 1 to locate a VIN voltage of 2.42V, we find the corresponding ALD part number to be ALD810019. ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 4 of 17 ALD8100XX/ALD9100XX FAMILY GENERAL DESCRIPTION (cont.) In the graph titled “Input Voltage vs. Output Current”, locate the VIN point as follows. First, find the Vt of the ALD810019 from the SAB MOSFET Selection Table, which is 1.90V. Next, subtract 1.90V from 2.42V, which is 0.52V. Check the IOUT current variation and voltage variation as a function of temperature. If the temperature variation allowance is 60mV, then the maximum supercap inbalance voltage is 2.48V (2.42V + 0.06V) across temperature. tiple supercapacitor stacks to operate at higher operating voltages. It is only important to limit the voltage across any two pins within a single SAB MOSFET array package to be less than its absolute maximum voltage and current ratings. In cases where the supercapacitor leakage current is 1mA max., the ALD810019 is suggested. In cases where supercapacitor leakage currents are up to 3mA, then a part such as the ALD81016 can be used, although this may cause increased leakage current through the SAB MOSFET itself. Another way to reduce leakage currents would be to parallel connect mulitple ALD810019 devices to auto-balance leakage currents greater than 1mA. Supercapacitors offer an important benefit in energy harvesting applications with a high impedance energy source, in buffering and storing such energy to drive a higher power load. A 4.2V SUPERCAPACITOR STACK DESIGN EXAMPLE A supply voltage of 4.2V across two supercapacitors gives 2.1V across each supercapacitor cell. With a maximum leakage current of 100µA for each cell at 2.22V maximum VIN cell voltage, the corresponding ALD part number is ALD910020SAL, a dual 8L SOIC package. The ALD910020 would support an IOUT (supercapacitor leakage current) of 300µA at VIN = 2.30V; 100µA at VIN = 2.22V; 10µA at VIN = 2.10V and 1µA at VIN = 2.00V, respectively. An inbalance leakage current ratio between two supercapacitor cell units of 100µA to 1µA, a 100 to 1 ratio, would produce one cell voltage of 2.22V and the other cell voltage of 1.98V, which adds up to 4.20V. Similarly, a lower supply voltage than 4.2V would be divided between the two supercapacitors corresponding to their respective leakage currents. Consider the case when the supply voltage is 4.10V, each with an ALD910020 connected to it. If the leakage current ratio between the supercapacitors remains the same, then one cell would be biased at 2.22V (100µA) and the other would be biased at 1.88V (4.10V - 2.22V). This would cause the ALD910020 to have a max. leakage current contribution of less than 0.1µA. PARALLEL-CONNECTED AND SERIES-CONNECTED SAB MOSFETS In the first design example on the previous page, note that the ALD810026 is a quad pack, with four SAB MOSFETs in a single SOIC package. For applications where two supercapacitors are connected in series, the ALD9100xx dual SAB MOSFET is recommended for charge balancing. If a two-stack supercapacitor requires charge balancing, then there is also an option to parallelconnect two additional SAB MOSFETs of the quad ALD8100xx for each of the two supercapacitors. Parallel-connection means that the drain, gate and source terminals of each of the two SAB MOSFETs are connected together to form a single MOSFET with twice the output current and twice the output current sensitivity to voltage change. In this case, at an operating VIN voltage of 2.50V, the additional IOUT current contribution by the SAB MOSFET is equal to 2 x 0.1µA = 0.2µA. The total current for the combined supercapacitor and SAB MOSFET is = 2.5µA + 0.2µA ~= 2.7µA @ 2.50V operating voltage. At max. voltage of 2.70V across the SAB MOSFET, VIN = 2.70V results in a IOUT of 2 x 10µA = 20µA. So this configuration would be chosen to increase max. supercapacitor charge balancing leakage current at 2.70V to 20µA, at the expense of an additional 0.1µA IOUT leakage at 2.50V. For stacks of series-connected supercapacitors consisting of more than three or four cells, it is possible to use a single SAB MOSFET array for every supercapacitor stack (up to 4 cells) connected in series. Multiple SAB MOSFET arrays can be arrayed across mul- LOW LEAKAGE ENERGY HARVESTING APPLICATIONS For energy harvesting applications, supercapacitor leakage currents are a critical design parameter, as the average energy harvesting input charge must exceed the average supercapacitor internal leakage currents in order for any net energy to be harvested. When the input energy is a variable, meaning that its input voltage and current magnitude is not constant and dependent upon other parameters such as the source energy availability (energy sensor conversion efficiency, etc.), the energy harvested and stored must supply and exceed the necessary leakage currents, which tend to be steady DC currents. In these types of applications, in order to minimize the amount of energy loss due to leakage currents, it is essential to choose supercapacitors with low leakage specifications and to use SAB MOSFETs to balance them. For the first 90% of the initial voltages of a supercapacitor used in energy harvesting applications, supercapacitor charge loss is lower than its maximum leakage rating, at less than its max. rated voltage. SAB MOSFETs, used for charge balancing, would be completely turned off, consuming zero leakage current while the supercapacitor is being charged, maximizing any energy harvesting gathering efforts. The SAB MOSFET would not become active until the supercapacitor is already charged to over 90% of its max. rated voltage. The trickle charging of supercapacitors with energy harvesting techniques tends to work well with SAB MOSFETs as charge balancing devices, as it is less likely to have high transient energy spurts resulting in excessive voltage or current excursions. If an energy harvesting source only provides a few µA of current, the power budget would not allow wasting any of this current on capacitor leakage currents, and on many other conventional charge balancing methods. Resistors or operational amplifiers used as charge-balancing circuits would dissipate far more energy than desired. It may also be an important consideration to reduce long term DC leakage currents as energy harvesting charging at low levels may take up to many days. In summary, in order for an energy harvesting application to be successful, the input energy harvested must exceed all the energy spent, due to the leakages of the supercapacitors and the chargebalancing circuits, plus any load requirements. With their unique balancing characteristics and near-zero charge loss, SAB MOSFETs are ideal devices to use for supercapacitor charge-balancing within energy harvesting applications. LONG TERM BACKUP BATTERY APPLICATIONS Similar to energy harvesting applications, any low leakage longterm application, such as a long-term backup battery requiring supercapacitors at the output to reduce output impedance and to boost its output power, would benefit from SAB MOSFET deployment. Over a long time span, reducing leakge currents is an important design parameter. For example, a low DC leakage current of just 1µA over 5 years translates into 44.8mAhr of energy lost. ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 5 of 17 TABLE 1. ALD 8100XX SUPERCAPACITOR AUTO BALANCING (SAB™) MOSFETS EQUIVALENT ON RESISTANCE AT DIFFERENT INPUT VOLTAGES AND OUTPUT CURRENTS ALD Part Number OUTPUT CURRENT IOUT = IDS(ON) (µA) 1 GateThreshold VIN (V) 2 Voltage Equivalent ON Vt (V) Resistance (MΩ) 0.0001 0.001 0.01 0.1 1 10 TA = 25°C 100 300 1000 3000 10000 ALD810028 2.80 VIN (V) RDS(ON) (MΩ) 2.40 24000 2.50 2500 2.60 260 2.70 27 2.80 2.8 2.90 0.29 3.04 0.030 3.14 0.01 3.32 0.003 3.62 0.001 4.22 0.0004 ALD810027 2.70 VIN (V) RDS(ON) (MΩ) 2.30 23000 2.40 2400 2.50 250 2.60 26 2.70 2.7 2.80 0.28 2.94 0.029 3.04 0.01 3.22 0.003 3.52 0.001 4.12 0.0004 ALD810026 2.60 VIN (V) RDS(ON) (MΩ) 2.20 2.30 2.40 2.50 2.60 2.70 2.84 2.94 3.12 3.42 4.02 22000 2300 240 25 2.6 0.27 0.028 0.01 0.003 0.001 0.0004 ALD810025 2.50 VIN (V) RDS(ON) (MΩ) 2.10 21000 2.20 2200 2.30 230 2.40 24 2.50 2.5 2.60 0.26 2.74 0.027 2.84 0.01 3.02 0.003 3.32 0.001 3.92 0.0004 ALD810024 2.40 VIN (V) RDS(ON) (MΩ) 2.00 20000 2.10 2100 2.20 220 2.30 23 2.40 2.4 2.50 0.25 2.64 0.026 2.74 0.009 2.92 0.003 3.22 0.001 3.82 0.0004 ALD810023 2.30 VIN (V) RDS(ON) (MΩ) 1.90 19000 2.00 2000 2.10 210 2.20 22 2.30 2.3 2.40 0.24 2.54 0.025 2.64 0.009 2.82 0.003 3.12 0.001 3.72 0.0004 ALD810022 2.20 VIN (V) RDS(ON) (MΩ) 1.80 18000 1.90 1900 2.00 200 2.10 21 2.20 2.2 2.30 0.23 2.44 0.024 2.54 0.008 2.72 0.003 3.02 0.001 3.62 0.0004 ALD810021 2.10 VIN (V) RDS(ON) (MΩ) 1.70 17000 1.80 1800 1.90 190 2.00 20 2.10 2.1 2.20 0.22 2.34 0.023 2.44 0.008 2.62 0.003 2.92 0.001 3.52 0.0004 ALD810020 2.00 VIN (V) RDS(ON) (MΩ) 1.60 16000 1.70 1700 1.80 180 1.90 19 2.00 2.0 2.10 0.21 2.24 0.022 2.34 0.008 2.52 0.003 2.82 0.001 3.42 0.0003 ALD810019 1.90 VIN (V) RDS(ON) (MΩ) 1.50 15000 1.60 1600 1.70 170 1.80 18 1.90 1.9 2.00 0.20 2.14 0.021 2.24 0.007 2.42 0.002 2.72 0.001 3.32 0.0003 ALD810018 1.80 VIN (V) RDS(ON) (MΩ) 1.40 14000 1.50 1500 1.60 160 1.70 17 1.80 1.8 1.90 0.19 2.04 0.020 2.14 0.007 2.32 0.002 2.62 0.001 3.22 0.0003 ALD810017 1.70 VIN (V) RDS(ON) (MΩ) 1.30 13000 1.40 1400 1.50 150 1.60 16 1.70 1.7 1.80 0.18 1.94 0.019 2.04 0.007 2.22 0.002 2.52 0.001 3.12 0.0003 ALD810016 1.60 VIN (V) RDS(ON) (MΩ) 1.20 12000 1.30 1300 1.40 140 1.50 15 1.60 1.6 1.70 0.17 1.84 0.018 1.94 0.007 2.12 0.002 2.42 0.001 3.02 0.0003 Selection of an SAB MOSFET device depends on a set of desired voltage vs. current characteristics that closely match the supercapacitor operating VIN voltage and IOUT currents that provide the best leakage and regulation profile of a supercapacitor load. The table lists VIN which corresponds to different supercapacitor load voltages. At each VIN = VGS = VDS bias voltage, a corresponding IOUT, Drain Source ON Current, IDS(ON), is produced by a specific SAB MOSFET, which is equal to the amount of current available to compensate for supercapacitor leakage current inbalances. This current results in an Equivalent ON Resistance RDS(ON) across a supercapacitor cell. Selection of an SAB MOSFET part number operating at maximum supercapacitor operating voltage at an IOUT that corresponds to the maximum supercapacitor leakage current offer the best possible tradeoff between leakage current balancing and voltage regulation. Notes: 1) The SAB MOSFET Output Current (IOUT) = Drain Source ON Current (IDS(ON)) and is the maximum current available to offset the supercapacitor leakage current. 2) The Input Voltage (VIN) = Drain Gate Source Voltage (VGS = VDS) and is normally the same as the voltage across the supercapacitor. ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 6 of 17 TABLE 2. ALD 9100XX SUPERCAPACITOR AUTO BALANCING (SAB™) MOSFETS EQUIVALENT ON RESISTANCE AT DIFFERENT INPUT VOLTAGES AND OUTPUT CURRENTS ALD Part Number OUTPUT CURRENT IOUT = IDS(ON) (µA) 1 GateThreshold VIN (V) 2 Voltage Equivalent ON Vt (V) Resistance (MΩ) 0.0001 0.001 0.01 0.1 1 10 TA = 25°C 100 300 1000 3000 10000 ALD910028 2.80 VIN (V) RDS(ON) (MΩ) 2.40 24000 2.50 2500 2.60 260 2.70 27 2.80 2.8 2.90 0.29 3.02 0.030 3.10 0.01 3.24 0.003 3.30 0.001 3.80 0.0004 ALD910027 2.70 VIN (V) RDS(ON) (MΩ) 2.30 23000 2.40 2400 2.50 250 2.60 26 2.70 2.7 2.80 0.28 2.92 0.029 3.00 0.01 3.14 0.003 3.20 0.001 3.70 0.0004 ALD910026 2.60 VIN (V) RDS(ON) (MΩ) 2.20 2.30 2.40 2.50 2.60 2.70 2.82 2.90 3.04 3.10 3.60 22000 2300 240 25 2.6 0.27 0.028 0.01 0.003 0.001 0.0004 ALD910025 2.50 VIN (V) RDS(ON) (MΩ) 2.10 21000 2.20 2200 2.30 230 2.40 24 2.50 2.5 2.60 0.26 2.72 0.027 2.80 0.01 2.94 0.003 3.00 0.001 3.50 0.0004 ALD910024 2.40 VIN (V) RDS(ON) (MΩ) 2.00 20000 2.10 2100 2.20 220 2.30 23 2.40 2.4 2.50 0.25 2.62 0.026 2.70 0.009 2.84 0.003 2.90 0.001 3.40 0.0003 ALD910023 2.30 VIN (V) RDS(ON) (MΩ) 1.90 19000 2.00 2000 2.10 210 2.20 22 2.30 2.3 2.40 0.24 2.52 0.025 2.60 0.009 2.74 0.003 2.80 0.001 3.30 0.0003 ALD910022 2.20 VIN (V) RDS(ON) (MΩ) 1.80 18000 1.90 1900 2.00 200 2.10 21 2.20 2.2 2.30 0.23 2.42 0.024 2.50 0.008 2.64 0.003 2.70 0.001 3.20 0.0003 ALD910021 2.10 VIN (V) RDS(ON) (MΩ) 1.70 17000 1.80 1800 1.90 190 2.00 20 2.10 2.1 2.20 0.22 2.32 0.023 2.40 0.008 2.54 0.003 2.60 0.001 3.10 0.0003 ALD910020 2.00 VIN (V) RDS(ON) (MΩ) 1.60 16000 1.70 1700 1.80 180 1.90 19 2.00 2.0 2.10 0.21 2.22 0.022 2.30 0.008 2.44 0.002 2.50 0.001 3.00 0.0003 ALD910019 1.90 VIN (V) RDS(ON) (MΩ) 1.50 15000 1.60 1600 1.70 170 1.80 18 1.90 1.9 2.00 0.20 2.12 0.021 2.20 0.007 2.34 0.002 2.40 0.001 2.90 0.0003 ALD910018 1.80 VIN (V) RDS(ON) (MΩ) 1.40 14000 1.50 1500 1.60 160 1.70 17 1.80 1.8 1.90 0.19 2.02 0.020 2.10 0.007 2.24 0.002 2.30 0.001 2.80 0.0003 ALD910017 1.70 VIN (V) RDS(ON) (MΩ) 1.30 13000 1.40 1400 1.50 150 1.60 16 1.70 1.7 1.80 0.18 1.92 0.019 2.00 0.007 2.14 0.002 2.20 0.001 2.70 0.0003 ALD910016 1.60 VIN (V) RDS(ON) (MΩ) 1.20 12000 1.30 1300 1.40 140 1.50 15 1.60 1.6 1.70 0.17 1.82 0.018 1.90 0.007 2.04 0.002 2.10 0.001 2.60 0.0003 Selection of an SAB MOSFET device depends on a set of desired voltage vs. current characteristics that closely match the supercapacitor operating VIN voltage and IOUT currents that provide the best leakage and regulation profile of a supercapacitor load. The table lists VIN which corresponds to different supercapacitor load voltages. At each VIN = VGS = VDS bias voltage, a corresponding IOUT, Drain Source ON Current, IDS(ON), is produced by a specific SAB MOSFET, which is equal to the amount of current available to compensate for supercapacitor leakage current inbalances. This current results in an Equivalent ON Resistance RDS(ON) across a supercapacitor cell. Selection of an SAB MOSFET part number operating at maximum supercapacitor operating voltage at an IOUT that corresponds to the maximum supercapacitor leakage current offer the best possible tradeoff between leakage current balancing and voltage regulation. Notes: 1) The SAB MOSFET Output Current (IOUT) = Drain Source ON Current (IDS(ON)) and is the maximum current available to offset the supercapacitor leakage current. 2) The Input Voltage (VIN) = Drain Gate Source Voltage (VGS = VDS) and is normally the same as the voltage across the supercapacitor. ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 7 of 17 TYPICAL PERFORMANCE CHARACTERISTICS ALD8100xx INPUT VOLTAGE vs. OUTPUT CURRENT ALD8100xx FORWARD TRANSFER CHARACTERISTICS - LOW VOLTAGE -02 1.0 E 500 -03 1.0 E OUTPUT CURRENT IOUT = IDS(ON) (A) OUTPUT CURRENT IOUT = IDS(ON) (µA) -04 1.0 E + 125°C -05 1.0 E -06 1.0 E + 70°C - 40°C -07 1.0 E 0°C -08 1.0 E 400 VIN = VGS = VDS TA = + 25°C 300 200 100 + 25°C -09 1.0 E -10 0 1.0 E Vt-0.5 Vt-0.3 Vt-0.1 Vt+0.1 Vt+0.3 Vt+0.5 Vt+0.7 -0.3 -0.2 INPUT VOLTAGE - VIN = VGS = VDS (V) -0.1 +0.1 0 +0.2 +0.3 +0.4 +0.5 INPUT OVERDRIVE VOLTAGE VIN - Vt (V) ALD8100xx OUTPUT CHARACTERISTICS ALD8100xx FORWARD TRANSFER CHARACTERISTICS EXPANDED (SUBTHRESHOLD) 100 1000000.00 VIN = VGS = VDS TA = + 25°C 10000.00 OUTPUT CURRENT IOUT = IDS(ON) (mA) OUTPUT CURRENT IOUT = IDS(ON) (nA) 100000.00 1000.00 100.00 10.00 1.00 80 60 40 Vt = 2.80V 20 0.10 0 0.01 -0.4 -0.3 -0.2 -0.1 0.0 +0.1 +0.2 0 +0.3 OFFSET VOLTAGE - VOS (mV) EQUIVALENT ON RESISTANCE RDS(ON) (MΩ) 100000.00 TA = + 25°C 1000.00 100.00 10.00 1.00 0.10 0.01 0.001 Vt -0.3 Vt -0.2 Vt -0.1 Vt Vt +0.1 Vt +0.2 8 10 ALD8100xx OFFSET VOLTAGE vs. AMBIENT TEMPERATURE ALD8100xx EQUIVALENT ON RESISTANCE vs. INPUT VOLTAGE 10000.00 6 4 2 INPUT VOLTAGE - VIN = VGS = VDS (V) INPUT OVERDRIVE VOLTAGE VIN - Vt (V) Vt -0.4 Vt = 2.50V Vt = 2.00V Vt +0.3 Vt +0.4 +10 +8 THREE REPRESENTATIVE UNITS VOS = VtM1 - VtM2 VOS = VtM3 - VtM4 +6 +4 +2 0 -2 -4 -6 -8 -10 -50 INPUT VOLTAGE - VIN (V) ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY -25 0 +25 +50 +75 +100 +125 AMBIENT TEMPERATURE - TA (°C) 8 of 17 TYPICAL PERFORMANCE CHARACTERISTICS (cont.) ALD8100xx OUTPUT CURRENT vs. AMBIENT TEMPERATURE 2.0 600 1.8 OUTPUT CURRENT IOUT = IDS(ON) ( mA) DRAIN OFF LEAKAGE CURRENT IDS(OFF) (pA) ALD8100xx DRAIN OFF LEAKAGE CURRENT vs. AMBIENT TEMPERATURE 500 VIN = Vt - 1.0V 400 300 200 IDS(OFF) 100 1.6 125°C 1.4 1.2 1.0 Zero Temperature Coefficient (ZTC) 0.8 0.6 0.4 - 25°C 0.2 0 0 -50 0 -25 +25 +50 +75 +100 +0.0 +125 +0.2 +0.4 +0.6 +1.0 +0.8 INPUT OVERDRIVE VOLTAGE VIN - Vt (V) AMBIENT TEMPERATURE - TA (°C) ALD9100xx INPUT VOLTAGE vs. OUTPUT CURRENT ALD9100xx FORWARD TRANSFER CHARACTERISTICS - LOW VOLTAGE -02 1.0 E 500 -03 OUTPUT CURRENT IOUT = IDS(ON) (µA) OUTPUT CURRENT IOUT = IDS(ON) (A) 1.0 E -04 1.0 E + 125°C -05 1.0 E -06 1.0 E -07 + 70°C - 40°C 1.0 E 0°C -08 1.0 E VIN = VGS = VDS TA = + 25°C 300 200 100 + 25°C -09 1.0 E 0 -10 1.0 E Vt-0.5 400 Vt-0.3 Vt-0.1 Vt+0.1 Vt+0.3 Vt+0.5 -0.3 Vt+0.7 -0.2 -0.1 0 +0.1 +0.2 +0.3 +0.4 +0.5 INPUT OVERDRIVE VOLTAGE VIN - Vt (V) INPUT VOLTAGE - VIN = VGS = VDS (V) ALD9100xx FORWARD TRANSFER CHARACTERISTICS EXPANDED (SUBTHRESHOLD) ALD9100xx OUTPUT CHARACTERISTICS 1000000.00 100 10000.00 VIN = VGS = VDS TA = + 25°C OUTPUT CURRENT IOUT = IDS(ON) (mA) OUTPUT CURRENT IOUT = IDS(ON) (nA) 100000.00 1000.00 100.00 10.00 1.00 80 60 Vt = 2.80V 40 Vt = 2.50V Vt = 2.00V 20 0.10 0 0.01 -0.4 -0.3 -0.2 -0.1 0.0 +0.1 +0.2 +0.3 INPUT OVERDRIVE VOLTAGE VIN - Vt (V) ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 0 2 4 6 8 10 INPUT VOLTAGE - VIN = VGS = VDS (V) 9 of 17 TYPICAL PERFORMANCE CHARACTERISTICS (cont.) ALD9100xx EQUIVALENT ON RESISTANCE vs. INPUT VOLTAGE ALD9100xx OFFSET VOLTAGE vs. AMBIENT TEMPERATURE 10000.00 OFFSET VOLTAGE - VOS (mV) EQUIVALENT ON RESISTANCE RDS(ON) (MΩ) 100000.00 TA = + 25°C 1000.00 100.00 10.00 1.00 0.10 0.01 THREE REPRESENTATIVE UNITS VOS = VtM1 - VtM2 +6 +4 +2 0 -2 -4 -6 -8 -10 0.001 Vt -0.4 +10 +8 Vt -0.3 Vt -0.2 Vt -0.1 Vt Vt +0.1 Vt +0.2 Vt +0.3 Vt +0.4 -50 0 +25 +50 +75 +100 +125 ALD9100xx OUTPUT CURRENT vs. AMBIENT TEMPERATURE ALD9100xx DRAIN OFF LEAKAGE CURRENT vs. AMBIENT TEMPERATURE 4.0 600 3.6 500 OUTPUT CURRENT IOUT = IDS(ON) ( mA) DRAIN OFF LEAKAGE CURRENT IDS(OFF) (pA) -25 AMBIENT TEMPERATURE - TA (°C) INPUT VOLTAGE - VIN (V) VIN = Vt - 1.0V 400 300 200 IDS(OFF) 100 3.2 125°C 2.8 2.4 2.0 Zero Temperature Coefficient (ZTC) 1.6 1.2 0.8 - 25°C 0.4 0 0 -50 -25 0 +25 +50 +75 +100 +125 +0.0 AMBIENT TEMPERATURE - TA (°C) ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY +0.2 +0.4 +0.6 +0.8 +1.0 INPUT OVERDRIVE VOLTAGE VIN - Vt (V) 10 of 17 TYPICAL ALD8100XX APPLICATIONS TYPICAL CONNECTION FOR A FOUR-SUPERCAP STACK ALD8100xx PIN DIAGRAM 1 IC* M1 DN1 2 M2 GN1 3 V- SN1 4 V- V- 5 M3 M4 DN4 6 GN4 7 SN4 16 IC* 15 DN2 14 GN2 13 SN2 12 V+ 11 DN3 10 V- 8 V- 9 SCHEMATIC DIAGRAM OF A TYPICAL CONNECTION FOR A FOUR-SUPERCAP STACK ALD8100XX 2, 12 3 V+ ≤ +15.0V IDS(ON) ≤ 80mA + M1 4 14 M2 13 11 10 7 + M4 V- 8 + C2 13 V+ 11 V2 + C3 V- 9 EXAMPLE OF ALD810025 CONNECTION ACROSS FOUR SUPERCAPS IN SERIES V+ = 10.0V ALD810025 2, 12 Vt=2.5V + M1 C1 4 15 7 V1 ≈ 7.5V + M4 C2 V2 ≈ 5.0V Vt=2.5V + M3 9 6 C4 Vt=2.5V M2 13 11 10 C3 V3 ≈ 2.5V Vt=2.5V + C4 1, 5, 8, 16 1, 5, 8, 16 1-16 DENOTES PACKAGE PIN NUMBERS C1-C4 DENOTES SUPERCAPACITORS V1 10 C4 V3 + M3 M4 7 + 14 C3 V- 12 6 3 C2 V- 5 V3 V2 M3 9 6 V1 15 14 4 V1 + M2 3 + C1 C1 15 M1 2 GN3 SN3 16 1 V+ 1-16 DENOTES PACKAGE PIN NUMBERS C1-C4 DENOTES SUPERCAPACITORS ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 11 of 17 TYPICAL ALD8100XX APPLICATIONS (cont.) TYPICAL PARALLEL CONNECTION OF SAB MOSFETS WITH TWO SUPERCAPS V+ ≤ +15.0V IDS(ON) ≤ 80mA ALD8100XX 15 14 2, 12 3 M2 13 + M1 V+ ≤ +30.0V (2 x 15.0V) 2, 12 3 C1 4 V1 11 6 7 SERIES CONNECTION OF TWO FOUR-SUPERCAP STACKS EACH WITH A SEPARATE SAB MOSFET PACKAGE 10 M4 14 C2 ALD8100XX STACK 1 V+ - VA ≤ +15.0V 9 1, 5, 8, 16 + M1 4 C1A 15 + M3 IDS(ON) ≤ 80mA 1-16 DENOTES PACKAGE PIN NUMBERS C1-C2 DENOTES SUPERCAPACITORS M2 13 11 10 + M3 9 6 7 + + M4 C2A C3A C4A 1, 5, 8, 16 EXAMPLE OF ALD810025 CONNECTION ACROSS TWO SUPERCAPS IN SERIES VA ALD810025 2, 12 V+ = 10.0V 3 2, 12 3 M1 4 + ALD8100XX STACK 2 VA ≤ +15.0V C1 M2 13 M3 9 + + + M3 9 6 7 M4 + C2B C3B C4B C2 6 7 M2 13 11 10 V1 ≈ 5.0V 11 10 C1B 15 14 15 14 + M1 4 1, 5, 8, 16 M4 1, 5, 8, 16 1-16 DENOTES PACKAGE PIN NUMBERS C1A-C4B DENOTES SUPERCAPACITORS 1-16 DENOTES PACKAGE PIN NUMBERS C1-C2 DENOTES SUPERCAPACITORS ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 12 of 17 TYPICAL ALD8100XX APPLICATIONS (cont.) TYPICAL SERIES CONNECTION OF SAB MOSFETS WITH THREE SUPERCAPS V+ ≤ +15.0V IDS(ON) ≤ 80mA ALD8100XX SERIES CONNECTION OF TWO THREE-SUPERCAP STACKS EACH WITH A SEPARATE SAB MOSFET PACKAGE V+ ≤ +30.0V (2 x 15.0V) 2, 12 3 + M1 4 IDS(ON) ≤ 80mA C1 V1 15 14 2, 12 3 + M2 ALD8100XX STACK 1 V+ - VA ≤ +15.0V C2 13 V2 11 10 + C1A 15 14 M2 + C2A 13 + M3 M1 4 C3 11 9 10 1, 5, 6, 7, 8, 16 M3 + C3A 9 1, 5, 6, 7, 8, 16 1-16 DENOTES PACKAGE PIN NUMBERS C1-C3 DENOTES SUPERCAPACITORS VA 2, 12 3 EXAMPLE OF ALD810028 CONNECTION ACROSS THREE SUPERCAPS IN SERIES 14 14 ALD8100XX STACK 2 VA ≤ +15.0V 2, 12 Vt=2.8V + C1 M1 4 15 M2 + M2 + C2B 13 11 10 M3 + C3B 9 V1 = 5.4V Vt=2.8V C1B 15 V+ = 8.1V ALD810028 3 + M1 4 1, 5, 6, 7, 8, 16 C2 13 11 10 M3 V2 = 2.7V Vt=2.8V + C3 1-16 DENOTES PACKAGE PIN NUMBERS C1A-C3B DENOTES SUPERCAPACITORS 9 1, 5, 6, 7, 8, 16 1-16 DENOTES PACKAGE PIN NUMBERS C1-C3 DENOTES SUPERCAPACITORS ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 13 of 17 TYPICAL ALD9100XX APPLICATIONS ALD9100XX PIN DIAGRAM TYPICAL CONNECTION FOR A TWO-SUPERCAP STACK V+ 8 V+ 1 GN1 2 7 GN2 2 7 DN1 3 6 DN2 3 6 IC* 1 V- + 8 V- C1 SN1 4 5 SN2, V- SCHEMATIC DIAGRAM OF A TYPICAL CONNECTION FOR A TWO-SUPERCAP STACK ALD9100XX 3, 8 2 7 M2 + C2 5 EXAMPLE OF ALD910028 CONNECTION ACROSS TWO SUPERCAPS IN SERIES V+ ≤ +15.0V V+ = 5.4V ALD910028 IDS(ON) ≤ 80mA + 2 C1 M1 4 6 4 V1 3, 8 Vt=2.8V + C1 M1 4 V1 6 + 7 C2 M2 1, 5 1-8 DENOTES PACKAGE PIN NUMBERS C1-C2 DENOTES SUPERCAPACITORS V1 ≈ 2.7V Vt=2.8V + C2 1, 5 1-8 DENOTES PACKAGE PIN NUMBERS C1-C2 DENOTES SUPERCAPACITORS ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 14 of 17 TYPICAL ALD9100XX APPLICATIONS (cont.) SERIES CONNECTION OF TWO TWO-SUPERCAP STACKS EACH WITH A SEPARATE SAB MOSFET PACKAGE EXAMPLE OF ALD910026 CONNECTION ACROSS TWO TWO-SUPERCAP STACKS EACH WITH A SEPARATE SAB MOSFET PACKAGE V+ ≤ +30.0V (2 x 15.0V) V+ ≈ 10.0V IDS(ON) ≤ 80mA 3, 8 2 M1 ALD9100XX STACK 1 V+ - VA ≤ +15.0V 2 + C1A 4 6 7 ALD910026 STACK 1 V+ - VA ≈ +5.0V + 6 ALD9100XX STACK 2 VA ≤ +15.0V 7 M2 + C2A 2 C1B + C2B ALD910026 STACK 2 VA ≈ +5.0V 1, 5 1-8 DENOTES PACKAGE PIN NUMBERS C1A-C2B DENOTES SUPERCAPACITORS VA ≈ 5.0V 3, 8 + 4 6 Vt=2.6V M2 VA 3, 8 M1 C1A 1, 5 1, 5 2 + 4 7 C2A M2 3, 8 Vt=2.6V M1 M1 Vt=2.6V + Vt=2.6V + C1B 4 6 7 M2 C2B 1, 5 1-8 DENOTES PACKAGE PIN NUMBERS C1A-C2B DENOTES SUPERCAPACITORS ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 15 of 17 SOIC-16 PACKAGE DRAWING 16 Pin Plastic SOIC Package E Millimeters Dim S (45°) D A Min 1.35 Max 1.75 Min 0.053 Max 0.069 A1 0.10 0.25 0.004 0.010 b 0.35 0.45 0.014 0.018 C 0.18 0.25 0.007 0.010 D-16 9.80 10.00 0.385 0.394 E 3.50 4.05 0.140 0.160 1.27 BSC e e Inches 0.050 BSC H 5.70 6.30 0.224 0.248 L 0.60 0.937 0.024 0.037 A ø 0° 8° 0° 8° A1 S 0.25 0.50 0.010 0.020 b S (45°) H L C ø ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 16 of 17 SOIC-8 PACKAGE DRAWING 8 Pin Plastic SOIC Package E Millimeters Dim S (45°) D A Min 1.35 Max 1.75 Min 0.053 Max 0.069 A1 0.10 0.25 0.004 0.010 b 0.35 0.45 0.014 0.018 C 0.18 0.25 0.007 0.010 D-8 4.69 5.00 0.185 0.196 E 3.50 4.05 0.140 0.160 1.27 BSC e A A1 e b Inches 0.050 BSC H 5.70 6.30 0.224 0.248 L 0.60 0.937 0.024 0.037 ø 0° 8° 0° 8° S 0.25 0.50 0.010 0.020 S (45°) H L C ø ALD8100XX/ALD9100XX SUPERCAPACITOR Advanced Linear Devices, Inc. AUTO BALANCING (SAB) MOSFET ARRAY FAMILY 17 of 17