Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD19538Q2 SLPS582 – JULY 2016 CSD19538Q2 100-V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • 1 Product Summary Ultra-Low Qg and Qgd Low-Thermal Resistance Avalanche Rated Lead Free RoHS Compliant Halogen Free SON 2-mm × 2-mm Plastic Package TA = 25°C TYPICAL VALUE Drain-to-Source Voltage 100 V Qg Gate Charge Total (10 V) 4.3 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage Power Over Ethernet (PoE) Power Sourcing Equipment (PSE) Motor Control This 100-V, 49-mΩ, SON 2-mm × 2-mm NexFET™ power MOSFET is designed to minimize losses in power conversion applications. Top View 1 6 mΩ V MEDIA QTY PACKAGE SHIP 3000 CSD19538Q2T 7-Inch Reel 250 SON 2.00-mm x 2.00-mm Plastic Package Tape and Reel Absolute Maximum Ratings TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 100 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package Limited) 14.4 Continuous Drain Current (Silicon Limited), TC = 25°C 13.1 D 5 2 S 4 D PD S P0108-01 Continuous Drain Current(1) 4.6 Pulsed Drain Current(2) 34.4 Power Dissipation(1) 2.5 Power Dissipation, TC = 25°C 20.2 TJ, Tstg Operating Junction Temperature, Storage Temperature EAS Avalanche Energy, Single Pulse ID = 12.6 A, L = 0.1 mH, RG = 25 Ω A A W –55 to 150 °C 8 mJ (1) Typical RθJA = 50°C/W on a 1-in2, 2-oz Cu pad on a 0.06-in thick FR4 PCB. (2) Max RθJC = 6.2°C/W, pulse duration ≤ 100 μs, duty cycle ≤ 1%. . . RDS(on) vs VGS Gate Charge 10 200 TC = 25qC, ID = 5 A TC = 125qC, ID = 5 A 180 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 49 3.2 7-Inch Reel IDM 3 VGS = 10 V DEVICE D G mΩ CSD19538Q2 ID D nC 58 (1) For all available packages, see the orderable addendum at the end of the data sheet. 3 Description D 0.8 VGS = 6 V Device Information(1) 2 Applications • • • UNIT VDS 160 140 120 100 80 60 40 20 0 ID = 5 A 9 VDS = 100 V 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 0 0.5 1 1.5 2 2.5 3 3.5 Qg - Gate Charge (nC) 4 4.5 5 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD19538Q2 SLPS582 – JULY 2016 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 1 1 1 2 3 7 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 Q2 Package Dimensions .......................................... 8 7.2 Q2 Tape and Reel Information................................ 11 Device and Documentation Support.................... 7 4 Revision History 2 DATE REVISION NOTES July 2016 * Initial release. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 CSD19538Q2 www.ti.com SLPS582 – JULY 2016 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 80 V 1 μA IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA V RDS(on) Drain-to-source on-resistance gfs Transconductance 100 2.8 V 3.2 3.8 VGS = 6 V, ID = 5 A 58 72 VGS = 10 V, ID = 5 A 49 59 VDS = 10 V, ID = 5 A 19 mΩ S DYNAMIC CHARACTERISTICS Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance Qg Gate charge total (10 V) Qgd Gate charge gate-to-drain Qgs Gate charge gate-to-source Qg(th) Gate charge at Vth Qoss Output charge td(on) Turnon delay time tr Rise time td(off) Turnoff delay time tf Fall time VGS = 0 V, VDS = 50 V, ƒ = 1 MHz VDS = 50 V, ID = 5 A VDS = 50 V, VGS = 0 V VDS = 50 V, VGS = 10 V, IDS = 5 A, RG = 0 Ω 349 454 pF 69 90 pF 12.6 16.4 pF 4.6 9.2 Ω 4.3 5.6 nC 0.8 nC 1.6 nC 1.0 nC 12.3 nC 5 ns 3 ns 7 ns 2 ns DIODE CHARACTERISTICS VSD Diode forward voltage ISD = 5 A, VGS = 0 V 0.85 1.0 V Qrr Reverse recovery charge nC Reverse recovery time VDS= 50 V, IF = 5 A, di/dt = 300 A/μs 94 trr 32 ns 5.2 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC (1) RθJC Junction-to-case thermal resistance RθJA Junction-to-ambient thermal resistance (1) (2) (1) (2) MIN TYP MAX UNIT 6.2 °C/W 65 RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 3 CSD19538Q2 SLPS582 – JULY 2016 GATE www.ti.com GATE Source Source Max RθJA = 250°C/W when mounted on a minimum pad area of 2-oz (0.071-mm) thick Cu. Max RθJA = 65°C/W when mounted on 1-in2 (6.45-cm2) of 2-oz (0.071-mm) thick Cu. DRAIN DRAIN M0161-02 M0161-01 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 CSD19538Q2 www.ti.com SLPS582 – JULY 2016 Typical MOSFET Characteristics (continued) 30 30 27 27 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) TA = 25°C (unless otherwise stated) 24 21 18 15 12 9 6 VGS = 6 V VGS = 8 V VGS = 10 V 3 TC = 125° C TC = 25° C TC = -55° C 24 21 18 15 12 9 6 3 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VDS - Drain-to-Source Voltage (V) 4.5 5 1 2 3 4 5 VGS - Gate-to-Source Voltage (V) D002 6 7 D003 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 9 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 1000 100 10 2 1 1 0 0 0.5 1 1.5 2 2.5 3 3.5 Qg - Gate Charge (nC) ID = 5 A 4 4.5 0 5 10 20 D004 100 D005 Figure 5. Capacitance 200 RDS(on) - On-State Resistance (m:) 3.8 VGS(th) - Threshold Voltage (V) 90 VDS = 100 V Figure 4. Gate Charge 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 -75 30 40 50 60 70 80 VDS - Drain-to-Source Voltage (V) TC = 25qC, ID = 5 A TC = 125qC, ID = 5 A 180 160 140 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 175 0 2 D006 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 5 CSD19538Q2 SLPS582 – JULY 2016 www.ti.com Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise stated) 100 2 VGS = 6 V VGS = 10 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 2.2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 -75 TC = 25° C TC = 125° C 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) 125 150 175 0 0.2 D008 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) 1 1.2 D009 ID = 5 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 100 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 100 10 1 0.1 DC 10 ms 1 ms 0.01 0.1 100 µs 10 µs 1 10 100 VDS - Drain-to-Source Voltage (V) 1000 TC = 25q C TC = 125q C 10 1 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D011 Single Pulse, Max RθJC = 6.2°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (qC) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 CSD19538Q2 www.ti.com SLPS582 – JULY 2016 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.3 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 7 CSD19538Q2 SLPS582 – JULY 2016 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q2 Package Dimensions 2.1 1.9 A B PIN 1 INDEX AREA 2.1 1.9 0.8 MAX C SEATING PLANE 0.05 0.00 0.75±0.1 PKG (0.2) (0.2) TYP (0.47) 0.3±0.05 3 4 7 4X 0.65 (0.5) PKG 2X 1.3 8 0.95±0.1 6 1 (0.2) PIN 1 ID (45 X0.3) 6X 1±0.1 6X 0.3 0.2 0.35 0.25 0.1 0.05 C A C B 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance. 8 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 CSD19538Q2 www.ti.com SLPS582 – JULY 2016 Q2 Package Dimensions (continued) 7.1.1 Recommended PCB Pattern (1) PKG 6X (0.45) 1 6 8 6X (0.3) (0.95) (0.325) PKG 4X (0.65) (0.65) 7 4 3 (R0.05) TYP (0.3) (0.095) (0.75) (1.95) 0.05 MIN ALL AROUND 0.05 MAX ALL AROUND SOLDER MASK OPENING METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED 1. For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 2. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 9 CSD19538Q2 SLPS582 – JULY 2016 www.ti.com Q2 Package Dimensions (continued) 7.1.2 Recommended Stencil Pattern (0.9) METAL ALL AROUND, TYP PKG 6X (0.45) 1 6 6X (0.3) 8 (0.86) (0.325) PKG 4X (0.65) (0.65) 3 (R0.05) TYP 7 (0.29) 4 (0.095) (0.7) (1.95) 1. All linear dimensions are in millimeters. 2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 CSD19538Q2 www.ti.com SLPS582 – JULY 2016 7.2 Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Other material available 4. Typical SR of form tape Max 109 OHM/SQ 5. All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD19538Q2 11 PACKAGE OPTION ADDENDUM www.ti.com 12-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD19538Q2 ACTIVE WSON DQK 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 150 1958 CSD19538Q2T ACTIVE WSON DQK 6 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 150 1958 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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