OKI MSM7716PMB Single rail linear codec Datasheet

FEDL7716P-01
OKI Semiconductor
MSM7716P
This issue: June 17, 2004
Single Rail Linear CODEC
GENERAL DESCRIPTION
The MSM7716P is an extended temperature range version for the MSM7716 which is a single-channel CODEC
CMOS IC for voice signals that contains filters for linear A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is optimized for
applications for the analog interfaces of audio signal processing DSPs and digital wireless systems.
The analog output signal can directly drive a ceramic type handset receiver. In addition, levels for analog outputs
can be set by external control.
FEATURES
• Single power supply
: +3.0V to +3.6 V
• Operating temperature
: -40°C to +85 °C
Remarks : Standard operating temperature range version MSM7716 (without “P”)
- Power Supply Voltage : +2.7V to +3.6 V
- Operating temperature : -30°C to +85 °C
• Low power consumption
Operating mode
: 30 mW Typ.
Power down mode
: 0.05 mW Typ.
• Digital signal input/output interface : 14-bit serial code in 2's complement format
• Sampling frequency(fs)
: 4 to 16 kHz
• Transmission clock frequency
: fs × 14 min., 2048 kHz max.
• Filter characteristics
: when fs = 8 kHz, complies with ITU-T Recommendation G. 714
• Built-in PLL eliminates a master clock
• Two input circuits in transmit section
• Two output circuits in receive section
• Transmit gain adjustable using an external resistor
• Receive gain adjustable by external control 8 steps, 4 dB/step
• Transmit mic-amp is eliminated by the gain setting of a maximum of 36 dB.
• Analog outputs can drive a load of a minimum of 1 kΩ ; an amplitude of a maximum of 4.0 VPP with push-pull
driving.
• Built-in reference voltage supply
• Package options:
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (MSM7716PMB)
1/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
BLOCK DIAGRAM
MAO
SW1
MAIN
SW1
RC
LPF
SW1
8th
BPF
14BIT
ADCONV
PCMOUT
T CONT
SYNC
PBO
BCLK
SW2
PBIN
SW2
AUT O
ZERO
SW2
SG
GEN
SGC
VR
GEN
SG
VFO
SW4
SW4
PWI
RT IM
SW3
VOL
SW3
SW4
AUXO
PLL
RC
LPF
5th
LPF
SW4
14BIT
DACONV
PWD
RCONT
PCMIN
PWD Logic
PDN
CONT
Logic
DEN
SG
SW
CONT
SG
VOL
CONT
SW3
CDIN
DCLK
SW3
AOUT-
VDD
SG
AOUT+
AG
DG
SG
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FEDL7716P-01
OKI Semiconductor
MSM7716P
PIN CONFIGURATION (TOP VIEW)
AG
AUXO
AOUT+
AOUT–
PWI
VFO
NC
NC
NC
VDD
DCLK
NC
CDIN
DEN
DG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SGC
PBIN
PBO
NC
NC
MAO
MAIN
NC
NC
PDN
SYNC
NC
BCLK
PCMOUT
PCMI
NC : No connect pin
30-Pin Plastic SSOP
3/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
PIN AND FUNCTIONAL DESCRIPTIONS
MAIN, MAO
Transmit microphone input and the level adjustment.
MAIN is connected to the noninverting input of the op-amp, and MAO is connected to the output of the op-amp.
The level adjustment should be configured as shown below.
During power saving and power down modes, the MAO output is in high impedance state.
C1
R2
Microphone input
MAO
MAIN
R1
–
+
R1 : variable
R2 > 20 kΩ
C1 > 1/ (2 × 3.14 × 30 × R3) (F)
Gain = R2/R1 < 63
SG
PBIN, PBO
Transmit handset input and the level adjustment.
PBIN is connected to the noninverting input of the op-amp, and PBO is connected to the output of the op-amp. The
level adjustment should be configured as shown below.
During power saving and power down, the PBO output is in high impedance state.
R4
Handset
microphone input
C2
PBO
PBIN
R3
–
+
R3 : variable
R4 > 20 kΩ
C2 > 1/ (2 × 3.14 × 30 × R3) (F)
Gain = R4/R3 < 63
SG
VDD
Power supply pin for +3.0 to 3.6 V (Typically 3.3 V).
AG
Analog signal ground.
DG
Ground pin for the digital signal circuits.
This ground is separated from the analog signal ground in this device. The DG pin must be connected to the AG pin
on the printed circuit board.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
VFO
Receive filter output.
The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage when the digital signal of
+3 dBm0 is input to PCMIN. VFO can drive a load of 20 kΩ or more.
This output can be externally controlled in the level range of 0 to –28 dB in 4 dB increments.
During power saving or power down, VFO output is at the voltage level (VDD/2) of SG with a high impedance
state.
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Thus, a receive level can be adjusted with the pins PWI,
AOUT–, and VFO described above.
The output of AOUT+ is inverted with respect to the output of AOUT– with a gain of 1.
The output signal amplitudes are a maximum of 2.0 VPP.
These outputs, above and below the signal ground voltage (VDD/2), can drive a load of a minimum of 1 kΩ with
push-pull driving (a load connected between AOUT+ and AOUT–).
The output amplitudes are 4 VPP maximum during push-pull driving. These outputs can be mute controlled
externally. These outputs are operational during power saving and output the SG voltage (VDD/2) in the high
impedance state.
AUXO
Auxiliary receive filter output.
The output signal is inverted with respect to the VFO output with a gain of 1. The output signal swings above and
below the SG voltage (VDD/2), and can drive a minimum load of 0.5 kΩ with respect to the SG voltage.
The output can be mute controlled externally.
During power saving and power down, AUXO outputs the SG voltage (VDD/2) in the high impedance state.
BCLK
Shift clock signal input for PCMIN and PCMOUT.
The frequency is equal to the data rate. Setting this signal to logic “1” or “0” drives both transmit and receive
circuits to the power-saving state.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
SYNC
Synchronizing signal input.
In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously with this
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the
transmit section.
In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN pin by the
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in
phase with the BCLK.
When this signal frequency is 8 kHz, the transmit and receive section have the frequency characteristics specified
by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in this data sheet.
For different frequencies of the SYNC signal, the frequency values in this data sheet should be translated
according to the following equation:
Frequency values described in the data sheet
8 kHz
× the SYNC frequency values to be actually used
Setting this signal to logic “1” or “0” drives the device to power-saving state.
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal synchronously with the SYNC signal and
BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal. The PCM signal is latched into the internal register
when shifted by 14 bits.
The top of the data (MSD) is identified at the rising edge of SYNC.
The input signal should be input in the 14-bit 2’s complement format.
The MSD bit represents the polarity of the signal with respect to the signal ground.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
PCMOUT
PCM signal output.
The PCM output signal is output from MSD in sequential order, synchronously with the rising edge of the BCLK
signal.
MSD may be output at the rising edge of the SYNC signal, depending on the timing between BCLK and SYNC.
This pin is in high impedance state except during 14-bit PCM output, and is in either in high impedance or in “L”
output state during power down and power saving mode.
A pull-up resistor must be connected to this pin, because its output is configured as an open drain.
The output coding format is in 14-bit 2’s complement.
The MSD represents a polarity of the signal with respect to the signal ground.
Table 1
Input/Output Level
PCMIN/PCMOUT
MSD
+Full scale
0
1
1
1
1
1
1
1
1
1
1
1
1
1
+1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–Full scale
1
0
0
0
0
0
0
0
0
0
0
0
0
0
PDN
Power down control signal input.
A digital “L” level drives both transmit and receive circuits to a power down state.
The control registers are set to the initial state.
Be sure to initialize the control registers by to execute this power down by keeping this pin to digital '0' level for
100 ns or longer after the power is turned on the power and the VDD exceeds 3.0 V.
SGC
Connection of a bypass capacitor for generating the signal ground voltage level.
Connect a 0.1 µF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
DEN, DCLK, CDIN
Serial control ports for the microcontroller interface.
Writing data to the 8-bit control register enables control of the receive output level and the signal path.
DEN is the “Enable” signal pin, DCLK is the data shift clock input pin, and CDIN is the control data input pin.
When powered down (PDN = 0), the initial values are set as shown in Tables 2, 3, and 4. The initial values are held
unless the control data is written after power-down release.
The control data is shifted at the rising edge of the DCLK signal and latched into the internal control register at the
rising edge of the DEN signal.
When the microcontroller interface is not used, these pins should be connected to DG.
The bit map of the 8-bit control register is shown below.
B7
B6
B5
B4
B3
B2
B1
B0
SW1
SW2
SW3
SW4
—
VOL1
VOL2
VOL3
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FEDL7716P-01
OKI Semiconductor
MSM7716P
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
VDD
AG = DG = 0 V
–0.3 to +7.0
V
Analog Input Voltage
VAIN
AG = DG = 0 V
–0.3 to VDD +0.3
V
Digital Input Voltage
VDIN
AG = DG = 0 V
–0.3 to VDD +0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Power Supply Voltage
VDD
—
3.0
3.3
3.6
V
Operating Temperature
Ta
—
–40
+25
+85
°C
Analog Input Voltage
VAIN
Gain = 1
—
—
1.4
VPP
High Level Input Voltage
VIH
SYNC, BCLK, PCMIN, PDN,
DEN, DCLK, CDIN
0.45×VD
—
VDD
V
—
0.16×VD
V
Low Level Input Voltage
VIL
D
0
D
Clock Frequency
FC
BCLK
14 × FS
—
128 × FS
kHz
Sync Pulse Frequency
FS
SYNC
4.0
8.0
16
kHz
Clock Duty Ratio
DC
BCLK
40
50
60
%
Digital Input Rise Time
tlr
—
50
ns
tlf
SYNC, BCLK, PCMIN, PDN,
DEN, DCLK, CDIN
—
Digital Input Fall Time
—
—
50
ns
100
—
—
ns
Sync Pulse Setting Time
tXS, tRS BCLK → SYNC, See Fig. 1
tSX, tSR SYNC → BCLK, See Fig. 1
100
—
—
ns
High Level Sync Pulse Width *1
tWSH
SYNC, See Fig. 1
1 BCLK
—
—
—
Low Level Sync Pulse Width *1
tWSL
SYNC, See Fig. 1
1 BCLK
—
—
—
PCMIN Setup Time
tDS
Refer to Fig. 1
100
—
—
ns
PCMIN Hold Time
tDH
Refer to Fig. 1
100
—
—
ns
RDL
Pull-up resistor
Digital Output Load
DCLK Pulse Width
DEN Setting Time 1
DEN Setting Time 2
0.5
—
—
kΩ
CDL
—
—
—
100
pF
tWCL
DCLK Low width, See Fig. 2
50
—
—
tWCH
DCLK High width, See Fig. 2
50
—
—
tCDL
DCLK → DEN, See Fig. 2
50
—
—
tDCL
DEN → DCLK, See Fig. 2
50
—
—
tCDH
DCLK → DEN, See Fig. 2
50
—
—
tDCH
DEN → DCLK, See Fig. 2
50
—
—
ns
ns
ns
CDIN Setup Time
tCDS
See Fig. 2
50
—
—
CDIN Hold Time
tCDH
See Fig. 2
50
—
—
Analog Input Allowable DC Offset
Voff
Transmit gain stage, Gain = 0 dB
–100
—
+100
mV
Transmit gain stage, Gain = 20 dB
–10
—
+10
mV
Allowable Jitter Width
—
—
—
1000
ns
SYNC, BCLK
ns
*1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is 2048 kHz.
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FEDL7716P-01
OKI Semiconductor
MSM7716P
RECOMMENDED OPERATING CONDITIONS (Continued)
Parameter
Symbol
Condition
tSD
Digital Output Delay Time
tXD1
CL = 50 pF + 1 LSTTL
Pull-up resistor = 500 Ω
tXD2
tXD3
Min.
Typ.
Max.
20
—
100
20
—
100
20
—
100
20
—
100
Unit
ns
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(Fs = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Parameter
Power Supply Current
High Level Input Voltage
Low Level Input Voltage
Symbol
Condition
Min.
Typ.
Max.
VDD = 3.6 V
—
10.0
17.0
Unit
IDD1
Operating mode
No signal
VDD = 3.0 V
—
8.0
13.0
IDD2
Power-saving mode, PDN = 1,
SYNC, BCLK → OFF
—
6.0
11.0
mA
IDD3
Power-down mode, PDN = 0
—
0.01
0.05
mA
—
VDD
V
VIH
VIL
0.45×VD
SYNC, BCLK, PCMIN, DEN,
CDIN, DCLK, PDN
mA
D
0.0
—
0.16×VD
V
D
High Level Input Leakage Current
IIH
—
—
—
2.0
µA
Low Level Input Leakage Current
IIL
—
—
—
0.5
µA
VOL
PCMOUT pull-up resistor = 500 Ω
0.0
0.2
0.4
V
Digital Output Leakage Current
IO
—
—
—
10
µA
Input Capacitance
CIN
—
—
5
—
pF
Digital Output Low Voltage
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FEDL7716P-01
OKI Semiconductor
MSM7716P
Transmit Analog Interface Characteristics
(Fs = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Min.
Typ.
Max.
Unit
Input Resistance
Parameter
Symbol
RINX
MAIN, PBIN
Condition
10
—
—
MΩ
Output Load Resistance
RLGX
MAO, PBO with respect to SG
20
—
—
kΩ
Output Load Capacitance
CLGX
—
—
30
pF
Output Amplitude
VOGX
–0.7
—
+0.7
V
Offset Voltage
VOSGX
–20
—
+20
mV
Gain = 1
Receive Analog Interface Characteristics
(Fs = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Parameter
Output Resistance
Output Load Resistance
Symbol
Min.
Typ.
Max.
Unit
AUXO, AOUT+, AOUT–
—
—
10
Ω
ROVO
VFO
—
—
100
Ω
RLAO
AUXO, AOUT+, AOUT–
(each) with respect to SG
0.5
—
—
kΩ
ROAO
Condition
RLVO
VFO with respect to SG
20
—
—
kΩ
Output Load Capacitance
CLAO
Output open
—
—
50
pF
Output Amplitude
VOAO
AUXO, AOUT+, AOUT–, VFO
with respect to SG
–1.0
—
+1.0
V
Offset Voltage
VOSA
AUXO, AOUT+, AOUT–, VFO
with respect to SG
–100
—
+100
mV
11/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
AC Characteristics
(FS = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Parameter
Overall Frequency Response
Transmit Frequency Response
(Expected Value)
Receive Frequency Response
(Expected Value)
Symbol
Freq.
(Hz)
Loss 1
60
Loss 2
300
Loss 3
1020
Loss 4
2020
Condition
Min.
Typ.
Max.
20
—
—
—
+0.4
–0.2
0
Analog
to
Analog
Reference
–0.2
—
+0.4
Loss 5
3000
–0.2
—
+0.4
Loss 6
3400
0
—
1.6
Loss T1
60
20
—
—
Loss T2
300
–0.15
—
+0.2
Loss T3
1020
Loss T4
2020
Loss T5
Loss T6
Reference
0
–0.15
—
+0.2
3000
–0.15
—
+0.2
3400
0
—
0.8
Loss R1
300
–0.15
—
+0.2
Loss R2
1020
Loss R3
2020
–0.15
—
+0.2
Loss R4
3000
–0.15
—
+0.2
Loss R5
3400
0.0
—
0.8
0
3
55.9
—
—
SD 2
0
55.9
—
—
55.9
—
—
45.9
—
—
35.9
—
—
SD 4
–10
1020
SD 5
–20
–30
Analog
to
Analog
*1
SD 6
–40
25.9
—
—
SD 7
–50
15.9
—
—
SD T1
3
58
—
—
SD T2
0
58
—
—
SD T3
–10
58
—
—
48
—
—
Transmit Signal to Distortion Ratio
SD T4
(Expected Value)
SD T5
1020
–20
*1
–30
38
—
—
SD T6
–40
28
—
—
SD T7
–50
18
—
—
SD R1
3
58
—
—
SD R2
0
58
—
—
58
—
—
48
—
—
38
—
—
SD R3
Receive Signal to Distortion Ratio
SD R4
(Expected Value)
SD R5
–10
1020
Unit
dB
dB
Reference
SD 1
SD 3
Overall Signal to Distortion Ratio
Level
(dBm0)
–20
–30
*1
SD R6
–40
28
—
—
SD R7
–50
18
—
—
dB
dB
dB
dB
*1 Psophometric filter is used.
12/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
AC Characteristics (Continued)
(FS = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
Freq.
(Hz)
GT 1
Transmit Gain Tracking
(Expected Value)
Receive Gain Tracking
(Expected Value)
GT 3
Condition
3
GT 2
Overall Gain Tracking
Level
(dBm0)
–10
1020
–40
Analog
to
Analog
Min.
Typ.
Max.
–0.4
+0.01
+0.4
Reference
–0.3
0.00
+0.8
–1.3
–0.03
+1.3
GT 4
–50
GT 5
–55
–1.6
–0.15
+1.6
GT T1
3
–0.3
+0.01
+0.3
GT T2
GT T3
–10
1020
–0.3
0.00
+0.3
GT T4
–50
–0.6
–0.03
+0.6
GT T5
–55
–1.2
+0.15
+1.2
GT R1
3
–0.3
–0.06
+0.3
GT R3
–10
1020
dB
Reference
–40
GT R2
Unit
dB
Reference
–40
–0.3
–0.02
+0.3
GT R4
–50
–0.6
–0.02
+0.6
GT R5
–55
–1.2
–0.27
+1.2
dB
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FEDL7716P-01
OKI Semiconductor
MSM7716P
AC Characteristics (Continued)
(FS = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Symbol
Freq.
(Hz)
Level
(dBm0)
Overall Idle Channel Noise
Nidle A
—
—
Transmit Idle Channel Noise
(Expected Value)
Nidle T
—
—
Parameter
Receive Idle Channel Noise
(Expected Value)
Nidle R
—
—
1020
0
AV T
Absolute Level (Initial Level)
AV R
Absolute Level
(Deviation of Temperature and
Power)
Absolute Delay
Transmit Group Delay
Receive Group Delay
Crosstalk Attenuation
AV Rt
1020
tGD T1
500
tGD T2
600 to 2600
tGD T3
2800
tGD R1
500 to 2600
tGD R2
2800
CR T
CR R
AIN: no signal
*1
AIN: no signal
*1
1020
Min.
Typ.
Max.
Unit
—
–70
–66
dBm0p
—
–71
–67
dBm0p
—
–76
–74
0.350
0.362
0.500
0.518
–0.2
—
+0.2
dB
–0.2
—
+0.2
dB
—
0.6
ms
VDD=3.0 V 0.338
Ta=25°C
*2 0.483
VDD = +3.0
to 3.6 V
Ta = –40
to 85°C
AV Tt
tD
Condition
Vrms
0
A to A
BCLK
= 64 kHz
—
—
—
0.325
0
*3
—
—
0.175
—
—
0.325
—
0.00
0.125
—
0.12
0.325
TRANS→RECV
75
85
—
RECV→TRANS
70
80
—
0
0
*3
ms
ms
dB
*1 Psophometric filter is used.
*2 AVT is defined at MAO and PBO-PCMOUT.
AVR is defined at PCMIN-VFO.
VOL = 0 dB
*3 Minimum value of the group delay distortion
14/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
AC Characteristics (Continued)
(FS = 8 kHz, VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
Parameter
Discrimination
Out-of-band Spurious
Intermodulation Distortion
Power Supply Noise Rejection
Ratio
Auxiliary Output Gain
VOL Gain Setting Value
Symbol
Freq.
(Hz)
Level
(dBm0)
Condition
Min.
Typ.
Max.
Unit
DIS
4.6 to
72 kHz
0
0 to
4000 Hz
30
32
—
dB
S
300 to
3400
0
4.6 to 100
kHz
—
–37.5
–35
dBm0
IMD
fa = 470
fb = 320
–4
2fa – fb
—
–52
–40
dBm0
PSR R
0 to
50 kHz
50 mVPP
*1
—
30
—
dB
GAUX
1020
0
VFO to AUXO
–1.0
0
+1.0
dB
GV2
Set at –4 dB
–5
–4
–3
GV3
–8 dB
–9
–8
–7
GV4
–12 dB
–13
–12
–11
–17
–16
–15
–21
–20
–19
GV7
Referenced –16 dB
to 0 dB
–20 dB
setting
–24 dB
–25
–24
–23
GV8
–28 dB
–29
–28
–27
PSR T
GV5
GV6
1020
0
dB
*1 Measured inband.
15/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
TIMING DIAGRAM
PCM Data Output Timing
Transmit Timing
BCLK
1
tXS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
16
17
tSX
tWSL
tWSH
SYNC
tSD
tXD1
PCMOUT
MSD D2
D3
D4
tXD2
D5
D6
D7
tXD3
D9 D10 D11 D12 D13 D14
D8
When tXS ≤ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1.
When tSX < 1/2 • Fc, the Delay of the MSD bit is defined as tSD.
Receive Timing
BCLK
1
tRS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tSR
tWSL
tWSH
SYNC
PCMIN
MSD D2
D3
D4
tDS
D5
tDH
D6
D7
D8
D9 D10 D11 D12 D13 D14
Figure 1 Basic Timing Diagram
MCU Interface Timing
DCLK
1
tCDL
2
3
4
5
6
tDCL
7
8
tCDH
9
10
11
12
13
tDCH
tWCL tWCH
DEN
tCDH
tCDS
CDIN
B7
B6
B5
B4
B3
B2
B1
B0
Figure 2 MCU Interface Timing Diagram
16/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
FUNCTIONAL DESCRIPTION
Control Data Description
SW1, SW2······Control bits for the transmit speech path switch.
The AD converter input is selected according to the bit data shown in Table 2.
Table 2
State
SW
2
SW
1
AD Converter Input
MAO
Output
PBO
Output
Remarks
T1
0
0
No signal (muting state)
SG
SG
—
T2
0
1
Input signal to MAIN
Effective
SG
At initial setting
T3
1
0
Input signal to PBIN
SG
Effective
—
T4
1
1
Addition signal of both
MAIN and PBIN
Effective
Effective
The gain of each input drops by 6dB
SW3, SW4······Control bits for the receive speech path switch.
The control should be performed according to Table 3.
Table 3
State
SW4
SW3
AOUT+, AOUT– Output
AUXO Output
Remarks
R1
0
0
SG
SG
—
R2
0
1
PWI
SG
At initial setting
R3
1
0
SG
DA
—
R4
1
1
PWI
DA
—
DA: DA converter output.
SG: signal ground voltage.
VOL1, VOL2, VOL3········Control bits for the receive signal output level.
By controlling these bits, the output levels of VFO and AUXO can be controlled
according to Table 4.
Table 4
VOL1
VOL2
VOL3
Receive Signal Gain
Remarks
0
0
0
0 dB
At initial setting
0
0
1
–4 dB
—
0
1
0
–8 dB
—
0
1
1
–12 dB
—
1
0
0
–16 dB
—
1
0
1
–20 dB
—
1
1
0
–24 dB
—
1
1
1
–28 dB
—
17/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
APPLICATION CIRCUIT
1 kΩ
+3.3V
MSM7716P
Microphone
analog input
Handset
analog input
Addition
signal input
1 µF
1 µF
1 µF
MAIN PCMOUT
PCM output
MAO
PCMIN
PCM input
PBIN
BCLK
PCM shift clock input
PBO
SYNC
8 kHz SYNC pulse input
20 kΩ
20 kΩ
20 kΩ
20 kΩ
VFO
20 kΩ
20 kΩ
PWI
PDN
20 kΩ
Analog output*
AOUT
Analog inverted
output*
AOUT
AUXO
Auxiliary output*
0.1 µF
SGC
AG
0V
Power down control input
“1” = Operation
“0” = Power down
DCLK
DEN
Controller
CDIN
DG
10 µF
+3.3 V
0 to 10 Ω
+
1 µF
VDD
* The swing of the analog output signal is a maximum of ±1.0 V above and below the VDD/2 offset level.
18/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
APPLICATION INFORMATION
Digital pattern for 0 dBm0
The digital pattern for 0 dBm0 is shown below.
(SYNC frequency = 8 kHz, signal frequency = 1 kHz)
S2
S3
S1
S4
SG
S5
S8
S6
S7
Sample No.
MSD
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
S1
0
0
1
0
0
0
1
0
1
0
1
0
1
1
S2
0
1
0
1
0
0
1
1
1
0
1
1
1
0
S3
0
1
0
1
0
0
1
1
1
0
1
1
1
0
S4
0
0
1
0
0
0
1
0
1
0
1
0
1
1
S5
1
1
0
1
1
1
0
1
0
1
0
1
0
0
S6
1
0
1
0
1
1
0
0
0
1
0
0
0
1
S7
1
0
1
0
1
1
0
0
0
1
0
0
0
1
S8
1
1
0
1
1
1
0
1
0
1
0
1
0
0
19/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
NOTES ON USE
• To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for
the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is
unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power
supply transformers surround the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-up that may otherwise
occur when power is turned on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid
erroneous operation and the degradation of the characteristics of these devices.
20/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
PACKAGE DIMENSIONS
(Unit: mm)
SSOP30-P-56-0.65-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.19 TYP.
5/Dec. 5, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
21/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
REVISION HISTORY
Document
No.
Date
FEDL7716P-01
Jun. 17, 2004
Page
Previous Current
Edition
Edition
–
–
Description
First edition
22/23
FEDL7716P-01
OKI Semiconductor
MSM7716P
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2004 Oki Electric Industry Co., Ltd.
23/23
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