LTC3852 Low Input Voltage, Synchronous Step-Down DC/DC Controller DESCRIPTION FEATURES n n n n n n n n n n n n n n Charge Pump Input Range: 2.7V to 5.5V Controller Input Range: 4V to 38V Integrated Charge Pump Provides 5V Gate Drive to Logic Level MOSFETs RSENSE or DCR Current Sensing ±1.25% Output Voltage Accuracy Over Temperature Phase-Lockable Fixed Frequency: 250kHz to 750kHz Power Good Output Voltage Monitor Adjustable Soft-Start Voltage Ramping Current Foldback Disabled During Start-Up No Reverse Current During Soft-Start Selectable Constant Frequency, Pulse-Skipping, or Burst Mode Operation Output Overvoltage Protection Very Low Dropout Operation: 99% Duty Cycle Available in a 24-Lead (3mm ¥ 5mm) QFN Package The LTC®3852 is a constant frequency, current mode step-down DC/DC controller which can be powered by an onboard charge pump. Input supplies as low as 2.7V, when doubled by the charge pump, provide 5V to the LTC3852’s control logic and gate drives, supporting a wide selection of logic-level N-channel power MOSFETs. The constant-frequency current mode architecture allows for a phase-lockable fixed frequency of up to 750kHz. The RUN pin provides a precision enable threshold while the TRACK/SS pin combines tracking and adjustable soft-start features. The MODE/PLLIN pin selects among Burst Mode® operation, pulse-skipping mode, and continuous current mode. Current foldback limits MOSFET power dissipation during short-circuit conditions. Reverse current and current foldback functions are disabled during soft-start. A power good output pin indicates when the output is within ±10% of its designed set point. APPLICATIONS n n n L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 6498466, 6580258, 6611131. General Purpose 3.3V Systems Lithium-Ion Powered Devices Distributed DC Power Systems TYPICAL APPLICATION High Efficiency Synchronous Step-Down Converter 100k VIN1 TG MODE/PLLIN VIN 2.7V TO 5.5V 22μF 0.36μH FREQ/PLLFLTR SW 0.1μF 95.3k INTVCC 1nF ITH LTC3852 CHARGE PUMP 2.2μF ×2 4.7μF BG GND2 100pF RUN OFF ON 2.1k VIN2 SHDN C+ C– SENSE GND1 VPUMP 3852 TA01 0.1μF 20k 1% 4.5 EFFICIENCY 80 4 70 3.5 60 3 50 2.5 40 2 30 + SENSE– VFB 90 1.5 POWER LOSS 20 1 10 0.5 0 40.2k 1% 1 10 POWER LOSS (W) TRACK/SS 0.1μF 12.1k + 470μF BOOST 5 100 VOUT 1.2V 20A EFFICIENCY (%) PGO0D INTVCC Efficiency and Power Loss vs Load Current 0 20 LOAD CURRENT (A) 3852 TA01a 3852f 1 LTC3852 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) RUN TRACK/SS ITH VFB TOP VIEW 24 23 22 21 SENSE– 1 20 FREQ/PLLFLTR SENSE+ 2 19 MODE/PLLIN PGOOD 3 18 SW GND2 4 17 TG 25 GND BG 5 16 BOOST 15 VIN2 C+ 7 14 INTVCC C– 8 13 VPUMP VIN1 10 11 12 GND1 9 NC NC 6 SHDN Input Supply Voltage (VIN1) .........................6V to – 0.3V Top Side Driver Voltage (BOOST)...............46V to – 0.3V Switch Voltage (SW) ..................................40V to – 0.3V VPUMP ....................................................... 5.5V to – 0.3V SHDN, RUN ..................................................6V to – 0.3V VPUMP Short-Circuit Duration .......................... Indefinite VIN2 ............................................................40V to – 0.3V INTVCC, (BOOST-SW), RUN, PGOOD ...........6V to – 0.3V INTVCC, Peak Output Current .................................50mA SENSE+, SENSE– ..........................................6V to – 0.3V MODE/PLLIN, TRACK/SS .....................INTVCC to – 0.3V FREQ/PLLFLTR .....................................INTVCC to – 0.3V ITH, VFB ........................................................ 3V to – 0.3V Operating Junction Temperature (Note 2) ............. 125°C Storage Temperature Range ..................– 65°C to 125°C UDD PACKAGE 24-LEAD (3mm s 5mm) PLASTIC QFN TJMAX = 125°C, qJA = 38°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3852EUDD#PBF LTC3852EUDD#TRPBF LFRJ 24-Lead (3mm ¥ 5mm) Plastic QFN –40°C to 125°C LTC3852IUDD#PBF LTC3852IUDD#TRPBF LFRJ 24-Lead (3mm ¥ 5mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3852f 2 LTC3852 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN1 = 3.3V, VIN2 = 15V, VRUN = 3.3V, SHDN = 0V, MODE/PLLIN = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop (Step-Down Regulator) VIN2 Controller Input Voltage Range VFB Regulated Feedback Voltage (Note 3); ITH Voltage = 1.2V IFB Feedback Current (Note 3) VREFLNREG Reference Voltage Line Regulation (Notes 3, 9); VIN2 = 6V to 38V VLOADREG Output Voltage Load Regulation (Note 3) Measured in Servo Loop; DITH Voltage = 1.2V to 0.7V Measured in Servo Loop; DITH Voltage = 1.2V to 1.6V l 4 l 0.790 38 V 0.800 0.810 V –10 –50 nA 0.002 0.02 %/V l 0.01 0.1 % l –0.01 –0.1 % gm Transconductance Amplifier gm (Note 3); ITH = 1.2V; Sink/Source 5μA 2 IQ(VIN2) Controller Input DC Supply Current (Note 4) VFB = 0.9V (RUN = 3.3V) 1.4 Shutdown Supply Current RUN = 0V 25 Total Input DC Supply Current (Notes 4, 7) VFB = 0.9V (RUN = SHDN = 3.3V) 7 mA Shutdown Supply Current (Note 7) RUN = SHDN = 0V 5 μA Undervoltage Lockout INTVCC Ramping Down IQ(VIN1) UVLO Undervoltage Hysteresis VOVL Feedback Overvoltage Lockout ISENSE SENSE Pins Current ITRACK/SS Soft-Start Charge Current Measured at VFB l 0.86 VRUN Rising l mA 50 μA 3.25 V 0.4 V 0.88 –2.0 VTRACK/SS = 0V mmho 0.90 V 2.0 μA μA 0.5 1 2 1.1 1.22 1.35 VRUN RUN Pin On Threshold VRUN(HYS) RUN Pin On Hysteresis VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE– = 3.3V TG RUP TG Driver Pull-Up On-Resistance TG High 2.2 Ω TG RDOWN TG Driver Pull-Down On-Resistance TG Low 1.2 Ω BG RUP BG Driver Pull-Up On-Resistance BG High 2.1 Ω BG RDOWN BG Driver Pull-Down On-Resistance BG Low 1.1 Ω TG tr TG tf Top Gate Rise Time Top Gate Fall Time CLOAD = 3300pF (Note 5) 25 25 ns ns BG tr BG tf Bottom Gate Rise Time Bottom Gate Fall Time CLOAD = 3300pF (Note 5) 25 25 ns ns TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CLOAD = 3300pF (Note 5) 30 ns BG/TG t1D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time CLOAD = 3300pF (Note 5) 30 ns tON(MIN) Minimum On-Time (Note 6) 90 ns 130 l 40 53 V mV 68 mV 3852f 3 LTC3852 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN1 = 3.3V, VIN2 = 15V, VRUN = 3.3V, SHDN = 0V, MODE/PLLIN = 0V unless otherwise noted. SYMBOL PARAMETER Oscillator and Phase-Locked Loop (Step-Down Regulator) fNOM1 Nominal Frequency Lowest Frequency fLOW1 Highest Frequency fHIGH1 Nominal Frequency fNOM2 Lowest Frequency fLOW2 Highest Frequency fHIGH2 MODE/PLLIN Minimum Input Frequency fMODE MODE/PLLIN Maximum Input Frequency MODE/PLLIN Input Resistance RMODE/PLLIN Phase Detector Output Current IFREQ Sinking Capability Sourcing Capability PGOOD Output PGOOD Voltage Low VPGL PGOOD Leakage Current IPGOOD PGOOD Trip Level VPG CONDITIONS MIN TYP MAX UNITS RFREQ = 60k RFREQ = 160k RFREQ = 36k RFREQ = 60k (Note 7) RFREQ = 160k (Note 7) RFREQ = 36k (Note 7) MODE/PLLIN = External Clock 460 205 690 460 205 690 500 235 750 500 235 750 250 750 100 540 265 810 540 265 810 kHz kHz kHz kHz kHz kHz kHz kHz kΩ fMODE > fOSC fMODE < fOSC –90 75 IPGOOD = 2mA VPGOOD = 5V VFB with Respect to Regulated Voltage VFB Ramping Negative VFB Ramping Positive VPUMP Charge Pump Supply (VIN1 = 3.3V; VSHDN = 3.3V, VRUN = 0); CVIN1 = 4.7μF, CFLY = 2.2μF, CVPUMP = 4.7μF Input Voltage Range VIN1 Charge Pump Doubler Output Voltage CFLY = 2.2μF VPUMP l 2.7V < VIN1 < 5.5V; IVPUMP = 1mA Shutdown Pin Current SHDN = 0V; VPUMP = 0V ISHDN Output Ripple at VPUMP IVPUMP = 50mA (Note 10) VRIPPLE fPUMP Charge Pump Frequency l SHDN Input Threshold VIH l SHDN Input Threshold VIL SHDN Input Current IIH SHDN Input Current IIL Effective Open-Loop Output Resistance VIN1 = 2.7V, VPUMP = 4.5V ROL (Note 8) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3852 is tested under pulsed load conditions such that TJ ≈ TA . The LTC3852E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3852I is guaranteed over the –40°C to 125°C operating junction temperature range. TJ is calculated from the ambient temperature, TA and power dissipation PD according to the following formula: TJ = TA + (PD • 38°C/W) Note 3: The LTC3852 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications information. –12 8 0.1 0.3 ±1 V μA –10 10 –8 12 % % 5.5 V 5.3 1 V μA 2.7 4.8 0.6 1.3 μA μA 5.05 20 1.2 1.8 0.4 1 1 –1 –1 6 mVP-P MHz V V μA μA Ω Note 5: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Rise and fall times are assured by design, characterization and correlation with statistical process controls. Note 6: The minimum on-time condition is specified for an inductor peak-to-peak ripple current equal to 40% of IMAX (see Minimum On-Time Considerations in the Applications Information Section). Note 7: VIN1 = 3.3V; Connect VPUMP, VIN2 and INTVCC together. Note 8: ROL = (2VIN - VOUT)/IOUT Note 9: VIN2 swept while not connected to VPUMP or INTVCC. Note 10: Guaranteed by design, not tested in production. 3852f 4 LTC3852 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Output Current and Mode Load Step (Burst Mode Operation) Load Step 100 ILOAD 10A/DIV 5A TO 15A Burst Mode OPERATION ILOAD 10A/DIV 1A TO 12A EFFICIENCY(%) 80 IL 10A/DIV IL 10A/DIV 60 CCM PULSE-SKIPPING 20 0 0.01 VOUT = 1.5V 50μs/DIV VIN1 = 3.3V FIGURE 16 CIRCUIT FIGURE 16 CIRCUIT 0.1 VOUT 100mV/DIV AC-COUPLED VOUT 100mV/DIV AC-COUPLED 40 1 10 LOAD CURRENT (A) 3852 G04 VOUT = 1.2V 20μs/DIV VIN1 = 3.3V FIGURE 17 CIRCUIT 3852 G05 100 3852 G02 Load Step (Pulse-Skipping Mode) Load Step (Forced Continuous Mode) ILOAD 10A/DIV 1A TO 12A ILOAD 10A/DIV 1A TO 12A IL 10A/DIV IL 10A/DIV VOUT 100mV/DIV ACCOUPLED VOUT 100mV/DIV ACCOUPLED 3852 G06 VOUT = 1.2V 20μs/DIV VIN1 = 3.3V FIGURE 17 CIRCUIT Inductor Current at Light Load FORCED CONTINOUS MODE 5A/DIV Burst Mode OPERATION 5A/DIV PULSESKIPPING MODE 5A/DIV VOUT = 1.2V 20μs/DIV VIN1 = 3.3V FIGURE 17 CIRCUIT 3852 G07 Coincident Tracking with Master Supply Start-Up with Prebiased Output at 0.5V VMASTER 0.5V/DIV VOUT 1V/DIV TRACK/SS 0.5V/DIV 0V FIGURE 16 CIRCUIT Ratiometric Tracking with Master Supply VOUT 2A LOAD 0.5V/DIV VFB 0.5V/DIV 20ms/DIV 3852 G08 VMASTER 0.5V/DIV VOUT 2A LOAD 0.5V/DIV 0V VOUT = 1.5V 1μs/DIV VIN2 = 3.3V ILOAD = 500mA FIGURE 17 CIRCUIT 0V 3852 G09 100ms/DIV FIGURE 16 CIRCUIT 3852 G10 10ms/DIV 3852 G11 FIGURE 16 CIRCUIT 3852f 5 LTC3852 TYPICAL PERFORMANCE CHARACTERISTICS Controller Maximum Current Sense Threshold vs Common Mode Voltage Controller Input DC Supply Current vs Input Voltage (VIN2) 3.0 90 90 80 80 2.5 1.5 1.0 0.5 70 60 60 VSENSE (mV) 2.0 50 40 30 0 4 8 12 16 20 24 28 32 INPUT VOLTAGE (V) 36 30 20 MINIMUM 10 BURST COMPARATOR FALLING THRESHOLD: VITH = 0.4V 90 90 80 80 70 70 MAXIMUM VSENSE (mV) 40 CURRENT SENSE THRESHOLD (mV) 50 VSENSE (mV) 3852 G15 Controller Maximum Current Sense Threshold vs Feedback Voltage (Current Foldback) Controller Maximum Current Sense Threshold vs Duty Cycle MAXIMUM 60 50 40 30 60 50 40 30 20 20 10 10 0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VITH (V) 0 20 60 40 DUTY CYCLE (%) 0 100 80 3852 G16 1.5 REGULATED FEEDBACK VOLTAGE (mV) RUN PIN VOLTAGE (V) 1.3 1.0 0.9 0.8 0.7 RUN RISING THRESHOLD (ON) 1.2 RUN FALLING THRESHOLD (OFF) 1.1 1.0 0.6 100 125 3852 G19 0.9 –50 0.8 806 1.4 1.3 0.7 Controller Regulated Feedback Voltage vs Temperature 1.4 1.1 0.2 0.3 0.4 0.5 0.6 FEEDBACK VOLTAGE (V) 3852 G18 Controller Shutdown (RUN) Threshold vs Temperature 1.2 0.1 3852 G17 Controller TRACK/SS Pull-Up Current vs Temperature TRACK/SS CURRENT (μA) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VITH (V) 5 3852 G14 60 50 25 0 75 TEMPERATURE (°C) 20 –20 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VSENSE COMMON MODE VOLTAGE (V) 3852 G12 –25 30 0 0 Controller Burst Mode Peak Current Sense Threshold vs ITH Voltage 0.5 –50 40 –10 0 40 50 10 20 10 0 DUTY CYCLE RANGE: 0% TO 100% 70 VSENSE THRESHOLD (mV) SUPPLY CURRENT (mA) Controller Maximum Peak Current Sense Threshold vs ITH Voltage –25 50 0 25 75 TEMPERATURE (°C) 100 125 3852 G20 804 802 800 798 796 794 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3852 G21 3852f 6 LTC3852 TYPICAL PERFORMANCE CHARACTERISTICS Controller Oscillator Frequency vs Temperature 5 700 600 RFREQ = 60k 500 400 300 RFREQ = 160k 200 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 4 INTVCC RAMPING UP 3 INTVCC RAMPING DOWN 2 1 0 –50 125 –25 50 0 75 25 TEMPERATURE (°C) 3852 G22 100 20 15 10 5 0 –50 –25 75 50 25 TEMPERATURE (°C) 0 100 15 10 5 2.0 1.5 1.0 0.5 1.4 1.25 1.3 FREQUENCY (MHz) 1.50 0.25 15 20 25 30 INPUT VOLTAGE (V) 35 40 50 25 75 0 TEMPERATURE (°C) 100 80 70 60 50 40 30 20 10 0 125 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 INTVCC VOLTAGE(V) 3852 G28 Charge Pump SHDN Threshold Voltage vs Supply Voltage Charge Pump Oscillator Frequency vs Temperature 0.50 10 3852 G27 Charge Pump Oscillator Frequency vs Supply Voltage 0.75 5 Maximum Current Sense Threshold vs INTVCC Voltage 2.5 0 –50 –25 125 1.00 0 90 3852 G26 FREQUENCY (MHz) 20 3852 G25 CURRENT SENSE THRESHOLD (mV) INPUT DC SUPPLY CURRENT (mA) 25 25 0 125 3.0 30 30 Input DC Supply Current vs Temperature Controller Only 40 35 35 3852 G24 Shutdown Input DC Supply Current vs Temperature Controller Only SHUTDOWN INPUT DC SUPPLY CURRENT (μA) SHUTDOWN SUPPLY CURRENT (μA) RFREQ = 36k 40 0.9 VIN = 4.5V THRESHOLD VOLTAGE (V) FREQUENCY (kHz) 800 INTVCC VOLTAGE AT UVLO THRESHOLD (V) 900 0 Shutdown Input DC Supply Current vs Input Voltage Controller Only Controller Undervoltage Lockout Threshold (INTVCC) vs Temperature 1.2 VIN = 2.4V 1.1 1.0 LOW-TO-HIGH THRESHOLD 0.8 0.7 HIGH-TO-LOW THRESHOLD 0.6 0.9 1.5 2.0 2.5 3.0 3.5 SUPPLY VOLTAGE (V) 4.0 4.5 3852 G29 0.8 –50 –20 10 40 70 TEMPERATURE (oC) 100 130 3852 G30 0.5 1.5 2.0 2.5 3.0 3.5 SUPPLY VOLTAGE (V) 4.0 4.5 3852 G31 3852f 7 LTC3852 TYPICAL PERFORMANCE CHARACTERISTICS Charge Pump SHDN LO-to-HI Threshold vs Temperature Charge Pump SHDN HI-to-LO Threshold vs Temperature 0.8 SHDN THRESHOLD HI-TO-LO (V) SHDN THRESHOLD LO-TO-HI (V) 0.9 0.8 VIN = 3.2V 0.7 VIN = 2.4V 0.6 0.5 –50 50 0 100 VIN = 3.2V 0.7 VIN = 2.4V 0.6 0.5 0.4 –50 150 50 0 100 3852 G33 3852 G32 Charge Pump Short-Circuit Current vs Supply Voltage 5.20 350 5.10 300 SHORT-CIRCUIT CURRENT (mA) OUTPUT VOLTAGE (V) Charge Pump Load Regulation 5.00 VIN = 4.2V 4.90 VIN = 3.6V 4.80 VIN = 2.7V 4.70 4.60 100 200 400 300 LOAD CURRENT (mA) 250 200 DEVICE CYCLES IN AND OUT OF THERMAL SHUTDOWN 150 100 50 0 1.5 4.50 0 500 2.0 2.5 3.0 3.5 SUPPLY VOLTAGE (V) EFFECTIVE OPEN-LOOP OUTPUT RESISTANCE (Ω) Charge Pump Output Load Capability at 4% Below Regulation 500 OUTPUT LOAD (mA) 400 125°C 85°C 25°C –45°C 350 300 250 200 150 100 50 0 2.4 2.9 3.4 SUPPLY VOLTAGE (V) 3.9 4.0 4.5 3852 G34 3852 G35 450 150 TEMPERATURE (oC) TEMPERATURE (oC) Charge Pump Effective Open-Loop Output Resistance vs Temperature 8 VIN = 2.7V VOUT = 4.5V 7 6 5 4 –50 0 50 100 TEMPERATURE (oC) 3852 G36 3852f 8 LTC3852 TYPICAL PERFORMANCE CHARACTERISTICS Charge Pump Load Transient Response Charge Pump Output Ripple IPUMP 50mA/DIV VPUMP 20mV/DIV (AC-COUPLED) VPUMP 50mV/DIV (AC-COUPLED) VIN1 = 3.3V IPUMP = 25mA CVPUMP = 4.7μF 3852 G38 1μs/DIV 3852 G39 VIN = 3.3V 10μs/DIV IPUMP = 25mA TO 50mA STEP Charge Pump Line Regulation with 25mA Load Efficiency vs Supply Voltage 100 5.5 90 THEORETICAL MAX 80 5 EFFICIENCY (%) VPUMP (V) 70 4.5 4 60 IPUMP = 100mA IPUMP = 10mA 50 IPUMP = 1mA 40 30 125°C 85°C 25°C –45°C 3.5 3 1.8 2.8 3.8 VIN1 (V) 20 10 0 2.7 4.8 3852 G40 3.0 3.3 3.6 3.9 4.2 SUPPLY VOLTAGE (VIN1) 4.5 3852 G41 PIN FUNCTIONS SENSE– (Pin 1): The (–) Input to the Current Sense Comparators. Kelvin connect to VOUT at the current sense resistor or, if DCR sensing is used, at the inductor. SENSE+ (Pin 2): Current Sense Comparator Noninverting Input. The (+) input to the current comparator is normally connected to the DCR sensing network or current sensing resistor. PGOOD (Pin 3): Power Good Indicator Output. Open drain logic out that is pulled to ground when the output voltage exceeds the ±10% regulation window, after the internal 17μs power bad mask timer expires. GND2 (Pin 4): Buck Controller Ground. All small-signal components and compensation components should be Kelvin connected to this ground. The (–) terminal of CINTVCC should be closely connected to this pin. The exposed pad must be soldered to the PCB to provide electrical contact for the IC and for optimum thermal performance. BG (Pin 5): Bottom Gate Driver Output. This pin drives the gate of the bottom N-channel MOSFET between GND and INTVCC . C+ (Pin 7): Flying Capacitor Positive Terminal. 3852f 9 LTC3852 PIN FUNCTIONS C– (Pin 8): Flying Capacitor Negative Terminal. VIN1 (Pin 12): Input Supply Voltage to Charge Pump. VIN1 should be bypassed with a 1μF to 4.7μF low ESR ceramic capacitor. MODE/PLLIN (Pin 19): Forced Continuous Mode, Burst Mode operation or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to INTVCC to force continuous conduction mode of operation. Connect to GND2 to enable pulse-skipping mode of operation. To select Burst Mode operation, tie this pin to INTVCC through a resistor no less than 50k, but no greater than 250k. A clock on the pin will force the controller into forced continuous mode of operation and synchronize the internal oscillator. VPUMP (Pin 13): Regulated Output Voltage from Charge Pump. For best performance, VPUMP should be bypassed with a low ESR ceramic capacitor providing at least 2.2μF of capacitance as close to the pin as possible. FREQ/PLLFLTR (Pin 20): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, a resistor can be connected between this pin and GND2 to vary the frequency of the internal oscillator. INTVCC (Pin 14): Gate Drive Supply. The MOSFET drivers and internal logic are powered from this voltage. Bypass this pin to GND with a minimum 2.2μF low ESR tantalum or ceramic capacitor, CINTVCC. RUN (Pin 21): Run Control Input. Forcing the pin below 1.25V shuts down the step-down controller. There is a 2μA pull-up current on this pin. SHDN (Pin 10): Active Low Shutdown Input. A low on SHDN disables the charge pump. This pin must not be allowed to float. GND1 (Pin 11): Charge Pump Ground. The (–) terminals of CIN and CVPUMP should be closely connected to this pin. VIN2 (Pin 15): Main Supply Pin for Step-Down Controller. A bypass capacitor should be tied between this pin and the GND2 pin. BOOST (Pin 16): Boosted Floating Driver Supply. The (+) terminal of the booststrap capacitor is connected to this pin. This pin swings from a diode voltage drop below INTVCC up to VIN1 + INTVCC . TG (Pin 17): Top Gate Driver Output. This is the output of a floating driver with a voltage swing equal to INTVCC superimposed on the switch node voltage. SW (Pin 18): Switch Node Connection to the Inductor. Voltage swing at this pin is from a diode (external) voltage drop below ground to the buck regulator power stage VIN . TRACK/SS (Pin 22): Output Voltage Tracking and Soft-Start Input. A capacitor to ground at this pin sets the ramp rate for the output voltage. An internal soft-start current of 1μA charges this capacitor. ITH (Pin 23): Error Amplifier Output and Switching Regulator Compensation Point. The current comparator input threshold increases with this control voltage. VFB (Pin 24): Error Amplifier Feedback Input. This pin receives the remotely sensed feedback voltage from an external resistive divider across the output. GND (Exposed Pad Pin 25): Ground. Must be soldered to PCB, providing a local ground for the IC. 3852f 10 LTC3852 FUNCTIONAL DIAGRAM MODE/PLLIN BUCK REGULATOR 100k VIN2 0.8V MODE/SYNC DETECT FREQ/ PLLFLTR 5V REG + – VIN 38V MAX PLL-SYNC BOOST BURSTEN OSC S R CB TG PULSE SKIP Q M1 SW ON 5k + – ICMP IREV + – SWITCH LOGIC AND ANTISHOOT THROUGH SENSE+ DB L1 VOUT SENSE– RUN + INTVCC OV COUT BG M2 CINTVCC SLOPE COMPENSATION GND2 PGOOD INTVCC UVLO 1 100k ITHB + 0.72V UV VFB R2 – R1 FAULT LOGIC VIN2 + SLEEP OV – – + SS + – RUN – 0.88V + 1μA EA – + + 0.8V REF 0.64V 1.25V 2μA RUN 0.4V SOFT-START AND SWITCH CONTROL VPUMP CSS SHDN ON/OFF CPUMP 1.2MHz OSCILLATOR + CC1 TRACK/SS – ITH RC CHARGE PUMP VIN1 2.7V to 5.5V C+ VIN1 CFLY C– CIN CHARGE PUMP GND1 3852 FD 3852f 11 LTC3852 OPERATION Main Control Loop The LTC3852 is a constant frequency, current mode step-down DC/DC controller which can be powered by an onboard charge pump. Supplies as low as 2.7V, when doubled by the charge pump, provide 5V to the LTC3852’s control logic and gate drives, supporting a wide selection of logic-level MOSFETs. During normal operation, the controller’s top MOSFET is turned on when the clock sets the RS latch, and is turned off when the main current comparator, ICMP , resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The VFB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, IREV, or the beginning of the next cycle. The charge pump section uses a switched capacitor doubler to boost VIN1 to 2 ¥ VIN1, with a regulated maximum of 5V. Regulation is achieved by sensing the output voltage through an internal resistor divider and modulating the charge pump output current based on the error signal. A 2-phase nonoverlapping clock activates the charge pump switches. The flying capacitor is charged from VIN1 on the first phase of the clock. On the second phase of the clock it is stacked in series with VIN1 and connected to VPUMP. This sequence of charging and discharging the flying capacitor continues at a free running frequency of 1.2MHz (typ). Two configurations address most LTC3852 applications. Figure 1a covers the single low input voltage case, typically 3.3V. The input to the charge pump, VIN1, is connected to the same input voltage as the drain of the top MOSFET. VPUMP, VIN2 and INTVCC are tied together, so that the charge pump’s 5V output provides all power to the buck controller section. The alternative arrangement in Figure 1b allows the LTC3852 to step down from as high as 38V, while powering itself from an available 3.3V bus. The input to the charge pump, VIN1, is connected to 3.3V instead of the drain of the top MOSFET. It is not necessary to step the high input voltage down to 5V through a linear regulator. Logic level MOSFETs are usable in both cases. VIN 3.3V VIN1 TG BG VPUMP VIN2 INTVCC 3852 F01a Figure 1a VIN ≤ 38V 3.3V VIN1 TG VPUMP BG VIN2 INTVCC 3852 F01b Figure 1b INTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. Peak current drawn from INTVCC should not exceed 50mA. The top MOSFET driver is biased from the floating bootstrap capacitor, CB , which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 1/10 of the clock period every tenth cycle to allow CB to recharge. However, it 3852f 12 LTC3852 OPERATION is recommended that there is always a load present during the drop-out transition to ensure CB is recharged. Shutdown and Start-Up (RUN, SHDN and TRACK/SS) The switching regulator section of the LTC3852 can be shut down using the RUN pin. Pulling this pin below 1.1V disables the controller and most of the internal circuitry. Releasing the RUN pin allows an internal 2μA current to pull up the pin and enable the controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of the controller’s output voltage, VOUT , is controlled by the voltage on the TRACK/SS pin. When the voltage on the TRACK/SS pin is less than the 0.8V internal reference, the LTC3852 regulates the VFB voltage to the TRACK/SS pin voltage instead of the 0.8V reference. This allows the TRACK/SS pin to be used to program a soft-start by connecting an external capacitor from the TRACK/SS pin to GND. An internal 1μA pull-up current charges this capacitor, creating a voltage ramp on the TRACK/SS pin. As the TRACK/SS voltage rises linearly from 0V to 0.8V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively, the TRACK/SS pin can be used to cause the start-up of VOUT to “track” another supply. Typically, this requires connecting to the TRACK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the RUN pin is pulled low to disable the controller, or when INTVCC drops below its undervoltage lockout threshold of 3.2V, the TRACK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, the controller is disabled and the external MOSFETs are held off. The charge pump is separately controlled by SHDN. In shutdown mode, all charge pump circuitry is turned off and it draws only leakage current from the VIN1 supply. Furthermore, VPUMP is disconnected from VIN1. The SHDN pin is a CMOS input with a threshold voltage of approximately 0.7V. The charge pump is in shutdown when a logic low is applied to the SHDN pin. Since the SHDN pin is a very high impedance CMOS input, it should never be allowed to float. To ensure that its state is defined, it must always be driven with a valid logic level not exceeding VIN1, even if it is tied to RUN. Since the output voltage of the charge pump can go above the input voltage, special circuitry is required to control the internal logic. Detection logic will draw an input current of 5μA when in shutdown. However, this current will be eliminated if the output voltage (VPUMP) is less than approximately 0.8V. The charge pump has built-in soft-start circuitry to prevent excessive current flow during start-up. The soft-start is achieved by charging an internal capacitor with a very weak current source. The voltage on this capacitor, in turn, slowly ramps the amount of current available to the output storage capacitor from zero to a value of 50mA over a period of approximately 125μs. The soft-start circuit is reset in the event of a commanded shutdown or thermal shutdown. Light Load Current Operation (Burst Mode Operation, Pulse skipping or Continuous Conduction) The LTC3852 can be enabled for high efficiency Burst Mode operation, constant frequency pulse skipping mode or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to INTVCC . To select pulse skipping mode of operation, float the MODE/PLLIN pin or tie it to GND2. To select Burst Mode operation, tie MODE/PLLIN to INTVCC through a resistor no less than 50k, but no greater than 250k. When the controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-fourth of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.4V, the internal sleep signal goes high (enabling sleep mode) and both external MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator, IREV , turns off the bottom external MOSFET just before the 3852f 13 LTC3852 OPERATION inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and constant frequency operation. When the MODE/PLLIN pin is connected to GND2, the LTC3852 operates in PWM pulse skipping mode at light loads. At very light loads the current comparator, ICMP, may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ/PLLFLTR and MODE/PLLIN Pins) The selection of a switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3852’s controller can be selected using the FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ/PLLFLTR pin can be used to program the controller’s operating frequency from 250kHz to 750kHz. A phase-locked loop (PLL) is available on the LTC3852 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller operates in forced continuous mode of operation when it is synchronized. A series RC should be connected between the FREQ/PLLFLTR pin and GND to serve as the PLL’s loop filter. It is suggested that the external clock be applied before enabling the controller unless a second resistor is connected in parallel with the series RC loop filter network. The second resistor prevents low switching frequency operation if the controller is enabled before the clock. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output of the step-down controller. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Power Good (PGOOD) Pin The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the VFB pin voltage is not within ±10% of the 0.8V reference voltage. The PGOOD pin is also pulled low when the RUN pin is low (shut down) or when the LTC3852’s controller is in the soft-start or tracking phase. When the VFB pin voltage is within the ±10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V (abs max). The PGOOD pin will flag power good immediately when the VFB pin is within the ±10% window. However, there is an internal 17μs power bad mask when VFB goes out of the ±10% window. Short-Circuit/Thermal Protection The charge pump has built-in short-circuit current limit as well as over-temperature protection. During a short-circuit condition, it will automatically limit VPUMP output current to approximately 300mA. At higher temperatures, or if the input voltage is high enough to cause excessive self-heating of the part, the thermal shutdown circuitry will shut down the charge pump once the junction temperature exceeds approximately 160°C. It will enable the charge pump once its junction temperature drops back to approximately 150°C. The charge pump will cycle in and out of thermal shutdown indefinitely until the short-circuit condition on VPUMP is removed. The maximum rated junction temperature will be exceeded when this thermal shutdown protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. 3852f 14 LTC3852 APPLICATIONS INFORMATION The Typical Application on the first page of this data sheet is a basic LTC3852 application circuit. The LTC3852 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice of the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. DCR sensing is popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and the inductor value. Next, the power MOSFETs and Schottky diodes are selected. Finally, input and output capacitors are selected. half the peak-to-peak ripple current, DIL. Allowing a margin of 20% for variations in the IC and external component values yields: RSENSE = 0.8 • VMAX IMAX + ΔIL /2 VIN2 INTVCC VIN BOOST TG SW RSENSE VOUT LTC3852 BG GND2 SENSE+ SENSE+ and SENSE– Pins The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of the current comparators is 0V to 5.5V. Both SENSE pins are high impedance inputs with small base currents of less than 1μA. When the SENSE pins ramp up from 0V to 1.4V, the small base currents flow out of the SENSE pins. When the SENSE pins ramp down from 5V to 1.1V, the small base currents flow into the SENSE pins. The high impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to float these pins during normal operation. Low Value Resistors Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2. RSENSE is chosen based on the required output current. For simplicity, the charge pump section is omitted. The current comparator has a maximum threshold, VMAX = 50mV. The current comparator threshold sets the maximum peak of the inductor current, yielding a maximum average output current, IMAX , equal to the peak value less SENSE– FILTER COMPONENTS PLACED NEAR SENSE PINS 3852 F02 Figure 2. Using a Resistor to Sense Current with the LTC3852 Inductor DCR Sensing For applications requiring the highest possible efficiency, the LTC3852 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 3. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less than 1mW for today’s low value, high current inductors. If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR multiplied by R2/(R1 + R2). Therefore, R2 may be used to scale the voltage across the sense terminals when the DCR is greater than the target sense resistance. Check the manufacturer’s data sheet for specifications regarding the inductor DCR, in order to properly dimension the external filter components. The DCR of the inductor can also be measured using a good RLC meter. 3852f 15 LTC3852 APPLICATIONS INFORMATION VIN2 INTVCC Accepting larger values of DIL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is DIL = 0.3(IMAX). The maximum DIL occurs at the maximum input voltage. VIN BOOST INDUCTOR TG L SW DCR VOUT LTC3852 BG GND2 R1** SENSE+ C1* R2 SENSE– *PLACE C1 NEAR SENSE+, SENSE– PINS **PLACE R1 NEAR INDUCTOR R1||R2 • C1 = L DCR 3852 F03 R2 RSENSE(EQ) = DCR R1 + R2 Figure 3. Current Mode Control Using the Inductor DCR Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, this results in a reduction of maximum inductor peak current for duty cycles >40%. However, the LTC3852 uses a novel scheme that allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current DIL decreases with higher inductance or frequency and increases with higher VIN: ΔIL = ⎛ V ⎞ 1 VOUT ⎜1– OUT ⎟ f •L VIN ⎠ ⎝ The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below ≈10% of the current limit determined by RSENSE. Lower inductor values (higher DIL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for the LTC3852 controller: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. 3852f 16 LTC3852 APPLICATIONS INFORMATION The peak-to-peak drive levels are set by the VPUMP voltage. This voltage is typically 5V when the charge pump is active. Consequently, logic-level threshold MOSFETs may be used in most applications. Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER , input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode, the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN Synchronous Switch Duty Cycle = VIN – VOUT VIN The MOSFET power dissipations at maximum output current are given by: PMAIN V 2 = OUT (IMAX ) (1+ δ)RDS(ON) + VIN ⎞ (VIN)2 ⎛⎜⎝ IMAX (R )(C )• 2 ⎟⎠ DR MILLER ⎡ 1 ⎤ 1 + ⎢ ⎥ (f) ⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦ PSYNC = VIN – VOUT 2 IMAX ) (1+ δ)RDS(ON) ( VIN where d is the temperature dependency of RDS(ON) and RDR (approximately 2W) is the effective driver resistance at the MOSFET’s Miller threshold voltage. VTH(MIN) is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + d) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but d = 0.005/°C can be used as an approximation for low voltage MOSFETs. The optional Schottky diode conducts during the dead time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 2% in efficiency at high VIN. A 1A to 3A Schottky is generally a good size due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. Soft-Start and Tracking The LTC3852 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. When the LTC3852 is configured to soft-start by itself, a capacitor should be connected to the TRACK/SS pin. The LTC3852 is in the shutdown state if the RUN pin voltage is below 1.25V. TRACK/SS pin is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.25V, the LTC3852 powers up. A soft-start current of 1μA then starts to charge its softstart capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TRACK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is 0V to 0.8V on the TRACK/SS pin. The total soft-start time can be calculated as: t SOFT-START = 0.8 • CSS 1.0µA 3852f 17 LTC3852 APPLICATIONS INFORMATION In order to track down another supply after the soft-start phase expires, the LTC3852 must be configured for forced continuous operation by connecting MODE/PLLIN to INTVCC. Output Voltage Tracking The LTC3852 allows the user to program how its output ramps up and down by means of the TRACK/SS pins. Through this pin, the output can be set up to either coincidentally or ratiometrically track with another supply’s output, as shown in Figure 4. In the following discussions, VMASTER refers to a master supply and VOUT refers to the LTC3852’s output as a slave supply. To implement the coincident tracking in Figure 4a, connect a resistor divider to VMASTER and connect its midpoint to the TRACK/SS pin of the LTC3852. The ratio of this divider should be selected the same as that of the LTC3852’s feedback divider as shown in Figure 5a. In this tracking mode, VMASTER must be higher than VOUT. To implement ratiometric tracking, the ratio of the resistor divider connected to VMASTER is determined by: VOUT VMASTER R2 ⎛ R3 + R4⎞ = R4 ⎜⎝ R1+ R2 ⎟⎠ VMASTER OUTPUT VOLTAGE When the regulator is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TRACK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, one can select the tracking resistive divider value to be small enough to make this error negligible. So which mode should be programmed? While either mode in Figure 5 satisfies most practical applications, the coincident mode offers better output regulation. This concept can be better understood with the help of Figure 6. At the input stage of the LTC3852’s error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. The top two current sources are of the same amplitude. In the coincident mode, the TRACK/SS voltage is substantially higher than 0.8V at steady-state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB and the internal precision 0.8V reference. In the ratiometric mode, however, TRACK/SS equals 0.8V at steady-state. D1 will divert part of the bias current to make VFB slightly lower than 0.8V. VOUT TIME 3852 F04a (4a) Coincident Tracking VMASTER OUTPUT VOLTAGE Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse skipping mode up to TRACK/SS = 0.64V. Between TRACK/SS = 0.64V and 0.72V, it will operate in forced continuous mode and revert to the selected mode once TRACK/SS > 0.72V. The output ripple is minimized during the 80mV forced continuous mode window. VOUT TIME 3852 F04b (4b) Ratiometric Tracking Figure 4. Two Different Modes of Output Voltage Tracking 3852f 18 LTC3852 APPLICATIONS INFORMATION VMASTER VOUT R3 R3 TO TRACK/SS PIN TO VFB PIN R4 VBOOST = VIN + VINTVCC R4 The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET. The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). 3852 F05a (5a) Coincident Tracking Setup VMASTER VOUT R1 R3 TO TRACK/SS PIN TO VFB PIN R2 R4 3852 F05b (5b) Ratiometric Tracking Setup Figure 5. Setup for Coincident and Ratiometric Tracking I I + D1 D2 EA TRACK/SS – 0.8V VFB and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: D3 3852 F06 Figure 6. Equivalent Input Circuit of Error Amplifier Although this error is minimized by the exponential I-V characteristic of the diode, it does impose a finite amount of output voltage deviation. Furthermore, when the master supply’s output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. Topside MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate source of the MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN Undervoltage Lockout The LTC3852 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out switching action when INTVCC falls below 3.25V. To prevent oscillation when there is a disturbance on the INTVCC , the UVLO comparator has 400mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pin has a precision turn-on reference of 1.25V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. CIN Selection In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/VIN . To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS ⎛ V ⎞ V ≅ IO(MAX) OUT ⎜ IN – 1⎟ VIN ⎝ VOUT ⎠ 1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IO(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. 3852f 19 LTC3852 APPLICATIONS INFORMATION COUT Selection The selection of COUT is primarily determined by the effective series resistance, ESR, to minimize voltage ripple. The output ripple, DVOUT, in continuous mode is determined by: ⎛ 1 ⎞ ΔVOUT ≅ ΔIL ⎜ESR + 8fCOUT ⎟⎠ ⎝ where f = operating frequency, COUT = output capacitance and DIL = ripple current in the inductor. The output ripple is highest at maximum input voltage since DIL increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. With DIL = 0.3IOUT(MAX) and allowing 2/3 of the ripple to be due to ESR, the output ripple will be less than 50mV at maximum VIN and: COUT Required ESR < 2.2RSENSE COUT > 1 8fRSENSE The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. The selection of output capacitors for applications with large load current transients is primarily determined by the voltage tolerance specifications of the load. The resistive component of the capacitor, ESR, multiplied by the load current change, plus any output voltage ripple must be within the voltage tolerance of the load. The required ESR due to a load current step is: RESR ≤ ΔV ΔI where DI is the change in current from full load to zero load (or minimum load) and DV is the allowed voltage deviation (not including any droop due to finite capacitance). The amount of capacitance needed is determined by the maximum energy stored in the inductor. The capacitance must be sufficient to absorb the change in inductor current when a high current to low current transition occurs. The opposite load current transition is generally determined by the control loop OPTI-LOOP components, so make sure not to over compensate and slow down the response. The minimum capacitance to assure the inductors’ energy is adequately absorbed is: L (ΔI) > 2 (ΔV) VOUT 2 COUT where DI is the change in load current. Manufacturers such as Nichicon, United Chemi-Con and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor electrolyte capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications, ESR, RMS current handling and load step specifications may require multiple capacitors in parallel. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have much lower capacitive density per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 1.5mm to 4.1mm. Aluminum electrolytic capacitors can be used in cost-driven applications, provided that consideration 3852f 20 LTC3852 APPLICATIONS INFORMATION is given to ripple current ratings, temperature and longterm reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, NEC Neocap, Panasonic SP and Sprague 595D series. Consult manufacturers for other specific recommendations. Like all components, capacitors are not ideal. Each capacitor has its own benefits and limitations. Combinations of different capacitor types have proven to be a very cost effective solution. Remember also to include high frequency decoupling capacitors. They should be placed as close as possible to the power pins of the load. Any inductance present in the circuit board traces negates their usefulness. sense voltage is progressively lowered from its maximum programmed value to about 25% of the that value. Foldback current limiting is disabled during soft-start or tracking. Under short-circuit conditions with very low duty cycles, the LTC3852 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC3852 (≈90ns), the input voltage and inductor value: ΔIL(SC) = tON(MIN) • VIN L The resulting short-circuit current is: ISC = 1/4MaxVSENSE 1 – ΔIL(SC) RSENSE 2 Setting Output Voltage Programming Switching Frequency The LTC3852 output voltage is set by an external feedback resistive divider carefully placed across the output, as shown in Figure 7. The regulated output voltage is determined by: To set the switching frequency of the LTC3852, connect a resistor, RFREQ, between FREQ/PLLFLTR and GND. The relationship between the oscillator frequency and RFREQ is shown in Figure 8. A 0.1μF bypass capacitor should be connected in parallel with RFREQ. ⎛ R ⎞ VOUT = 0.8V ⎜1+ B ⎟ ⎝ RA ⎠ 750 To improve the transient response, a feed-forward capacitor, CFF , may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. VOUT LTC3852 RB CFF VFB RA 3852 F07 OSCILLATOR FREQUENCY (kHz) 700 650 600 550 500 450 400 350 300 250 20 40 60 80 100 120 RFREQ (kΩ) 140 160 3852 F08 Figure 7. Settling Output Voltage Figure 8. Relationship Between Oscillator Frequency and Resistor Connected Between FREQ/PLLFLTR and GND Fault Conditions: Current Limit and Current Foldback The LTC3852 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 40% of its nominal output level, the maximum 3852f 21 LTC3852 APPLICATIONS INFORMATION Phase-Locked Loop and Frequency Synchronization The LTC3852 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. This phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the FREQ/PLLFLTR pin. Note that the LTC3852 can only be synchronized to an external clock whose frequency is within range of the LTC3852’s internal VCO.This is guaranteed to be between 250kHz and 750kHz. A simplified block diagram is shown in Figure 9. 2.7V RLP CLP FREQ/PLLFLTR MODE/ PLLIN EXTERNAL OSCILLATOR DIGITAL PHASE/ FREQUENCY DETECTOR The loop filter components, CLP and RLP , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP is 1k to 10k and CLP is 2200pF to 0.01μF. When the external oscillator is active before the LTC3852 is enabled, the internal oscillator frequency will track the external oscillator frequency as described in the preceding paragraphs. In situations where the LTC3852 is enabled before the external oscillator is active, a low free-running oscillator frequency of approximately 50kHz will result. It is possible to increase the free-running, pre-synchronization frequency by adding a second resistor in parallel with RLP and CLP . The second resistor will also cause a phase difference between the internal and external oscillator signals. The magnitude of the phase difference is inversely proportional to the value of the second resistor. The external clock (on MODE/PLLIN pin) input high threshold is nominally 1.6V, while the input low threshold is nominally 1.2V. Maximum Available Charge Pump Current VCO For the charge pump, the maximum available output current and voltage can be calculated from the effective open-loop output resistance, ROL, and the effective input voltage, 2VIN1(MIN). 3852 F09 ROL Figure 9. Phase-Locked Loop Block Diagram If the external clock frequency is greater than the internal oscillator’s frequency, fOSC , then current is sunk continuously from the phase detector output, pulling down the FREQ/PLLFLTR pin. When the external clock frequency is less than fOSC , current is sourced continuously, pulling up the FREQ/PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the FREQ/PLLFLTR pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. + – 2VIN1 + IOUT VPUMP – 3852 F10 Figure 10. Equivalent Open-Loop Circuit From Figure 10, the available current is given by: IPUMP = 2VIN1 – VPUMP ROL The actual current (into VIN2 and INTVCC) should not exceed 50mA. 3852f 22 LTC3852 APPLICATIONS INFORMATION Effective Open Loop Output Resistance (ROL) The effective open loop output resistance (ROL) of a charge pump is a very important parameter which determines the strength of the charge pump. The value of this parameter depends on many factors such as the oscillator frequency (fOSC), value of the flying capacitor (CFLY), the nonoverlap time, the internal switch resistances (RS), and the ESR of the external capacitors. A first order approximation for ROL is given below: ROL ≅ 2∑RS + S=1 TO 4 1 f OSC •CFLY EFFECTIVE OPEN-LOOP OUTPUT RESISTANCE (7) Typical ROL values as a function of temperature are shown in Figure 11. 8 VIN = 2.7V VPUMP = 4.5V 7 6 5 4 –50 0 50 100 TEMPERATURE (oC) 3852 F11 Figure 11. Typical ROL vs Temperature Charge Pump Capacitor Selection The style and value of capacitors used with the charge pump determine several important parameters such as regulator control loop stability, output ripple, charge pump strength and minimum start-up time. To reduce noise and ripple, it is recommended that low ESR (<0.1W) ceramic capacitors be used for both CIN and CPUMP. These capacitors should be 2.2μF or greater. Tantalum and aluminum capacitors are not recommended because of their high ESR. The value of CPUMP directly controls the amount of output ripple for a given load current. Increasing the size of CPUMP will reduce the output ripple at the expense of higher minimum turn-on time. The peak-to-peak output ripple of a charge pump is approximately given by the expression: IPUMP VRIPPLE(P−P) ≅ 2f OSC •CPUMP where fOSC is the charge pump frequency (typically 1.2MHz) and CPUMP is the value of the VPUMP storage capacitor. Also, the value and style of the CPUMP capacitor can significantly affect the stability of the charge pump. As shown in the Functional Diagram, the charge pump uses a linear control loop to adjust the strength of the charge pump to match the current required at the output. The error signal of this loop is stored directly on the output storage capacitor. This output capacitor also serves to form the dominant pole of the control loop. To prevent ringing or instability on the charge pump, it is important to maintain at least 1μF of capacitance over all conditions. Excessive ESR on the CPUMP capacitor can degrade the loop stability of the charge pump. Its closed loop output resistance is designed to be 0.5W. For a 50mA load current change, the output voltage will change by about 25mV. If the output capacitor has 0.5W or more of ESR, the closed loop frequency response will cease to roll off in a simple one-pole fashion and poor load transient response or instability could result. Ceramic capacitors typically have exceptional ESR performance and combined with a good board layout should yield very good stability and load transient performance. As the value of CPUMP controls the amount of output ripple, the value of CIN controls the amount of ripple present at the input pin (VIN1). The input current to the charge pump will be relatively constant during the input charging phase or the output charging phase but will drop to zero during the nonoverlap times. Since the nonoverlap time is small (~25ns), these missing notches will result in only a small perturbation on the input power supply line. Note that a higher ESR capacitor such as tantalum will have higher input noise due to the voltage drop in the ESR. Therefore, ceramic capacitors are again recommended for their exceptional ESR performance. 3852f 23 LTC3852 APPLICATIONS INFORMATION Further input noise reduction can be achieved by powering VIN1 through a very small series inductor as shown in Figure 12. A 10nH inductor will reject the fast current notches, thereby presenting a nearly constant current load to the input power supply. For economy, the 10nH inductor can be fabricated on the PC board with about 1cm (0.4") of PC board trace. 1cm OF PCB TRACE 10nH VIN 0.22μF 12 VIN1 11 Table 1 shows a list of ceramic capacitor manufacturers and how to contact them: Table 1. LTC3852 2.2μF provide any more capacitance than a 0.22μF 10V X7R capacitor available in the same 0603 case. In fact, for the charge pump, these capacitors can be considered roughly equivalent. The capacitor manufacturer’s data sheet should be consulted to ensure the desired capacitance at all temperatures and voltages. GND1 3852 F12 Figure 12. 10nH Inductor Used for Additional Input Noise Reduction AVX www.avx.com Kemet www.kemet.com Murata www.murata.com Taiyo Yuden www.t-yuden.com TDK www.component.tdk.com Vishay www.vishay.com Flying Capacitor Selection Efficiency Considerations Warning: A polarized capacitor such as tantalum or aluminum should never be used for the flying capacitor since its voltage can reverse upon start-up of the charge pump. Low ESR ceramic capacitors should always be used for the flying capacitor. The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100. It is often useful to analyze the individual loss components to determine what limits the efficiency and which change would produce the biggest improvement. The efficiency can be expressed as: The flying capacitor controls the strength of the charge pump. In order to achieve the rated output current, it is necessary to have at least 1μF of capacitance for the flying capacitor. Ceramic Capacitors Ceramic capacitors of different materials lose their capacitance with higher temperature and voltage at different rates. For example, a capacitor made of X5R or X7R material will retain most of its capacitance from –40°C to 85°C whereas a Z5U or Y5V style capacitor will lose considerable capacitance over that range. Z5U and Y5V capacitors may also have a poor voltage coefficient causing them to lose 60% or more of their capacitance when the rated voltage is applied. Therefore when comparing different capacitors, it is often more appropriate to compare the amount of achievable capacitance for a given case size rather than discussing the specified capacitance value. For example, over rated voltage and temperature conditions, a 1μF 10V Y5V ceramic capacitor in a 0603 case may not % Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, there are five main sources of power loss in LTC3851 circuits: 1) I2R losses, 2) transition losses in the top MOSFET, 3) gate charge losses within the controller due to the input capacitance of the power MOSFETs, 4) the DC bias current of the controller (VIN2), and 5) the efficiency of the charge pump. 1. I2R losses are predicted from the DC resistances of the fuse (if used), top and bottom MOSFET on-resistances, the inductor DCR and the current sense resistor (if used). In continuous conduction mode (CCM), the average output current flows through the inductor (L) and sense resistor (RSENSE), but is “chopped” between the top and bottom MOSFETs. Since the two MOSFETs rarely have the same RON, an effective MOSFET resistance 3852f 24 LTC3852 APPLICATIONS INFORMATION can be computed using the duty cycle (D = VOUT/VIN). The effective MOSFET DC resistance is therefore: RON(EFF) = D • RON(TOP) + (1-D) • RON(BOT) The effective MOSFET resistance can then be summed with the DCR of the inductor and the sense resistor to obtain the overall series resistance. For example, consider a DC/DC converter with a 3.3V input voltage and a 1.2V/15A output. The nominal duty cycle of this converter is 36% (1.2V/3.3V). For a design with RON(TOP) = 8mΩ and RON(BOT) = 2mΩ, the effective MOSFET DC resistance is (0.36) • 0.008 + (1-0.36) • 0.002 = 4.2mΩ. For an inductor DCR = 1mΩ and a 2mΩ sense resistor, the total series resistance is 7.2mΩ. For an output current range of 5A to 15A, the total I2R losses range from 1% to 9% for a 1.2V output. It is worth noting that the losses due to the sense resistor at full load (15A) are 450mW, or 2.5%. If the same application used a DCR current sensing scheme, the peak efficiency would be 2.5% higher, an expensive component would be eliminated from the bill of materials, and the solution size would be smaller. The efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 2. Since the LTC3852 was optimized for low supply voltage applications, the transition losses for the top MOSFET can normally be neglected. Transition losses for the top MOSFET only become significant when operating at high input voltages (typically 15V or greater). This condition can occur, however, when the input to the charge pump is not the same voltage as the input to the DC/DC converter power stage. For example, an auxiliary, low current 3.3V supply could be connected to the input of the charge pump (VIN1), while the DC/DC converter power stage could draw power from a high current 12V supply. Transition losses for the upper power MOSFET can be estimated from the following equation: Transition Loss = (1.7)VDS(MAX)2 • IO(MAX) • CRSS • fSW 3. The INTVCC current is the sum of the MOSFET driver and DC bias requirements of the internal circuitry. The gate drive current results from charging the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched on, a packet of charge QG moves from INTVCC to the MOSFET gate. The resulting dQ/dt is a current into INTVCC that is typically much larger than the DC bias current for the internal control circuitry. In CCM operation, IGATE = fSW • (QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT) are the gate charges of the top and bottom MOSFETs respectively. These parameters are listed on most power MOSFET datasheets. 4. The DC bias current for the controller is specified in the Electrical Characteristics table, and is typically 1.2mA. This current is almost always much smaller than the gate charge current associated with the power MOSFETs in CCM operation. 5. In most LTC3852 applications, the output of the charge pump will be connected to the VIN2 and INTVCC pins of the controller. The DC bias current into the controller VIN2 pin, as well as the gate charge current associated with the power MOSFETs, will typically be supplied by the charge pump. Because the charge pump has a finite power efficiency, the input current will be higher that the output current when the charge pump is active. For a 3.3V input application where the output of the charge pump is 5.1V, this efficiency is approximately 72%, as shown in the graph in the Typical Performance Characteristics. As a result, for every 1mA of current required by the controller, about 1.4mA will be drawn from the VIN1 pin. The DC bias current of the charge pump within the LTC3852 is typically only 60μA. For the purposes of power losses, this bias current is typically 2 orders of magnitude lower than the gate drive current, and can therefore be neglected. Other “hidden” losses such as copper trace and the battery internal resistance can account for an additional several percent efficiency degradation in portable systems. It is very important to include these “system” level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require 3852f 25 LTC3852 APPLICATIONS INFORMATION a minimum of 20μF to 40μF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. Other losses including Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to DILOAD (ESR), where ESR is the effective series resistance of COUT. DILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Typical Application circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The midband gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3852. These items are also illustrated graphically in the layout diagram of Figure 13. Check the following in your layout: 1. Are the board signal and power grounds segregated? The LTC3852 ground pins should connect to the ground plane close to the output capacitor(s). The low current or signal ground lines should make a single point tie directly to the GND1 and GND2 pins. The synchronous MOSFET source pins should connect to the input capacitor(s) ground. 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1, R2 must be connected between the (+) plate of COUT and signal 3852f 26 LTC3852 APPLICATIONS INFORMATION RPGOOD RUN SHDN MODE/PLLIN + FREQ/PLLFLTR CSS TRACK/SS SW BOOST VIN CC1 RC D1 ITH CC2 VIN2 LTC3852 CB DB M2 INTVCC RA VFB CFF CIN2 M1 TG 1 CFLTR + IN RFREQ VIN1 PGOOD OFF ON C VPULL-UP VPUMP CINTVCC – – GND1, 2 RB SENSE– CS SENSE+ RS1 RS2 BG C+ CFLY C– L1 VOUT RSENSE COUT1 COUT2 + 3852 F13 + Figure 13. LTC3852 Switching Regulator Layout Diagram ground. The 47pF to 100pF capacitor should be as close as possible to the LTC3852. Be careful locating the feedback resistors too far away from the LTC3852. The VFB line should not be routed close to any other nodes with high slew rates. 3. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the LTC3852. Ensure accurate current sensing with Kelvin connections as shown in Figure 14. Series resistance can be added to the SENSE lines to increase noise rejection and to compensate for the ESL of RSENSE. 4. Does the (+) terminal of CIN connect to the drain of the topside MOSFET(s) as closely as possible? This capacitor provides the AC current to the MOSFET(s). 5. Is the INTVCC ceramic decoupling capacitor connected closely between INTVCC and GND2? This capacitor carries the MOSFET driver peak currents. 6. Keep the switching node (SW), top gate node (TG) and boost node (BOOST) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3852 and occupy minimum PC trace area. HIGH CURRENT PATH 3852 F14 SENSE+ SENSE– CURRENT SENSE RESISTOR (RSENSE) Figure 14. Kelvin Sensing RSENSE Layout Considerations (Charge Pump) Due to the high switching frequency and high transient currents produced by the charge pump, careful board layout is necessary for optimum performance. A true ground plane and short connections to all the external capacitors 3852f 27 LTC3852 APPLICATIONS INFORMATION will improve performance and ensure proper regulation under all conditions. Figure 15 shows an example layout for the charge pump. C+ LTC3852EUDD CFLY 0603 C– VPUMP GND1 CPUMP 0603 VIN1 sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN , the Schottky and the top MOSFET to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC. Design Example CIN 0603 3852 F15 Figure 15. Recommended Charge Pump Layout PC Board Layout Debugging It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pick-up at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current As a design example, assume VIN = 3.3V (nominal), VIN = 5.5V (maximum), VOUT = 1.5V, IMAX = 15A, and f = 400kHz (refer to Figure 16). The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Connect a 68.1k resistor between the FREQ/PLLFLTR and GND pins, generating 400kHz operation. The inductance for 30% ripple current is: L= = ⎛ V ⎞ VOUT ⎜1− OUT ⎟ VIN ⎠ ΔIL (f) ⎝ 1 1 ⎛ 1.5V ⎞ 1.5V ⎜1− = 454nH ⎝ 3.3V ⎟⎠ 4.5A (400kHz) A 400nH inductor will produce 34% ripple current.The peak inductor current will be the maximum DC value (15A) plus one-half the ripple current (2.5A), or 17.5A. The minimum on-time occurs at maximum VIN : tON(MIN) = VOUT VIN(MAX) (f) = 1.5V = 682ns 5.5V (400kHz) which is greater than the 90ns minimum on-time. The RSENSE resistor value can be calculated by using the minimum current sense voltage specification with a 20% increase for current limit. RSENSE ≤ VSENSE(MIN) IPEAK • 1.2 ≤ 40mV = 1.9mΩ 17.5A • 1.2 Choosing 1% resistors: R1 = 20k and R2 = 37.4k yields an output voltage of 1.496V. 3852f 28 LTC3852 APPLICATIONS INFORMATION with a typical value of RDS(ON) and d = (0.005/°C)(25°C) = 0.125. The resulting power dissipated in the bottom MOSFET is: The power dissipation on the topside MOSFET can be easily estimated. Choosing Vishay SIR438DP MOSFETs results in: RDS(ON) = 0.0023W, CMILLER = 445pF. At maximum input voltage with T (estimated) = 50°C: PSYNC = 1.5V PMAIN = (15)2 ⎡⎣1+ (0.005)(50°C − 25°C)⎤⎦ 5.5V 2 ⎛ 15A ⎞ • (0.0023Ω) + (5.5V) ⎜ (2Ω)(445pF) ⎝ 2 ⎟⎠ which is less than under full-load conditions. CIN is chosen for an RMS current rating of at least 9A at temperature. COUT is chosen with an ESR of 0.02W for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: 1⎤ ⎡ 1 •⎢ + ⎥ (400kHz) = 108mW ⎣5 − 1 1⎦ A short-circuit to ground will result in a folded back current of: ISC 1 ) 65mV ( 1 ⎛ 90ns (5.5V)⎞ = 4.8A = 4 – 2 ⎜⎝ 0.003Ω 5.5V–1.5V 2 15A) (1.125) (0.0023Ω)= 423mW ( 5.5V VORIPPLE = RESR (DIL) = 0.02W (5.1A) = 102mVP-P 400nH ⎟⎠ TYPICAL APPLICATIONS VIN 2.7V TO 5.5V GND 1 2 CCM BURST PS 3 4 C1 INTVCC 100k R5 68.1k 1% JP2 MODE/ C+ PLLIN FREQ/PLLFLTR C9 150pF ITH VIN1 Q1 L1 0.4μH TG D1 RUN C11 0.01μF PGOOD VIN R16 100k C6 0.1μF R11 100Ω SENSE+ 4V ×2 C12 R12 1000pF 100Ω SENSE– GND1 GND GND2 VOUT 1.5V/15A CIN1: SANYO 6TPE220MI COUT1: AVX 12106D107MAT2A COUT2: SANYO 4TPE330MI D1: CENTRAL SEMI CMDSH-3 L1: VITEC 59PR9875N Q1, Q3: VISHAY SILICONIX SiR438DP Q3 BG TRACK/SS SHDN OUT2 + C330μF GND C15 4.7μF 10V PGOOD R17 100k COUT1 100μF 6.3V VIN2 INTVCC 1 2 3 RS1 0.002 1% SW VPUMP LTC3852 OFF C– BOOST JP1 RUN ON CIN5 10μF 16V 1206 ×2 CIN1 220μF 6.3V 2.2μF 10V 0603 R9 5.9k C8 2200pF + C5 0.1μF MODE FB 24 R19 20k 1% R20 17.4k 1% 3852 F16 Figure 16. High Efficiency 1.5V/15A Step-Down Converter From Design Example 3852f 29 LTC3852 TYPICAL APPLICATIONS CIN1 56μF 50V MODE CCM BURST PS 3 4 INTVCC 100k VIN 4V TO 36V + 1 2 R1 1k JP2 C5 0.1μF C1 R5 82.5k 1% 2.2μF 10V 0603 MODE/ C+ PLLIN C– VIN1 TG Q1 L1 3.6μH RS1 0.003Ω 1% SW R9 3.6k COUT1 47μF 10V BOOST C9 150pF ITH VPUMP LTC3852 3V RUN OFF ON D1 Q3 C11 0.1μF R16 INTVCC 100k R11 100Ω TRACK/SS SENSE+ C12 1000pF PGOOD SENSE– SHDN FB GND1 GND GND2 R19 8.06k 1% VOUT 5V/10A (VIN > 5V) CIN1: SUNCON 50HVP56M CIN5: TDK C3225X7R1H335 COUT1: TDK C3225X5ROJ476 COUT2: SANYO 6TPE220MI D1: CENTRAL SEMI CMDSH-3 L1: COILTRONICS HC1-3R6-R Q1: RENESAS RJK0451DPB Q3: RENESAS RJKO453DPB C15 4.7μF 10V BG 0V + COUT2 220μF 6.3V GND C6 0.1μF VIN2 INTVCC PGOOD D3 BAT85 CIN5 3.3μF ×4 50V C1 4.7μF 10V FREQ/ PLLFLTR C8 2200pF Q2 2N3904 D2 4.7V R12 100Ω R20 42.2k 1% 3852 F18 Figure 17. 5V/10A Converter Providing 5V Drive to MOSFETs for 4V < VIN < 36V INTVCC During Line Transient (VIN1 < 5V) VIN = 7V VOUT = 5V INTVCC 5V 2V/DIV 10ms 3852 F17a 3852f 30 LTC3852 PACKAGE DESCRIPTION UDD Package 24-Lead Plastic QFN (3mm s 5mm) (Reference LTC DWG # 05-08-1833 Rev Ø) 0.70 ±0.05 3.50 ± 0.05 2.10 ± 0.05 3.65 ± 0.05 1.50 REF 1.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.50 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.75 ± 0.05 3.00 ± 0.10 1.50 REF 23 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.25 s 45° CHAMFER 24 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.65 ± 0.10 5.00 ± 0.10 3.50 REF 1.65 ± 0.10 (UDD24) QFN 0808 REV Ø 0.200 REF 0.00 – 0.05 R = 0.115 TYP 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3852f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC3852 TYPICAL APPLICATIONS CIN1 220μF 6.3V s2 VIN 2.7V TO 5.5V + C5 0.1μF R5 95.3k 1% CIN5 10μF 16V 1206 C1 INTVCC 2.2μF 10V 0603 MODE/ C+ PLLIN C– COUT1 100μF 6.3V s5 R8 2.1k BOOST C9 100pF LTC3852EUDD RUN C11 0.1μF R16 VIN R17 100k 100k VOUT 1.2V/20A OUT3 470μF/4V s2 GND C6 0.1μF C15 4.7μF 10V Q3 BG CIN1: SANYO 6TPE220MI COUT1: AVX 12106D107MAT2A COUT3: SANYO 4TPF470ML D1: CENTRAL SEMI CMDSH-3 L1: VISHAY IHLP4040DZ-01 Q1, Q3: VISHAY SILICONIX SiR438DP TRACK/SS SENSE+ C12 0.1μF PGOOD PGOOD +C VIN2 INTVCC 1 2 3 D1 VPUMP ITH JP1 RUN OFF L1 0.36μH SW R9 12.1k ON Q1 TG FREQ/PLLFLTR C8 1nF VIN1 SENSE– SHDN FB GND1 GND GND2 R19 40.2k 1% R20 20k 1% 3852 F17 Figure 18. 1.2V/20A Low Ripple DCR Sense Application RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3736/LTC3736-1/ Dual, 2-Phase Synchronous Step-Down Controller LTC3736-2 2.75V ≤ VIN ≤ 9.8V, No RSENSE™ LTC3772/LTC3772B Micropower, No RSENSE Constant Frequency Step-Down DC/DC Controller 2.75V ≤ VIN ≤ 9.8V, No RSENSE, 40μA No-Load IQ LTC3776 Dual 2-Phase, No RSENSE Synchronous Controller for DDR/ QDR Memory Termination 2.75V ≤ VIN ≤ 9.8V, VOUT2 Tracks 1/2 VREF LT3808 No RSENSE, Low EMI, Synchronous DC/DC Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, Spread Spectrum Modulation for Low Noise LTC3809/LTC3809-1 No RSENSE, Low Input Voltage, Synchronous DC/DC Controller 2.75V ≤ VIN ≤ 9.8V, Output Tracking (LTC3809-1) or Spread Spectrum Modulation LTC3822/LTC3822-1 Low Input Voltage Synchronous Step-Down Controller 2.75V ≤ VIN ≤ 4.5V, No RSENSE LTC3836 Dual, Low Input Voltage Synchronous Step-Down Controller 2.75V ≤ VIN ≤ 4.5V, No RSENSE 3852f 32 Linear Technology Corporation LT 1010 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com ” LINEAR TECHNOLOGY CORPORATION 2010