STMicroelectronics M58LT128GST 128mbit (8mb x16, multiple bank, multi-level, burst) 1.8v supply secure flash memory Datasheet

M58LT128GST
M58LT128GSB
128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst)
1.8V Supply Secure Flash Memories
PRELIMINARY DATA
Features Summary
■
SUPPLY VOLTAGE
– VDD = 1.7 to 2.0V for program, erase and
read
– VDDQ = 2.7 to 3.6V for I/O Buffers
– VPP = 9V for fast program
■
SYNCHRONOUS / ASYNCHRONOUS READ
– Random Access: 110ns
– Asynchronous Page Read: 25ns.
– Synchronous Burst Read: 52MHz
■
SYNCHRONOUS BURST READ SUSPEND
■
PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
■
MEMORY ORGANIZATION
– Multiple Bank Memory Array:
8 Mbit Banks
– Parameter Blocks (Top or Bottom location)
■
DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■
HARDWARE PROTECTION
– All Blocks Write Protected when VPP≤VPPLK
■
SECURITY
– Software Security Features
– 64-bit Unique Device Identifier
– 2112 bits of User-Programmable OTP
memory
■
COMMON FLASH INTERFACE (CFI)
BGA
TBGA64 (ZA)
10 x 13mm
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code:
M58LT128GST: 88C6h
M58LT128GSB: 88C7h
■
ECOPACK® PACKAGE AVAILABLE
September 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev 1.0
1/98
www.st.com
1
M58LT128GST, M58LT128GSB
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2
Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10.1 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
4
2/98
2.11
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.13
VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M58LT128GST, M58LT128GSB
4.6
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8
Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9
Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . 23
4.9.1
Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.9.2
Program and Verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.9.3
Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11
Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11.1 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.12
5
6
7
Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2
Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3
Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4
Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5
VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6
Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.7
Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . 33
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1
Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2
X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3
Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4
Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.5
Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.6
Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.7
Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.8
Wrap Burst Bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.9
Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1
Asynchronous Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1.1
Asynchronous Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3/98
M58LT128GST, M58LT128GSB
7.1.2
7.2
Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Synchronous Burst Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.1
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.2
Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8
Dual Operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . . . 45
9
Program and Erase times and Endurance cycles . . . . . . . . . . . . . . . . . . 47
10
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13
Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Appendix C Flowcharts and Pseudo Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Appendix D Command Interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14
4/98
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
M58LT128GST, M58LT128GSB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standard Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Protection Register Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Wait at the Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Dual Operations Allowed In Same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Dual Operation Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Program/Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DC Characteristics - Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Asynchronous Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Package Mechanical Data . . . . . . 66
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
M58LT128GST - Parameter Bank Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
M58LT128GST - Main Bank Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
M58LT128GST - Block Addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
M58LT128GSB - Parameter Bank Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
M58LT128GSB- Main Bank Base Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
M58LT128GSB - Block Addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Command Interface States - Modify Table, Next Output State. . . . . . . . . . . . . . . . . . . . . . 92
Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5/98
M58LT128GST, M58LT128GSB
Table 49.
Table 50.
6/98
Command Interface States - Lock Table, Next Output State . . . . . . . . . . . . . . . . . . . . . . . 95
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
M58LT128GST, M58LT128GSB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Synchronous Burst Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Clock input AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Bottom View Package Outline . . . 66
Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Program Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 85
Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 88
Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 89
7/98
1 Summary description
1
M58LT128GST, M58LT128GSB
Summary description
The M58LT128GST and M58LT128GSB are 128 Mbit (8 Mbit x16) non-volatile Secure Flash
memories.
The devices may be erased electrically at block level and programmed in-system on a Word-byWord basis using a 1.7 to 2.0V VDD supply for the circuitry and a 2.7 to 3.6V VDDQ supply for
the Input/Output pins. An optional 9V VPP power supply is provided to speed up factory
programming.
The devices feature an asymmetrical block architecture and are based on a multi-level cell
technology. The memory array is organized as 131 blocks, and is divided into 8 Mbit banks.
There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank
containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords.
The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one
bank, read operations are possible in other banks. Only one bank at a time is allowed to be in
program or erase mode. It is possible to perform burst reads that cross bank boundaries. The
bank architecture is summarized in Table 2, and the memory maps are shown in Figure 3. The
Parameter Blocks are located at the top of the memory address space for the M58LT128GST,
and at the bottom for the M58LT128GSB.
Each block can be erased separately. Erase can be suspended, in order to perform a program
or read operation in any other block, and then resumed. Program can be suspended to read
data at any memory location except for the one being programmed, and then resumed. Each
block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There
is a Buffer Enhanced Factory programming command available to speed up programming.
Program and erase commands are written to the Command Interface of the memory. An
internal Program/Erase Controller takes care of the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error conditions
identified in the Status Register. The command set required to control the memory is consistent
with JEDEC standards.
The device supports Synchronous Burst Read and Asynchronous Read and Page Read from
all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In
Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to
52MHz. The Synchronous Burst Read operation can be suspended and resumed.
The device features an Automatic Standby mode. When the bus is inactive during
Asynchronous Read operations, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value and the outputs
are still driven.
The M58LT128GST and M58LT128GSB are equipped with several features to increase data
protection:
8/98
●
Hardware Protection: all blocks are protected from program and erase operations when
the VPP ≤VPPLK .
●
A full set of Software Security Features described in a dedicated Application Note. Please
contact STMicroelectronics for further details.
●
64-bit Unique Device Identifier
●
2112 bits of User-Programmable OTP memory
M58LT128GST, M58LT128GSB
1 Summary description
The device includes 17 Protection Registers and 2 Protection Register locks, one for the first
Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection
Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit
segment containing a unique device number written by ST, and a 64 bit segment One-TimeProgrammable (OTP) by the user. The user programmable segment can be permanently
protected. Figure 4 shows the Protection Register Memory Map.
The devices are offered in TBGA64 10 x 13mm, 1mm pitch.
In order to meet environmental requirements, ST offers the M58LT128GST and M58LT128GSB
in ECOPACK® package. ECOPACK package is Lead-free. The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
The memories are supplied with all the bits erased (set to ’1’).
Figure 1.
Logic Diagram
VDD VDDQ VPP
16
DQ0-DQ15
A0-A22
W
E
G
WAIT
M58LT128GSB
M58LT128GST
RP
L
K
VSS
VSSQ
AI10259b
9/98
M58LT128GST, M58LT128GSB
1 Summary description
Table 1.
10/98
Signal Names
A0-A22
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset
K
Clock
L
Latch Enable
WAIT
Wait
VDD
Supply Voltage
VDDQ
Supply Voltage for Input/Output Buffers
VPP
Optional Supply Voltage for Fast Program & Erase and Write Protect
VSS
Ground
VSSQ
Ground Input/Output Supply
NC
Not Connected Internally
M58LT128GST, M58LT128GSB
Figure 2.
1 Summary description
TBGA64 Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A0
A5
A7
VPP
A12
VDD
A17
A21
B
A1
VSS
A8
E
A13
NC
A18
WAIT
C
A2
A6
A9
A11
A14
NC
A19
A20
D
A3
A4
A10
RP
NC
NC
A15
A16
E
DQ8
DQ1
DQ9
DQ3
DQ4
NC
DQ15
NC
F
K
DQ0
DQ10
DQ11
DQ12
NC
NC
G
G
A22
NC
DQ2
VDDQ
DQ5
DQ6
DQ14
W
H
L
NC
VDD
VSSQ
DQ13
VSS
DQ7
NC
AI10270b
Table 2.
Bank Architecture
Parameter Bank
8 Mbits
4 blocks of 16 KWords
7 blocks of 64 KWords
Bank 1
8 Mbits
-
8 blocks of 64 KWords
Bank 2
8 Mbits
-
8 blocks of 64 KWords
Bank 3
8 Mbits
-
8 blocks of 64 KWords
----
Main Blocks
----
Parameter Blocks
----
Bank Size
----
Number
Bank 14
8 Mbits
-
8 blocks of 64 KWords
Bank 15
8 Mbits
-
8 blocks of 64 KWords
11/98
M58LT128GST, M58LT128GSB
1 Summary description
Figure 3.
Memory Map
M58LT128GSB - Bottom Boot Block
Address lines A22-A0
M58LT128GST - Top Boot Block
Address lines A22-A0
000000h
00FFFFh
64 KWord
070000h
07FFFFh
64 KWord
Bank 15
600000h
60FFFFh
8 Main
Blocks
Parameter
Bank
7E0000h
7EFFFFh
7F0000h
7F3FFFh
7FC000h
7FFFFFh
4 Parameter
Blocks
16 KWord
64 KWord
7 Main
Blocks
64 KWord
64 KWord
8 Main
Blocks
64 KWord
64 KWord
8 Main
Blocks
Bank 2
170000h
17FFFFh
180000h
18FFFFh
64 KWord
Bank 1
770000h
77FFFFh
780000h
78FFFFh
0F0000h
0FFFFFh
100000h
10FFFFh
64 KWord
8 Main
Blocks
16 KWord
Bank 1
64 KWord
8 Main
Blocks
00C000h
00FFFFh
010000h
01FFFFh
070000h
07FFFFh
080000h
08FFFFh
64 KWord
Bank 2
6F0000h
6FFFFFh
700000h
70FFFFh
Parameter
Bank
64 KWord
Bank 3
670000h
67FFFFh
680000h
68FFFFh
000000h
003FFFh
8 Main
Blocks
64 KWord
64 KWord
8 Main
Blocks
Bank 3
64 KWord
1F0000h
1FFFFFh
64 KWord
780000h
78FFFFh
64 KWord
7F0000h
7FFFFFh
64 KWord
64 KWord
7 Main
Blocks
64 KWord
16 KWord
4 Parameter
Blocks
16 KWord
8 Main
Blocks
Bank 15
AI10261
12/98
M58LT128GST, M58LT128GSB
2
2 Signal descriptions
Signal descriptions
See Figure 1: Logic Diagram and Table 1: Signal Names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A22)
The Address Inputs select the cells in the memory array to access during Bus Read operations.
During Bus Write operations they control the commands sent to the Command Interface of the
Program/Erase Controller.
2.2
Data Input/Output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense
amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When
Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power
consumption is reduced to the stand-by level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the Bus Read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the Bus Write operation of the memory’s Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable
whichever occurs first.
2.6
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is
in reset mode: the outputs are high impedance and the current consumption is reduced to the
Reset Supply Current IDD2. Refer to Table 20: DC Characteristics - Currents, for the value of
IDD2. After Reset all blocks are in the Protected state and the Configuration Register is reset.
When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required
to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to
VRPH (refer to Table 21: DC Characteristics - Voltages).
13/98
2 Signal descriptions
2.7
M58LT128GST, M58LT128GSB
Latch Enable (L)
Latch Enable latches the A0-A22 address bits on its rising edge. The address latch is
transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.
2.8
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read
and in write operations.
2.9
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at
VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The
WAIT signal is forced deasserted when Output Enable is at VIH.
2.10
VDD Supply Voltage
VDD provides the power supply to the internal core of the memory device. It is the main power
supply for all operations (Read, Program and Erase).
2.10.1 VDDQ Supply Voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered
independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
2.11
VPP Program Supply Voltage
The VPP pin is both a power supply and a write protect pin. The functions are selected by the
voltage range applied to the pin.
When VPP is lower than VPPLK, it is seen as a write protect pin protecting the whole memory
array. Program and erase operations on all blocks are ignored while VPP is Low.
When VPP is Higher than VPP1, the memory reverts to the previous protection state of the
memory array. Program and erase operations can now modify the data in any block (refer to
Table 21: DC Characteristics - Voltages for VPPLK and VPP1 values). VPP is only sampled at the
beginning of a program or erase; a change in its value after the operation has started does not
have any effect and program or erase operations continue.
If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable
until the Program/Erase algorithm is completed.
The VPP pin must not be left floating or unconnected or the device may become unreliable. A
0.1µF capacitor should be connected between the VPP pin and the VSS Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the
currents required during Unlock Bypass Program, IPP.
14/98
M58LT128GST, M58LT128GSB
2.12
2 Signal descriptions
VSS Ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.13
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS
Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1µF
ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should
be as close as possible to the package). See Figure 8: AC Measurement Load Circuit. The
PCB track widths should be sufficient to carry the required VPP program and erase currents.
15/98
3 Bus operations
3
M58LT128GST, M58LT128GSB
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus Write,
Address Latch, Output Disable, Standby and Reset. See Table 3: Bus Operations, for a
summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory
and do not affect Bus Write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output
Enable must be at VIL in order to perform a read operation. The Chip Enable input should be
used to enable the device. Output Enable should be used to gate data onto the output. The
data read depends on the previous command written to the memory (see Command Interface
section). See Figure 9, Figure 11 and Figure 12 Read AC Waveforms, and Table 22 and
Table 23 Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write Commands to the memory or latch Input Data to be programmed. A
bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output
Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the
write operation by toggling Latch Enable. In this case the Latch Enable should be tied to VIH
during the bus write operation. See Figure 15 and Figure 16, Write AC Waveforms, and
Table 24 and Table 25, Write AC Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at
VIL during address latch operations. The addresses are latched on the rising edge of Latch
Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power
consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH
during a program or erase operation, the device enters Standby mode when finished.
16/98
M58LT128GST, M58LT128GSB
3.6
3 Bus operations
Reset
During Reset mode the memory is deselected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the
Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory
content is no longer valid.
Table 3.
Bus Operations
Operation(1)
WAIT(2)
E
G
W
L
RP
Bus Read
VIL
VIL
VIH
VIH
VIH
Data Output
Bus Write
VIL
VIH
VIL
VIH
VIH
Data Input
Address Latch
VIL
VIH
X
VIL
VIH
Address Input
Output Disable
VIL
VIH
VIH
VIH
VIH
Hi-Z
Standby
VIH
X
X
X
VIH
Hi-Z
Hi-Z
X
X
X
X
VIL
Hi-Z
Hi-Z
Reset
DQ15-DQ0
1. X = Don't care.
2. WAIT signal polarity is configured using the Set Configuration Register command.
17/98
M58LT128GST, M58LT128GSB
4 Command Interface
4
Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. An internal Program/Erase Controller
handles all timings and verifies the correct execution of the program and erase commands. The
Program/Erase Controller provides a Status Register whose output may be read at any time to
monitor the progress or the result of the operation.
The Command Interface is reset to read mode when power is first applied, when exiting from
Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly.
Any invalid combination of commands will be ignored.
Refer to Table 4: Command Codes, Table 5: Standard Commands, Table 6: Factory Program
Command, and Appendix D: Command Interface state tables, for a summary of the Command
Interface.
Note: The security features are described in a dedicated Application Note. Please contact
STMicroelectronics for further details.
Table 4.
Command Codes
Hex Code
18/98
Command
03h
Set Configuration Register Confirm
10h
Alternative Program Setup
20h
Block Erase Setup
40h
Program Setup
50h
Clear Status Register
70h
Read Status Register
80h
Buffer Enhanced Factory Program
90h
Read Electronic Signature
98h
Read CFI Query
B0h
Program/Erase Suspend
C0h
Program Register Program
D0h
Program/Erase Resume, Block Erase Confirm, or Buffer Program Confirm
E8h
Buffer Program
FFh
Read Array
M58LT128GST, M58LT128GSB
4.1
4 Command Interface
Read Array command
The Read Array command returns the addressed bank to Read Array mode.
One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read
Array mode, subsequent read operations will output the data from the memory array.
A Read Array command can be issued to any banks while programming or erasing in another
bank.
If the Read Array command is issued to a bank currently executing a program or erase
operation, the bank will return to Read Array mode but the program or erase operation will
continue, however the data output from the bank is not guaranteed until the program or erase
operation has finished. The read modes of other banks are not affected.
4.2
Read Status Register command
The device contains a Status Register that is used to monitor program or erase operations.
The Read Status Register command is used to read the contents of the Status Register for the
addressed bank.
One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in
Read Status Register mode, subsequent read operations will output the contents of the Status
Register.
The Status Register data is latched on the falling edge of the Chip Enable or Output Enable
signals. Either Chip Enable or Output Enable must be toggled to update the Status Register
data
The Read Status Register command can be issued at any time, even during program or erase
operations. The Read Status Register command will only change the read mode of the
addressed bank. The read modes of other banks are not affected. Only Asynchronous Read
and Single Synchronous Read operations should be used to read the Status Register. A Read
Array command is required to return the bank to Read Array mode.
See Table 9 for the description of the Status Register Bits.
4.3
Read Electronic Signature command
The Read Electronic Signature command is used to read the Manufacturer and Device Codes,
the Protection Status of the addressed bank, the Configuration Register and the Protection
Register.
One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank
is in Read Electronic Signature mode, subsequent read operations in the same bank will output
the Manufacturer Code, the Device Code, the Protection Status of the addressed bank, or the
Configuration Register (see Table 7).
The Read Electronic Signature command can be issued at any time, even during program or
erase operations, except during Protection Register Program operations. Dual operations
between the Parameter bank and the Electronic Signature location are not allowed (see
Table 15: Dual Operation Limitations for details).
If a Read Electronic Signature command is issued to a bank that is executing a program or
erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus Read
19/98
4 Command Interface
M58LT128GST, M58LT128GSB
cycles will output the Electronic Signature data and the Program/Erase controller will continue
to program or erase in the background.
The Read Electronic Signature command will only change the read mode of the addressed
bank. The read modes of other banks are not affected. Only Asynchronous Read and Single
Synchronous Read operations should be used to read the Electronic Signature. A Read Array
command is required to return the bank to Read Array mode.
4.4
Read CFI Query command
The Read CFI Query command is used to read data from the Common Flash Interface (CFI).
One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in
Read CFI Query mode, subsequent Bus Read operations in the same bank read from the
Common Flash Interface.
The Read CFI Query command can be issued at any time, even during program or erase
operations.
If a Read CFI Query command is issued to a bank that is executing a program or erase
operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output
the CFI data and the Program/Erase controller will continue to program or erase in the
background.
The Read CFI Query command will only change the read mode of the addressed bank. The
read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous
Read operations should be used to read from the CFI. A Read Array command is required to
return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI
memory space are not allowed (see Table 15: Dual Operation Limitations for details).
See Appendix B: Common Flash Interface, Table 36, Table 37, Table 38, Table 39, Table 40,
Table 42, Table 43, Table 44 and Table 45 for details on the information contained in the
Common Flash Interface memory area.
4.5
Clear Status Register command
The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1, 3, 4
and 5) in the Status Register.
One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status
Register command does not affect the read mode of the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command is
issued. The error bits in the Status Register should be cleared before attempting a new
program or erase command.
20/98
M58LT128GST, M58LT128GSB
4.6
4 Command Interface
Block Erase command
The Block Erase command is used to erase a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost.
If the block is protected then the erase operation will abort, the data in the block will not be
changed and the Status Register will output the error.
Two Bus Write cycles are required to issue the command.
1.
The first bus cycle sets up the Block Erase command.
2.
The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5
are set and the command is aborted.
Once the command is issued the bank enters Read Status Register mode and any read
operation within the addressed bank will output the contents of the Status Register. A Read
Array command is required to return the bank to Read Array mode.
During Block Erase operations the bank containing the block being erased will only accept the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored.
The Block Erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be
guaranteed when the Block Erase operation is aborted, the block must be erased again.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed in banks not being erased.
Typical Erase times are given in Table 16: Program/Erase Times and Endurance Cycles.
See Appendix C, Figure 22: Block Erase Flowchart and Pseudo Code, for a suggested
flowchart for using the Block Erase command.
4.7
Program command
The program command is used to program a single Word to the memory array.
Two Bus Write cycles are required to issue the Program Command.
1.
The first bus cycle sets up the Program command.
2.
The second latches the address and data to be programmed and starts the Program/
Erase Controller.
Once the programming has started, read operations in the bank being programmed output the
Status Register content.
During a Program operation, the bank containing the Word being programmed will only accept
the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored. A Read Array
command is required to return the bank to Read Array mode.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed in banks not being programmed.
Typical Program times are given in Table 16: Program/Erase Times and Endurance Cycles.
The Program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed
when the Program operation is aborted, the Word must be reprogrammed.
21/98
4 Command Interface
M58LT128GST, M58LT128GSB
See Appendix C, Figure 19: Program Flowchart and Pseudo Code, for the flowchart for using
the Program command.
4.8
Buffer Program command
The Buffer Program Command makes use of the device’s 32-Word Write Buffer to speed up
programming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program
command dramatically reduces in-system programming time compared to the standard nonbuffered Program command.
Four successive steps are required to issue the Buffer Program command.
1.
The first Bus Write cycle sets up the Buffer Program command. The setup code can be
addressed to any location within the targeted block.
After the first Bus Write cycle, read operations in the bank will output the contents of the
Status Register. Status Register bit SR7 should be read to check that the buffer is
available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program
command to update the Status Register contents.
2.
The second Bus Write cycle sets up the number of Words to be programmed. Value n is
written to the same block address, where n+1 is the number of Words to be programmed.
3.
Use n+1 Bus Write cycles to load the address and data for each Word into the Write
Buffer. Addresses must lie within the range from the start address to the start address + n.
Optimum performance is obtained when the start address corresponds to a 32 Word
boundary. If the start address is not aligned to a 32 word boundary, the total programming
time is doubled
4.
The final Bus Write cycle confirms the Buffer Program command and starts the program
operation.
All the addresses used in the Buffer Program operation must lie within the same block.
Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will
set an error in the Status Register and abort the operation without affecting the data in the
memory array.
If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not
accepted. Clear the Status Register before re-issuing the command.
If the block being programmed is protected an error will be set in the Status Register and the
operation will abort without affecting the data in the memory array.
During Buffer Program operations the bank being programmed will only accept the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend command, all other commands will be ignored.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed in banks not being programmed.
See Appendix C, Figure 20: Buffer Program Flowchart and Pseudo Code, for a suggested
flowchart on using the Buffer Program command.
22/98
M58LT128GST, M58LT128GSB
4.9
4 Command Interface
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up
programming in manufacturing environments where the programming time is critical.
It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device
enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number
of times as long as the address remains within the same block. Only one block can be
programmed at a time.
The use of the Buffer Enhanced Factory Program command requires certain operating
conditions:
●
The targeted block must be unprotected. if it is protected, the user must return the device
to read mode.
●
VPP must be set to VPPH.
●
VDD must be within operating range.
●
Ambient temperature TA must be 30°C ± 10°C.
●
The start address must be aligned with the start of a 32 Word buffer boundary.
●
The address must remain the Start Address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation and
the command cannot be suspended.
The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase,
the Program and Verify Phase, and the Exit Phase, See Appendix C, Figure 25: Buffer
Enhanced Factory Program Flowchart and Pseudo Code, for a suggested flowchart on using
the Buffer Program command and to Table 6: Factory Program Command for details on the
Buffer Enhanced Factory Program command.
4.9.1
Setup phase
The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the
command.
1.
The first Bus Write cycle sets up the Buffer Enhanced Factory Program command.
2.
The second Bus Write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status
Register. The read Status Register command must not be issued as it will be interpreted as
data to program.
The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed
to the next phase.
If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program
operation is terminated. See Status Register section for details on the error.
23/98
4 Command Interface
4.9.2
M58LT128GST, M58LT128GSB
Program and Verify phase
The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write Buffer.
The data is stored sequentially, starting at the first address of the Write Buffer, until the Write
Buffer is full (32 Words). To program less than 32 Words, the remaining Words should be
programmed with FFFFh.
Three successive steps are required to issue and execute the Program and Verify Phase of the
command.
1.
Use one Bus Write operation to latch the Start Address and the first Word to be
programmed. The Status Register Bank Write Status bit SR0 should be read to check that
the P/E.C. is ready for the next Word.
2.
Each subsequent Word to be programmed is latched with a new Bus Write operation. The
address must remain the Start Address as the P/E.C. increments the address location.If
any address that is not in the same block as the Start Address is given, the Program and
Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write
cycle to check that the P/E.C. is ready for the next Word.
3.
Once the Write Buffer is full, the data is programmed sequentially to the memory array.
After the program operation the device automatically verifies the data and reprograms if
necessary.
The Program and Verify phase can be repeated, without re-issuing the command, to
program additional 32 Word locations as long as the address remains in the same block.
4.
Finally, after all Words, or the entire block have been programmed, write one Bus Write
operation to any address outside the block containing the Start Address, to terminate
Program and Verify Phase.
Status Register bit SR0 must be checked to determine whether the program operation is
finished. The Status Register may be checked for errors at any time but it must be checked after
the entire block has been programmed.
4.9.3
Exit phase
Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has exited the Buffer
Enhanced Factory Program operation and returned to Read Status Register mode. A full Status
Register check should be done to ensure that the block has been successfully programmed.
See the section on the Status Register for more details.
For optimum performance the Buffer Enhanced Factory Program command should be limited to
a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal
algorithm will continue to work properly but some degradation in performance is possible.
Typical program times are given in Table 16
See Appendix C, Figure 25: Buffer Enhanced Factory Program Flowchart and Pseudo Code,
for a suggested flowchart on using the Buffer Enhanced Factory Program command.
24/98
M58LT128GST, M58LT128GSB
4.10
4 Command Interface
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Block Erase operation.
The command can be addressed to any bank.
The Program/Erase Resume command is required to restart the suspended operation.
One bus write cycle is required to issue the Program/Erase Suspend command. Once the
Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be
set to ‘1’.
The following commands are accepted during Program/Erase Suspend:
●
Program/Erase Resume
●
Read Array (data from erase-suspended block or program-suspended Word is not valid)
●
Read Status Register
●
Read Electronic Signature
●
Read CFI Query.
In addition, if the suspended operation was a Block Erase then the following commands are
also accepted:
●
Clear Status Register
●
Program (except in erase-suspended block)
●
Buffer Program (except in erase suspended blocks)
It is possible to accumulate multiple suspend operations. For example: suspend an erase
operation, start a program operation, suspend the program operation, then read the array.
If a Program command is issued during a Block Erase Suspend, the erase operation cannot be
resumed until the program operation has completed.
The Program/Erase Suspend command does not change the read mode of the banks. If the
suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query
mode the bank remains in that mode and outputs the corresponding data.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed during Program/Erase Suspend.
During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip
Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL.
See Appendix C, Figure 21: Program Suspend & Resume Flowchart and Pseudo Code, and
Figure 23: Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the
Program/Erase Suspend command.
4.11
Program/Erase Resume command
The Program/Erase Resume command is used to restart the program or erase operation
suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue
the command. The command can be issued to any address.
The Program/Erase Resume command does not change the read mode of the banks. If the
suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query
mode the bank remains in that mode and outputs the corresponding data.
25/98
4 Command Interface
M58LT128GST, M58LT128GSB
If a Program command is issued during a Block Erase Suspend, then the erase cannot be
resumed until the program operation has completed.
See Appendix C, Figure 21: Program Suspend & Resume Flowchart and Pseudo Code, and
Figure 23: Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the
Program/Erase Resume command.
4.11.1 Protection Register Program command
The Protection Register Program command is used to program the user One-TimeProgrammable (OTP) segments of the Protection Register and the two Protection Register
Locks.
The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown
in Figure 4: Protection Register Map. The segments are programmed one Word at a time.
When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’.
Two Bus Write cycles are required to issue the Protection Register Program command.
1.
The first bus cycle sets up the Protection
2.
Register Program command.
3.
The second latches the address and data to be programmed to the Protection Register
and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the
program operation has started.
Attempting to program a previously protected Protection Register will result in a Status Register
error.
The Protection Register Program cannot be suspended. Dual operations between the
Parameter Bank and the Protection Register memory space are not allowed (see Table 15:
Dual Operation Limitations for details).
The two Protection Register Locks are used to protect the OTP segments from further
modification. The protection of the OTP segments is not reversible. Refer to Figure 4:
Protection Register Map, and Table 8: Protection Register Lock Bits, for details on the Lock bits.
See Appendix C, Figure 24: Protection Register Program Flowchart and Pseudo Code, for a
flowchart for using the Protection Register Program command.
4.12
Set Configuration Register command
The Set Configuration Register command is used to write a new value to the Configuration
Register.
Two Bus Write cycles are required to issue the Set Configuration Register command.
1.
The first cycle sets up the Set Configuration Register command and the address
corresponding to the Configuration Register content.
2.
The second cycle writes the Configuration Register data and the confirm command.
The Configuration Register data must be written as an address during the bus write cycles, that
is DQ0 = CR0, DQ1 = CR1, …, DQ15 = CR15. Addresses A0-A22 are ignored.
Read operations output the array content after the Set Configuration Register command is
issued.
26/98
M58LT128GST, M58LT128GSB
4 Command Interface
The Read Electronic Signature command is required to read the updated contents of the
Configuration Register.
Table 5.
Standard Commands
Commands
Cycles
Bus Operations(1)
1st Cycle
2nd Cycle
Op.
Add
Data
Op.
Add
Data
Read Array
1+
Write
BKA
FFh
Read
WA
RD
Read Status Register
1+
Write
X
70h
Read
BKA(2)
SRD
Read Electronic Signature
1+
Write
X
90h
Read
BKA(2)
ESD
Read CFI Query
1+
Write
BKA
98h
Read
BKA(2)
QD
Clear Status Register
1
Write
BKA
50h
Block Erase
2
Write
BKA or
BA(3)
20h
Write
BA
D0h
Program
2
Write
BKA or
WA(3)
40h or 10h
Write
WA
PD
Write
BA
E8h
Write
BA
n
Write
PA1
PD1
Write
PA2
PD2
Write
PAn+1(4)
PDn+1(4)
Write
X
D0h
Write
PRA
PRD
Write
CRD
03h
Buffer Program
n+4
Program/Erase Suspend
1
Write
X
B0h
Protection Register Program
2
Write
PRA
C0h
Program/Erase Resume
1
Write
X
D0h
Set Configuration Register
2
Write
CRD
60h
1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic
Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA = Protection Register
Address, PRD = Protection Register Data, CRD=Configuration Register Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7
3. Any address within the bank can be used.
4. n+1 is the number of Words to be programmed.
27/98
M58LT128GST, M58LT128GSB
4 Command Interface
Table 6.
Factory Program Command
Command
Cycles
Bus Write Operations(1)
Phase
2nd
3rd
Add
Data
Add
Data Add
2
BKA or
WA(2)
80h
WA1
D0h
≥32
WA1
PD1
WA1
PD2
1
NOT
BA1(4)
X
Setup
Buffer
Enhanced Program/
Factory
Verify(3)
Program
1st
Exit
WA1
Final -1
Final
Data
Add
Data
Add
Data
PD3
WA1
PD31
WA1
PD32
1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address, X = Don’t Care.
2. Any address within the bank can be used.
3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same
block.
4. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1.
Table 7.
Electronic Signature Codes
Code
Address (h)
Data (h)
Manufacturer Code
Bank Address + 00
0020
Top
Bank Address + 01
88C6h (M58LT128GST)
Bottom
Bank Address + 01
88C7h (M58LT128GSB)
Die Revision Code
Block Address + 03
DRC(1)
Configuration Register
Bank Address + 05
CR(1)
Device Code
ST Factory Default
Protection
Register PR0
OTP Area Permanently
Locked
bit 0 = ‘0’
Bank Address + 80
bit 1 = ‘0’
Bank Address + 81
Bank Address + 84
Unique Device Number
Bank Address + 85
Bank Address + 88
OTP Area
Protection Register PR1 through PR16 Lock
Bank Address + 89
PRLD
Protection Registers PR1-PR16
Bank Address + 8A
Bank Address + 109
OTP Area
Protection Register PR0
1. CR = Configuration Register, DRC = Die Revision Code.
28/98
M58LT128GST, M58LT128GSB
Figure 4.
4 Command Interface
Protection Register Map
PROTECTION REGISTERS
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah
Protection Register Lock 89h
88h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR0
User Programmable OTP
85h
84h
Unique device number
81h
80h
Protection Register Lock
1 0
AI07563
29/98
M58LT128GST, M58LT128GSB
4 Command Interface
Table 8.
Protection Register Lock Bits
Lock
Description
Number
Protection
Register
Lock 1
Protection
Register
Lock 2
30/98
Address
Bits
Bit 0
Read-only bit preprogrammed to ‘0’ protect Unique Device Number (address
81h to 84h in PR0)
Bit 1
protects 64bits of OTP segment (address 85h to 88h in PR0) when set to ‘0’
Default Value is ‘1’
Bit 0
protects 128bits of OTP segment PR1
Bit 1
protects 128bits of OTP segment PR2
Bit 2
protects 128bits of OTP segment PR3
---
---
Bit 13
protects 128bits of OTP segment PR14
Bit 14
protects 128bits of OTP segment PR15
Bit 15
protects 128bits of OTP segment PR16
80h
89h
M58LT128GST, M58LT128GSB
5
5 Status Register
Status Register
The Status Register provides information on the current or previous program or erase
operations. Issue a Read Status Register command to read the contents of the Status Register,
refer to Read Status Register Command section for more details. To output the contents, the
Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable
signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register
can only be read using single Asynchronous or Single Synchronous reads. Bus Read
operations from any address within the bank, always read the Status Register during program
and erase operations.
The various bits convey information about the status and any errors of the operation. Bits SR7,
SR6, SR2 and SR0 give information on the status of the device and are set and reset by the
device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but
must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is
set to ‘1’ the Status Register should be reset before issuing another command.
Refer to Table 9: Status Register Bits in conjunction with the following text descriptions.
5.1
Program/Erase Controller Status Bit (SR7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is
active or inactive in any bank.
When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller
is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the
device is ready to process a new command.
The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High.
5.2
Erase Suspend Status Bit (SR6)
The Erase Suspend Status bit indicates that an erase operation has been suspended in the
addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase
Suspend command has been issued and the memory is waiting for a Program/Erase Resume
command.
The Erase Suspend Status bit should only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase
Suspend Latency time of the Program/Erase Suspend command being issued therefore the
memory may still complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
Low.
31/98
5 Status Register
5.3
M58LT128GST, M58LT128GSB
Erase Status Bit (SR5)
The Erase Status bit is used to identify if there was an error during a block or bank erase
operation.
When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the
maximum number of pulses to the block or bank and still failed to verify that it has erased
correctly.
The Erase Status bit should be read once the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
Once set High, the Erase Status bit must be set Low by a Clear Status Register command or a
hardware reset before a new erase command is issued, otherwise the new command will
appear to fail.
5.4
Program Status Bit (SR4)
The Program Status bit is used to identify if there was an error during a program operation.
The Program Status bit should be read once the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the
maximum number of pulses to the Word and still failed to verify that it has programmed
correctly.
Attempting to program a '1' to an already programmed bit while VPP = VPPH will also set the
Program Status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the
attempt is not shown.
Once set High, the Program Status bit must be set Low by a Clear Status Register command or
a hardware reset before a new program command is issued, otherwise the new command will
appear to fail.
5.5
VPP Status Bit (SR3)
The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and
erase operations. The VPP pin is only sampled at the beginning of a program or erase
operation. Program and erase operations are not guaranteed if VPP becomes invalid during an
operation.
When the VPP Status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid
voltage.
when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP
Lockout Voltage, VPPLK, the memory is protected and program and erase operations cannot be
performed.
Once set High, the VPP Status bit must be set Low by a Clear Status Register command or a
hardware reset before a new program or erase command is issued, otherwise the new
command will appear to fail.
32/98
M58LT128GST, M58LT128GSB
5.6
5 Status Register
Program Suspend Status Bit (SR2)
The Program Suspend Status bit indicates that a program operation has been suspended in the
addressed block. The Program Suspend Status bit should only be considered valid when the
Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command
has been issued and the memory is waiting for a Program/Erase Resume command.
SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command
being issued therefore the memory may still complete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns
Low.
SR1. Reserved.
5.7
Bank Write/Multiple Word Program Status Bit (SR0)
The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In
Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is
ready to accept a new Word to be programmed to the memory array.
The Bank Write Status bit should only be considered valid when the Program/Erase Controller
Status SR7 is Low (set to ‘0’).
When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set
to ‘0’), the addressed bank is executing a program or erase operation. When the Program/Erase
Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a
program or erase operation is being executed in a bank other than the one being addressed.
In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to
‘0’), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to
‘1’) the device is not ready for the next Word.
For further details on how to use the Status Register, see the Flowcharts and Pseudo codes
provided in Appendix C.
33/98
M58LT128GST, M58LT128GSB
5 Status Register
Table 9.
Bit
Status Register Bits
Name
SR7 P/E.C. Status
SR6 Erase Suspend Status
SR5 Erase Status
SR4 Program Status
SR3 VPP Status
SR2
Program Suspend
Status
Type
Logic Level
Definition
'1'
Ready
'0'
Busy
'1'
Erase Suspended
'0'
Erase In progress or Completed
'1'
Erase Error
'0'
Erase Success
'1'
Program Error
'0'
Program Success
'1'
VPP Invalid, Abort
'0'
VPP OK
'1'
Program Suspended
'0'
Program In Progress or Completed
Status
Status
Error
Error
Error
Status
SR1 Reserved
SR7 = ‘1’ Not Allowed
'1'
SR7 = ‘0’
Bank Write Status
Status
Program or erase operation in a bank other than
the addressed bank
SR7 = ‘1’ No Program or erase operation in the device
'0'
SR7 = ‘0’ Program or erase operation in addressed bank
SR0
SR7 = ‘1’ Not Allowed
Multiple Word Program
Status (Enhanced
Factory Program mode)
'1'
SR7 = ‘0’ the device is NOT ready for the next Word
Status
SR7 = ‘1’ the device is exiting from BEFP
'0'
SR7 = ‘0’
1. Logic level '1' is High, '0' is Low.
34/98
the device is ready for the next Word
M58LT128GST, M58LT128GSB
6
6 Configuration Register
Configuration Register
The Configuration Register is used to configure the type of bus access that the memory will
perform. Refer to Read Modes section for details on read operations.
The Configuration Register is set through the Command Interface using the Set Configuration
Register command. After a reset or power-up the device is configured for asynchronous read
(CR15 = 1). The Configuration Register bits are described in Table 10 They specify the
selection of the burst length, burst type, burst X latency and the read operation. Refer to
Figure 5 and Figure 6 for examples of synchronous burst configurations.
6.1
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read
operations.
When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read
Select bit is set to ’0’, read operations are synchronous.
Synchronous Burst Read is supported in both parameter and main blocks and can be
performed across banks.
On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.
6.2
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous Read operations to set the number of clock
cycles between the address being latched and the first data becoming available. For correct
operation the X-Latency bits can only assume the values in Table 10: Configuration Register.
The correspondence between X-Latency settings and the maximum sustainable frequency
must be calculated taking into account some system parameters. Two conditions must be
satisfied:
1.
Depending on whether tAVK_CPU or tDELAY is supplied either one of the following two
equations must be satisfied:
(n + 1) tK ≥ tAVQV - tAVK_CPU + tQVK_CPU
(n + 2) tK ≥ tAVQV + tDELAY + tQVK_CPU
2.
and also
tK > tKQV + tQVK_CPU
where
●
n is the chosen X-Latency configuration code
●
tK is the clock period
●
tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last
●
tDELAY is address valid, L Low, or E Low to clock, whichever occurs last
●
tQVK_CPU is the data setup time required by the system CPU,
●
tKQV is the clock to data valid time
●
tAVQV is the random access time of the device.
35/98
6 Configuration Register
M58LT128GST, M58LT128GSB
Refer to Figure 5: X-Latency and Data Output Configuration Example.
6.3
Wait Polarity Bit (CR10)
The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst
Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data
output are valid or a WAIT state must be inserted.
When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is
set to ‘1’ the Wait signal is active High.
6.4
Data Output Configuration Bit (CR9)
The Data Output Configuration bit is used to configure the output to remain valid for either one
or two clock cycles during synchronous mode.
When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle, when
the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles.
The Data Output Configuration must be configured using the following condition:
●
tK > tKQV + tQVK_CPU
where
●
tK is the clock period
●
tQVK_CPU is the data setup time required by the system CPU
●
tKQV is the clock to data valid time.
If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock
cycles). Refer to Figure 5: X-Latency and Data Output Configuration Example.
6.5
Wait Configuration Bit (CR8)
The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in
Synchronous Burst Read mode.
When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid.
When the Wait Configuration bit is Low (set to ’0’) the Wait output pin is asserted during the
WAIT state. When the Wait Configuration bit is High (set to ’1’), the Wait output pin is asserted
one data cycle before the WAIT state.
6.6
Burst Type Bit (CR7)
The Burst Type bit determines the sequence of addresses read during Synchronous Burst
Reads.
The Burst Type bit is High (set to ’1’), as the memory outputs from sequential addresses only.
See Table 11: Burst Type Definition, for the sequence of addresses output from a given starting
address in sequential mode.
36/98
M58LT128GST, M58LT128GSB
6.7
6 Configuration Register
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during
synchronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling edge
of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the rising edge
of the Clock is the active edge.
6.8
Wrap Burst Bit (CR3)
The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst
reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary
(no wrap).
When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’) the
burst read does not wrap.
6.9
Burst length Bits (CR2-CR0)
The Burst Length bits are used to set the number of Words to be output during a Synchronous
Burst Read operation as result of a single address latch cycle.
They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words are
read sequentially. In continuous burst mode the burst sequence can cross bank boundaries.
In continuous burst mode, in 4, 8 or 16 Words no-wrap, depending on the starting address, the
device asserts the WAIT signal to indicate that a delay is necessary before the data is output.
If the starting address is aligned to an 8 Word boundary no WAIT states are needed and the
WAIT output is not asserted.
If the starting address is not aligned to the 8 Word boundary, WAIT will be asserted when the
burst sequence crosses the first 16 Word boundary to indicate that the device needs an internal
delay to read the successive Words in the array.
In the worst case, the number of WAIT states is one clock cycle less than the latency setting.
The exact number is reported in Table 12: Wait at the Boundary.
WAIT will be asserted only once during a continuous burst access. See also Table 11: Burst
Type Definition.
CR14, CR5 and CR4 are reserved for future use.
37/98
M58LT128GST, M58LT128GSB
6 Configuration Register
Table 10.
Configuration Register
Bit
CR15
CR14
CR13-CR11
Description
Value
Description
0
Synchronous Read
1
Asynchronous Read (Default at power-on)
010
2 clock latency(1)
011
3 clock latency
100
4 clock latency
101
5 clock latency
110
6 clock latency
111
7 clock latency (default)
Read Select
Reserved
X-Latency
Other configurations reserved
CR10
CR9
CR8
CR7
CR6
CR5-CR4
CR3
CR2-CR0
0
WAIT is active Low (default)
1
WAIT is active High
0
Data held for one clock cycle
1
Data held for two clock cycles (default)(1)
0
WAIT is active during WAIT state (default)
1
WAIT is active one data cycle before WAIT state(1)
0
Reserved
1
Sequential (default)
0
Falling Clock edge
1
Rising Clock edge (default)
0
Wrap
1
No Wrap (default)
001
4 Words
010
8 Words
011
16 Words
111
Continuous (default)
Wait Polarity
Data Output
Configuration
Wait Configuration
Burst Type
Valid Clock Edge
Reserved
Wrap Burst
Burst Length
1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not
supported.
38/98
M58LT128GST, M58LT128GSB
Mode
Table 11.
Start
Add.
6 Configuration Register
Burst Type Definition
Sequential
Continuous Burst
4 Words
8 Words
16 Words
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-1415
0-1-2-3-4-5-6...
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-1415-0
1-2-3-4-5-6-7...
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-150-1
2-3-4-5-6-7-8...
3
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-01-2
3-4-5-6-7-8-9...
7-4-5-6
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-45-6
7-8-9-10-11-12-13...
12
12-13-14-15
12-13-14-15-8-9-1011
12-13-14-15-0-1-2-3-4-5-6-7-8-9-1011
12-13-14-15-16-17...
13
13-14-15-12
13-14-15-8-9-10-1112
13-14-15-0-1-2-3-4-5-6-7-8-9-10-1112
13-14-15-16-17-18...
14
14-15-12-13
14-15-8-9-10-11-1213
14-15-0-1-2-3-4-5-6-7-8-9-10-11-1213
14-15-16-17-18-19...
15
15-12-13-14
15-8-9-10-11-12-1314
15-0-1-2-3-4-5-6-7-8-9-10-11-12-1314
15-16-17-18-19-20...
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-1415
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8--9-10-11-12-13-1415-16
2
2-3-4-5
2-3-4-5-6-7-8-9...
2-3-4-5--6-7-8-9-10-11-12-13-14-1516-17
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-1516-17-18
7-8-9-10
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-15-16-17-1819-20-21-22
12
12-13-14-15
12-13-14-15-16-1718-19
12-13-14-15-16-17-18-19-20-21-2223-24-25-26-27
13
13-14-15-16
13-14-15-16-17-1819-20
13-14-15-16-17-18-19-20-21-22-2324-25-26-27-28
14
14-15-16-17
14-15-16-17-18-1920-21
14-15-16-17-18-19-20-21-22-23-2425-26-27-28-29
15
15-16-17-18
15-16-17-18-19-2021-22
15-16-17-18-19-20-21-22-23-24-2526-27-28-29-30
Wrap
...
7
...
No-wrap
...
7
...
Same as for Wrap
(Wrap /No Wrap
has no effect on
Continuous Burst)
39/98
M58LT128GST, M58LT128GSB
6 Configuration Register
Table 12.
Start
Address
Wait at the Boundary
Number of WAIT states
X-Latency = 7
X-Latency = 6
X-Latency = 5
X-Latency = 4
X-Latency = 3
X-Latency = 2
0
0
0
0
0
0
0
1
0
0
0
0
0
0
2
1
0
0
0
0
0
3
2
1
0
0
0
0
4
3
2
1
0
0
0
5
4
3
2
1
0
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Figure 5.
X-Latency and Data Output Configuration Example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
A22-A0
tDELAY
VALID ADDRESS
tAVK_CPU
tQVK_CPU
tACC
tK
tKQV
tQVK_CPU
DQ15-DQ0
VALID ADDRESS
VALID DATA VALID DATA
AI10262
1. The settings shown are X-latency = 4, Data Output held for one clock cycle.
40/98
M58LT128GST, M58LT128GSB
Figure 6.
6 Configuration Register
Wait Configuration Example
E
K
L
G
A22-A0
VALID ADDRESS
DQ15-DQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
AI10263
41/98
7 Read modes
7
M58LT128GST, M58LT128GSB
Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is
asynchronous; if the data output is synchronized with clock, the read operation is synchronous.
The read mode and format of the data output are determined by the Configuration Register.
(See Configuration Register section for details). All banks support both asynchronous and
synchronous read operations.
7.1
Asynchronous Read modes
In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data
corresponding to the address latched, that is the memory array, Status Register, Common
Flash Interface or Electronic Signature depending on the command issued. CR15 in the
Configuration Register must be set to ‘1’ for asynchronous operations. In Asynchronous Read
mode, the WAIT signal is always deasserted.
The device features an Automatic Standby mode. During Asynchronous Read operations, after
a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In
this condition the power consumption is reduced to the standby value and the outputs are still
driven.
Asynchronous Read operations can be performed in two different ways, Asynchronous
Random Read and Asynchronous Page Read.
7.1.1
Asynchronous Random Read
Asynchronous Random Read operations are controlled by the Latch Enable, L, signal.
A valid bus operation involves setting the desired address on the Address Inputs, setting Chip
Enable and Latch Enable Low, VIL, and keeping Write Enable High, VIH. The address is latched
on the rising edge of Latch Enable, L, before the value is output on the data bus. Once latched,
the Address Inputs can change. Set Output Enable Low, VIL, to read the data on the Data
Inputs/Outputs.
See Table 22: Asynchronous Read AC Characteristics, and Figure 9: Asynchronous Random
Access Read AC Waveforms for details.
7.1.2
Asynchronous Page Read
Only Asynchronous Page Read takes full advantage of the internal page storage so different
timings are applied. In Asynchronous Page Read mode, a Page of data is internally read and
stored in a Page Buffer. The Page size is 8 Words and is addressed by address inputs A0, A1
and A2.
The first read operation within the Page has the normal access time (tAVQV), subsequent reads
within the same Page have much shorter access times (tAVQV1). If the Page changes then the
normal longer timings apply again.
See Table 22: Asynchronous Read AC Characteristics, Figure 10: Asynchronous Page Read
AC Waveforms for details.
42/98
M58LT128GST, M58LT128GSB
7.2
7 Read modes
Synchronous Burst Read modes
In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is
possible to perform burst reads across bank boundaries.
Synchronous Burst Read mode can only be used to read the memory array. For other read
operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single
Synchronous Read or Asynchronous Random Access Read must be used.
In Synchronous Burst Read mode the flow of the data output depends on parameters that are
configured in the Configuration Register.
A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge
bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable,
whichever occurs last. Addresses are internally incremented and data is output on each data
cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration
Register.
The number of Words to be output during a Synchronous Burst Read operation can be
configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0). The
data can be configured to remain valid for one or two clock cycles (Data Output Configuration
bit CR9).
The order of the data output can be modified through the Wrap Burst bit in the Configuration
Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 Word
boundary (Wrap) or overcome the boundary (No Wrap).
The WAIT signal may be asserted to indicate to the system that an output delay will occur. This
delay will depend on the starting address of the burst sequence and on the burst configuration.
WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word
burst. It is only deasserted when output data are valid or when G is at VIH. In Continuous Burst
Read mode a WAIT state will occur when crossing the first 16 Word boundary. If the starting
address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration has no
impact on the output sequence.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register.
See Table 23: Synchronous Read AC Characteristics, and Figure 11: Synchronous Burst Read
AC Waveforms, for details.
7.2.1
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher
priority devices. It can be suspended during the initial access latency time (before data is
output) in which case the initial latency time can be reduced to zero, or after the device has
output data. When the Synchronous Burst Read operation is suspended, internal array sensing
continues and any previously latched internal data is retained. A burst sequence can be
suspended and resumed as often as required as long as the operating conditions of the device
are met.
A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the
current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The
Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High.
When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous
Burst Read operation is resumed exactly where it stopped.
43/98
7 Read modes
M58LT128GST, M58LT128GSB
WAIT being gated by E, it will remain active and will not revert to high impedance when G goes
High. So if two or more devices are connected to the system’s READY signal, to prevent bus
contention the WAIT signal of the M58LT128GST and M58LT128GSB should not be directly
connected to the system’s READY signal.
WAIT will revert to high-impedance when Output Enable, G, or Chip Enable, E, goes High.
See Table 23: Synchronous Read AC Characteristics, and Figure 13: Synchronous Burst Read
Suspend AC Waveforms, for details.
7.2.2
Single Synchronous Read mode
Single Synchronous Read operations are similar to Synchronous Burst Read operations except
that the memory outputs the same data to the end of the operation.
Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI,
Configuration Register Status, or Protection Register. When the addressed bank is in Read
CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is deasserted
when Output Enable, G, is at VIH or for the one clock cycle during which output data is valid.
Otherwise, it is asserted.
See Table 23: Synchronous Read AC Characteristics, and Figure 11: Synchronous Burst Read
AC Waveforms, for details.
44/98
M58LT128GST, M58LT128GSB
8
8 Dual Operations and Multiple Bank architecture
Dual Operations and Multiple Bank architecture
The Multiple Bank Architecture of the M58LT128GST and M58LT128GSB gives greater
flexibility for software developers to split the code and data spaces within the memory array.
The Dual Operations feature simplifies the software management of the device by allowing
code to be executed from one bank while another bank is being programmed or erased.
The Dual Operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency (only one bank at a time is allowed to
be in program or erase mode).
If a read operation is required in a bank, which is programming or erasing, the program or erase
operation can be suspended.
Also if the suspended operation was erase then a program command can be issued to another
block, so the device can have one block in Erase Suspend mode, one programming and other
banks in read mode.
Bus Read operations are allowed in another bank between setup and confirm cycles of
program or erase operations.
By using a combination of these features, read operations are possible at any moment in the
M58LT128GST and M58LT128GSB devices.
Dual operations between the Parameter Bank and either of the CFI, or the Electronic Signature
memory space are not allowed. Table 15 shows which dual operations are allowed or not
between the CFI, the Electronic Signature locations and the memory array.
Table 13 and Table 14 show the dual operations possible in other banks and in the same bank.
Table 13.
Dual Operations Allowed In Other Banks
Commands allowed in another bank
Read
Array
Read
Status
Register
Read
CFI
Query
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
Yes
Yes
Yes
Yes
–
–
Yes
–
Erasing
Yes
Yes
Yes
Yes
–
–
Yes
–
Program Suspended
Yes
Yes
Yes
Yes
–
–
–
Yes
Erase Suspended
Yes
Yes
Yes
Yes
Yes
–
–
Yes
Status of bank
Read
Program/ Program/
Program,
Block
Electronic
Erase
Erase
Buffer Program Erase
Signature
Suspend Resume
45/98
M58LT128GST, M58LT128GSB
8 Dual Operations and Multiple Bank architecture
Table 14.
Dual Operations Allowed In Same Bank
Commands allowed in same bank
Status of bank
Read
Array
Read
Read
Read CFI
Status
Electronic
Query
Register
Signature
Program,
Buffer
Program
Block
Erase
Program/ Program/
Erase
Erase
Suspend Resume
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
–(1)
Yes
Yes
Yes
–
–
Yes
–
Erasing
–(1)
Yes
Yes
Yes
–
–
Yes
–
Program
Suspended
Yes(2)
Yes
Yes
Yes
–
–
–
Yes
Erase Suspended
Yes(2)
Yes
Yes
Yes
Yes(2)
–
–
Yes
1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
2. Not allowed in the Word that is being erased or programmed.
Table 15.
Dual Operation Limitations
Commands allowed
Current Status
Read Parameter
Blocks
No
No
No
Yes
Located in
Parameter
Bank
No
No
No
Yes
Not Located in
Parameter
Bank
No
Yes
Yes
In Different Bank
Only
Programming / Erasing
Parameter Blocks
Programming
/ Erasing Main
Blocks
46/98
Read Main Blocks
Read CFI / Electronic
Signature
Located in
Not Located in
Parameter Bank Parameter Bank
M58LT128GST, M58LT128GSB
9
9 Program and Erase times and Endurance cycles
Program and Erase times and Endurance cycles
The Program and Erase times and the number of Program/ Erase cycles per block are shown in
Table 16 Exact erase times may change depending on the memory array condition. The best
case is when all the bits in the block are at ‘0’ (pre-programmed). The worst case is when all the
bits in the block are at ‘1’ (not preprogrammed). Usually, the system overhead is negligible with
respect to the erase time. In the M58LT128GST and M58LT128GSB the maximum number of
Program/Erase cycles depends on the VPP voltage supply used.
Table 16.
Program/Erase Times and Endurance Cycles
Parameter
Condition(1)(2)
Min
Parameter Block (16 KWord)
Erase
Main Block (64
KWord)
Preprogrammed
Typ
Typical
after
100kW/E
Cycles
Max
Unit
0.4
1
2.5
s
1
3
4
s
Not Preprogrammed
1.2
4
s
Word Program
30
60
µs
Buffer Program
30
60
µs
Word Program
90
180
µs
Buffer Program
90
180
µs
Buffer (32 Words) (Buffer Program)
440
880
µs
Main Block (64 KWord)
880
Program
20
25
µs
Erase
20
25
µs
VPP = VDD
SIngle Cell
Program(3)
Single Word
ms
Suspend Latency
Main Blocks
Program/Erase
Cycles (per Block) Parameter Blocks
100,000
cycles
100,000
cycles
47/98
M58LT128GST, M58LT128GSB
9 Program and Erase times and Endurance cycles
Parameter
Condition(1)(2)
Max
Unit
0.4
2.5
s
1
4
s
Word Program
30
60
µs
Word Program
85
170
µs
Buffer Enhanced
Factory Program(4)
10
Buffer Program
340
Buffer Enhanced
Factory Program
320
µs
Buffer Program
640
ms
Buffer Enhanced
Factory Program
640
ms
Buffer Program
10
s
Buffer Enhanced
Factory Program
10
s
Parameter Block (16 KWord)
Min
Typ
Typical
after
100kW/E
Cycles
Erase
Main Block (64 KWord)
Single Cell
VPP = VPPH
Single Word
Buffer (32 Words)
Program(3)
Main Block (64
KWords)
Bank (16 Mbits)
Main Blocks
Program/Erase
Cycles (per Block) Parameter Blocks
µs
680
1000 cycles
2500 cycles
1. TA = –25 to 85°C; VDD = 1.7V to 2V; VDDQ = 2.7 to 3.6V.
2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling
execution).
3. Excludes the time needed to execute the command sequence.
4. This is an average value on the entire device.
48/98
µs
M58LT128GST, M58LT128GSB
10
10 Maximum Rating
Maximum Rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause
permanent damage to the device. These are stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
Table 17.
Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
Ambient Operating Temperature
–25
85
°C
TBIAS
Temperature Under Bias
–25
85
°C
TSTG
Storage Temperature
–65
125
°C
VIO
Input or Output Voltage
–0.5
4.2
V
VDD
Supply Voltage
–0.2
2.5
V
Input/Output Supply Voltage
–0.6
5
V
Program Voltage
–0.2
10
V
Output Short Circuit Current
100
mA
Time for VPP at VPPH
100
hours
TA
VDDQ
VPP
IO
tVPPH
49/98
M58LT128GST, M58LT128GSB
11 DC and AC parameters
11
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 18: Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 18.
Operating and AC Measurement Conditions
M58LT128GST,
M58LT128GSB
Parameter
Units
110
Min
Max
VDD Supply Voltage
1.7
2.0
V
VDDQ Supply Voltage
2.7
3.6
V
VPP Supply Voltage (Factory environment)
8.5
9.5
V
VPP Supply Voltage (Application environment)
–0.4
VDDQ+0.4
V
Ambient Operating Temperature
–25
85
°C
Load Capacitance (CL)
30
Input Rise and Fall Times
5
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 7.
ns
0 to VDDQ
V
VDDQ/2
V
AC Measurement I/O Waveform
VDDQ
VDDQ/2
0V
AI06161
50/98
pF
M58LT128GST, M58LT128GSB
Figure 8.
11 DC and AC parameters
AC Measurement Load Circuit
VDDQ
VDDQ
VDD
16.7kΩ
DEVICE
UNDER
TEST
CL
0.1µF
16.7kΩ
0.1µF
CL includes JIG capacitance
Table 19.
Symbol
CIN
COUT
AI06162
Capacitance
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min(1)
Max(1)
Unit
VIN = 0V
6
8
pF
VOUT = 0V
8
12
pF
1. Sampled only, not 100% tested.
51/98
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Table 20.
DC Characteristics - Currents
Symbol
Parameter
Test Condition
Typ
Max
Unit
0V ≤VIN ≤VDDQ
±1
µA
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤VOUT ≤VDDQ
Supply Current
Asynchronous Read (f=5MHz)
E = VIL, G = VIH
13
15
mA
4 Word
16
18
mA
8 Word
18
20
mA
16 Word
23
25
mA
Continuous
25
27
mA
RP = VSS ± 0.2V
25
70
µA
IDD1
Supply Current
Synchronous Read (f=52MHz)
IDD2
Supply Current
(Reset)
IDD3
Supply Current (Standby)
E = VDD ± 0.2V
25
70
µA
IDD4
Supply Current (Automatic Standby)
E = VIL, G = VIH
25
70
µA
VPP = VPPH
8
15
mA
VPP = VDD
10
20
mA
VPP = VPPH
8
15
mA
VPP = VDD
10
20
mA
Program/Erase in one Bank,
Asynchronous Read in another
Bank
23
35
mA
Program/Erase in one Bank,
Synchronous Read (Continuous
f=52MHz) in another Bank
35
47
mA
E = VDD ± 0.2V
25
70
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP Supply Current (Read)
VPP ≤VDD
0.2
5
µA
VPP Supply Current (Standby)
VPP ≤VDD
0.2
5
µA
Supply Current (Program)
IDD5 (1)
Supply Current (Erase)
Supply Current
IDD6 (1)(2)
(Dual Operations)
IDD7(1)
Supply Current Program/ Erase
Suspended (Standby)
VPP Supply Current (Program)
IPP1(1)
VPP Supply Current (Erase)
IPP2
IPP3(1)
1. Sampled only, not 100% tested.
2. VDD Dual Operation current is the sum of read and program or erase currents.
52/98
M58LT128GST, M58LT128GSB
Table 21.
Symbol
11 DC and AC parameters
DC Characteristics - Voltages
Parameter
Test Condition
Min
Typ
Max
Unit
VIL
Input Low Voltage
0
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
IOH = –100µA
VDDQ –0.1
VPP1
VPP Program Voltage-Logic
Program, Erase
1.1
1.8
3.3
V
VPPH
VPP Program Voltage Factory
Program, Erase
8.5
9.0
9.5
V
VPPLK
Program or Erase Lockout
0.4
V
VLKO
VDD Lock Voltage
VRPH
RP pin Extended High
Voltage
V
1
V
3.3
V
53/98
54/98
Hi-Z
Hi-Z
tGLTV
tELQX
tELTV
tGLQV
tLHAX
tGLQX
tELQV
tLLQV
tAVQV
Note. Write Enable, W, is High, WAIT is active Low.
WAIT
DQ0-DQ15
G
E
tELLH
tLLLH
tAVLH
VALID
tGHTZ
VALID
tEHQZ
tEHQX
tEHTZ
tGHQZ
tGHQX
tAXQX
VALID
AI08311
Figure 9.
L
A0-A22
tAVAV
11 DC and AC parameters
M58LT128GST, M58LT128GSB
Asynchronous Random Access Read AC Waveforms
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Figure 10. Asynchronous Page Read AC Waveforms
A2-A22
VALID ADDRESS
tAVAV
A0-A2
VALID ADDRESS
VALID ADD. VALID ADD. VALID ADD.
tLHAX
tAVLH
L
tLLLH
tLLQV
tELLH
E
tELQV
tELQX
G
tGLTV
WAIT (1)
Hi-Z
tELTV
tGLQV
tGLQX
tAVQV1
VALID
DATA
DQ0-DQ15
Outputs
Valid Address Latch
Note 1. WAIT is active Low.
Enabled
VALID
DATA
VALID
DATA
Valid Data
VALID
DATA
Standby
AI08334b
55/98
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Table 22.
Asynchronous Read AC Characteristics
Symbol
Alt
M58LT128GST,
M58LT128GSB
Parameter
Unit
110
tAVAV
tRC
Address Valid to Next Address Valid
Min
110
ns
tAVQV
tACC
Address Valid to Output Valid (Random)
Max
110
ns
tAVQV1
tPAGE
Address Valid to Output Valid (Page)
Max
25
ns
tAXQX(1)
tOH
Address Transition to Output Transition
Min
0
ns
Chip Enable Low to Wait Valid
Max
16
ns
Read Timings
tELTV
tELQV(2)
tCE
Chip Enable Low to Output Valid
Max
110
ns
tELQX(1)
tLZ
Chip Enable Low to Output Transition
Max
0
ns
Chip Enable High to Wait Hi-Z
Max
17
ns
tEHTZ
tEHQX(1)
tOH
Chip Enable High to Output Transition
Min
0
ns
tEHQZ(1)
tHZ
Chip Enable High to Output Hi-Z
Max
17
ns
tGLQV (2)
tOE
Output Enable Low to Output Valid
Max
30
ns
tGLQX(1)
tOLZ
Output Enable Low to Output Transition
Min
0
ns
Output Enable Low to WAIT Valid
Max
17
ns
Latch Timings
tGLTV
tGHQX (1)
tOH
Output Enable High to Output Transition
Min
0
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
Max
17
ns
tGHTZ
tDF
Output Enable High to WAIT Hi-Z
Max
17
ns
tAVLH
tAVADVH
Address Valid to Latch Enable High
Min
11
ns
tELLH
tELADVH
Chip Enable Low to Latch Enable High
Min
10
ns
tLHAX
tADVHAX
Latch Enable High to Address Transition
Min
9
ns
Min
11
ns
Max
110
ns
tLLLH
tLLQV
tADVLADVH Latch Enable Pulse Width
tADVLQV
Latch Enable Low to Output Valid
(Random)
1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
56/98
Hi-Z
tELKH
Hi-Z
tLLLH
Address
Latch
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
X Latency
tGLTV
tGLQX
Note 2
Note 1
VALID
Valid Data Flow
tKHTV
tKHQV
tKHQV
VALID
Note 2
tKHTX
tKHQX
tKHQX
VALID
Boundary
Crossing
Note 2
tKHTV
tKHTX
tKHQV
tKHQX
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
WAIT
G
E
K(4)
L
A0-A22
DQ0-DQ15
Data
Valid
tGHQZ
tGHQX
Standby
tEHTZ
AI08309
tEHQZ
tEHQX
tEHEL
VALID
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Figure 11. Synchronous Burst Read AC Waveforms
57/98
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Figure 12. Single Synchronous Read AC Waveforms
A0-A22
VALID ADDRESS
tAVKH
L
tLLKH
K(2)
tELKH
tKHQV
tELQV
E
tGLQV
tGLQX
G
tELQX
DQ0-DQ15
tGHTZ
Hi-Z
VALID
tKHTV
tGLTV
WAIT(1,2)
Hi-Z
Note 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can
be configured as the active edge. Here, the active edge is the rising one.
AI08312
58/98
tELKH
Hi-Z
Hi-Z
tLLLH
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
tGLTV
tGLQV
tGLQX
Note 1
tKHQV
VALID
VALID
tGHTZ
tGHQZ
Note 3
tGLTV
tGLQV
tGHQZ
tGHQX
tEHEL
tEHQZ
AI08308
tEHTZ
NOT VALID
tEHQX
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
3. The CLOCK signal can be held high or low
4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.
Here, the active edge is the rising one.
WAIT(2)
G
E
K(4)
L
A0-A22
DQ0-DQ15
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Figure 13. Synchronous Burst Read Suspend AC Waveforms
59/98
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Figure 14. Clock input AC Waveform
tKHKL
tKHKH
tr
tf
tKLKH
AI06981
Table 23.
Synchronous Read AC Characteristics
Symbol
Alt
M58LT128GST,
M58LT128GSB
Parameter(1)
Unit
Synchronous Read Timings
110
tAVKH
tAVCLKH
Address Valid to Clock High
Min
11
ns
tELKH
tELCLKH
Chip Enable Low to Clock High
Min
11
ns
tELTV
Chip Enable Low to Wait Valid
Max
16
ns
tEHEL
Chip Enable Pulse Width (subsequent
synchronous reads)
Min
17
ns
tEHTZ
Chip Enable High to Wait Hi-Z
Max
17
ns
tGLTV
Output Enable Low to Wait Valid
Max
17
ns
tCLKHAX
Clock High to Address Transition
Min
10
ns
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
17
ns
tCLKHQX
Clock High to Output Transition
Clock High to WAIT Transition
Min
3
ns
tLLKH
tADVLCLKH
Latch Enable Low to Clock High
Min
11
ns
tGHTZ
tDF
Output Enable High to WAIT Hi-Z
Max
17
ns
tKHKH
tCLK
Clock Period (f=52MHz)
Min
19
ns
tKLKH
Clock High to Clock Low
Clock Low to Clock High
Min
6
ns
tf, tr
Clock Fall or Rise Time
Max
2
ns
tKHAX
tKHQV
tKHTV
tKHQX
Clock Specifications
tKHTX
tKHKL
1. Sampled only, not 100% tested.
For other timings please refer to Table 22: Asynchronous Read AC Characteristics.
60/98
K
VPP
DQ0-DQ15
W
G
E
L
A0-A22
tWHDX
CONFIRM COMMAND
OR DATA INPUT
tWHVPL
tELKV
tWHEL
tWHGL
tWHAV
tWHAX
CMD or DATA
VALID ADDRESS
tAVWH
tVPHWH
tWHWL
tWHEH
tWHLL
tWLWH
tLHAX
COMMAND
tLLLH
SET-UP COMMAND
tDVWH
tGHWL
tELWL
tELLH
tAVLH
BANK ADDRESS
tAVAV
tQVVPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
AI08016c
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Figure 15. Write AC Waveforms, Write Enable Controlled
61/98
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Table 24.
Write AC Characteristics, Write Enable Controlled
Symbol
M58LT128GST,
M58LT128GSB
Parameter(1)
Alt
Unit
110
tAVAV
tWC
Address Valid to Next Address Valid
Min
110
ns
tAVLH
Address Valid to Latch Enable High
Min
11
ns
tAVWH(2)
Address Valid to Write Enable High
Min
50
ns
Data Valid to Write Enable High
Min
50
ns
Chip Enable Low to Latch Enable High
Min
11
ns
Chip Enable Low to Write Enable Low
Min
0
ns
tELQV
Chip Enable Low to Output Valid
Min
110
ns
tELKV
Chip Enable Low to Clock Valid
Min
9
ns
tGHWL
Output Enable High to Write Enable Low
Min
17
ns
tLHAX
Latch Enable High to Address Transition
Min
9
ns
tLLLH
Latch Enable Pulse Width
Min
11
ns
tWHAV(2)
Write Enable High to Address Valid
Min
0
ns
tWHAX(2)
Write Enable High to Address Transition
Min
0
ns
tDVWH
tDS
tELLH
Protection Timings
Write Enable Controlled Timings
tELWL
tCS
tWHDX
tDH
Write Enable High to Input Transition
Min
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
ns
tWHEL(3)
Write Enable High to Chip Enable Low
Min
25
ns
tWHLL
Write Enable High to Latch Enable Low
Min
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
25
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
50
ns
Output (Status Register) Valid to VPP Low
Min
0
ns
VPP High to Write Enable High
Min
200
ns
Write Enable High to VPP Low
Min
200
ns
tQVVPL
tVPHWH
tWHVPL
tVPS
1. Sampled only, not 100% tested.
2. These timings are meaningful only if Latch Enable, L, is always kept Low, VIL.
3. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may
insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array
operation in a different bank tWHEL is 0ns.
62/98
K
VPP
DQ0-DQ15
E
G
W
L
A0-A22
tGHEL
tELEH
tLHAX
COMMAND
SET-UP COMMAND
tDVEH
tLLLH
tELLH
tWLEL
tAVLH
BANK ADDRESS
tEHDX
tEHEL
tEHWH
CMD or DATA
tEHAX
CONFIRM COMMAND
OR DATA INPUT
tVPHEH
tAVEH
VALID ADDRESS
tAVAV
tEHVPL
tELKV
tWHEL
tEHGL
AI08017c
tQVVPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Figure 16. Write AC Waveforms, Chip Enable Controlled
63/98
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Table 25.
Write AC Characteristics, Chip Enable Controlled
Symbol
M58LT128GST,
M58LT128GSB
Parameter(1)
Alt
Unit
110
Chip Enable Controlled Timings
tAVAV
tWC
Address Valid to Next Address Valid
Min
110
ns
tAVEH
Address Valid to Chip Enable High
Min
50
ns
tAVLH
Address Valid to Latch Enable High
Min
11
ns
tDVEH
tDS
Data Valid to Chip Enable High
Min
50
ns
tEHAX
tAH
Chip Enable High to Address Transition
Min
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
ns
tEHEL
tWPH
Chip Enable High to Chip Enable Low
Min
25
ns
Chip Enable High to Output Enable Low
Min
0
ns
Chip Enable High to Write Enable High
Min
0
ns
Chip Enable Low to Clock Valid
Min
7
ns
Chip Enable Low to Chip Enable High
Min
50
ns
tELLH
Chip Enable Low to Latch Enable High
Min
11
ns
tELQV
Chip Enable Low to Output Valid
Min
110
ns
tGHEL
Output Enable High to Chip Enable Low
Min
17
ns
tLHAX
Latch Enable High to Address Transition
Min
9
ns
tLLLH
Latch Enable Pulse Width
Min
11
ns
Write Enable High to Chip Enable Low
Min
25
ns
Write Enable Low to Chip Enable Low
Min
0
ns
tEHVPL
Chip Enable High to VPP Low
Min
200
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
ns
VPP High to Chip Enable High
Min
200
ns
tEHGL
tEHWH
tCH
tELKV
tELEH
tWP
tWHEL(2)
Protection Timings
tWLEL
tVPHEH
tCS
tVPS
1. Sampled only, not 100% tested.
2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may
insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array
operation in a different bank tWHEL is 0ns.
64/98
M58LT128GST, M58LT128GSB
11 DC and AC parameters
Figure 17. Reset and Power-up AC Waveforms
tPHWL
tPHEL
tPHGL
tPHLL
W, E, G, L
tPLWL
tPLEL
tPLGL
tPLLL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI06976
Table 26.
Reset and Power-up AC Characteristics
Symbol
Parameter
Test Condition
110
Unit
During Program
Min
25
µs
During Erase
Min
25
µs
Other Conditions
Min
110
ns
Reset High to
Write Enable Low
Chip Enable Low
Output Enable Low
Latch Enable Low
Min
30
ns
tPLPH(1)(2)
RP Pulse Width
Min
50
ns
tVDHPH(3)
Supply Voltages High to Reset High
Min
100
µs
tPLWL
tPLEL
tPLGL
tPLLL
tPHWL
tPHEL
tPHGL
tPHLL
Reset Low to
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
1. The device Reset is possible but not guaranteed if tPLPH < 50ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
65/98
M58LT128GST, M58LT128GSB
12 Package mechanical
12
Package mechanical
Figure 18. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Bottom View Package Outline
D
D1
FD
FE
E
SD
SE
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
1. Drawing is not to scale.
Table 27.
TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
A1
0.300
A2
0.800
b
0.200
0.350
Max
0.0472
0.0118
0.0079
0.0138
0.0138
0.0197
0.0315
0.350
0.500
D
10.000
9.900
10.100
0.3937
0.3898
0.3976
D1
7.000
–
–
0.2756
–
–
ddd
66/98
Max
0.100
0.0039
e
1.000
–
–
0.0394
–
–
E
13.000
12.900
13.100
0.5118
0.5079
0.5157
E1
7.000
–
–
0.2756
–
–
FD
1.500
–
–
0.0591
–
–
FE
3.000
–
–
0.1181
–
–
SD
0.500
–
–
0.0197
–
–
SE
0.500
–
–
0.0197
–
–
M58LT128GST, M58LT128GSB
13
13 Part Numbering
Part Numbering
Table 28.
Ordering Information Scheme
Example:
M58LT128GS T
1
ZA 5
E
Device Type
M58
Architecture
L = Multilevel, Multiple Bank, Burst Mode
Operating Voltage
T = VDD = 1.7V to 2.0V, VDDQ =2.7V to 3.6V
Density
128 = 128 Mbit (x16)
Technology
G = 0.13µm
Security
S = Security
Parameter Location
T = Top Boot
B = Bottom Boot
Speed
1 = 110ns
Package
ZA = TBGA64, 10 x 13mm, 1mm pitch
Temperature Range
5 = –25 to 85°C
Packing Option
Blank = Standard Packing
E = ECOPACK Package, Standard Packing
F =ECOPACK Package, 24mm Tape & Reel Packing
67/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Table 29.
Daisy Chain Ordering Scheme
Example:
M58LT128GS
-ZA E
Device Type
M58LT128GS
Daisy Chain
ZA = TBGA64, 10 x 13mm, 1mm pitch
Option
Blank = Standard Packing
E = ECOPACK Package, Standard Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of
this device, please contact the ST Sales Office nearest to you.
68/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Appendix A Block address tables
The following set of equations can be used to calculate a complete set of block addresses for
the M58LT128GST and M58LT128GSB using the information contained in Table 30 to Table 35.
To calculate the Block Base Address from the Block Number:
First it is necessary to calculate the Bank Number and the Block Number Offset. This can be
achieved using the following formulas:
Bank_Number = (Block_Number − 3) / 16
Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16)
If Bank_Number = 0, the Block Base Address can be directly read from Table 30 and Table 33
(Parameter Bank Block Addresses) in the Address Range column, in the row that corresponds
to the given block number.
Otherwise:
Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset
To calculate the Bank Number and the Block Number from the Block Base Address:
If the address is in the range of the Parameter Bank, the Bank Number is 0 and the Block
Number can be directly read from Table 30 for the M58LT128GST and Table 33 for the
M58LT128GSB (Parameter Bank Block Addresses), in the Block Number column, in the row
that corresponds to the address given. Otherwise, the Block Number can be calculated using
the formulas below:
For the top configuration (M58LT128GST):
Block_Number = ((NOT address) / 216) + 3
For the bottom configuration (M58LT128GSB):
Block_Number = (address / 216) + 3
For both configurations the Bank Number and the Block Number Offset can be calculated using
the following formulas:
Bank_Number = (Block_Number − 3) / 16
Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16)
69/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Table 30.
M58LT128GST - Parameter Bank Block Addresses
Block Number
Size (KWords)
Address Range
0
16
7FC000-7FFFFF
1
16
7F8000-7FBFFF
2
16
7F4000-7F7FFF
3
16
7F0000-7F3FFF
4
64
7E0000-7EFFFF
5
64
7D0000-7DFFFF
6
64
7C0000-7CFFFF
7
64
7B0000-7BFFFF
8
64
7A0000-7AFFFF
9
64
790000-79FFFF
10
64
780000-78FFFF
Table 31.
M58LT128GST - Main Bank Base Addresses
Bank Number
Block Numbers
Bank Base Address
1
11-18
700000
2
19-26
680000
3
27-34
600000
4
35-42
580000
5
43-50
500000
6
51-58
480000
7
59-66
400000
8
67-74
380000
9
75-82
300000
10
83-90
280000
11
91-98
200000
12
99-106
180000
13
107-114
100000
14
115-122
080000
15
123-130
000000
1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank
Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
70/98
M58LT128GST, M58LT128GSB
Table 32.
13 Part Numbering
M58LT128GST - Block Addresses in Main Banks
Block Number Offset
Block Base Address Offset
0
070000
1
060000
2
050000
3
040000
4
030000
5
020000
6
010000
7
000000
Table 33.
M58LT128GSB - Parameter Bank Block Addresses
Block Number
Size (KWords)
Address Range
10
64
070000-07FFFF
9
64
060000-06FFFF
8
64
050000-05FFFF
7
64
040000-04FFFF
6
64
030000-03FFFF
5
64
020000-02FFFF
4
64
010000-01FFFF
3
16
00C000-00FFFF
2
16
008000-00BFFF
1
16
004000-007FFF
0
16
000000-003FFF
71/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Table 34.
M58LT128GSB- Main Bank Base Addresses
Bank Number
Block Numbers
Bank Base Address
15
123-130
780000
14
115-122
700000
13
107-114
680000
12
99-106
600000
11
91-98
580000
10
83-90
500000
9
75-82
480000
8
67-74
400000
7
59-66
380000
6
51-58
300000
5
43-50
280000
4
35-42
200000
3
27-34
180000
2
19-26
100000
1
11-18
080000
1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank
Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
Table 35.
72/98
M58LT128GSB - Block Addresses in Main Banks
Block Number Offset
Block Base Address Offset
7
070000
6
060000
5
050000
4
040000
3
030000
2
020000
1
010000
0
000000
M58LT128GST, M58LT128GSB
13 Part Numbering
Appendix B Common Flash Interface
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the Read CFI Query Command is issued the device enters CFI Query mode and the
data structure is read from the memory. Table 36, Table 37, Table 38, Table 39, Table 40,
Table 42, Table 43, Table 44 and Table 45 show the addresses used to retrieve the data. The
Query data is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs
(DQ8-DQ15) are set to 0.
The CFI data structure also contains a security area where a 64 bit unique security number is
written (see Figure 4: Protection Register Map).This area can be accessed only in Read mode
by the final user. It is impossible to change the security number after it has been written by ST.
Issue a Read Array command to return to Read mode.
Table 36.
Query Structure Overview
Offset
Sub-section Name
Description
000h
Reserved
Reserved for algorithm-specific information
010h
CFI Query Identification String
Command set ID and algorithm data offset
01Bh
System Interface Information
Device timing & voltage information
027h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Security Code Area
Lock Protection Register
Unique device Number and
User Programmable OTP
080h
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main subsections detailed in Table 37, Table 38, Table 39 and Table 40. Query data is always presented on the lowest order data
outputs.
73/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Table 37.
CFI Query Identification String
Offset
Sub-section Name
000h
0020h
Manufacturer Code
001h
88C6h
88C7h
Device Code
002h
reserved
003h
DRC
004h-00Fh
reserved
010h
0051h
011h
0052h
012h
0059h
013h
0001h
014h
0000h
015h
offset = P = 000Ah
016h
0001h
017h
0000h
018h
0000h
019h
value = A = 0000h
01Ah
0000h
Table 38.
Description
Value
ST
M58LT128GST
M58LT128GSB
Top
Bottom
Reserved
Die Revision Code
Reserved
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16
bit ID code defining a specific algorithm
Address for Primary Algorithm extended Query table (see
Table 40)
p = 10Ah
Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported
NA
Address for Alternate Algorithm extended Query table
NA
CFI Query System Interface Information
Offset
Data
01Bh
0017h
01Ch
0020h
01Dh
0085h
Description
Value
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
1.7V
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
2V
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
8.5V
VPP [Programming] Supply Maximum Program/Erase voltage
9.5V
01Eh
0095h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
01Fh
0008h
Typical time-out per single byte/word program = 2n µs
256µs
020h
0009h
Typical time-out for Buffer Program = 2n µs
512µs
021h
000Ah
Typical time-out per individual block erase = 2n ms
1s
022h
0000h
Typical time-out for full chip erase = 2n ms
NA
74/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Offset
Data
023h
0001h
Maximum time-out for word program = 2n times typical
512µs
024h
0001h
Maximum time-out for Buffer Program = 2n times typical
1024µs
025h
0002h
Maximum time-out per individual block erase = 2n times typical
4s
026h
0000h
Maximum time-out for chip erase = 2n times typical
NA
TOP DEVICES
Table 39.
Value
Device Geometry Definition
Offset
Data
027h
0018h
Device Size = 2n in number of bytes
028h
029h
0001h
0000h
Flash Device Interface Code description
02Ah
02Bh
0006h
0000h
Maximum number of bytes in multi-byte program or page = 2n
64 Bytes
02Ch
0002h
Number of identical sized erase block regions within the device
bit 7 to 0 = x = number of Erase Block Regions
2
02Dh
02Eh
007Eh
0000h
Erase Block Region 1 Information
Number of identical-size erase blocks = 007Eh+1
02Fh
030h
0000h
0002h
Erase Block Region 1 Information
Block size in Region 1 = 0200h * 256 Byte
031h
032h
0003h
0000h
Erase Block Region 2 Information
Number of identical-size erase blocks = 0003h+1
033h
034h
0080h
0000h
Erase Block Region 2 Information
Block size in Region 2 = 0080h * 256 Byte
035h
038h
BOTTOM DEVICES
Description
Description
Reserved Reserved for future erase block region information
02Dh
02Eh
0003h
0000h
Erase Block Region 1 Information
Number of identical-size erase block = 0003h+1
02Fh
030h
0080h
0000h
Erase Block Region 1 Information
Block size in Region 1 = 0080h * 256 bytes
031h
032h
007Eh
0000h
Erase Block Region 2 Information
Number of identical-size erase block = 007Eh+1
033h
034h
0000h
0002h
Erase Block Region 2 Information
Block size in Region 2 = 0200h * 256 bytes
035h
038h
Reserved Reserved for future erase block region information
Value
16 MBytes
x16
Async.
127
128 KByte
4
32 KByte
NA
4
32 KBytes
127
128 KBytes
NA
75/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Table 40.
Primary Algorithm-Specific Extended Query Table
Offset
Data
(P)h = 10Ah
0050h
0052h
Description
Value
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
0049h
"R"
"I"
(P+3)h =10Dh
0031h
Major version number, ASCII
"1"
(P+4)h = 10Eh
0033h
Minor version number, ASCII
"3"
(P+5)h = 10Fh
00E6h
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
0003h
(P+7)h = 111h
(P+8)h = 112h
0000h
0000h
bit 0 Chip Erase supported(1 = Yes, 0 = No)
bit 1 Erase Suspend supported(1 = Yes, 0 = No)
bit 2 Program Suspend supported(1 = Yes, 0 = No)
bit 3 Reserved
bit 5 Instant individual block locking supported(1 = Yes, 0 = No)
bit 6 Protection bits supported(1 = Yes, 0 = No)
bit 7 Page mode read supported(1 = Yes, 0 = No)
bit 8 Synchronous read supported(1 = Yes, 0 = No)
bit 9 Simultaneous operation supported(1 = Yes, 0 = No)
bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31
bit field of optional features follows at the end of the bit-30 field.
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query
(P+9)h = 113h
0001h
Yes
bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
(P+A)h = 114h
0003h
(P+B)h = 115h
0000h
Reserved
VDD Logic Supply Optimum Program/Erase voltage (highest performance)
(P+C)h = 116h
0018h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
1.8V
VPP Supply Optimum Program/Erase voltage
(P+D)h = 117h
76/98
0090h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
9V
M58LT128GST, M58LT128GSB
Table 41.
13 Part Numbering
Protection Register Information
Offset
Data
(P+E)h = 118h
0002h
(P+F)h = 119h
0080h
(P+10)h = 11Ah
0000h
(P+11)h = 11Bh
0003h
(P+12)h = 11Ch
0003h
(P+13)h = 11Dh
0089h
(P+14)h = 11Eh
0000h
(P+15)h = 11Fh
0000h
(P+16)h = 120h
0000h
(P+17)h = 121h
0000h
Description
Number of protection register fields in JEDEC ID space. 0000h indicates
that 256 fields are available.
Protection Field 1: Protection Description
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
Value
2
80h
00h
8 Bytes
8 Bytes
89h
00h
Protection Register 2: Protection Description
Bits 0-31 protection register address
Bits 32-39 n number of factory programmed regions (lower byte)
Bits 40-47 n number of factory programmed regions (upper byte)
00h
00h
0
Bits 48-55 2n bytes in factory programmable region
Bits 56-63 n number of user programmable regions (lower byte)
Bits 64-71 n number of user programmable regions (upper byte)
0
Bits 72-79 2n bytes in user programmable region
16
(P+18)h = 122h
0000h
(P+19)h = 123h
0000h
(P+1A)h = 124h
0010h
(P+1B)h = 125h
0000h
0
(P+1C)h = 126h
0004h
16
Table 42.
0
Burst Read Information
Offset
Data
Description
Value
Page-mode read capability
(P+1D)h = 127h
0004h
(P+1E)h = 128h
0004h
bits 0-7 n’ such that 2n HEX value represents the number of read-page
16 Bytes
bytes. See offset 0028h for device word width to determine page-mode data
output width.
Number of synchronous mode read configuration fields that follow.
4
Synchronous mode read capability configuration 1
bit 3-7 Reserved
bit 0-2 n’ such that 2n+1 HEX value represents the maximum number of
continuous synchronous reads when the device is configured for its
maximum word width. A value of 07h indicates that the device is capable of
continuous linear bursts that will output data until the internal burst counter
reaches the end of the device’s burstable address space. This field’s 3-bit
value can be written directly to the read configuration register bit 0-2 if the
device is configured for its maximum word width. See offset 0028h for word
width to determine the burst data output width.
(P+1F)h = 129h
0001h
(P+20)h = 12Ah
0002h
Synchronous mode read capability configuration 2
8
(P-21)h = 12Bh
0003h
Synchronous mode read capability configuration 3
16
(P+22)h = 12Ch
0007h
Synchronous mode read capability configuration 4
Cont.
4
77/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Table 43.
Bank and Erase Block Region Information
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
(P+23)h = 12Dh
02h
(P+23)h = 12Dh
02h
Number of Bank Regions within the device
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Table 30 to Table 35.
78/98
M58LT128GST, M58LT128GSB
Table 44.
13 Part Numbering
Bank and Erase Block Region 1 Information
Flash memory (top)
Flash memory
(bottom)
Offset
Data
Offset
Data
(P+24)h = 12Eh
0Fh
(P+24)h = 12Eh
01h
(P+25)h = 12Fh
00h
(P+25)h = 12Fh
00h
Description
Number of identical banks within Bank Region 1
(P+26)h = 130h
(P+27)h = 131h
(P+28)h = 132h
(P+29)h = 133h
11h
00h
00h
01h
(P+26)h = 130h
(P+27)h = 131h
(P+28)h = 132h
(P+29)h = 133h
11h
Number of program or erase operations allowed in Bank
Region 1:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in other
banks while a bank in same region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in other
banks while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
02h
Types of erase block regions in Bank Region 1
n = number of erase block regions with contiguous same-size
erase blocks.
Symmetrically blocked banks have one blocking region(2).
(P+2A)h = 134h
07h
(P+2A)h = 134h
03h
(P+2B)h = 135h
00h
(P+2B)h = 135h
00h
(P+2C)h = 136h
00h
(P+2C)h = 136h
80h
(P+2D)h = 137h
02h
(P+2D)h = 137h
00h
(P+2E)h = 138h
64h
(P+2E)h = 138h
64h
(P+2F)h = 139h
00h
(P+2F)h = 139h
00h
(P+30)h = 13Ah
(P+31)h = 13Bh
02h
03h
(P+30)h = 13Ah
(P+31)h = 13Bh
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
02h
Bank Region 1 (Erase Block Type 1): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 1 (Erase Block Type 1): Page mode and
Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
79/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Flash memory (top)
Offset
Data
Flash memory
(bottom)
Description
Offset
Data
(P+32)h = 13Ch
06h
(P+33)h = 13Dh
00h
(P+34)h = 13Eh
00h
(P+35)h = 13Fh
02h
Bits 16-31: n×256 = number of bytes in erase block region
(P+36)h = 140h
64h
(P+37)h = 141h
00h
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
(P+38)h = 142h
(P+39)h = 143h
Bank Region 1 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized
erase blocks
02h
Bank Regions 1 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 1 (Erase Block Type 2): Page mode and
Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Table 30 to Table 35.
80/98
M58LT128GST, M58LT128GSB
Table 45.
13 Part Numbering
Bank and Erase Block Region 2 Information
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
(P+32)h = 13Ch
01h
(P+3A)h = 144h
0Fh
(P+33)h = 13Dh
00h
(P+3B)h = 145h
00h
Number of identical banks within Bank Region 2
(P+34)h = 13Eh
(P+35)h = 13Fh
(P+36)h = 140h
(P+37)h = 141h
11h
00h
00h
02h
(P+3C)h = 146h
(P+3D)h = 147h
(P+3E)h = 148h
(P+3F)h = 149h
11h
Number of program or erase operations allowed in Bank
Region 2:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in other
banks while a bank in this region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in other
banks while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
01h
Types of erase block regions in Bank Region 2
n = number of erase block regions with contiguous samesize erase blocks.
Symmetrically blocked banks have one blocking region.(2)
(P+38)h = 142h
06h
(P+40)h = 14Ah
07h
(P+39)h = 143h
00h
(P+41)h = 14Bh
00h
(P+3A)h = 144h
00h
(P+42)h = 14Ch
00h
(P+3B)h = 145h
02h
(P+43)h = 14Dh
02h
(P+3C)h = 146h
64h
(P+44)h = 14Eh
64h
(P+3D)h = 147h
00h
(P+45)h = 14Fh
00h
(P+3E)h = 148h
02h
(P+3F)h = 149h
03h
(P+40)h = 14Ah
03h
(P+41)h = 14Bh
00h
(P+42)h = 14Ch
80h
(P+43)h = 14Dh
00h
(P+46)h = 150h
(P+47)h = 151h
Bank Region 2 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
02h
Bank Region 2 (Erase Block Type 1): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 2 (Erase Block Type 1):Page mode and
Synchronous mode capabilities (defined in Table 42)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
81/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
(P+44)h = 14Eh
64h
(P+45)h = 14Fh
00h
(P+46)h = 150h
(P+47)h = 151h
Offset
Data
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
02h
Bank Region 2 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 2 (Erase Block Type 2): Page mode and
Synchronous mode capabilities (defined in Table 42)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+48)h = 152h
(P+48)h = 152h
Feature Space definitions
(P+49)h = 153h
(P+43)h = 153h
Reserved
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Table 30 to Table 32 for the M58LT128GST and Table 33 to Table 35 for
the M58LT128GSB.
82/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Appendix C Flowcharts and Pseudo Codes
Figure 19. Program Flowchart and Pseudo Code
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0x40);
/*writeToFlash (addressToProgram, 0x10);*/
/*see note (3)*/
Write 40h or 10h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram);
"see note (3)";
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06170b
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
83/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Figure 20. Buffer Program Flowchart and Pseudo Code
Start
Buffer Program E8h
Command,
Start Address
status_register=readFlash (Start_Address);
Read Status
Register
SR7 = 1
Buffer_Program_command (Start_Address, n, buffer_Program[] )
/* buffer_Program [] is an array structure used to store the address and
data to be programmed to the Flash memory (the address must be within
the segment Start Address and Start Address+n) */
{
do {writeToFlash (Start_Address, 0xE8) ;
NO
} while (status_register.SR7==0);
YES
writeToFlash (Start_Address, n);
Write n(1),
Start Address
Write Buffer Data,
Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data);
/*buffer_Program[0].address is the start address*/
X=0
X=n
x = 0;
YES
while (x<n)
NO
Write Next Buffer Data,
Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++;
X=X+1
}
Program
Buffer to Flash
Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status
Register
SR7 = 1
do {status_register=readFlash (Start_Address);
NO
} while (status_register.SR7==0);
YES
Full Status
Register Check(3)
full_status_register_check();
}
End
AI08913b
1. n + 1 is the number of data being programmed.
2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to
buffer_Program[].address.
3. Routine for Error Check by reading SR3, SR4 and SR1.
84/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Figure 21. Program Suspend & Resume Flowchart and Pseudo Code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR2 = 1
NO
Program Complete
YES
Write FFh
Read data from
another address
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
}
else
Write D0h
Write FFh
Write 70h(1)
Read Status Register
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
writeToFlash (bank_address, 0x70) ;
/*read status register to check if erase has completed */
}
}
Program Continues with
Bank in Read Status
Register Mode
AI10117
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
85/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Figure 22. Block Erase Flowchart and Pseudo Code
Start
erase_command ( blockToErase ) {
writeToFlash (blockToErase, 0x20) ;
/*see note (2) */
Write 20h (2)
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
status_register=readFlash (blockToErase) ;
/* see note (2) */
/* E or G must be toggled*/
Read Status
Register (2)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1)
YES
Command
Sequence Error (1)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
SR4, SR5 = 1
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
error_handler ( ) ;
NO
SR5 = 0
NO
Erase Error (1)
if ( (status_register.SR5==1) )
/* erase error */
error_handler ( ) ;
YES
SR1 = 0
NO
Erase to Protected
Block Error (1)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06174b
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
86/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR6 = 1
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
YES
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
}
else
Write D0h
Write FFh
Write 70h(1)
Read Status Register
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
/*read or program data from another address*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
writeToFlash (bank_address, 0x70) ;
/*read status register to check if erase has completed */
}
}
Erase Continues with
Bank in Read Status
Register Mode
AI10116
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
87/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Figure 24. Protection Register Program Flowchart and Pseudo Code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0xC0) ;
/*see note (3) */
Write C0h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram) ;
/* see note (3) */
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06177b
88/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Figure 25. Buffer Enhanced Factory Program Flowchart and Pseudo Code
SETUP PHASE Buffer_Enhanced_Factory_Program_Command
(start_address, DataFlow[]) {
Start
VerifyTargeted Block Protection Status
Verify Block
Protection Status
YES
if block protected Return Device to Read Mode
Protected
Block
NO
Write FFFFh to
Address WA1
Read Mode
Write 80h to
Address WA1
writeToFlash (start_address, 0x80) ;
Write D0h to
Address WA1
writeToFlash (start_address, 0xD0) ;
do {
do {
status_register = readFlash (start_address);
Read Status
Register
NO
SR7 = 0
YES
NO
Initialize count
X=0
SR4 = 1
Read Status Register
SR3 and SR1for errors
Write PDX
Address WA1
Exit
Increment Count
X=X+1
NO
if (status_register.SR4==1) { /*error*/
if (status_register.SR3==1) error_handler ( ) ;/*VPP error */
if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */
}
PROGRAM AND while (status_register.SR7==1)
VERIFY PHASE x=0; /* initialize count */
do {
writeToFlash (start_address, DataFlow[x]);
x++;
X = 32
}while (x<32)
do {
YES
Read Status
Register
NO
status_register = readFlash (start_address);
}while (status_register.SR0==1)
SR0 = 0
YES
NO
Last data?
} while (not last data)
YES
Write FFFFh to
Address = NOT WA1
Read Status
Register
NO
SR7 = 1
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
do {
status_register = readFlash (start_address)
}while (status_register.SR7==0)
YES
Full Status Register
Check
End
full_status_register_check();
}
AI10658
1. For how to check the targeted block protection status, refer to the Application Note concerning the device security features.
89/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Appendix D Command Interface state tables
Table 46.
Command Interface States - Modify Table, Next State
Command Input(1)
Current CI State
Read
Array
(FFh)(2)
Ready
Ready
Lock/CR Setup
Program
Setup
(10/40h)
(3)(4)
Buffer
Program
(E8h)(3)(4)
Block
Erase,
Setup
(20h)
BEFP
Setup
(80h)
(3)(4)
Buffer
Program
Setup
Program
Setup
Erase
Setup
(3)(4)
Ready (Lock Error)
Busy
(70h)
(50h)(5)
Program Suspend
(90h, 98h)
Program Busy
Program Busy
Program Suspend
Buffer Program Load 1 (give word count load (N-1));
Buffer
if N=0 go to Buffer Program Confirm. Else (N not =0) go to Buffer Program Load 2 (data load)
Buffer
Buffer Program Confirm when count =0; Else Buffer Program Load 2
(note: Buffer Program will fail at this point if any block address is different from the first address)
Load 2
Confirm
Buffer Program
Busy
Ready (error)
Busy
Ready (error)
Buffer
Program
Suspend
Buffer Program Busy
Buffer Program Busy
Suspend
Buffer Program Suspend
Buffer Program
Busy
Buffer Program Suspend
Setup
Ready (error)
Erase Busy
Ready (error)
Busy
Erase
Suspend
Program in
Erase
Suspend
Buffer
Program
Setup in
Erase
Suspend
Erase Suspend
Setup
Busy
Suspend
Erase
Suspend
Erase Busy
Erase
Suspend
Read
Electronic
Signature,
Read CFI
Query
Ready (Lock Error)
Program
Suspend
Program Busy
Load 1
90/98
Clear
status
Register
Ready
Ready
Setup
Program
in Erase
Suspend
Read
Status
Register
Program Busy
Suspend
Buffer
Program
Buffer
Program,
Program/
Erase
Suspend
(B0h)
BEFP
Setup
Setup
Program
Erase Confirm
P/E Resume,
BEFP
Confirm(D0h)
Erase Busy
Erase Busy
Erase Suspend
Program Busy in Erase Suspend
Program
Suspend in
Erase
Suspend
Program Busy in Erase Suspend
Program Suspend in Erase Suspend
Program Busy in
Erase Suspend
Program Busy in Erase Suspend
Program Suspend in Erase Suspend
M58LT128GST, M58LT128GSB
13 Part Numbering
Command Input(1)
Current CI State
Read
Array
(FFh)(2)
Buffer
Program
in Erase
Suspend
(3)(4)
Buffer
Program
(E8h)(3)(4)
Block
Erase,
Setup
(20h)
Erase Confirm
P/E Resume,
BEFP
Confirm(D0h)
BEFP
Setup
(80h)
(3)(4)
(3)(4)
Buffer
Program,
Program/
Erase
Suspend
(B0h)
Read
Status
Register
Clear
status
Register
(70h)
(50h)(5)
Read
Electronic
Signature,
Read CFI
Query
(90h, 98h)
Setup
Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N not =0) go to Buffer Program
Load 2
Buffer Load
1
Buffer Program Load 2 in Erase Suspend (data load)
Buffer Load
2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this
point if any block address is different from the first address)
Confirm
Busy
Suspend
Lock/CR Setup
in Erase Suspend
Buffer
EFP
Program
Setup
(10/40h)
Setup
Buffer Program
Busy in Erase
Suspend
Ready (error)
Ready (error)
Buffer
Program
Suspend in
Erase
Suspend
Buffer Program Busy in Erase Suspend
Buffer Program Busy in Erase Suspend
Buffer Program Suspend in Erase Suspend
Buffer Program
Busy in Erase
Suspend
Buffer Program Suspend in Erase Suspend
Erase Suspend (Lock Error)
Erase Suspend
Erase Suspend (Lock Error)
Ready (error)
BEFP Busy
Ready (error)
Busy
BEFP Busy(6)
1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/
Erase Controller.
2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined
data output.
3. The two cycle command should be issued to the same bank address.
4. If the P/E.C. is active, both cycles are ignored.
5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
6. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any
other commands are treated as data.
91/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Table 47.
Command Interface States - Modify Table, Next Output State
Command Input(1)(2)
Current CI State
Read
Array
(FFh)(3)
Program
Setup
(10/
40h)(4)(5)
Buffer
Program
(E8h)
Block
Erase,
Setup
(20h)(4)(5)
Erase
Confirm
BEFP
Setup
(80h)
P/E
Resume,
BEFP
Confirm
Program/
Erase
Suspend
(B0h)
Read
Status
Register
(70h)
Clear status
Register
(50h)
Read
Electronic
signature,
Read CFI
Query
(90h, 98h)
(D0h)(4)(5)
Program Setup
Erase Setup
Program in Erase Suspend
BEFP Setup
BEFP Busy
Buffer Program Setup
Buffer Program Load 1
Buffer Program Load 2
Status Register
Buffer Program Confirm
Buffer Program Setup in Erase
Suspend
Buffer Program Load 1 in Erase
Suspend
Buffer Program Load 2 in Erase
Suspend
Buffer Program Confirm in Erase
Suspend
Lock/CR Setup
Lock/CR Setup in Erase Suspend
Ready
Program Busy
Erase Busy
Buffer Program Busy
Program/Erase Suspend
Buffer Program Suspend
Program Busy in Erase Suspend
Buffer Program Busy in Erase
Suspend
Program Suspend in Erase
Suspend
Buffer Program Suspend in Erase
Suspend
92/98
Array
Status Register
Output Unchanged
Status
Register
Output
Unchanged
Electronic
Signature/
CFI
M58LT128GST, M58LT128GSB
13 Part Numbering
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank.
The next state does not depend on the bank output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/
Erase Controller.
3. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined
data output.
4. The two cycle command should be issued to the same bank address.
5. If the P/E.C. is active, both cycles are ignored.
Table 48.
Command Interface States - Lock Table, Next State
Command Input(1)(2)
Current CI State
Lock/CR Setup(60h)(2)
Ready
Lock/CR Setup
Lock/CR Setup
Ready (Lock error)
Program
Erase
Illegal Command(4)
Ready
Ready
WSM Operation
Completed
N/A
Ready (Lock error)
N/A
N/A
Busy
Program Busy
Ready
Suspend
Program Suspend
N/A
Setup
Buffer Program Load 1 (give word count load (N-1)
N/A
Buffer Program Load 2(5)
Exit
see note(5)
N/A
Buffer Load
2
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if
any block address is different from the first address)
N/A
Confirm
Ready (error)
N/A
Busy
Buffer Program Busy
Ready
Suspend
Buffer Program Suspend
N/A
Setup
Ready (error)
N/A
Busy
Erase Busy
Ready
Lock/CR Setup in Erase
Suspend
Erase Suspend
N/A
Setup
Program Busy in Erase Suspend
N/A
Busy
Program Busy in Erase Suspend
Erase Suspend
Suspend
Program Suspend in Erase Suspend
Setup
Buffer Program Load 1 in Erase Suspend (give word count load (N-1))
Buffer Load
1
Buffer
Program in
Erase
Suspend
(XXXXh)(3)
Program Busy
Suspend
Program in
Erase
Suspend
Block Address (WA0)
(03h)
Setup
Buffer Load
1
Buffer
Program
Set CR Confirm
Buffer Program Load 2 in Erase Suspend(6)
Exit
see note (6)
Buffer Load
2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note:
Buffer Program will fail at this point if any block address is different from the first address)
Confirm
Ready (error)
Busy
Buffer Program Busy in Erase Suspend
Suspend
Buffer Program Suspend in Erase Suspend
N/A
93/98
M58LT128GST, M58LT128GSB
13 Part Numbering
Command Input(1)(2)
Current CI State
Lock/CR Setup(60h)(2)
Lock/CR Setup
in Erase Suspend
Erase Suspend (Lock
error)
Set CR Confirm
Block Address (WA0)
(03h)
(XXXXh)(3)
Erase Suspend
(Lock error)
Erase Suspend
Setup
Illegal Command(4)
Ready (error)
WSM Operation
Completed
N/A
N/A
BEFP
Busy
BEFP Busy(7)
Exit
BEFP Busy(7)
N/A
1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/
Erase Controller, WA0 = Address in a block different from first BEFP address.
2. If the P/E.C. is active, both cycles are ignored.
3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
4. Illegal commands are those not defined in the command set.
5. if N=0 go to Buffer Program Confirm. Else (N ≠ 0) go to Buffer Program Load 2 (data load).
6. if N=0 go to Buffer Program Confirm in Erase Suspend. Else (N ≠ 0) go to Buffer Program Load 2 in Erase Suspend.
7. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any
other commands are treated as data.
94/98
M58LT128GST, M58LT128GSB
Table 49.
13 Part Numbering
Command Interface States - Lock Table, Next Output State
Command Input(1)(2)
Current CI State
Lock/CR Setup
Set CR Confirm
(60h)(3)
(03h)
BEFP Exit (FFFFh)(4)
Illegal Command(5)
WSM Operation Completed
Program Setup
Erase Setup
Program in Erase
Suspend
BEFP Setup
BEFP Busy
Buffer Program Setup
Buffer Program Load 1
Status Register
Buffer Program Load 2
Buffer Program Confirm
Buffer Program Setup in
Erase Suspend
Buffer Program Load 1
in Erase Suspend
Buffer Program Load 2
in Erase Suspend
Buffer Program Confirm
in Erase Suspend
Output Unchanged
Lock/CR Setup
Array
Lock/CR Setup in Erase
Suspend
Status Register
Ready
Program Busy
Erase Busy
Buffer Program Busy
Program/Erase Suspend
Status Register
Buffer Program Suspend
Output Unchanged
Array
Output Unchanged
Program Busy in Erase
Suspend
Buffer Program Busy in
Erase Suspend
Program Suspend in
Erase Suspend
Buffer Program Suspend
in Erase Suspend
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank.
The next state does not depend on the bank's output state.
95/98
13 Part Numbering
M58LT128GST, M58LT128GSB
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/
Erase Controller, WA0 = Address in a block different from first BEFP address.
3. If the P/E.C. is active, both cycles are ignored.
4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
5. Illegal commands are those not defined in the command set.
96/98
M58LT128GST, M58LT128GSB
14
14 Revision history
Revision history
Table 50.
Document Revision History
Date
Version
Revision Details
16-Nov-2004
0.1
First Issue.
10-Dec-2004
0.2
Asynchronous Page Read mode added in Summary description, Section 3: Bus
operations. Figure 10: Asynchronous Page Read AC Waveforms updated and
Table 22: Asynchronous Read AC Characteristics for tAVQV1.
17-Jan-2004
0.3
WP and R pins removed from Figure 1: Logic Diagram.
WP removed from Figure 15: Write AC Waveforms, Write Enable Controlled and
Figure 16: Write AC Waveforms, Chip Enable Controlled.
80ns speed class chagned into 85ns.
DU pins changed into NC in Figure 2: TBGA64 Connections (Top view through
package).
tWHQV removed from Figure 15, Figure 16.
20-Jun-2005
0.4
Table 22, Table 23 and Table 26 updated.
Table 24 updated; tWHQV removed and tAVWH, tELQV, tELKV, tGHWL, tWHAV, and
tWHAX timings added.
Table 25 updated, tWHQV removed, and tAVEH, tEHAX, tEHGL, tELKV, and tGHEL
added.
21-Jun-2005
0.5
tGHTZ added inTable 22: Asynchronous Read AC Characteristics and Table 23:
Synchronous Read AC Characteristics.
Burst frequency chagned from 54 to 52MHz.
85ns speed class removed.
tAVQV1 changed to 25ns.
29-Sep-2005
1.0
VIO maximum value updated in Table 17: Absolute Maximum Ratings.
tAVLH and tLLLH updated in Table 22: Asynchronous Read AC Characteristics.
tAVKH, tELKH and tLLKH updated in Table 23: Synchronous Read AC Characteristics.
tAVLH, tLLLH and tELLH updated in Table 24: Write AC Characteristics, Write Enable
Controlled and Table 25: Write AC Characteristics, Chip Enable Controlled.
97/98
M58LT128GST, M58LT128GSB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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98/98