AD ADSP-21375BSWZ-2B2 Sharc processor optimized for high performance audio processing Datasheet

SHARC Processor
ADSP-21371/ADSP-21375
SUMMARY
DEDICATED AUDIO COMPONENTS
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory, ADSP-21371—1M bits of on-chip SRAM
and 4M bits of on-chip mask-programmable ROM
On-chip memory, ADSP-21375—0.5M bits of on-chip
SRAM and 2M bits of on-chip mask-programmable ROM
ADSP-21371—S/PDIF-compatible digital audio
receiver/transmitter
ADSP-21371—8 dual data line serial ports that operate at up
to 50 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multiplier/divider ratios
Available in a 208-lead LQFP_EP package
Code compatible with all other members of the SHARC family
The ADSP-21371/ADSP-21375 processors are available with a
200/266 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Ordering Guide on Page 52.
Internal Memory
SIMD Core
Instruction
Cache
Block 0
RAM/ROM
Block 2
RAM
Block 3
RAM
5 stage
Sequencer
DAG1/2
Timer
PEx
PEy
B0D
64-BIT
S
PMD 64-BIT
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
DMD 64-BIT
DMD 64-BIT
FLAGx/IRQx/
TMREXP
Block 1
RAM/ROM
Core Bus
Cross Bar
Internal Memory I/F
PMD 64-BIT
IODO 32-BIT
EPD BUS 48-BIT
JTAG
PERIPHERAL BUS
32-BIT
IOD1
32-BIT
IOD0 BUS
MTM/
DTCP
PERIPHERAL BUS
CORE PCG
FLAGS C-D
TIMER
1-0
TWI
EP
SPI/B
UART
DPI Routing/Pins
PCG
A-D
S/PDIF IDP/ SPORT
Tx/Rx PDAP
7-0
7-0
DAI Routing/Pins
DPI Peripherals
DAI Peripherals
CORE PWM
FLAGS 3-0
AMI
SDRAM
External Port Pin MUX
Peripherals
External
Port
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.3113
© 2009 Analog Devices, Inc. All rights reserved.
ADSP-21371/ADSP-21375
TABLE OF CONTENTS
Summary ............................................................... 1
Maximum Power Dissipation ................................. 17
Dedicated Audio Components .................................... 1
Absolute Maximum Ratings ................................... 17
Revision History ...................................................... 2
ESD Sensitivity ................................................... 17
General Description ................................................. 3
Timing Specifications ........................................... 17
SHARC Family Core Architecture ............................ 4
Output Drive Currents ......................................... 45
Family Peripheral Architecture ................................ 6
Test Conditions .................................................. 45
I/O Processor Features ......................................... 10
Capacitive Loading .............................................. 45
System Design .................................................... 11
Thermal Characteristics ........................................ 46
Development Tools ............................................. 11
208-Lead LQFP_EP Pinout ....................................... 47
Additional Information ........................................ 12
Package Dimensions ............................................... 51
Pin Function Descriptions ....................................... 13
Automotive Products .............................................. 52
ADSP-21371/ADSP-21375 Specifications .................... 16
Ordering Guide ..................................................... 52
Operating Conditions .......................................... 16
Electrical Characteristics ....................................... 16
Package Information ........................................... 17
REVISION HISTORY
9/09—Rev. B to Rev. C
Corrected all outstanding document errata. Also replaced core
clock references (CCLK) in the timing specifications with
peripheral clock references (PCLK).
Added On-Chip Memory Bandwidth ............................ 5
Added External Port Throughput ................................. 8
Added operating conditions and electrical characteristics
for the 1.0 V, 200 MHz parts.
Added Input Data Port (IDP) ...................................... 9
For this revision the following sections have been removed. For
information see the ADSP-2137x SHARC Processor Hardware
Reference: “Address Data Pins as Flags”, “Address/Data Modes”,
Core Instruction Rate to CLKIN Ratio Modes.”
Added Scatter/Gather DMA .......................................11
Revised Figure 1, Functional Block Diagram ....................1
Corrected the pins names for the DAI and DPI in 208-Lead
LQFP_EP Pinout .....................................................47
Added Precision Clock Generator (PCG) ....................... 9
Added Table 2, ADSP-21371/ADSP-21375 Features ..........3
Added Figure 2, SHARC Core Block Diagram ..................4
Clarified VCO operations in
Voltage Controlled Oscillator .....................................18
Added Automotive Products ......................................52
Added Context Switch ...............................................5
Added Universal Registers ..........................................5
Added Timer ...........................................................5
Rev. C |
Page 2 of 52 |
September 2009
ADSP-21371/ADSP-21375
GENERAL DESCRIPTION
The ADSP-21371/ADSP-21375 SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x, and
ADSP-2116x DSPs, as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point processors optimized for high performance automotive audio
applications with their large on-chip SRAM and mask-programmable ROM, multiple internal buses to eliminate I/O
bottlenecks, and an innovative digital applications interface
(DAI).
Table 2. ADSP-21371/ADSP-21375 Features (Continued)
As shown in the functional block diagram on Page 1, the processors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the processors achieve an instruction
cycle time of 3.75 ns at 266 MHz. With its SIMD computational
hardware, the processors can perform 1.596 GFLOPS running
at 266 MHz.
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2137x processors. The core clock domain contains
the following features:
Table 1 shows performance benchmarks for these devices.
Table 2 shows the features of the individual product offerings.
Table 1. Processor Benchmarks (at 266 MHz)
Feature
ADSP-21371
ADSP-21375
Digital Peripheral
Interface (DPI)
Yes
Yes
S/PDIF Transceiver
Yes
No
SPI
2
2
TWI
Yes
Yes
Package
208-Lead LQFP_EP
208-Lead LQFP_EP
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core processor cycle
• One periodic interval timer with pinout
Speed
Benchmark Algorithm
(at 266 MHz)
1024 Point Complex FFT (Radix 4, With Reversal) 34.5 μs
FIR Filter (per Tap)1
1.88 ns
IIR Filter (per Biquad)1
7.5 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
16.91 ns
[4 × 4] × [4 × 1]
30.07 ns
Divide (y/x)
13.1 ns
Inverse Square Root
20.4 ns
1
Assumes two files in multichannel SIMD mode
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
ADSP-21375)
• On-chip mask-programmable ROM (4M bit, ADSP-21371;
2M bit, ADSP-21375)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user breakpoints which allow flexible exception handling.
The diagram on Page 1 also shows the peripheral clock domains
(also known as the I/O processor) and contains the following
features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
Table 2. ADSP-21371/ADSP-21375 Features
• Peripheral and external port bus for core connection
• Digital applications interface that includes four precision
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter, an input data port (IDP), eight
serial ports, eight serial interfaces, a 20-bit parallel input
port (PDAP), and a flexible signal routing unit (DAI SRU).
Feature
ADSP-21371
ADSP-21375
Frequency
266 MHz
(3.75 ns)
266 MHz
(3.75 ns)
RAM
1M bit
0.5M bit
ROM
4M bits
2M bits
Pulse-Width
Modulation
Yes
No
• Digital peripheral interface that includes two timers, one
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
Serial Ports
8
4
• External port with AMI and SDRAM controller
UART
1
1
• Four units for PWM control
Digital Application
Interface (DAI)
Yes
Yes
• One MTM for internal to internal memory transfers
Rev. C |
Page 3 of 52 |
September 2009
ADSP-21371/ADSP-21375
SHARC FAMILY CORE ARCHITECTURE
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
The ADSP-21371/ADSP-21375 processors are code compatible
at the assembly level with the ADSP-2136x, ADSP-2126x,
ADSP-21160x, and ADSP-21161N, and with the first generation
ADSP-2106x SHARC processors. The ADSP-21371/
ADSP-21375 processors share architectural features with the
ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC
processors, as shown in Figure 2 and detailed in the following
sections.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.
SIMD Computational Engine
The processors contain two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and
PEY, and each contains an ALU, multiplier, shifter, and register
file. PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing elements, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.
S
JTAG
FLAG
TIMER INTERRUPT CACHE
SIMD Core
PM ADDRESS 24
DMD/PMD 64
5 STAGE
PROGRAM SEQUENCER
PM DATA 48
DAG1
16x32
DAG2
16x32
PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
USTAT
4x32-BIT
PM DATA 64
PX
64-BIT
DM DATA 64
MULTIPLIER
MRF
80-BIT
SHIFTER
ALU
MRB
80-BIT
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ASTATx
ASTATy
STYKx
STYKy
ALU
Figure 2. SHARC Core Block Diagram
Rev. C |
Page 4 of 52 |
September 2009
SHIFTER
MULTIPLIER
MSB
80-BIT
MSF
80-BIT
ADSP-21371/ADSP-21375
Data Register File
Each processing element contains a general-purpose data register file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) register files,
combined with the SHARC’s enhanced Harvard architecture,
allow unconstrained data flow between computation units and
internal memory. The registers in PEX are referred to as
R0–R15 and in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result register all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Universal Registers
Universal registers can be used for general purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
The data bus exchange register PX permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM data bus. These registers contain hardware to handle the data width difference.
Timer
The processors contain a core timer that can generate periodic
software interrupts. The core timer can be configured to use
FLAG3 as a timer expired signal.
Single-Cycle Fetch of an Instruction and Four Operands
The processors feature an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 2). With the processor’s separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch four operands (two over each data bus)
and one instruction (from the cache), all in a single cycle.
Instruction Cache
The processors include an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract
in both processing elements while branching and fetching up to
four 32-bit values from memory—all in a single instruction.
On-Chip Memory
The ADSP-21371 processor contains 1 megabit of internal RAM
and four megabits of internal mask-programmable ROM (see
Table 3 on Page 6) and the ADSP-21375 processor contains 0.5
megabits of internal RAM and two megabits of internal maskprogrammable ROM (see Table 4 on Page 7). Each block can be
configured for different combinations of code and data storage.
Each memory block supports single-cycle, independent accesses
by the core processor and I/O processor. The processor’s memory architecture, in combination with its separate on-chip buses,
allow two data transfers from the core and one from the I/O
processor, in a single cycle.
The ADSP-21371 processor’s SRAM can be configured as a
maximum of 32k words of 32-bit data, 64k words of 16-bit data,
21.3k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 1 megabit. All of the memory
can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16bit floating-point storage format is supported that effectively
doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in
the cache.
On-Chip Memory Bandwidth
The internal memory architecture allows four accesses at the
same time to any of the four blocks, assuming no block conflicts. The total bandwidth is gained with DMD and PMD buses
(2 × 64-bits, core CLK) and the IOD0/1 buses (2 × 32-bit,
PCLK).
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
ROM-Based Security
The processors’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal
The processors have a ROM security feature that provides hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
Rev. C |
Page 5 of 52 |
September 2009
ADSP-21371/ADSP-21375
Table 3. ADSP-21371 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
Extended Precision Normal or
Instruction Word (48 bits)
Normal Word (32 bits)
Short Word (16 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
BLOCK 0 ROM
0x0008 0000–0x0008 AAA9
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0004 8000–0x0004 BFFF
Reserved
0x0008 AAAA–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
Reserved
0x0012 0000–0x0012 FFFF
BLOCK 0 RAM
0x0004 C000–0x0004 CFFF
BLOCK 0 RAM
0x0009 0000–0x0009 1554
BLOCK 0 RAM
0x0009 8000–0x0009 9FFF
BLOCK 0 RAM
0x0013 0000–0x0013 3FFF
Reserved
0x0004 D000–0x0004 FFFF
Reserved
0x0009 1555–0x0009 FFFF
Reserved
0x0009 A000–0x0009 FFFF
Reserved
0x0013 4000–0x0013 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
BLOCK 1 ROM
0x000A 0000–0x000A AAA9
BLOCK 1 ROM
0x000A 0000–0x000A FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0005 8000–0x0005 BFFF
Reserved
0x000A AAAA–0x000A FFFF
Reserved
0x000B 0000–0x000B 7FFF
Reserved
0x0016 0000–0x0016 FFFF
BLOCK 1 RAM
0x0005 C000–0x0005 CFFF
BLOCK 1 RAM
0x000B 0000–0x000B 1554
BLOCK 1 RAM
0x000B 8000–0x000B 9FFF
BLOCK 1 RAM
0x0017 0000–0x0017 3FFF
Reserved
0x0005 D000–0x0005 FFFF
Reserved
0x000B 1555–0x000B FFFF
Reserved
0x000B A000–0x000B FFFF
Reserved
0x0017 4000–0x0017 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 0FFF
BLOCK 2 RAM
0x000C 0000–0x000C 1554
BLOCK 2 RAM
0x000C 0000–0x000C 1FFF
BLOCK 2 RAM
0x0018 0000–0x0018 3FFF
Reserved
0x0006 1000–0x0006 FFFF
Reserved
0x000C 1555–0x000D FFFF
Reserved
0x000C 2000–0x000D FFFF
Reserved
0x0018 4000–0x001B FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 0FFF
BLOCK 3 RAM
0x000E 0000–0x000E 1554
BLOCK 3 RAM
0x000E 0000–0x000E 1FFF
BLOCK 3 RAM
0x001C 0000–0x001C 3FFF
Reserved
0x0007 1000–0x0007 FFFF
Reserved
0x000E 1555–0x000F FFFF
Reserved
0x000E 2000–0x000F FFFF
Reserved
0x001C 4000–0x001F FFFF
external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-21371/ADSP-21375 family contains a rich set of
peripherals that support a wide variety of applications, including high quality audio, medical imaging, communications,
military, test equipment, 3D graphics, speech recognition, monitor control, imaging, and other applications.
Rev. C |
Page 6 of 52 |
External Port
The external port on the ADSP-21371/ADSP-21375 SHARC
processors provide a high performance, glueless interface to a
wide variety of industry-standard memory devices. The 32-bit
wide bus (ADSP-21371) may be used to interface to synchronous and/or asynchronous memory devices through the use of
its separate internal memory controllers: the first is an SDRAM
controller for connection of industry-standard synchronous
DRAM devices and DIMMs (dual inline memory module),
while the second is an asynchronous memory controller
intended to interface to a variety of memory devices. Four
memory select pins enable up to four separate devices to coexist,
supporting any desired combination of synchronous and asynchronous device types.
September 2009
ADSP-21371/ADSP-21375
Table 4. ADSP-21375 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
Extended Precision Normal or
Instruction Word (48 bits)
Normal Word (32 bits)
Short Word (16 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 3FFF
BLOCK 0 ROM
0x0008 0000–0x0008 5554
BLOCK 0 ROM
0x0008 0000–0x0008 7FFF
BLOCK 0 ROM
0x0010 0000–0x0010 FFFF
Reserved
0x0004 4000–0x0004 BFFF
Reserved
0x0008 5555–0x0008 FFFF
Reserved
0x0008 8000–0x0009 7FFF
Reserved
0x0011 0000–0x0012 FFFF
BLOCK 0 RAM
0x0004 C000–0x0004 C7FF
BLOCK 0 RAM
0x0009 0000–0x0009 0AAA
BLOCK 0 RAM
0x0009 8000–0x0009 8FFF
BLOCK 0 RAM
0x0013 0000–0x0013 1FFF
Reserved
0x0004 C800–0x0004 FFFF
Reserved
0x0009 0AAB–0x0009 FFFF
Reserved
0x0009 9000–0x0009 FFFF
Reserved
0x0013 2000–0x0013 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 3FFF
BLOCK 1 ROM
0x000A 0000–0x000A 5554
BLOCK 1 ROM
0x000A 0000–0x000A 7FFF
BLOCK 1 ROM
0x0014 0000–0x0014 FFFF
Reserved
0x0005 4000–0x0005 BFFF
Reserved
0x000A 5555–0x000A FFFF
Reserved
0x000A 8000–0x000B 7FFF
Reserved
0x0015 0000–0x0016 FFFF
BLOCK 1 RAM
0x0005 C000–0x0005 C7FF
BLOCK 1 RAM
0x000B 0000–0x000B 0AAA
BLOCK 1 RAM
0x000B 8000–0x000B 8FFF
BLOCK 1 RAM
0x0017 0000–0x0017 1FFF
Reserved
0x0005 C800–0x0005 FFFF
Reserved
0x000B 0AAB–0x000B FFFF
Reserved
0x000B 9000–0x000B FFFF
Reserved
0x0017 2000–0x0017 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 07FF
BLOCK 2 RAM
0x000C 0000–0x000C 0AAA
BLOCK 2 RAM
0x000C 0000–0x000C 0FFF
BLOCK 2 RAM
0x0018 0000–0x0018 1FFF
Reserved
0x0006 0800–0x0006 FFFF
Reserved
0x000C 0AAB–0x000D FFFF
Reserved
0x000C 1000–0x000D FFFF
Reserved
0x0018 2000–0x001B FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 07FF
BLOCK 3 RAM
0x000E 0000–0x000E 0AAA
BLOCK 3 RAM
0x000E 0000–0x000E 0FFF
BLOCK 3 RAM
0x001C 0000–0x001C 1FFF
Reserved
0x0007 0800–0x0007 FFFF
Reserved
0x000E 0AAB–0x000F FFFF
Reserved
0x000E 1000–0x000F FFFF
Reserved
0x001C 2000–0x001F FFFF
Rev. C |
Page 7 of 52 |
September 2009
ADSP-21371/ADSP-21375
SDRAM Controller
External Port Throughput
The SDRAM controller provides an interface to up to four separate banks of industry-standard SDRAM devices or DIMMs.
Fully compliant with the SDRAM standard, each bank has its
own memory select line (MS0–MS3), and can be configured to
contain between 16M bytes and 256M bytes of memory.
SDRAM external memory address space is shown in Table 5.
The throughput for the external port, based on 133 MHz clock
and 32-bit data bus, is 177M bytes/s for the AMI and 532M
bytes/s for SDRAM.
The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single address
space, even if different size devices are used in the
different banks.
A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The
memory banks can be configured as 16 bits wide or as
32 bits wide. The SDRAM controller address, data, clock, and
command pins can drive loads up to 30 pF. For larger memory
systems, the SDRAM controller external buffer timing should
be selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
Size in Words
62M
64M
64M
64M
Address Range
0x0020 0000–0x03FF FFFF
0x0400 0000–0x07FF FFFF
0x0800 0000–0x0BFF FFFF
0x0C00 0000–0x0FFF FFFF
Note that the external memory bank addresses shown in Table 5
are for normal word accesses. If 48-bit instructions are placed in
any such bank (with two instructions packed into three 32-bit
locations), then care must be taken to map data buffers in the
same bank. For example, if 2k instructions are placed starting at
the bank 0 base address (0x0020 0000), then the data buffers can
be placed starting at an address that is offset by 3k words
(0x0020 0C00).
External Memory Code Execution
The program sequencer can execute code directly from external
memory bank 0 (SRAM, SDRAM) over the 48-bit external port
data bus (EPD). This allows a reduction in internal memory
size, thereby reducing the die area. With external execution,
programs run at slower speeds since 48-bit instructions are
fetched in parts from a 16-bit external bus coupled with the
inherent latency of fetching instructions from SDRAM. Fetching instructions from external memory generally takes 1.5
peripheral clock cycles per instruction. Non SDRAM external
memory address space is shown in Table 6.
Table 6. External Memory for Non SDRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in Words
14M
16M
16M
16M
Address Range
0x0020 0000–0x00FF FFFF
0x0400 0000–0x04FF FFFF
0x0800 0000–0x08FF FFFF
0x0C00 0000–0x0CFF FFFF
Rev. C |
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, flash, and EPROM,
as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 14.7M word window and banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit or 16-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to
high performance or to low cost and power.
Pulse-Width Modulation
Table 5. External Memory for SDRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Asynchronous Memory Controller
Page 8 of 52 |
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters.
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the processor’s DAI pins
(DAI_P1 to DAI_P20).
Programs make these connections using the signal routing unit
(SRU), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI
September 2009
ADSP-21371/ADSP-21375
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with nonconfigurable signal paths.
In the ADSP-21371, the DAI includes eight serial ports, four
precision clock generators (PCG), and an input data port (IDP).
For the ADSP-21375, the DAI includes four serial ports, four
precision clock generators (PCG) and an input data port (IDP).
The IDP provides an additional input path to the core of the
processor, configurable as either eight channels of I2S serial
data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is
independent from the processor’s serial ports.
Serial Ports
The processors feature eight synchronous serial ports on the
ADSP-21371 and four on the ADSP-21375. The SPORTs provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
For the ADSP-21371, serial ports are enabled via 16 programmable pins and simultaneous receive or transmit pins that
support up to 32 transmit or 32 receive channels of audio data
when all eight SPORTs are enabled, or eight duplex TDM
streams of 128 channels per frame.
For the ADSP-21375, serial ports are enabled via eight programmable pins and simultaneous receive or transmit pins that
support up to 16 transmit or 16 receive channels of audio data
when all four SPORTs are enabled, or four duplex TDM streams
of 128 channels per frame.
The serial ports operate at a maximum data rate of 50 Mbps.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in five modes:
• Standard DSP serial mode
• Multichannel (TDM) mode with support for packed I2S
mode
• I2S mode
• Packed I2S mode
• Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over various attributes of this mode.
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I2S channels (using two stereo
devices) per serial port, with a maximum of up to 32 I2S channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional μ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be internally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The ADSP-21371 S/PDIF receiver/transmitter has no separate
DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to
the receiver/transmitter can be formatted as left justified, I2S or
right justified with word widths of 16, 18, 20, or
24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
The ADSP-21375 does not have an S/PDIF-compatible digital
receiver/transmitter.
Input Data Port (IDP)
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I2S, left-justified sample pair, or right-justified
mode. One frame sync cycle indicates one 64-bit left/right pair,
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processor supports 24- and 32-bit I2S, 24and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats.
Precision Clock Generator (PCG)
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
Each of the serial ports supports the left-justified sample pair
and I2S protocols (I2S is an industry-standard interface commonly used by audio codecs, ADCs, and DACs such as the
Rev. C |
Page 9 of 52 |
September 2009
ADSP-21371/ADSP-21375
Digital Peripheral Interface (DPI)
Peripheral Timers
The digital peripheral interface provides connections to two
serial peripheral interface (SPI) ports, one universal asynchronous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers.
Two general-purpose timers can generate periodic interrupts
and be independently set to operate in one of three modes:
Serial Peripheral (Compatible) Interface
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
The ADSP-21371/ADSP-21375 SHARC processors contain two
serial peripheral interface ports (SPIs). The SPI is an industrystandard synchronous serial link, enabling the SPI-compatible
ports of the processors to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select
pin, and one clock pin. It is a full-duplex synchronous serial
interface, supporting both master and slave modes. The SPI port
can operate in a multimaster environment by interfacing with
up to four other SPI-compatible devices, either acting as a master or slave device.
The SPI-compatible peripheral implementation also features
programmable baud rates and clock phases and polarities. The
SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables the general-purpose timers
independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
• Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration
UART Port
• Digital filtering and timed event processing
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1
or 2 stop bits, and none, even, or odd parity. The UART port
supports two modes of operation:
• 7-bit addressing
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable. The port:
• Supports bit rates ranging from (fPCLK/1,048,576) to
(fPCLK/16) bits per second.
• Supports data formats from 7 to 12 bits per frame.
• Can be configured to generate maskable interrupts for both
transmit and receive operations.
In conjunction with the general-purpose timer functions, autobaud detection is supported.
Rev. C |
Page 10 of 52 |
• 100 kbps and 400 kbps data rates
• Low interrupt rate
I/O PROCESSOR FEATURES
The I/O processor provides many channels of DMA and controls the extensive set of peripherals described in the previous
sections.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur
between the ADSP-2137x processor’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
ports, the IDP (input data port), the parallel data acquisition
port (PDAP), or the UART (see Table 7).
Table 7. DMA Channels
Peripheral
SPORT
PDAP
SPI
UART
EP
MTM/DTCP
Total DMA Channels
September 2009
ADSP-21371
16
8
2
2
2
2
32
ADSP-21375
8
8
2
2
2
2
24
ADSP-21371/ADSP-21375
Delay Line DMA
DEVELOPMENT TOOLS
The processors provide delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(and hence to external memory) with limited core interaction.
The processors are supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21371/ADSP-21375.
Scatter/Gather DMA
The ADSP-2137x processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from noncontiguous memory blocks.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues. For complete system design
information, see the ADSP-2137x SHARC Processor Hardware
Reference.
Program Booting
The internal memory of the processor boots at system power-up
from an 8-bit EPROM via the external port, an SPI master, or an
SPI slave. Booting is determined by the boot configuration
(BOOT_CFG1–0) pins in Table 8. Selection of the boot source
is controlled via the SPI as either a master or slave device, or it
can immediately begin executing from ROM.
Table 8. Boot Mode Selection
BOOT_CFG1–0
00
01
10
11
Booting Mode
SPI Slave Boot
SPI Master Boot
EPROM/FLASH Boot
Reserved
The “Running Reset” feature allows programs to perform a reset
of the processor core and peripherals, but without resetting the
PLL and SDRAM controller, or performing a boot. The
RESETOUT pin acts as the input for initiating a running reset.
Power Supplies
The processors have separate power supply connections for the
internal (VDDINT), and external (VDDEXT) power supplies. The
internal supplies must meet the 1.2 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same power supply.
Target Board JTAG Emulator Connector
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC processor has architectural features that improve the efficiency of
compiled C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation.
Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and
modification of memory, registers, and processor stacks. The
processor’s JTAG interface ensures that the emulator will not
affect target system loading
or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User’s Guide”.
Rev. C |
Page 11 of 52 |
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
September 2009
ADSP-21371/ADSP-21375
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Definition File (LDF), allowing the developer to move between the
graphical and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family.
Hardware tools include SHARC processor PC plug-in cards.
Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the processor’s
architecture and functionality. For detailed information on the
core architecture and instruction set, refer to the ADSP-2137x
SHARC Processor Hardware Reference.
Designing an Emulator-Compatible DSP Board (Target)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices
Rev. C |
Page 12 of 52 |
September 2009
ADSP-21371/ADSP-21375
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 9:
A = asynchronous, I = input, O = output, S = synchronous,
(A/D) = active drive, (O/D) = open drain, and T = three-state,
(pd) = pull-down resistor, (pu) = pull-up resistor.
Table 9. Pin Descriptions
State During
and After
Reset
Description
Name
Type
ADDR23–0
O/T (pu)
Pulled high/
driven low
External Address. The processor outputs addresses for external memory and peripherals on these pins.
DATA31–0
I/O (pu)
Pulled high/
pulled high
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After
reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the external port
data pins for parallel input data. PDAP over 16-bit external port DATA is not supported
on the ADSP-21375 processor.
DAI _P20–1
I/O with
programmable
(pu)1
Pulled high/
pulled high
Digital Applications Interface Pins. These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determine the exact behavior of
the pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module
(ADSP-21371), IDP (2), and the PCGs (4), to the DAI_P20–1 pins. Pullups can be disabled
via the DAI_PIN_PULLUP register.
DPI _P14–1
I/O with
programmable
(pu)1
Pulled high/
pulled high
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and generalpurpose I/O (9) to the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP
register.
ACK
I (pu)
RD
O/T (pu)
Pulled high/
driven high
External Port Read Enable. RD is asserted whenever the processor reads a word from
external memory. RD has a 22.5 kΩ internal pull-up resistor.
WR
O/T (pu)
Pulled high/
driven high
External Port Write Enable. WR is asserted when the processor writes a word to
external memory. WR has a 22.5 kΩ internal pull-up resistor.
SDRAS
O/T (pu)
Pulled high/
driven high
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
O/T (pu)
Pulled high/
driven high
SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE
O/T (pu)
Pulled high/
driven high
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access.
Rev. C |
Page 13 of 52 |
September 2009
ADSP-21371/ADSP-21375
Table 9. Pin Descriptions (Continued)
State During
and After
Reset
Description
Name
Type
SDCKE
O/T (pu)
Pulled high/
driven high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDA10
O/T (pu)
Pulled high/
driven low
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a nonSDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDCLK
O/T
High-Z/driving
SDRAM Clock.
MS0–1
O/T (pu)
Pulled high/
driven high
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS3-0 lines are decoded memory address lines
that change at the same time as the other address lines. When no external memory
access is occurring the MS3-0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the
ADSP-2137x SHARC Processor Hardware Reference.
FLAG[0]/IRQ0
I/O
FLAG[0] INPUT
FLAG0/Interrupt Request0.
FLAG[1]/IRQ1
I/O
FLAG[1] INPUT
FLAG1/Interrupt Request1.
FLAG[2]/IRQ2/
MS2
I/O with
programmable pu
(for MS mode)
FLAG[2] INPUT
FLAG2/Interrupt Request/Memory Select2.
FLAG[3]/
TMREXP/ MS3
I/O with
programmable pu
(for MS mode)
FLAG[3] INPUT
FLAG3/Timer Expired/Memory Select3.
TDI
I (pu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 kΩ internal pull-up resistor.
TDO
O/T
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
I (pu)
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processor.
TRST
I (pu)
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor. TRST has a 22.5 kΩ
internal pull-up resistor.
EMU
O/T (pu)
Emulation Status. Must be connected to the processor. Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ internal
pull-up resistor.
CLK_CFG1–0
I
Core to CLKIN Ratio Control. These pins set the start up clock frequency. See the
ADSP-2137x SHARC Processor Hardware Reference for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
BOOT_CFG1–0
I
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOT_CFG pins must be valid before reset is asserted. See the ADSP-2137x SHARC
Processor Hardware Reference for information about boot modes.
Rev. C |
Page 14 of 52 |
September 2009
ADSP-21371/ADSP-21375
Table 9. Pin Descriptions (Continued)
1
State During
and After
Reset
Name
Type
Description
RESET
I
Processor Reset. Resets the processor to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
XTAL
O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
CLKIN
I
Local Clock In. Used in conjunction with XTAL. CLKIN is the processor clock input. It
configures the processor to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use the external clock source such as an external
clock oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
RESETOUT/
RUNRSTIN
I/O (pu)
Reset Out/Running Reset In. The default setting is reset out. This pin also has a second
function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register. For
more information, see the ADSP-2137x SHARC Processor Hardware Reference.
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Rev. C |
Page 15 of 52 |
September 2009
ADSP-21371/ADSP-21375
ADSP-21371/ADSP-21375 SPECIFICATIONS
OPERATING CONDITIONS
1.0 V, 200 MHz
Parameter1 Description
VDDINT
VDDEXT
VIH2
VIL2
VIH_CLKIN3
VIL_CLKIN3
TJUNCTION
TAMBIENT
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
High Level Input Voltage @ VDDEXT = max
Low Level Input Voltage @ VDDEXT = min
High Level Input Voltage @ VDDEXT = max
Low Level Input Voltage @ VDDEXT = min
Junction Temperature 208-Lead LQFP_EP @ TAMBIENT 0ºC to +70ºC
Ambient Temperature 208-Lead LQFP_EP @ TAMBIENT 0ºC to +70ºC
1.2 V, 266 MHz
Min
Max
Min
Max
Unit
0.95
3.13
2.0
–0.5
1.74
–0.5
0
–40
1.05
3.47
VDDEXT + 0.5
+0.8
VDDEXT + 0.5
+1.10
115
105
1.14
3.13
2.0
–0.5
1.74
–0.5
0
–40
1.26
3.47
VDDEXT + 0.5
+0.8
VDDEXT + 0.5
+1.10
115
105
V
V
V
V
V
V
ºC
ºC
1
Specifications subject to change without notice.
Applies to input and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOT_CFGx, CLKCFGx, RUNRSTIN,
RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
2
ELECTRICAL CHARACTERISTICS
1.0 V, 200 MHz
Parameter1 Description
Test Conditions
Min
VOH2
VOL2
IIH4, 5
IIL4
IILPU5
@ VDDEXT = min, IOH = –1.0 mA3
@ VDDEXT = min, IOL = 1.0 mA3
@ VDDEXT = max, VIN = VDDEXT max
@ VDDEXT = max, VIN = 0 V
@ VDDEXT = max, VIN = 0 V
2.4
IOZH6, 7
IOZL6
IOZLPU7
IDD-INTYP8, 9
10, 11
CIN
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current
Pull-up
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Pull-up
Supply Current (Internal)
Input Capacitance
Typ
1
Min
Typ
Max
Unit
0.4
10
10
200
0.4
10
10
200
V
V
μA
μA
μA
10
10
200
10
10
200
μA
μA
μA
2.4
@ VDDEXT = max, VIN = VDDEXT max
@ VDDEXT= max, VIN = 0 V
@ VDDEXT= max, VIN = 0 V
1.0V, 200 MHz: tCCLK = 5.00 ns,
VDDINT = 1.0 V, 25ºC
1.2V, 266 MHz: tCCLK = 3.75 ns,
VDDINT = 1.2 V, 25ºC
fIN = 1 MHz, TCASE = 25°C, VIN= 1.2 V
Max
1.2 V, 266 MHz
400
mA
600
4.7
mA
4.7
pF
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), RD, WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, SDRAS, SDCAS, SDWE,
SDCKE, SDA10, and SDCLK.
3
See Output Drive Currents on Page 45 for typical drive current capabilities.
4
Applies to input pins: BOOT_CFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 kΩ pull-ups: DAI_Px, DPI_Px, EMU.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for further information.
10
Applies to all signal pins.
11
Guaranteed, but not tested.
Rev. C |
Page 16 of 52 |
September 2009
ADSP-21371/ADSP-21375
PACKAGE INFORMATION
Table 11. Absolute Maximum Ratings (Continued)
The information presented in Figure 3 provides details about
the package branding for the ADSP-21371/ADSP-21375 processor. For a complete listing of product availability, see Ordering
Guide on Page 52.
Parameter
Load Capacitance
Storage Temperature Range
Junction Temperature under Bias
Rating
200 pF
–65°C to +150°C
125°C
ESD SENSITIVITY
a
ADSP-2137x
ESD (electrostatic discharge) sensitive device.
tppZ-cc
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
vvvvvv.x n.n
yyww country_of_origin
S
Figure 3. Typical Package Brand
TIMING SPECIFICATIONS
Table 10. Package Brand Information
Brand Key
t
pp
Z
ccc
vvvvvv.x
n.n
yyww
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 37 on Page 45 under Test Conditions for voltage reference levels.
Field Description
Temperature Range
Package Type
RoHS Compliant Part
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
MAXIMUM POWER DISSIPATION
See Engineer-to-Engineer Note “Estimating Power Dissipation
for ADSP-2137x SHARC Processors” (EE-318) for detailed
thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see
Thermal Characteristics on Page 46.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 11 may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 11. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage –0.5 V to VDDEXT
Output Voltage Swing –0.5 V to VDDEXT
Rating
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+0.5 V
+0.5 V
Rev. C |
Page 17 of 52 |
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 4). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
September 2009
ADSP-21371/ADSP-21375
Voltage Controlled Oscillator
fINPUT = CLKIN when the input divider is disabled or
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
fVCO specified in Table 14.
fINPUT = CLKIN ÷ 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 12. All
of the timing specifications for the ADSP-2137x peripherals are
defined in relation to tPCLK. See the peripheral specific section
for each peripheral’s timing information.
• The product of CLKIN and PLLM must never exceed 1/2
fVCO (max) in Table 14 if the input divider is not enabled
(INDIV = 0).
• The product of CLKIN and PLLM must never exceed fVCO
(max) in Table 14 if the input divider is enabled
(INDIV = 1).
Table 12. Clock Periods
Timing
Requirements
tCK
tCCLK
tPCLK
The VCO frequency is calculated as follows:
fVCO = 2 × PLLM × fINPUT
fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLD)
where:
fVCO = VCO output
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × tCCLK
Figure 4 shows core to CLKIN relationships with external oscillator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2137x SHARC Processor Hardware Reference.
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
fINPUT = Input frequency to the PLL.
PMCTL
(SDCKR)
PMCTL
(PLLBP)
CLKIN
DIVIDER
fINPUT
fVCO
LOOP
FILTER
VCO
PLL
DIVIDER
fCCLK
XTAL
CCLK
SDRAM
DIVIDER
BYPASS
MUX
CLKIN
BYPASS
MUX
PLL
PMCTL
(2xPLLD)
BUF
PMCTL
(INDIV)
PLL
MULTIPLIER
DIVIDE
BY 2
PMCTL
(PLLBP)
SDCLK
PCLK
PCLK
CLK_CFGx/PMCTL (2xPLLM)
CCLK
RESET
DELAY OF
4096 CLKIN
CYCLES
PIN MUX
CLKOUT (TEST ONLY)
RESETOUT
BUF
RESETOUT
CORERST
Figure 4. Core Clock and System Clock Relationship to CLKIN
Rev. C |
Page 18 of 52 |
September 2009
ADSP-21371/ADSP-21375
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 13.
Note that during power-up, a leakage current of approximately
200 μA may be observed on the RESET pin. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Table 13. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing Requirements
tRSTVDD
RESET Low Before VDDINT/VDDEXT On
tIVDDEVDD
VDDINT on Before VDDEXT
1
tCLKVDD
CLKIN Valid After VDDINT/VDDEXT Valid
tCLKRST
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
tPLLRST
Switching Characteristic
tCORERST
Core Reset Deasserted After RESET Deasserted
Min
Max
0
–50
0
102
203
+200
200
Unit
ns
ms
ms
μs
μs
4096 × tCK + 2 × tCCLK 4, 5
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on tSRST specification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
RESET
VDDINT
tRSTVDD
tIVDDEVDD
VDDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1–0
tPLLRST
tCORERST
RESETOUT
Figure 5. Power-Up Sequencing
Rev. C |
Page 19 of 52 |
September 2009
ADSP-21371/ADSP-21375
Clock Input
Table 14. Clock Input
Min
Parameter
Timing Requirements
tCK
tCKL
tCKH
tCKRF
tCCLK2
fVCO
1
2
22.51
11.251
11.251
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
VCO Frequency
3.75
200
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
tCK
CLKIN
tCKH
tCKL
Figure 6. Clock Input
Clock Signals
The processor can use an external clock or a crystal. See the
CLKIN pin description in Table 9. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 7 shows the
component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a 16.67
MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN
achieves a clock speed of 266 MHz). To achieve the full core
clock rate, programs need to configure the multiplier bits in the
PMCTL register.
ADSP-2137x
R1
1M⍀*
CLKIN
XTAL
R2
47⍀*
C1
22pF
Y1
C2
22pF
16.67 MHz
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Figure 7. 266 MHz Operation (Fundamental Mode Crystal)
Rev. C |
Page 20 of 52 |
September 2009
266 MHz
Max
100
45
45
6
10
800
Unit
ns
ns
ns
ns
ns
MHz
ADSP-21371/ADSP-21375
Reset
Table 15. Reset
Parameter
Timing Requirements
tWRST1
RESET Pulse Width Low
tSRST
RESET Setup Before CLKIN Low
1
Min
Max
4 × tCK
8
Unit
ns
ns
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tWRST
tSRST
RESET
Figure 8. Reset
Running Reset
The following timing specification applies to
RESETOUT/RUNRSTIN pin when it is configured as
RUNRSTIN.
Table 16. Running Reset
Parameter
Timing Requirements
tWRUNRST
Running RESET Pulse Width Low
tSRUNRST
Running RESET Setup Before CLKIN High
Min
Max
4 × tCK
8
CLKIN
tWRUNRST
tSRUNRST
RUNRSTIN
Figure 9. Running Reset
Rev. C |
Page 21 of 52 |
September 2009
Unit
ns
ns
ADSP-21371/ADSP-21375
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (TMREXP pin).
Table 17. Core Timer
Parameter
Switching Characteristic
tWCTIM
TMREXP Pulse Width
Min
Max
4 × tPCLK – 1
FLAG3
(TMREXP)
Unit
ns
tWCTIM
Figure 10. Core Timer
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts as well as the DAI_P20–1 and
DPI_P14–1 pins when they are configured as interrupts.
Table 18. Interrupts
Parameter
Timing Requirement
tIPW
IRQx Pulse Width
Min
2 × tPCLK +2
DAI_P20–1
DPI_P14–1
FLAG2–0
(IRQ2–0)
tIPW
Figure 11. Interrupts
Rev. C |
Page 22 of 52 |
September 2009
Max
Unit
ns
ADSP-21371/ADSP-21375
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0 and
Timer1 in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DPI_P14–1 pins through the DPI SRU.
Therefore, the specifications provided below are valid at the
DPI_P14–1 pins.
Table 19. Timer PWM_OUT Timing
Parameter
Switching Characteristic
tPWMO
Timer Pulse Width Output
Min
Max
Unit
2 × tPCLK – 2
2 × (231 – 1) × tPCLK
ns
tPWMO
DPI_P14–1
(TIMER1–0)
Figure 12. Timer PWM_OUT Timing
Timer WDTH_CAP Timing
The following timing specification applies to Timer0 and
Timer1 in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the specifications provided below are valid at
the DPI_P14–1 pins.
Table 20. Timer Width Capture Timing
Parameter
Timing Requirement
tPWI
Timer Pulse Width
Min
Max
Unit
2 × tPCLK
2 × (231– 1) × tPCLK
ns
tPWI
DPI_P14–1
(TIMER1–0)
Figure 13. Timer Width Capture Timing
Rev. C |
Page 23 of 52 |
September 2009
ADSP-21371/ADSP-21375
Pin to Pin Direct Routing (DAI and DPI)
For direct pin connections only (for example, DAI_PB01_I to
DAI_PB02_O).
Table 21. DAI/DPI Pin to Pin Routing
Parameter
Timing Requirement
tDPIO
Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid
Min
Max
Unit
1.5
10
ns
DAI_Pn
DPI_Pn
DAI_Pm
DPI_Pm
tDPIO
Figure 14. DAI/DPI Pin to Pin Direct Routing
Rev. C |
Page 24 of 52 |
September 2009
ADSP-21371/ADSP-21375
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins
(DAI_P01 through DAI_P20).
Table 22. Precision Clock Generator (Direct Pin Routing)
1.2 V, 266 MHz
Parameter
Min
Max
Unit
Timing Requirements
tPCGIP
Input Clock Period
tPCLK × 4
ns
PCG Trigger Setup Before Falling Edge of PCG 4.5
ns
tSTRIG
Input Clock
tHTRIG
PCG Trigger Hold After Falling Edge of PCG 3
ns
Input Clock
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active
Edge Delay After PCG Input Clock
2.5
10
ns
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger 2.5 + ((2.5) × tPCGIW)
10 + ((2.5) × tPCGIW)
ns
tDTRIGFS
PCG Frame Sync Delay After PCG Trigger
2.5 + ((2.5 + D – PH) × tPCGIW) 10 + ((2.5 + D – PH) × tPCGIW) ns
Output Clock Period
2 × tPCGIW – 1
ns
tPCGOW1
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Generators”
chapter.
1
Normal mode of operation.
tSTRIG
tHTRIG
DAI_Pn
DPI_Pn
PCG_TRIGx_I
tPCGIW
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
tDPCGIO
DAI_Py
DPI_Py
PCG_CLKx_O
tDTRIGCLK
tDPCGIO
DAI_Pz
DPI_Pz
PCG_FSx_O
tDTRIGFS
Figure 15. Precision Clock Generator (Direct Pin Routing)
Rev. C |
Page 25 of 52 |
September 2009
tPCGOW
ADSP-21371/ADSP-21375
Flags
The timing specifications provided below apply to the FLAG3–0
and DPI_P14–1 pins, and the DATA31–0 pins. See Table 9 on
Page 13 for more information on flag use.
Table 23. Flags
Parameter
Timing Requirement
DPI_P14–1, DATA31–0, FLAG3–0 IN Pulse Width
tFIPW
Switching Characteristic
tFOPW
DPI_P14–1, DATA31–0, FLAG3–0 OUT Pulse Width
Min
ns
2 × tPCLK – 2
ns
tFIPW
DPI_P14–1
(FLAG3–0OUT)
(DATA31–0)
tFOPW
Figure 16. Flags
Page 26 of 52 |
Unit
2 × tPCLK + 3
DPI_P14–1
(FLAG3–0IN)
(DATA31–0)
Rev. C |
Max
September 2009
ADSP-21371/ADSP-21375
SDRAM Interface Timing
Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK.
Table 24. SDRAM Interface Timing1
Parameter
Timing Requirements
tSSDAT
DATA Setup Before SDCLK
DATA Hold After SDCLK
tHSDAT
Switching Characteristics
tSDCLK
SDCLK Period
tSDCLKH
SDCLK Width High
tSDCLKL
SDCLK Width Low
tDCAD
Command, ADDR, Data Delay After SDCLK2
Command, ADDR, Data Hold After SDCLK2
tHCAD
tDSDAT
Data Disable After SDCLK
tENSDAT
Data Enable After SDCLK
1
2
Min
1.2 V, 266 MHz
Max
0.58
2.2
ns
ns
7.5
3
3
ns
ns
ns
ns
ns
ns
ns
5.3
1.3
5.3
1.6
For FCCLK = 133 MHz (SDCLK ratio = 1:2).
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
tSDCLKH
tSDCLK
SDCLK
tSSDAT
tSDCLKL
tHSDAT
DATA (IN)
tDCAD
tENSDAT
tDCAD
CMND ADDR
(OUT)
tHCAD
Figure 17. SDRAM Interface Timing for 133 MHz SDCLK
Page 27 of 52 |
tDSDAT
tHCAD
DATA (OUT)
Rev. C |
Unit
September 2009
ADSP-21371/ADSP-21375
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read—Bus Master
1.2 V, 266 MHz
Max
Parameter
Min
Timing Requirements
tDAD
Address, Selects Delay to Data Valid1, 2
tDRLD
RD Low to Data Valid1
tSDS
Data Setup to RD High
2.2
tHDRH
Data Hold from RD High3, 4
0
2, 5
tDAAK
ACK Delay from Address, Selects
tDSAK
ACK Delay from RD Low4
Switching Characteristics
tDRHA
Address Selects Hold After RD High
RHC + 0.38
tDARL
Address Selects to RD Low2
tSDCLK – 3.3
tRW
RD Pulse Width
W – 1.4
tRWR
RD High to WR, RD, Low
HI + tSDCLK – 0.8
W = (number of wait states specified in AMICTLx register) × tSDCLK
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) × tSDCLK
IC = (number of idle cycles specified in AMICTLx register) × tSDCLK)
H = (number of hold cycles specified in AMICTLx register) × tSDCLK
Unit
W + tSDCLK – 5.12
W–3
tSCDCLK – 10. + W
W – 7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Data delay/setup: System must meet tDAD, tDRLD, or tSDS.
The falling edge of MSx, is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
4
Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 45 for the calculation of hold times given capacitive and dc loads.
5
ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.
2
ADDR
MSx
tDARL
tRW
tDRHA
RD
tDRLD
tSDS
tDAD
tHDRH
DATA
tRWR
tDSAK
tDAAK
ACK
WR
Figure 18. Memory Read—Bus Master
Rev. C |
Page 28 of 52 |
September 2009
ADSP-21371/ADSP-21375
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 26. Memory Write—Bus Master
1.2 V, 266 MHz
Parameter
Min
Max
Unit
Timing Requirements
tDAAK
ACK Delay from Address, Selects1, 2
tSDCLK – 10.1 + W
ns
tDSAK
ACK Delay from WR Low 1, 3
W – 7.1
ns
Switching Characteristics
tDAWH
Address, Selects to WR Deasserted2
tSDCLK – 3.6 + W
ns
tDAWL
Address, Selects to WR Low2
tSDCLK – 2.7
ns
WR Pulse Width
W – 1.3
ns
tWW
tDDWH
Data Setup Before WR High
tSDCLK – 3.0 + W
ns
tDWHA
Address Hold After WR Deasserted
H + 0.15
ns
tDWHD
Data Hold After WR Deasserted
H + 0.02
ns
tDATRWH
Data Disable After WR Deasserted4
tSDCLK – 1.37 + H
tSDCLK + 4.9+ H
ns
tWWR
WR High to WR, RD Low
tSDCLK – 1.5+ H
ns
Data Disable Before RD Low
2tSDCLK – 5.1
ns
tDDWR
tWDE
WR Low to Data Enabled
tSDCLK – 4.1
ns
W = (number of wait states specified in AMICTLx register) × tSDCLK, H = (number of hold cycles specified in AMICTLx register) × tSDCLK
1
ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 45 for calculation of hold times given capacitive and dc loads.
2
ADDR
MSx
tDWHA
tDAWH
tDAWL
tWW
WR
tWWR
tWDE
tDATRWH
tDDWH
DATA
tDSAK
tDWHD
tDAAK
ACK
RD
Figure 19. Memory Write—Bus Master
Rev. C |
Page 29 of 52 |
September 2009
tDDWR
ADSP-21371/ADSP-21375
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
1
tHFSE
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
1
tSDRE
Receive Data Setup Before Receive SCLK
tHDRE1
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Switching Characteristics
tDFSE2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
tHOFSE2
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in either Transmit or Receive Mode)
tDDTE2
Transmit Data Delay After Transmit SCLK
2
tHDTE
Transmit Data Hold After Transmit SCLK
1.2 V, 266 MHz
Max
Min
Unit
2.5
ns
2.5
2.5
2.5
(tPCLK × 4) ÷ 2 – 0.5
tPCLK × 4
ns
ns
ns
ns
ns
10.5
ns
11
ns
ns
ns
2
2
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 28. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
tHFSI1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit or Receive Mode)
Receive Data Setup Before SCLK
tSDRI1
tHDRI1
Receive Data Hold After SCLK
Switching Characteristics
tDFSI2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
tHOFSI2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode)
2
tDFSIR
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)
tHOFSIR2
tDDTI2
Transmit Data Delay After SCLK
2
tHDTI
Transmit Data Hold After SCLK
tSCKLIW3
Transmit or Receive SCLK Width
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
Minimum SPORT divisor register value.
Rev. C |
Page 30 of 52 |
September 2009
Min
1.2 V, 266 MHz
Max
Unit
7
ns
2.5
7
2.5
ns
ns
ns
4
–1.0
10.7
–1.0
3.6
–1.0
0.5tPCLK – 2
0.5tPCLK + 2
ns
ns
ns
ns
ns
ns
ns
ADSP-21371/ADSP-21375
Table 29. Serial Ports—Enable and Three-State
1.2 V, 266 MHz
Min
Max
Unit
Parameter
Switching Characteristics
tDDTEN1
Data Enable from External Transmit SCLK
tDDTTE1
Data Disable from External Transmit SCLK
1
tDDTIN
Data Enable from Internal Transmit SCLK
1
2
10
–1
ns
ns
ns
Referenced to drive edge.
Table 30. Serial Ports—External Late Frame Sync
Parameter
Switching Characteristics
tDDTLFSE1
Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with
MCE = 1, MFD = 0
tDDTENFS1
Data Enable for MCE = 1, MFD = 0
1
The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
Rev. C |
Page 31 of 52 |
September 2009
1.2 V, 266 MHz
Min
Max
Unit
10
0.5
ns
ns
ADSP-21371/ADSP-21375
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
tHFSE/I
tSFSE/I
DAI_P20–1
(FRAME SYNC)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL
A/B)
2ND BIT
1ST BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
tSFSE/I
tHFSE/I
DAI_P20–1
(FRAME SYNC)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL
A/B)
2ND BIT
1ST BIT
tDDTLFSE
NOTES
1. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20–1 PINS.
THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND
FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU.
Figure 20. External Late Frame Sync1
1
This figure reflects changes made to support left-justified sample pair mode.
Rev. C |
Page 32 of 52 |
September 2009
ADSP-21371/ADSP-21375
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
DATA RECEIVE—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK)
SAMPLE EDGE
tSCLKW
DAI_P20–1
(SCLK)
tDFSIR
tDFSE
tSFSI
tHOFSIR
tHFSI
DAI_P20–1
(FRAME SYNC)
tSFSE
tHFSE
tSDRE
tHDRE
tHOFSE
DAI_P20–1
(FRAME SYNC)
tSDRI
tHDRI
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(DATA
CHANNEL A/B)
NOTES
1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK)
tSCLKW
SAMPLE EDGE
DAI_P20–1
(SCLK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
DAI_P20–1
(SCLK)
tHOFSE
tSFSE
tHFSE
DAI_P20–1
(FRAME SYNC)
tDDTI
tHDTI
tHDTE
DAI_P20–1
(DATA
CHANNEL A/B)
tDDTE
DAI_P20–1
(DATA
CHANNEL A/B)
NOTES
1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK, EXT)
SCLK
tDDTEN
tDDTTE
DAI_P20–1
(FRAME SYNC)
DRIVE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
tDDTIN
Figure 21. Serial Ports
Rev. C |
Page 33 of 52 |
September 2009
ADSP-21371/ADSP-21375
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 31. IDP
signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 31. Input Data Port (IDP)
Parameter
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
tSIHFS1
tSISD1
Data Setup Before Serial Clock Rising Edge
1
tSIHD
Data Hold After Serial Clock Rising Edge
tIDPCLKW
Clock Width
tIDPCLK
Clock Period
1
Min
1.2 V, 266 MHz
Max
3.8
2.5
2.5
2.5
(tPCLK × 4) ÷ 2 – 1
tPCLK × 4
Unit
ns
ns
ns
ns
ns
ns
The data, serial clock, and frame sync signals can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either
CLKIN or any of the DAI pins.
SAMPLE EDGE
tIPDCLK
tIPDCLKW
DAI_P20–1
(SERIAL CLOCK)
tSISFS
tSIHFS
DAI_P20–1
(FRAME SYNC)
tSISD
tSIHD
DAI_P20–1
(DATA)
Figure 22. IDP Master Timing
Rev. C |
Page 34 of 52 |
September 2009
ADSP-21371/ADSP-21375
Note that the 20-bits of external PDAP data can be provided
through the external port DATA31–12 pins. On the
ADSP-21375 processors, PDAP can not be multiplexed on the
external port (since only DATA15–0). Use the SRU DAI
instead.
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 32. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-2137x SHARC Processor Hardware
Reference.
Table 32. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
tSPCLKEN1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
tHPCLKEN1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
tPDSD1
PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge
tPDHD1
PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge
Clock Width
tPDCLKW
tPDCLK
Clock Period
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
tPDSTRIB
PDAP Strobe Pulse Width
1
Min
ns
ns
ns
ns
ns
ns
2 × tPCLK + 3
2 × tPCLK – 1
ns
ns
tPDCLK
tPDCLKW
DAI_P20–1
(PDAP_CLK)
tSPCLKEN
tHPCLKEN
DAI_P20–1
(PDAP_CLKEN)
tPDSD
tPDHD
DATA
DAI_P20–1
(PDAP_STROBE)
tPDHLDD
Figure 23. PDAP Timing
Rev. C |
Page 35 of 52 |
September 2009
Unit
2.5
2.5
3.85
2.5
(tPCLK × 4) ÷ 2 – 3
tPCLK × 4
Data source pins are DATA31–12 or DAI pins. Source pins for serial clock and frame sync are: 1) DATA11–10 pins, 2) DAI pins
SAMPLE EDGE
Max
tPDSTRB
ADSP-21371/ADSP-21375
Pulse-width modulation generator information does not apply
to the ADSP-21375.
Pulse-Width Modulation Generators (PWM)
For the ADSP-21371, the following timing specifications apply
when the DATA31–16 pins are configured as PWM.
Table 33. Pulse-Width Modulation (PWM) Timing
Parameter
Switching Characteristics
tPWMW
PWM Output Pulse Width
tPWMP
PWM Output Period
Min
Max
Unit
tPCLK – 2.5
2 × tPCLK – 2.5
(216 – 2) × tPCLK – 2.5
(216 – 1) × tPCLK – 2.5
ns
ns
tPWMW
PWM
OUTPUTS
tPWMP
Figure 24. PWM Timing
Rev. C |
Page 36 of 52 |
September 2009
ADSP-21371/ADSP-21375
output mode) from an LRCLK transition, so that when there are
64 serial clock periods per LRCLK period, the LSB of the data
will be right-justified to the next LRCLK transition.
S/PDIF Transmitter
For the ADSP-21371, serial data input to the S/PDIF transmitter
can be formatted as left-justified, I2S, or right-justified with
word widths of 16-, 18-, 20-, or 24-bits. The following sections
provide timing for the transmitter.
S/PDIF transmitter information does not apply to the
ADSP-21375.
Figure 26 shows the default I2S-justified mode. LRCLK is low
for the left channel and high for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to an
LRCLK transition but with a single serial clock period delay.
S/PDIF Transmitter-Serial Input Waveforms
Figure 25 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit
DAI_P20–1
LRCLK
Figure 27 shows the left-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no MSB delay.
RIGHT CHANNEL
LEFT CHANNEL
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LSB + 1
MSB – 2
LSB
MSB – 1
LSB + 1
MSB – 2
LSB
MSB
MSB
LSB + 2
LSB
MSB – 1
LSB + 2
Figure 25. Right-Justified Mode
RIGHT CHANNEL
DAI_P20–1
LRCLK
LEFT CHANNEL
DAI_P20–1
SCLK
MSB – 2
DAI_P20–1
SDATA
MSB – 1
MSB – 2
LSB + 1
LSB + 1
MSB
LSB
MSB
LSB + 2
MSB – 1
LSB
MSB
LSB + 2
Figure 26. I2S-Justified Mode
DAI_P20–1
LRCLK
RIGHT CHANNEL
LEFT CHANNEL
DAI_P20–1
SCLK
DAI_P20–1
SDATA
MSB – 2
MSB – 1
MSB – 2
LSB + 1
MSB
LSB
LSB + 1
MSB
LSB + 2
LSB
MSB – 1
Figure 27. Left-Justified Mode
Rev. C |
Page 37 of 52 |
September 2009
LSB + 2
MSB
MSB + 1
ADSP-21371/ADSP-21375
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 34. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 34. S/PDIF Transmitter Input Data Timing
Parameter
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge
tSIHRS1
Frame Sync Hold After Serial Clock Rising Edge
tSISD1
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
tSIHD1
tSITXCLKW
Transmit Clock Width
tSITXCLK
Transmit Clock Period
tSISCLKW
Clock Width
tSISCLK
Clock Period
1
1.2 V, 266 MHz
Max
Min
3
3
3
3
9
20
36
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
The data, serial clock, and frame sync can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN
or any of the DAI pins.
SAMPLE EDGE
tSITXCLKW
tSITXCLK
DAI_P20–1
(TxCLK)
tSISCLKW
DAI_P20–1
(SERIAL CLOCK)
tSISCLK
tSISFS
tSIHFS
tSISD
tSIHD
DAI_P20–1
(FRAME SYNC)
DAI_P20–1
(DATA)
Figure 28. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 35. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
TxCLK Frequency for TxCLK = 384 × Frame Sync
TxCLK Frequency for TxCLK = 256 × Frame Sync
Frame Rate (FS)
Max
Oversampling Ratio × Frame Sync <= 1/tSITXCLK
49.2
192.0
Rev. C |
Page 38 of 52 |
September 2009
Unit
MHz
MHz
kHz
ADSP-21371/ADSP-21375
S/PDIF Receiver
Internal Digital PLL Mode
For the ADSP-21371, the following section describes timing as it
relates to the S/PDIF receiver.
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × Frame Sync clock. The S/PDIF
receiver information does not apply to the ADSP-21375.
Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter
Switching Characteristics
tDFSI
LRCLK Delay After Serial Clock
LRCLK Hold After Serial Clock
tHOFSI
tDDTI
Transmit Data Delay After Serial Clock
tHDTI
Transmit Data Hold After Serial Clock
tSCLKIW1
Transmit Serial Clock Width
1
Min
1.2 V, 266 MHz
Max
5
–2
5
–2
38.5
Serial lock frequency is 64 × Frame Sync where FS = the frequency of LRCLK.
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
DAI_P20–1
(SERIAL CLOCK)
tDFSI
tHOFSI
DAI_P20–1
(FRAME SYNC)
tDDTI
tHDTI
DAI_P20–1
(DATA CHANNEL
A/B)
Figure 29. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. C |
Page 39 of 52 |
September 2009
Unit
ns
ns
ns
ns
ns
ADSP-21371/ADSP-21375
SPI Interface—Master
The processor contains two SPI ports. Both primary and secondary are available through DPI only. The timing provided in
Table 37 and Table 38 applies to both.
Table 37. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing Requirements
Data Input Valid To SPICLK Edge (Data Input Setup Time)
tSSPIDM
tHSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid
Switching Characteristics
tSPICLKM
Serial Clock Cycle
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
tDDSPIDM
tHDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
tSDSCIM
FLAG3–0IN (SPI device select) Low to First SPICLK Edge
tHDSM
Last SPICLK Edge to FLAG3–0IN High
tSPITDM
Sequential Transfer Delay
Min
Max
Unit
8.2
2
ns
ns
8 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
ns
ns
ns
ns
ns
ns
ns
ns
2.5
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 1
FLAG3–0
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLKM
tSPITDM
tHDSM
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
tDDSPIDM
MOSI
(OUTPUT)
tHDSPIDM
LSB
MSB
tSSPIDM
tSSPIDM
tHSPIDM
CPHASE = 1
MISO
(INPUT)
tHSPIDM
MSB
VALID
LSB VALID
tHDSPIDM
tDDSPIDM
MOSI
(OUTPUT)
CPHASE = 0
MISO
(INPUT)
MSB
tSSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 30. SPI Master Timing
Rev. C |
Page 40 of 52 |
September 2009
ADSP-21371/ADSP-21375
SPI Interface—Slave
Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Timing Requirements
tSPICLKS
tSPICHS
tSPICLS
tSDSCO
1.2 V, 266 MHz
Max
Min
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
tHDS
Last SPICLK Edge to SPIDS Not Asserted (CPHASE=0)
tSSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time)
tHSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
tSDPPW
SPIDS Deassertion Pulse Width (CPHASE=0)
Switching Characteristics
tDSOE
SPIDS Assertion to Data Out Active
tDSDHI
SPIDS Deassertion to Data High Impedance
tDDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
tHDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
tDSOV
SPIDS Assertion to Data Out Valid (CPHASE = 0)
Unit
4 × tPCLK – 2
2 × tPCLK – 2
2 × tPCLK – 2
ns
ns
ns
ns
2 × tPCLK
2 × tPCLK
2 × tPCLK
2
2
2 × tPCLK
ns
ns
ns
ns
0
0
6.8
6.8
9.5
ns
ns
ns
ns
ns
2 × tPCLK
5 × tPCLK
SPIDS
(INPUT)
tSPICHS
tSPICLS
tSPICLKS
tHDS
tSDPPW
SPICLK
(CP = 0)
(INPUT)
tSPICLS
tSDSCO
SPICLK
(CP = 1)
(INPUT)
tSPICHS
tDSDHI
tDDSPIDS
tDSOE
tDDSPIDS
MISO
(OUTPUT)
MSB
LSB
tSSPIDS tHSPIDS
tSSPIDS
CPHASE = 1
MOSI
(INPUT)
MSB VALID
LSB VALID
tHDSPIDS
tDDSPIDS
MISO
(OUTPUT)
MSB
LSB
tDSOV
CPHASE = 0
MOSI
(INPUT)
tHDSPIDS
tHSPIDS
tSSPIDS
MSB VALID
LSB VALID
Figure 31. SPI Slave Timing
Rev. C |
Page 41 of 52 |
September 2009
tDSDHI
ADSP-21371/ADSP-21375
generation of internal UART interrupts and the external data
operations. These latencies are negligible at the data transmission rates for the UART.
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing
Figure 32 describes UART port receive and transmit operations.
The maximum baud rate is PCLK/16 where PCLK = 1/tPCLK. As
shown in Figure 32 there is some latency between the
Table 39. UART Port
Parameter
Timing Requirement
Incoming Data Pulse Width
tTXD1
Switching Characteristic
tRXD1
Incoming Data Pulse Width
1
Min
Max
16tPCLK–1
ns
16tPCLK–1
ns
UART signals TXD and RXD are routed through DPI P14-1 pins using the SRU.
DPI_P14–1
[RxD]
DATA (5–8)
STOP
tRXD
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
DPI_P14–1
[TxD]
DATA (5–8)
STOP (1–2)
tTXD
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 32. UART Port—Receive and Transmit Timing
Rev. C |
Page 42 of 52 |
Unit
September 2009
ADSP-21371/ADSP-21375
TWI Controller Timing
Table 40 and Figure 33 provide timing information for the TWI
interface. Input signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins.
Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices1
Parameter
fSCL
tHDSTA
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUF
tSP
1
SCL Clock Frequency
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated.
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated Start Condition
Data Hold Time for TWI-Bus Devices
Data Setup Time
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Spikes Suppressed By the Input Filter
Min
0
Standard Mode
Max
100
4.0
4.7
4.0
4.7
0
250
4.0
4.7
n/a
Min
0
Fast Mode
Max
400
0.6
1.3
0.6
0.6
0
100
0.6
1.3
0
n/a
50
All values referred to VIHmin and VILmax levels. For more information, see Electrical Characteristics on page 16.
DPI_P14–1
SDA
tBUF
tSP
tHDSTA
tSUDAT
tLOW
DPI_P14–1
SCL
S
tHDSTA
tHDDAT
tHIGH
tSUSTA
Sr
tSUSTO
Figure 33. Fast and Standard Mode Timing on the TWI Bus
Rev. C |
Page 43 of 52 |
September 2009
P
S
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
ADSP-21371/ADSP-21375
JTAG Test Access Port and Emulation
Table 41. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS1
System Inputs Setup Before TCK High
1
tHSYS
System Inputs Hold After TCK High
tTRSTW
TRST Pulse Width
Switching Characteristics
tDTDO
TDO Delay from TCK Low
2
tDSYS
System Outputs Delay After TCK Low
1
2
Min
tCK
5
6
7
18
4 × tCK
tTCK
TCK
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 34. IEEE 1149.1 JTAG Test Access Port
Rev. C |
Page 44 of 52 |
September 2009
Unit
ns
ns
ns
ns
ns
ns
7
tCK ÷ 2 + 7
System Inputs = ADDR15–0, CLKCFG1–0, RESET, BOOT_CFG1–0, DAI_Px, and FLAG3–0.
System Outputs = DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.
tSTAP
Max
ns
ns
ADSP-21371/ADSP-21375
OUTPUT DRIVE CURRENTS
CAPACITIVE LOADING
Figure 35 shows typical I-V characteristics for the output drivers of the processors. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 36). Figure 40 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 38, Figure 39, and Figure 40 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
40
VOH
3.3V, 25°C
20
3.47V, -45°C
12
10
3.11V, 125°C
10
0
- 10
3.11V, 125°C
- 20
3.3V, 25°C
VOL
- 30
3.47V, -45°C
- 40
0
0.5
1.0
1.5
2.0
2.5
SWEEP (VDDEXT ) VOLTAGE (V)
3.0
3.5
y = 0.0467x + 1.6323
RISE AND FALL TIMES (ns)
SOURCE (VDDEXT) CURRENT (mA)
30
FALL
8
6
4
y = 0.045x + 1.524
2
Figure 35. Typical Drive at Junction Temperature
0
0
50
TEST CONDITIONS
100
150
200
250
LOAD CAPACITANCE (pF)
The ac signal specifications (timing parameters) appear in
Table 15 on Page 21 through Table 41 on Page 44. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 36.
ȍ
VLOAD
30pF
Figure 38. Typical Output Rise/Fall Time (20% to 80%,
VDDEXT = Max)
12
RISE
10
RISE AND FALL TIMES (ns)
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 37. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
TO
OUTPUT
PIN
RISE
y = 0.049x + 1.5105
FALL
8
6
y = 0.0482x + 1.4604
4
2
0
0
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
50
100
150
200
LOAD CAPACITANCE (pF)
Figure 39. Typical Output Rise/Fall Time (20% to 80%,
VDDEXT = Min)
INPUT
1.5V
OR
OUTPUT
1.5V
Figure 37. Voltage Reference Levels for AC Measurements
Rev. C |
Page 45 of 52 |
September 2009
250
ADSP-21371/ADSP-21375
Values of θJB are provided for package comparison and PCB
design considerations. Note that the thermal characteristics values provided in Table 42 are modeled values.
10
OUTPUT DELAY OR HOLD (ns)
8
Table 42. Thermal Characteristics for 208-Lead LQFP
E_PAD (With Exposed Pad Soldered to PCB)
Y = 0.0488X - 1.5923
6
4
2
0
-2
-4
0
50
100
150
200
LOAD CAPACITANCE (pF)
Figure 40. Typical Output Delay or Hold vs. Load Capacitance
(at Ambient Temperature)
Parameter
θJA
θJMA
θJMA
θJC
ΨJT
ΨJMT
ΨJMT
ΨJB
ΨJMB
ΨJMB
THERMAL CHARACTERISTICS
The processor is rated for performance over the temperature
range specified in Operating Conditions on Page 16.
Table 42 airflow measurements comply with JEDEC standards
JESD51-2 and JESD51-6 and the junction-to-board measurement complies with JESD51-8. Test board design complies with
JEDEC standard JESD51-7 (LQFP_EP). The junction-to-case
measurement complies with MIL- STD-883. All measurements
use a 2S2P JEDEC test board.
To determine the junction temperature of the device while on
the application PCB, use
T J = T CASE + ( Ψ JT × P D )
where:
TJ = junction temperature °C
TCASE = case temperature (°C) measured at the top center of the
package
ΨJT = junction-to-top (of package) characterization parameter
is the Typical value from Table 42.
PD = power dissipation
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first order approximation of TJ by the equation
T J = T A + ( θ JA × P D )
where:
TA = ambient temperature °C
Values of θJC are provided for package comparison and PCB
design considerations when an external heatsink is required.
Rev. C |
Page 46 of 52 |
September 2009
Condition
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Airflow = 0 m/s
Airflow = 1 m/s
Airflow = 2 m/s
Typical
17.1
14.7
14.0
9.6
0.23
0.39
0.45
11.5
11.2
11.0
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
ADSP-21371/ADSP-21375
208-LEAD LQFP_EP PINOUT
Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Signal
VDDINT
DATA28
DATA27
GND
VDDEXT
DATA26
DATA25
DATA24
DATA23
GND
VDDINT
DATA22
DATA21
DATA20
VDDEXT
GND
DATA19
DATA18
VDDINT
GND
DATA17
VDDINT
GND
VDDINT
GND
DATA16
DATA15
DATA14
DATA13
DATA12
VDDEXT
GND
VDDINT
GND
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
VDDEXT
GND
VDDINT
DATA4
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Signal
VDDINT
GND
VDDEXT
ADDR0
ADDR2
ADDR1
ADDR4
ADDR3
ADDR5
GND
VDDINT
GND
VDDEXT
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
GND
VDDINT
GND
VDDEXT
ADDR11
ADDR12
ADDR13
GND
VDDINT
NC
NC
GND
CLKIN
XTAL
VDDEXT
GND
VDDINT
ADDR14
GND
VDDEXT
ADDR15
ADDR16
ADDR17
ADDR18
GND
VDDEXT
Rev. C |
Pin No.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Page 47 of 52 |
Signal
VDDINT
GND
VDDEXT
SDCAS
SDRAS
SDCKE
SDWE
WR
SDA10
GND
VDDEXT
SDCLK
GND
VDDINT
RD
ACK
FLAG3
FLAG2
FLAG1
FLAG0
DAI_P20 (SFS5)
GND
VDDINT
GND
VDDEXT
DAI_P19 (SCLK5)
DAI_P18 (SD5B)
DAI_P17 (SD5A)
DAI_P16 (SD4B)
DAI_P15 (SD4A)
DAI_P14 (SFS3)
DAI_P13 (SCLK3)
DAI_P12 (SD3B)
VDDINT
VDDEXT
GND
VDDINT
GND
DAI_P11 (SD3A)
DAI_P10 (SD2B)
DAI_P8 (SFS1)
DAI_P9 (SD2A)
DAI_P6 (SD1B)
DAI_P7 (SCLK1)
September 2009
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Signal
VDDINT
VDDINT
GND
VDDINT
VDDINT
VDDINT
TDI
TRST
TCK
GND
VDDINT
TMS
CLK_CFG0
BOOT_CFG0
CLK_CFG1
EMU
BOOT_CFG1
TDO
DAI_P4 (SFS0)
DAI_P2 (SD0B)
DAI_P3 (SCLK0)
DAI_P1 (SD0A)
VDDEXT
GND
VDDINT
GND
DPI_P14 (TIMER1)
DPI_P13 (TIMER0)
DPI_P12 (TWI_CLK)
DPI_P11 (TWI_DATA)
DPI_P10 (UART0RX)
DPI_P09 (UART0TX)
DPI_P08 (SPIFLG3)
DPI_P07 (SPIFLG2)
VDDEXT
GND
VDDINT
GND
DPI_P06 (SPIFLG1)
DPI_P05 (SPIFLG0)
DPI_P04 (SPIDS)
DPI_P03 (SPICLK)
DPI_P01 (SPIMOSI)
DPI_P02 (SPIMISO)
ADSP-21371/ADSP-21375
Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued)
Pin No.
45
Signal
DATA5
Pin No.
97
Signal
ADDR19
Pin No.
149
Signal
DAI_P5 (SD1A)
Pin No.
201
46
47
48
49
50
51
52
DATA2
DATA3
DATA0
DATA1
VDDEXT
GND
VDDINT
98
99
100
101
102
103
104
ADDR20
ADDR21
ADDR23
ADDR22
MS1
MS0
VDDINT
150
151
152
153
154
155
156
VDDEXT
GND
VDDINT
GND
VDDINT
GND
VDDINT
202
203
204
205
206
207
208
Rev. C |
Page 48 of 52 |
September 2009
Signal
RESETOUT/
RUNRSTIN
RESET
VDDEXT
GND
DATA30
DATA31
DATA29
VDDINT
ADSP-21371/ADSP-21375
Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Signal
VDDINT
NC
NC
GND
VDDEXT
NC
NC
NC
NC
GND
VDDINT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDINT
GND
VDDINT
GND
NC
DATA15
DATA14
DATA13
DATA12
VDDEXT
GND
VDDINT
GND
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
VDDEXT
GND
VDDINT
DATA4
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Signal
VDDINT
GND
VDDEXT
ADDR0
ADDR2
ADDR1
ADDR4
ADDR3
ADDR5
GND
VDDINT
GND
VDDEXT
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
GND
VDDINT
GND
VDDEXT
ADDR11
ADDR12
ADDR13
GND
VDDINT
NC
NC
GND
CLKIN
XTAL
VDDEXT
GND
VDDINT
ADDR14
GND
VDDEXT
ADDR15
ADDR16
ADDR17
ADDR18
GND
VDDEXT
Rev. C |
Pin No.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Page 49 of 52 |
Signal
VDDINT
GND
VDDEXT
SDCAS
SDRAS
SDCKE
SDWE
WR
SDA10
GND
VDDEXT
SDCLK
GND
VDDINT
RD
ACK
FLAG3
FLAG2
FLAG1
FLAG0
DAI_P20 (SFS5)
GND
VDDINT
GND
VDDEXT
DAI_P19 (SCLK5)
DAI_P18 (SD5B)
DAI_P17 (SD5A)
DAI_P16 (SD4B)
DAI_P15 (SD4A)
DAI_P14 (SFS3)
DAI_P13 (SCLK3)
DAI_P12 (SD3B)
VDDINT
VDDEXT
GND
VDDINT
GND
DAI_P11 (SD3A)
DAI_P10 (SD2B)
DAI_P8 (SFS1)
DAI_P9 (SD2A)
DAI_P6 (SD1B)
DAI_P7 (SCLK1)
September 2009
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Signal
VDDINT
VDDINT
GND
VDDINT
VDDINT
VDDINT
TDI
TRST
TCK
GND
VDDINT
TMS
CLK_CFG0
BOOT_CFG0
CLK_CFG1
EMU
BOOT_CFG1
TDO
DAI_P4 (SFS0)
DAI_P2 (SD0B)
DAI_P3 (SCLK0)
DAI_P1 (SD0A)
VDDEXT
GND
VDDINT
GND
DPI_P14 (TIMER1)
DPI_P13 (TIMER0)
DPI_P12 (TWI_CLK)
DPI_P11 (TWI_DATA)
DPI_P10 (UART0RX)
DPI_P09 (UART0TX)
DPI_P08 (SPIFLG3)
DPI_P07 (SPIFLG2)
VDDEXT
GND
VDDINT
GND
DPI_P06 (SPIFLG1)
DPI_P05 (SPIFLG0)
DPI_P04 (SPIDS)
DPI_P03 (SPICLK)
DPI_P01 (SPIMOSI)
DPI_P02 (SPIMISO)
ADSP-21371/ADSP-21375
Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued)
Pin No.
45
Signal
DATA5
Pin No.
97
Signal
ADDR19
Pin No.
149
Signal
DAI_P5 (SD1A)
Pin No.
201
46
47
48
49
50
51
52
DATA2
DATA3
DATA0
DATA1
VDDEXT
GND
VDDINT
98
99
100
101
102
103
104
ADDR20
ADDR21
ADDR23
ADDR22
MS1
MS0
VDDINT
150
151
152
153
154
155
156
VDDEXT
GND
VDDINT
GND
VDDINT
GND
VDDINT
202
203
204
205
206
207
208
Rev. C |
Page 50 of 52 |
September 2009
Signal
RESETOUT/
RUNRSTIN
RESET
VDDEXT
GND
DATA30
DATA31
DATA29
VDDINT
ADSP-21371/ADSP-21375
PACKAGE DIMENSIONS
The processors are available in a 208-lead RoHS compliant
LQFP_EP package.
0.75
0.60
0.45
1.00 REF
30.20
30.00 SQ
29.80
1.60 MAX
25.50
REF
28.10
28.00 SQ
27.90
8.712
REF
157
208
156
1
157
1
PIN 1
SEATING
PLANE
TOP VIEW
8.890
REF
*EXPOSED
PAD
(PINS DOWN)
1.45
1.40
1.35
208
156
0.20
0.15
0.09
0.15
0.10
0.05
0.08
COPLANARITY
7°
3.5°
0°
BOTTOM VIEW
105
104
52
53
VIEW A
ROTATED 90° CCW
(PINS UP)
105
104
VIEW A
52
53
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD
*NOTE:
THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO GND.
THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A GND PCB LAND THAT IS THE SAME SIZE
AS THE EXPOSED PAD. THE GND PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE GND PLANE IN THE PCB
WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.
Figure 41. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]
(SW-208-1)
Dimensions shown in millimeters
Rev. C |
Page 51 of 52 |
September 2009
ADSP-21371/ADSP-21375
AUTOMOTIVE PRODUCTS
Some ADSP-21371/ADSP-21375 models are available for automotive applications with controlled manufacturing. Note that
this special model may have specifications that differ from the
general release models.
The automotive grade products shown in Table 45 are available
for use in automotive applications. Contact your local ADI
account representative or authorized ADI product distributor
for specific product ordering information. Note that all automotive products are RoHS compliant.
Table 45. Automotive Products
1
Model
Temperature
Range1
Instruction
Rate
On-Chip
SRAM
ROM
Package Description
Package Option
AD21371WBSWZ2xx
–40ºC to 85ºC
266 MHz
1M bit
4M bit
208-Lead LQFP_EP
SW-208-1
AD21371WYSWZ1xx
–40ºC to 105ºC
200 MHz
1M bit
4M bit
208-Lead LQFP_EP
SW-208-1
AD21375WBSWZ2xx
–40ºC to 85ºC
266 MHz
0.5M bit
2M bit
208-Lead LQFP_EP
SW-208-1
AD21375WYSWZ1xx
–40ºC to 105ºC
200 MHz
0.5M bit
2M bit
208-Lead LQFP_EP
SW-208-1
Referenced temperature is ambient temperature.
ORDERING GUIDE
Model
ADSP-21371KSWZ-2A2
ADSP-21371KSWZ-2B2
ADSP-21371BSWZ-2B2, 3
ADSP-21375KSWZ-2B2
ADSP-21375BSWZ-2B2, 3
Temperature
Range1
0ºC to +70ºC
0ºC to +70ºC
-40ºC to +85ºC
0ºC to +70ºC
-40ºC to +85ºC
Instruction
Rate
200 MHz
266 MHz
266 MHz
266 MHz
266 MHz
On-Chip
SRAM
1M bit
1M bit
1M bit
0.5M bit
0.5M bit
ROM
4M bit
4M bit
4M bit
2M bit
2M bit
1
Package Description
208-Lead LQFP_EP
208-Lead LQFP_EP
208-Lead LQFP_EP
208-Lead LQFP_EP
208-Lead LQFP_EP
Referenced temperature is ambient temperature.
Z = RoHS Compliant Part
3
Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software.
For a complete list, visit our website at www.analog.com/SHARC
2
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07170-0-9/09(C)
Rev. C |
Page 52 of 52 |
September 2009
Package Option
SW-208-1
SW-208-1
SW-208-1
SW-208-1
SW-208-1
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