Sharp LH28F800 8 m-bit (512 kb x 16) smartvoltage flash memory Datasheet

LH28F800SG-L/SGH-L (FOR TSOP, CSP)
LH28F800SG-L/SGH-L
(FOR TSOP, CSP)
8 M-bit (512 kB x 16) SmartVoltage
Flash Memories
DESCRIPTION
The LH28F800SG-L/SGH-L flash memories with
SmartVoltage technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F800SG-L/SGH-L
can operate at VCC = 2.7 V and VPP = 2.7 V. Their
low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Their symmetrically-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for resident flash
arrays, SIMMs and memory cards. Their enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F800SG-L/SGH-L
offer three levels of protection : absolute protection
with VPP at GND, selective hardware block locking,
or flexible software block locking.These alternatives
give designers ultimate control of their code security
needs.
FEATURES
• SmartVoltage technology
– 2.7 V, 3.3 V or 5 V VCC
– 2.7 V, 3.3 V, 5 V or 12 V VPP
• High performance read access time
LH28F800SG-L70/SGH-L70
– 70 ns (5.0±0.25 V)/80 ns (5.0±0.5 V)/
85 ns (3.3±0.3 V)/100 ns (2.7 to 3.0 V)
LH28F800SG-L10/SGH-L10
– 100 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/
120 ns (2.7 to 3.0 V)
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Flexible block locking
– Block erase/word write lockout during power
transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture
– Sixteen 32 k-word erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/chip
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases ICC
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Packages
– 48-pin TSOP TypeI (TSOP048-P-1220)
Normal bend/Reverse bend
– 48-ball CSP(FBGA048-P-0808)
∗ ETOX is a trademark of Intel Corporation.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
COMPARISON TABLE
VERSIONS
OPERATING TEMPERATURE
PACKAGE
0 to +70˚C
48-pin TSOP (I)
48-ball CSP
LH28F800SG-L
(FOR TSOP, CSP)
LH28F800SGH-L
– 40 to +85˚C
(FOR TSOP, CSP)
LH28F800SG-L∗1
0 to +70˚C
(FOR SOP)
WRITE PROTECT FUNCTION
Controlled by
48-pin TSOP (I)
WP# and RP# pins
Controlled by
48-ball CSP
WP# and RP# pins
44-pin SOP
Controlled by RP# pin
∗1 Refer to the datasheet of LH28F800SG-L (FOR SOP).
PIN CONNECTIONS
48-PIN TSOP (Type I)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
48-BALL CSP
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
A16
NC
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
TOP VIEW
1
2
3
4
5
6
7
8
A
A2
A5
A17
WP#
WE#
A8
A11
A14
B
A3
A6
A18
VPP
RP#
NC
A10
A13
C
A1
A4
A7
RY/BY#
NC
A9
A12
A15
D
A0
OE#
DQ1
DQ10
DQ12
DQ6
DQ15
A16
E GND
DQ8
DQ2
DQ11
VCC
DQ5
DQ14
GND
F
DQ0
DQ9
DQ3
DQ4
DQ13
DQ7
NC
CE#
(FBGA048-P-0808)
(TSOP048-P-1220)
NOTE :
Reverse bend available on request.
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LH28F800SG-L/SGH-L (FOR TSOP, CSP)
BLOCK DIAGRAM
DQ0-DQ15
INPUT
BUFFER
I/O
LOGIC
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
REGISTER
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
CE#
WE#
COMMAND
USER
INTERFACE
OE#
WP#
RP#
DATA
COMPARATOR
A0-A18
INPUT
BUFFER
ADDRESS
LATCH
Y DECODER
X DECODER
Y GATING
16
32 k-WORD
BLOCKS
ADDRESS
COUNTER
-3-
VCC
WRITE
STATE
MACHINE
RY/BY#
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
PIN DESCRIPTION
SYMBOL
TYPE
A0-A18
INPUT
DQ0-DQ15
INPUT/
OUTPUT
NAME AND FUNCTION
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
CE#
INPUT
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
RP#
INPUT
power-down sets the device to read array mode.
RP# at VHH allows to set permanent lock-bit. Block erase, word write, or lock-bit
configuration with VIH < RP# < VHH produce spurious results and should not be
OE#
INPUT
WE#
INPUT
WP#
INPUT
RY/BY#
OUTPUT
attempted.
OUTPUT ENABLE : Controls the device's outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECT : Master control for block locking. When VIL, locked blocks cannot be
erased and programmed, and block lock-bits can not be set and reset.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, word write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and word write is inactive, word write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :
For erasing array blocks, writing words, or configuring lock-bits. With VPP ≤ VPPLK,
VPP
SUPPLY
memory contents cannot be altered. Block erase, word write, and lock-bit configuration
with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious
results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configured the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp VCC down to GND and then
VCC
SUPPLY
ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
GND
NC
SUPPLY
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
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LH28F800SG-L/SGH-L (FOR TSOP, CSP)
1 INTRODUCTION
This datasheet contains LH28F800SG-L/SGH-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800SG-L/
SGH-L flash memories documentation also includes
ordering information which is referenced in
Section 7.
1.1
the power of 5 V VCC. But, 5 V VCC provides the
highest read performance. VPP at 2.7 V, 3.3 V and
5 V eliminates the need for a separate 12 V
converter, while VPP = 12 V maximizes block erase
and word write performance. In addition to flexible
erase and program voltages, the dedicated VPP pin
gives complete data protection when VPP ≤ VPPLK.
Table 1 VCC and VPP Voltage Combinations
Offered by SmartVoltage Technology
New Features
VCC VOLTAGE
Key enhancements of LH28F800SG-L/SGH-L
SmartVoltage flash memories are :
2.7 V
3.3 V
5V
• SmartVoltage Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
• Permanent Lock Capability,
VPP VOLTAGE
2.7 V, 3.3 V, 5 V, 12 V
3.3 V, 5 V, 12 V
5 V, 12 V
Internal VCC and VPP detection circuitry automatically configures the device for optimized read
and write operations.
Note following important differences :
• VPPLK has been lowered to 1.5 V to support
3.3 V and 5 V block erase, word write, and lockbit configuration operations. Designs that switch
VPP off during read operations should make sure
that the VPP voltage transitions to GND.
• To take advantage of SmartVoltage technology,
allow VCC connection to 2.7 V, 3.3 V or 5 V.
• Once set the permanent lock bit, the blocks
which have been set block lock-bit can not be
erased, written forever.
1.2
Product Overview
The LH28F800SG-L/SGH-L are high-performance
8 M-bit SmartVoltage flash memories organized as
512 k-word of 16 bits. The 512 k-word of data is
arranged in sixteen 32 k-word blocks which are
individually erasable, lockable, and unlockable insystem. The memory map is shown in Fig. 1.
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.
2.7 to 3.6 V VCC consumes approximately one-fifth
-5-
A command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timing
necessary for block erase, word write, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
32 k-word blocks typically within 1.2 second (5 V
VCC, 12 V VPP) independent of other blocks. Each
block can be independently erased 100 000 times
(1.6 million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
Writing memory data is performed in word
increments typically within 7.5 µs (5 V VCC, 12 V
VPP). Word write suspend mode enables the
system to read data from, or write data to any other
flash memory array location.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
The selected block can be locked or unlocked
individually by the combination of sixteen block lock
bits and the RP# or WP#. Block erase or word
write must not be carried out by setting block lock
bits and setting WP# to low and RP# to VIH. Even
if WP# is high state or RP# is set to VHH, block
erase and word write to locked blocks is prohibited
by setting permanent lock bit.
The status register or RY/BY# indicates when the
WSM’s block erase, word write, or lock-bit
configuration operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, word write, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and word write is inactive), word
write is suspended, or the device is in deep powerdown mode.
The access time is 70 ns (tAVQV) at the VCC supply
voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F800SG-L)/
– 40 to +85°C (LH28F800SGH-L). At 4.5 to 5.5 V
VCC, the access time is 80 ns or 100 ns. At lower
VCC voltage, the access time is 85 ns or 100 ns
(3.0 to 3.6 V) and 100 ns or 120 ns (2.7 to 3.0 V).
When CE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
32 k-Word Block
15
32 k-Word Block
14
32 k-Word Block
13
32 k-Word Block
12
32 k-Word Block
11
32 k-Word Block
10
32 k-Word Block
9
32 k-Word Block
8
32 k-Word Block
7
32 k-Word Block
6
32 k-Word Block
5
32 k-Word Block
4
32 k-Word Block
3
32 k-Word Block
2
32 k-Word Block
1
32 k-Word Block
0
Fig. 1 Memory Map
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
5 V VCC and 3 mA at 2.7 to 3.6 V VCC.
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LH28F800SG-L/SGH-L (FOR TSOP, CSP)
2 PRINCIPLES OF OPERATION
The LH28F800SG-L/SGH-L SmartVoltage flash
memories include an on-chip WSM to manage
block erase, word write, and lock-bit configuration
functions. It allows for : 100% TTL-level control
inputs, fixed power supplies during block erasure,
word write, and lock-bit configuration, and minimal
processor overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby, and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
block erasure, word writing, and lock-bit
configuration. All functions associated with altering
memory contents — block erase, word write, lockbit configuration, status, and identifier codes — are
accessed via the CUI and verified through the
status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as
input to the WSM, which controls the block erase,
word write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal verification, and margining
of data. Addresses and data are internally latched
during write cycles. Writing the appropriate
command outputs array data, accesses the
identifier codes, or outputs status register data.
Interface software that initiates and polls progress
of block erase, word write, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read/write
-7-
data from/to blocks other than that which is
suspended. Word write suspend allows system
software to suspend a word write to read data from
any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erases, word writes, or lock-bit configurations are
required) or hardwired to VPPH1/2/3. The device
accommodates either design practice and
encourages optimization of the processor-memory
interface.
When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase, word
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to VPP. All write
functions are disabled when VCC is below the write
lockout voltage VLKO or when RP# is at VIL. The
device’s block locking capability provides additional
protection from inadvertent code or data alteration
by gating erase and word write operations.
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1
Read
Information can be read from any block, identifier
codes, or status register independent of the VPP
voltage. RP# can be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep powerdown mode, the device automatically resets to read
array mode. Five control pins dictate the data flow
in and out of the component : CE#, OE#, WE#,
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the
device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ0-DQ15) control and when active drives
the selected memory data onto the I/O bus. WE#
must be at VIH and RP# must be at VIH or VHH.
Fig. 13 illustrates read cycle.
During block erase, word write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time tPHWL is required
after RP# goes to logic-high (VIH) before another
command can be written.
3.2
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
word write, or lock-bit configuration modes. If a
CPU reset occurs with no flash memory reset,
proper CPU initialization may not occur because
the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In
this application, RP# is controlled by the same
RESET# signal that resets the system CPU.
Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ15 are
placed in a high-impedance state.
3.3
Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ15 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase, word write, or lockbit configuration, the device continues functioning,
and consuming active power until the operation
completes.
3.4
Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
-8-
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
3.5
Read Identifier Codes
3.6
The read identifier codes operation outputs the
manufacture code, device code, block lock
configuration codes for each block, and the
permanent lock configuration code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms. The block lock and
permanent lock configuration codes identify locked
and unlocked blocks and permanent lock-bit setting.
7FFFF
78004
Reserved for
Future Implementation
Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the
command and address of the location to be written.
Set Permanent and Block Lock-Bit commands
require the command and address within the device
(Permanent Lock) or block within the device (Block
Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address
within the device.
78003
78002
78001
78000
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 14 and
Fig. 15 illustrate WE# and CE# controlled write
operations.
Block 15 Lock Configuration Code
Reserved for
Future Implementation
Block 15
(Blocks 2 through 14)
0FFFF
08004
Reserved for
Future Implementation
4 COMMAND DEFINITIONS
08003
08002
Block 1 Lock Configuration Code
08001
Reserved for
Future Implementation
08000
When the VPP ≤ VPPLK, read operations from the
status register, identifier codes, or blocks are
enabled. Placing VPPH1/2/3 on VPP enables
successful block erase, word write and lock-bit
configuration operations.
Block 1
07FFF
Reserved for
Future Implementation
00004
00003
Permanent Lock Configuration Code
00002
Block 0 Lock Configuration Code
00001
Device Code
00000
Manufacture Code
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Block 0
Fig. 2 Device Identifier Code Memory Map
-9-
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
Table 2 Bus Operations
MODE
Read
NOTE
RP#
OE#
WE#
ADDRESS
VPP
DQ0-15
RY/BY#
VIL
VIL
VIH
X
X
DOUT
X
Output Disable
3
VIH or VHH
VIL
VIH
VIH
X
X
High Z
X
Standby
3
VIH or VHH
VIH
X
X
X
X
High Z
X
Deep Power-Down
4
VIL
X
X
X
X
X
High Z
VOH
VIL
VIL
VIL
VIH
VIH
VIL
See Fig. 2
X
X
X
(NOTE 5)
DIN
VOH
X
Read Identifier Codes
Write
1, 2, 3, 8 VIH or VHH
CE#
8
VIH or VHH
3, 6, 7, 8 VIH or VHH
NOTES :
1.
2.
3.
Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.
RY/BY# is VOL when the WSM is executing internal
block erase, word write, or lock-bit configuration
algorithms. It is VOH during when the WSM is not busy,
in block erase suspend mode (with word write inactive),
word write suspend mode, or deep power-down mode.
4.
5.
6.
7.
8.
- 10 -
RP# at GND±0.2 V ensures the lowest deep powerdown current.
See Section 4.2 for read identifier code data.
VIH < RP# < VHH produce spurious results and should
not be attempted.
Refer to Table 3 for valid DIN during a write operation.
Don’t use the timing both OE# and WE# are VIL.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
Table 3 Command Definitions (NOTE 9)
COMMAND
Read Array/Reset
BUS CYCLES
REQ’D.
1
NOTE
FIRST BUS CYCLE
Oper (NOTE 1)
Addr (NOTE 2)
Data (NOTE 3)
Write
X
FFH
Write
Write
X
X
90H
70H
Write
X
50H
SECOND BUS CYCLE
Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
Read Identifier Codes
Read Status Register
≥2
2
Clear Status Register
1
Block Erase
2
5
Write
BA
20H
Word Write
2
5, 6
Write
WA
40H or 10H
Block Erase and
Word Write Suspend
1
5
Write
X
B0H
1
5
Write
X
D0H
2
7
Write
BA
60H
Write
BA
01H
2
2
7
8
Write
Write
X
X
60H
60H
Write
Write
X
X
F1H
D0H
Block Erase and
Word Write Resume
Set Block Lock-Bit
Set Permanent Lock-Bit
Clear Block Lock-Bits
4
Read
Read
IA
X
ID
SRD
Write
BA
D0H
Write
WA
WD
NOTES :
1.
2.
3.
4.
5.
Bus operations are defined in Table 2.
X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
SRD = Data read from status register. See Table 6 for a
description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or CE# (whichever
goes high first).
ID = Data read from identifier codes.
Following the Read Identifier Codes command, read
operations access manufacture, device, block lock, and
permanent lock codes. See Section 4.2 for read
identifier code data.
If the block is locked and the permanent lock-bit is not
set, WP# must be at VIH or RP# must be at VHH to
enable block erase or word write operations. Attempts to
issue a block erase or word write to a locked block while
WP# is VIH or RP# is VHH.
6.
7.
8.
9.
- 11 -
Either 40H or 10H is recognized by the WSM as the
word write setup.
If the permanent lock-bit is set, WP# must be at VIH or
RP# must be at VHH to set a block lock-bit. RP# must
be at VHH to set the permanent lock-bit. If the permanent
lock-bit is set, a block lock-bit cannot be set. Once the
permanent lock-bit is set, permanent lock-bit reset is
unable.
If the permanent lock-bit is set, clear block lock-bits
operation is unable. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the permanent
lock-bit is not set, the Clear Block Lock-Bits command
can be done while WP# is VIH or RP# is VHH.
Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
4.1
Read Array Command
4.3
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, word write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Word
Write Suspend command. The Read Array
command functions independently of the VPP
voltage and RP# can be VIH or VHH.
4.2
4.4
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or word write suspend modes.
Table 4 Identifier Codes
CODE
ADDRESS DATA
Manufacture Code
00000H
00B0H
Device Code
00001H
0050H
Block Lock Configuration (NOTE 2) XX002H (NOTE 1)
• Unlocked
DQ0 = 0
• Locked
DQ0 = 1
• Reserved for future enhancement
DQ1-15
Permanent Lock Configuration (NOTE 2)
00003H
• Unlocked
DQ0 = 0
• Locked
DQ0 = 1
• Reserved for future enhancement
DQ1-15
4.5
NOTES :
2.
The status register may be read to determine when
a block erase, word write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs. OE# or CE# must toggle to
VIH before further reads to update the status
register latch. The Read Status Register command
functions independently of the VPP voltage. RP#
can be VIH or VHH.
Read Identifier Codes Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and permanent lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the following information can be read :
1.
Read Status Register Command
X selects the specific block lock configuration code to be
read. See Fig. 2 for the device identifier code memory map.
Block lock status and permanent lock status are output
by DQ0. DQ1-DQ15 are reserved for future enhancement.
Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
- 12 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to "1". Also,
reliable block erasure can only occur when VCC =
VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of
this high voltage, block contents are protected
against erasure. If block erase is attempted while
VPP ≤ VPPLK, SR.3 and SR.5 will be set to "1".
Successful block erase requires that the
corresponding block lock-bit be cleared or, if set,
that WP# = VIH or RP# = VHH. If block erase is
attempted when the corresponding block lock-bit is
set and WP# = VIL and RP# = VIH, SR.1 and SR.5
will be set to "1". Once permanent lock-bit is set,
the blocks which have been set block lock-bit are
unable to erase forever. Block erase operations
with VIH < RP# < VHH produce spurious results and
should not be attempted.
4.6
Word Write Command
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word write and write verify algorithms
internally. After the word write sequence is written,
the device automatically outputs status register data
when read (see Fig. 4). The CPU can detect the
completion of the word write event by analyzing the
RY/BY# pin or status register bit SR.7.
When word write is complete, status register bit
SR.4 should be checked. If word write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for "1"s that
do not successfully write to "0"s. The CUI remains
in read status register mode until it receives another
command.
Reliable word writes can only occur when VCC =
VCC1/2/3/4 and VPP = VPPH1/2/3. In the absence of
this high voltage, memory contents are protected
against word writes. If word write is attempted while
VPP ≤ VPPLK, status register bits SR.3 and SR.4 will
be set to "1". Successful word write requires that
the corresponding block lock-bit be cleared or, if
set, that WP# = VIH or RP# = VHH. If word write is
attempted when the corresponding block lock-bit is
set and WP# = VIL and RP# = VIH, SR.1 and SR.4
will be set to "1". Once permanent lock-bit is set,
the blocks which have been set block lock-bit are
unable to write forever. Word write operations with
VIH < RP# < VHH produce spurious results and
should not be attempted.
4.7
Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or word write data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to VOH.
Specification tWHRH2 defines the block erase
suspend latency.
- 13 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A Word Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the Word
Write Suspend command (see Section 4.8), a
word write operation can also be suspended.
During a word write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to VOL.
However, SR.6 will remain "1" to indicate block
erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to VOL. After the Erase
Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). VPP must remain at VPPH1/2/3
(the same VPP level used for block erase) while
block erase is suspended. RP# must also remain at
VIH or VHH (the same RP# level used for block
erase). WP# must also remain at VIL or VIH (the
same WP# level used for block erase). Block erase
cannot resume until word write operations initiated
during block erase suspend have completed.
4.8
Word Write Suspend Command
The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to VOH. Specification tWHRH1 defines
the word write suspend latency.
At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while word write is suspended are Read
Status Register and Word Write Resume. After
Word Write Resume command is written to the
flash memory, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear and RY/BY# will return to
VOL. After the Word Write Resume command is
written, the device automatically outputs status
register data when read (see Fig. 6). VPP must
remain at VPPH1/2/3 (the same VPP level used for
word write) while in word write suspend mode. RP#
must also remain at VIH or VHH (the same RP#
level used for word write). WP# must also remain
at VIL or VIH (the same WP# level used for word
write).
4.9
Set Block and Permanent LockBit Commands
The combination of the software command
sequence and hardware WP#, RP# pin provides
most flexible block lock (write protection) capability.
The word write/block erase operation is restricted
by the status of block lock-bit, WP# pin, RP# pin
and permanent lock-bit. The status of WP# pin,
RP# pin and permanent lock-bit restricts the set
block bit. When the permanent lock-bit has not
been set, and when WP# = VIH or RP# = VHH, the
block lock bit can be set with the status of the RP#
pin. When RP# = VHH, the permanent lock-bit can
be set with the permanent lock-bit set command.
After the permanent lock-bit has been set, the
write/erase operation to the block lock-bit can never
be accepted. Refer to Table 5 for the hardware
and the software write protection.
Set block lock-bit and permanent lock-bit are
executed by a two-cycle command sequence. The
- 14 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
set block or permanent lock-bit setup along with
appropriate block or device address is written
followed by either the set block lock-bit confirm (and
an address within the block to be locked) or the set
permanent lock-bit confirm (and any device
address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when
read (see Fig. 7). The CPU can detect the
completion of the set lock-bit event by analyzing the
RY/BY# pin output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Permanent Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when VCC = VCC1/2/3/4 and VPP =
VPPH1/2/3. In the absence of this high voltage, lockbit contents are protected against alteration.
A successful set block lock-bit operation requires
that the permanent lock-bit be cleared and WP# =
VIH or RP# = VHH. If it is attempted with the
permanent lock-bit set, SR.1 and SR.4 will be set
to "1" and the operation will fail. Set block lock-bit
operations while VIH < RP# < VHH produce
spurious results and should not be attempted. A
successful set permanent lock-bit operation requires
that RP# = VHH. If it is attempted with RP# = VIH,
SR.1 and SR.4 will be set to "1" and the operation
will fail. Set permanent lock-bit operations with VIH
< RP# < VHH produce spurious results and should
not be attempted.
4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the
permanent lock-bit not set and WP# = VIH or RP#
= VHH, block lock-bits can be cleared using the
Clear Block Lock-Bits command. If the permanent
lock-bit is set, clear block lock-bits operation is
unable. See Table 5 for a summary of hardware
and software write protection options.
Clear block lock-bits option is executed by a twocycle command sequence. A clear block lock-bits
setup is first written. After the command is written,
the device automatically outputs status register data
when read (see Fig. 8). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when VCC =
VCC1/2/3/4 and VPP = VPPH1/2/3. In a clear block lockbits operation is attempted while VPP ≤ VPPLK, SR.3
and SR.5 will be set to "1". In the absence of this
high voltage, the block lock-bit contents are
protected against alteration. A successful clear block
lock-bits operation requires that the permanent lockbit is not set and WP# = VIH or RP# = VHH. If it is
attempted with the permanent lock-bit set or WP# =
VIL and RP# = VIH, SR.1 and SR.5 will be set to "1"
and the operation will fail. A clear block lock-bits
operation with VIH < RP# < VHH produce spurious
results and should not be attempted.
- 15 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
If a clear block lock-bits operation is aborted due to
VPP or VCC transition out of valid range or WP# or
RP# active transition, block lock-bit values are left
in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit
contents to known values. Once the permanent
lock-bit is set, it cannot be cleared.
Table 5 Write Protection Alternatives
OPERATION
PERMANENT BLOCK
LOCK-BIT LOCK-BIT
X
0
WP#
X
VIH
Block Erase
or
0
VIL
X
VIH
Set Block
0
VIL
X
Lock-Bit
1
Set Permanent
Lock-Bit
X
X
0
X
1
X
Block Lock-Bit Override.
Block Erase and Word Write Enabled
Block Lock-Bit Override.
Block Erase and Word Write Enabled
Block is Locked.
Block Erase and Word Write Disabled
Permanent Lock-Bit is set.
Block Erase and Word Write Disabled
VIH or VHH Set Block Lock-Bit Enabled
VHH
Set Block Lock-Bit Enabled
VIL
VIH
Set Block Lock-Bit Disabled
X
X
Permanent Lock-Bit is set.
Set Block Lock-Bit Disabled
X
VHH
VIH
VIH
Clear Block
Lock-Bits
VIH or VHH
VIH
1
EFFECT
VIH or VHH Block Erase and Word Write Enabled
VHH
1
Word Write
RP#
Set Permanent Lock-Bit Enabled
Set Permanent Lock-Bit Disabled
VIH or VHH Clear Block Lock-Bits Enabled
VIL
VIL
VHH
VIH
Clear Block Lock-Bits Enabled
Clear Block Lock-Bits Disabled
X
X
Permanent Lock-Bit is set.
Clear Block Lock-Bits Disabled
- 16 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
Table 6 Status Register Definition
WSMS
7
ESS
6
ECLBS
5
WWSLBS
4
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
VPPS
3
WWSS
2
DPS
1
R
0
NOTES :
Check RY/BY# or SR.7 to determine block erase, word
write, or lock-bit configuration completion.
SR.6-0 are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase or lock-bit
configuration attempt, an improper command sequence was
entered.
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS) SR.3 does not provide a continuous indication of VPP level.
1 = Error in Block Erase or Clear Lock-Bits
The WSM interrogates and indicates the VPP level only after
0 = Successful Block Erase or Clear Lock-Bits
SR.4 = WORD WRITE AND SET LOCK-BIT STATUS (WWSLBS)
1 = Error in Word Write or Set Permanent/Block Lock-Bit
0 = Successful Word Write or Set Permanent/Block Lock-Bit
Block Erase, Word Write, Set Block/Permanent Lock-Bit, or
Clear Block Lock-Bits command sequences. SR.3 is not
guaranteed to reports accurate feedback only when VPP ≠
VPPH1/2/3.
SR.1 does not provide a continuous indication of Permanent
and block lock-bit values. The WSM interrogates the
VPP Low Detect, Operation Abort
Permanent lock-bit, block lock-bit, WP# and RP# only after
VPP OK
Block Erase, Word Write, or Lock-Bit configuration command
sequences. It informs the system, depending on the attempted
WORD WRITE SUSPEND STATUS (WWSS)
operation, if the block lock-bit is set, permanent lock-bit is set,
Word Write Suspended
and/or WP# is not VIH, RP# is not VHH. Reading the block
Word Write in Progress/Completed
lock and permanent lock configuration codes after writing the
DEVICE PROTECT STATUS (DPS)
Read Identifier Codes command indicates permanent and
Permanent Lock-Bit, Block Lock-Bit and/or block lock-bit status.
SR.3 = VPP STATUS (VPPS)
1 =
0 =
SR.2 =
1 =
0 =
SR.1 =
1 =
WP#/RP# Lock Detected, Operation Abort
SR.0 is reserved for future use and should be masked out
when polling the status register.
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
- 17 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
BUS
OPERATION COMMAND
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read
Status Register
No
0
Suspend Block
Erase Loop
Suspend
Block Erase
SR.7 =
Yes
1
COMMENTS
Write
Erase Setup
Data = 20H
Addr = Within Block to be Erased
Write
Erase
Confirm
Data = D0H
Addr = Within Block to be Erased
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after
a sequence of block erasures.
Write FFH after the last block erase operation to place device
in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION COMMAND
SR.1 =
1
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
RP# = VIH, Block Lock-Bit is Set
Only required for systems
implementing lock-bit configuration
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
VPP Range Error
0
Device Protect Error
0
SR.4, 5 =
1
Command Sequence
Error
0
SR.5 =
1
Block Erase
Error
COMMENTS
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple blocks
are erased before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
0
Block Erase
Successful
Fig. 3 Automated Block Erase Flowchart
- 18 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
BUS
OPERATION COMMAND
Start
Write 40H,
Address
Write Word
Data and Address
Read
Status Register
No
0
Suspend Word
Write Loop
Suspend Yes
Word Write
SR.7 =
COMMENTS
Write
Setup
Word Write
Data = 40H
Addr = Location to be Written
Write
Word Write
Data = Data to be Written
Addr = Location to be Written
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent word writes.
SR full status check can be done after each word write or after
a sequence of word writes.
Write FFH after the last word write operation to place device
in read array mode.
1
Full Status
Check if Desired
Word Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION COMMAND
SR.1 =
1
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
RP# = VIH, Block Lock-Bit is Set
Only required for systems
implementing lock-bit configuration
Standby
Check SR.4
1 = Data Write Error
VPP Range Error
0
Device Protect Error
0
SR.4 =
0
1
Word Write Error
COMMENTS
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
Word Write
Successful
Fig. 4 Automated Word Write Flowchart
- 19 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
BUS
OPERATION
Start
Write
Write B0H
Read
Status Register
SR.7 =
0
1
SR.6 =
Erase
Suspend
Data = B0H
Addr = X
Read
Status Register Data
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
Write
0
COMMENTS
COMMAND
Erase
Resume
Data = D0H
Addr = X
Block Erase
Completed
1
Read
Read
or Word
Write?
Read Array Data
Word Write
Word Write Loop
No
Done?
Yes
Write D0H
Write FFH
Block Erase
Resumed
Read
Array Data
Fig. 5 Block Erase Suspend/Resume Flowchart
- 20 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
BUS
OPERATION
Start
Write
Write B0H
Read
Status Register
0
SR.7 =
1
SR.2 =
Word Write
Completed
1
Word Write
Suspend
Data = B0H
Addr = X
Read
Status Register Data
Addr = X
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Word Write Suspended
0 = Word Write Completed
Write
0
COMMENTS
COMMAND
Read Array
Read array locations other
than that being written.
Read
Write
Data = FFH
Addr = X
Word Write
Resume
Data = D0H
Addr = X
Write FFH
Read
Array Data
Done
Reading
No
Yes
Write D0H
Write FFH
Word Write Resumed
Read
Array Data
Fig. 6 Word Write Suspend/Resume Flowchart
- 21 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
BUS
OPERATION
Start
Write 60H,
Block/Device Address
Write
Write 01H/F1H,
Block/Device Address
Write
Read
Status Register
COMMAND
COMMENTS
Set
Block/Permanent
Lock-Bit
Setup
Data = 60H
Addr = Block Address (Block),
Device Address (Parmanent)
Set
Data = 01H (Block),
Block or Permanent
F1H (Parmanent)
Lock-Bit
Addr = Block Address (Block),
Confirm
Device Address (Parmanent)
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
Repeat for subsequent lock-bit set operations.
SR.7 =
Full status check can be done after each lock-bit set
operation or after a sequence of lock-bit set operations.
1
Write FFH after the last lock-bit set operation to place device
in read array mode.
Full Status
Check if Desired
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION COMMAND
SR.1 =
1
1
Command Sequence
Error
Standby
Check SR.1
1 = Device Protect Detect
RP# = VIH
(Set Permanent Lock-Bit Operation)
WP# = VIL and RP# = VIH or
Permanent Lock-Bit is Set
(Set Block Lock-Bit Operation)
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.4
1 = Set Lock-Bit Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple lock-bits are
set before full status is checked.
0
SR.4 =
Check SR.3
1 = VPP Error Detect
Device Protect Error
0
SR.4, 5 =
Standby
VPP Range Error
0
COMMENTS
1
Set Lock-Bit
Error
If error is detected, clear the status register before attempting
retry or other error recovery.
0
Set Lock-Bit
Successful
Fig. 7 Set Block and Permanent Lock-Bit Flowchart
- 22 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
BUS
OPERATION
Start
Write 60H
Write
Clear Block
Lock-Bits
Setup
Data = 60H
Addr = X
Write
Clear Block
Lock-Bits
Confirm
Data = D0H
Addr = X
Write D0H
Read
Status Register
SR.7 =
COMMENTS
COMMAND
Read
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Write FFH after the last clear block lock-bits operation to place
device in read array mode.
0
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
BUS
OPERATION COMMAND
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
WP# = VIL and RP# = VIH or
Permanent Lock-Bit is Set
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Clear Block Lock-Bits Error
1
SR.3 =
VPP Range Error
0
SR.1 =
1
Device Protect Error
0
1
SR.4, 5 =
Command Sequence
Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command.
If error is detected, clear the status register before attempting
retry or other error recovery.
0
SR.5 =
COMMENTS
1
Clear Block Lock-Bits
Error
0
Clear Block Lock-Bits
Successful
Fig. 8 Clear Block Lock-Bits Flowchart
- 23 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
5 DESIGN CONSIDERATIONS
5.1
Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Threeline control provides for :
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2
RY/BY# and Block Erase, Word Write,
and Lock-Bit Configuration Polling
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, word
write and lock-bit configuration completion. It
transitions low after block erase, word write, or lockbit configuration commands and returns to VOH
when the WSM has finished executing the internal
algorithm.
RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also VOH when the device is in
block erase suspend (with word write inactive),
word write suspend or deep power-down modes.
5.3
Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its VCC and GND and between its VPP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between VCC
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4
VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for word writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
5.5
VCC, VPP, RP# Transitions
Block erase, word write and lock-bit configuration
are not guaranteed if VPP falls outside of a valid
VPPH1/2/3 range, VCC falls outside of a valid
VCC1/2/3/4 range, or RP# ≠ VIH or VHH. If VPP error
is detected, status register bit SR.3 is set to "1"
along with SR.4 or SR.5, depending on the
attempted operation. If RP# transitions to VIL during
block erase, word write, or lock-bit configuration,
RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the
device will enter deep power-down. The aborted
operation may leave data partially altered.
Therefore, the command sequence must be
- 24 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
repeated after normal operation is restored. Device
power-off or RP# transitions to VIL clear the status
register.
The CUI latches commands issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep powerdown or after VCC transitions below VLKO.
After block erase, word write, or lock-bit
configuration, even after VPP transitions down to
VPPLK, the CUI must be placed in read array mode
via the Read Array command if subsequent access
to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, word writing, or lock-bit
configuration during power transitions. Upon powerup, the device is indifferent as to which power
supply (VPP or VCC) powers-up first. Internal
circuitry resets the CUI to read array mode at
power-up.
5.7 Power Consumption
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solidstate storage can consume negligible power by
lowering RP# to VIL standby or sleep modes. If
access is again needed, the devices can be read
following the tPHQV and tPHWL wake-up cycles
required after RP# is first raised to VIH. See Section
6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS" and
Fig. 13, Fig. 14 and Fig. 15 for more information.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP# = VIL regardless of its control inputs
state.
- 25 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6 ELECTRICAL SPECIFICATIONS
6.1
NOTICE : The specifications are subject to
change without notice. Verify with your local
SHARP sales office that you have the latest
datasheet before finalizing a design.
Absolute Maximum Ratings∗
Operating Temperature
• LH28F800SG-L
During Read, Block Erase, Word Write,
and Lock-Bit Configuration ........ 0 to +70°C (NOTE 1)
Temperature under Bias............ – 10 to +80°C
• LH28F800SGH-L
During Read, Block Erase, Word Write,
and Lock-Bit Configuration ... –40 to +85°C (NOTE 2)
Temperature under Bias............. –40 to +85°C
∗WARNING : Stressing the device beyond the
"Absolute
Maximum Ratings" may cause
permanent damage. These are stress ratings only.
Operation beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device reliability.
NOTES :
1.
Storage Temperature ........................ –65 to +125°C
Voltage On Any Pin
(except VCC, VPP, and RP#) .... –2.0 to +7.0 V (NOTE 3)
2.
3.
VCC Supply Voltage ................. –2.0 to +7.0 V (NOTE 3)
VPP Update Voltage during
Block Erase, Word Write, and
Lock-Bit Configuration .... –2.0 to +14.0 V (NOTE 3, 4)
4.
5.
RP# Voltage with Respect to
GND during Lock-Bit
Configuration Operations .. –2.0 to +14.0 V (NOTE 3, 4)
Operating temperature is for commercial product defined
by this specification.
Operating temperature is for extended temperature
product defined by this specification.
All specified voltages are with respect to GND. Minimum
DC voltage is –0.5 V on input/output pins and – 0.2 V on
VCC and VPP pins. During transitions, this level may
undershoot to –2.0 V for periods < 20 ns. Maximum DC
voltage on input/output pins and VCC is VCC+0.5 V
which, during transitions, may overshoot to VCC+2.0 V
for periods < 20 ns.
Maximum DC voltage on VPP and RP# may overshoot
to +14.0 V for periods < 20 ns.
Output shorted for no more than one second. No more
than one output shorted at a time.
Output Short Circuit Current .............. 100 mA (NOTE 5)
6.2
Operating Conditions
SYMBOL
PARAMETER
NOTE
1
MIN.
0
MAX.
+70
–40
+85
UNIT
˚C
˚C
TA
Operating Temperature
VCC1
VCC2
VCC Supply Voltage (2.7 to 3.0 V)
VCC Supply Voltage (3.3±0.3 V)
2.7
3.0
3.0
3.6
V
V
VCC3
VCC4
VCC Supply Voltage (5.0±0.25 V)
VCC Supply Voltage (5.0±0.5 V)
4.75
4.50
5.25
5.50
V
V
NOTE :
1.
Test condition : Ambient temperature
- 26 -
VERSIONS
LH28F800SG-L
LH28F800SGH-L
LH28F800SG-L70/SGH-L70
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.1 CAPACITANCE (NOTE 1)
TA = +25˚C, f = 1 MHz
SYMBOL
CIN
COUT
PARAMETER
TYP.
MAX.
UNIT
7
9
10
12
pF
pF
Input Capacitance
Output Capacitance
CONDITION
VIN = 0.0 V
VOUT = 0.0 V
NOTE :
1.
Sampled, not 100% tested.
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7
INPUT
1.35
TEST POINTS
1.35 OUTPUT
0.0
AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 9 Transient Input/Output Reference Waveform for VCC = 2.7 to 3.0 V
3.0
INPUT
1.5
TEST POINTS
1.5
OUTPUT
0.0
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output
timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.
Fig. 10 Transient Input/Output Reference Waveform for VCC = 3.3±0.3 V and
VCC = 5.0±0.25 V (High Speed Testing Configuration)
2.4
2.0
INPUT
0.45
2.0
TEST POINTS
0.8
OUTPUT
0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing
begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to
90%) < 10 ns.
Fig. 11 Transient Input/Output Reference Waveform for
VCC = 5.0±0.5 V (Standard Testing Configuration)
- 27 -
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
Test Configuration Capacitance Loading Value
1.3 V
TEST CONFIGURATION
VCC = 3.3±0.3 V, 2.7 to 3.0 V
VCC = 5.0±0.25 V (NOTE 1)
1N914
VCC = 5.0±0.5 V
CL (pF)
50
30
100
NOTE :
RL = 3.3 kΩ
DEVICE
UNDER
TEST
1.
OUT
CL
CL Includes Jig
Capacitance
Fig. 12 Transient Equivalent Testing
Load Circuit
- 28 -
Applied to high-speed products, LH28F800SG-L70 and
LH28F800SGH-L70.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.3 DC CHARACTERISTICS
ILI
Input Load Current
1
±0.5
±1
µA
ILO
Output Leakage Current
1
±0.5
±10
µA
100
100
µA
2
2
mA
12
16
µA
25
50
mA
30
65
mA
—
35
30
—
30
25
mA
mA
mA
mA
mA
mA
TEST
CONDITIONS
VCC = VCC Max.
VIN = VCC or GND
VCC = VCC Max.
VOUT = VCC or GND
CMOS Inputs
VCC = VCC Max.
CE# = RP# = VCC±0.2 V
TTL Inputs
VCC = VCC Max.
CE# = RP# = VIH
RP# = GND±0.2 V
IOUT (RY/BY#) = 0 mA
CMOS Inputs
VCC = VCC Max.
CE# = GND
f = 5 MHz (3.3 V, 2.7 V),
8 MHz (5 V)
IOUT = 0 mA
TTL Inputs
VCC = VCC Max.
CE# = GND
f = 5 MHz (3.3 V, 2.7 V),
8 MHz (5 V)
IOUT = 0 mA
VPP = 2.7 to 3.6 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
VPP = 2.7 to 3.6 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
SYMBOL
ICCS
ICCD
ICCR
ICCW
ICCE
PARAMETER
VCC Standby Current
VCC Deep Power-Down
Current
VCC Read Current
VCC Word Write or
Set Lock-Bit Current
VCC Block Erase or
Clear Block Lock-Bits
Current
VCC Word Write or Block
Erase Suspend Current
ICCWS
ICCES
IPPS
VPP Standby or Read Current
IPPR
VPP Deep Power-Down
IPPD
Current
IPPW
IPPE
IPPWS
IPPES
VPP Word Write or
Set Lock-Bit Current
VPP Block Erase or
Clear Block Lock-Bits
Current
VPP Word Write or Block
Erase Suspend Current
NOTE
VCC = 2.7 to 3.6 V
TYP.
MAX.
VCC = 5.0±0.5 V
UNIT
TYP.
MAX.
1, 3, 6
1
1, 5, 6
1, 7
1, 7
17
17
12
17
17
12
—
—
1, 2
6
10
mA
CE# = VIH
1
±15
200
±15
200
µA
µA
VPP ≤ VCC
VPP > VCC
1
5
5
µA
RP# = GND±0.2 V
—
80
30
—
40
30
mA
mA
mA
mA
mA
mA
VPP
VPP
VPP
VPP
VPP
VPP
200
µA
VPP = VPPH1/2/3
1, 7
1, 7
1
80
80
30
40
40
30
200
- 29 -
—
—
=
=
=
=
=
=
2.7 to 3.6 V
5.0±0.5 V
12.0±0.6 V
2.7 to 3.6 V
5.0±0.5 V
12.0±0.6 V
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL
PARAMETER
NOTE
VCC = 2.7 to 3.6 V VCC = 5.0±0.5 V
UNIT
MIN.
MAX.
MIN.
MAX.
–0.5
0.8
–0.5
0.8
V
VCC
VCC
2.0
2.0
V
+0.5
+0.5
VIL
Input Low Voltage
7
VIH
Input High Voltage
7
VOL
Output Low Voltage
3, 7
VOH1
Output High Voltage
(TTL)
3, 7
2.4
2.4
VOH2
Output High Voltage
(CMOS)
3, 7
0.85
VCC
VCC
–0.4
0.85
VCC
VCC
–0.4
VLKO
VPP Lockout Voltage during
Normal Operations
VPP Voltage during
Word Write, Block Erase
or Lock-Bit Operations
VPP Voltage during
Word Write, Block Erase
or Lock-Bit Operations
VPP Voltage during
Word Write, Block Erase
or Lock-Bit Operations
VCC Lockout Voltage
VHH
RP# Unlock Voltage
VPPLK
VPPH1
VPPH2
VPPH3
0.4
4, 7
1.5
V
V
V
V
1.5
V
2.7
3.6
—
—
V
4.5
5.5
4.5
5.5
V
11.4
12.6
11.4
12.6
V
2.0
8
0.45
2.0
11.4
12.6
11.4
TEST
CONDITIONS
VCC = VCC Min.
IOL = 5.8 mA (VCC = 5 V),
IOL = 2.0 mA (VCC = 3.3 V, 2.7 V)
VCC = VCC Min.
IOH = –2.5 mA (VCC = 5 V),
IOH = –2.0 mA (VCC = 3.3 V, 2.7 V)
VCC = VCC Min.
IOH = –2.5 µA
VCC = VCC Min.
IOH = –100 µA
V
12.6
V
Set permanent lock-bit
Override block lock-bit
NOTES :
1.
2.
3.
4.
All currents are in RMS unless otherwise noted. Typical
values at nominal VCC voltage and TA = +25°C. These
currents are valid for all product versions (packages and
speeds).
ICCWS and ICCES are specified with the device deselected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of ICCWS or
ICCES and ICCR or ICCW, respectively.
Includes RY/BY#.
Block erases, word writes, and lock-bit configurations are
inhibited when VPP ≤ VPPLK, and not guaranteed in the
range between VPPLK (max.) and VPPH1 (min.), between
VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.)
and VPPH3 (min.), and above VPPH3 (max.).
5.
6.
7.
8.
- 30 -
Automatic Power Saving (APS) reduces typical ICCR to
1 mA at 5 V VCC and 3 mA at 2.7 to 3.6 V VCC in static
operation.
CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL
inputs are either VIL or VIH.
Sampled, not 100% tested.
Permanent lock-bit set operations are inhibited when
RP# = VIH. Block lock-bit configuration operations are
inhibited when the permanent lock-bit is set or RP# =
VIH and WP# = VIL. Block erases and word writes are
inhibited when the corresponding block lock-bit is set
and RP# = VIH and WP# = VIL or the permanent lock-bit
is set. Block erase, word write, and lock-bit configuration
operations are not guaranteed with VIH < RP# < VHH
and should not be attempted.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800SG-L70
LH28F800SGH-L70
VERSIONS
SYMBOL
PARAMETER
NOTE
tAVAV
tAVQV
Read Cycle Time
Address to Output Delay
tELQV
tPHQV
CE# to Output Delay
RP# High to Output Delay
tGLQV
OE# to Output Delay
2
tELQX
CE# to Output in Low Z
3
tEHQZ
CE# High to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# High to Output in High Z
3
tOH
Output Hold from Address, CE# or
OE# Change, Whichever Occurs First
3
MIN.
MAX.
100
2
LH28F800SG-L10
LH28F800SGH-L10 UNIT
MIN.
MAX.
120
100
120
ns
ns
100
600
120
600
ns
ns
50
ns
45
0
0
45
0
ns
55
0
20
0
ns
ns
25
0
ns
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800SG-L70
VERSIONS
SYMBOL
PARAMETER
LH28F800SGH-L70
NOTE
tAVAV
tAVQV
tELQV
Read Cycle Time
Address to Output Delay
CE# to Output Delay
tPHQV
RP# High to Output Delay
tGLQV
tELQX
OE# to Output Delay
CE# to Output in Low Z
2
3
tEHQZ
CE# High to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# High to Output in High Z
3
tOH
Output Hold from Address, CE# or
OE# Change, Whichever Occurs First
3
MIN.
MAX.
85
2
LH28F800SG-L10
LH28F800SGH-L10 UNIT
MIN.
85
85
100
100
ns
ns
ns
600
600
ns
45
ns
ns
40
0
0
40
0
45
0
15
0
0
See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
Sampled, not 100% tested.
- 31 -
ns
ns
20
NOTES :
1.
2.
3.
MAX.
100
ns
ns
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.4 AC CHARACTERISTICS - READ ONLY OPERATIONS (contd.) (NOTE 1)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
(NOTE 4)
VERSIONS
VCC±0.25 V LH28F800SG-L70
LH28F800SGH-L70
(NOTE 5)
SYMBOL
PARAMETER
tAVAV
Read Cycle Time
NOTE
tAVQV
tELQV
Address to Output Delay
CE# to Output Delay
tPHQV
RP# High to Output Delay
tGLQV
tELQX
OE# to Output Delay
CE# to Output in Low Z
2
3
tEHQZ
CE# High to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE# High to Output in High Z
3
tOH
Output Hold from Address,
CE# or OE# Change,
3
UNIT
(NOTE 5)
LH28F800SG-L70 LH28F800SG-L10
LH28F800SGH-L70 LH28F800SGH-L10
VCC±0.5 V
MIN.
70
MAX.
2
MIN.
80
MAX.
MAX.
ns
70
70
80
80
100
100
400
400
400
ns
40
45
50
ns
ns
55
ns
0
0
55
0
0
55
0
10
0
MIN.
100
0
10
0
ns
15
0
ns
ns
ns
ns
Whichever Occurs First
NOTES :
1.
2.
3.
4.
See AC Input/Output Reference Waveform (Fig. 9
through Fig. 11) for maximum allowable input slew rate.
OE# may be delayed up to tELQV-tGLQV after the falling
edge of CE# without impact on tELQV.
Sampled, not 100% tested.
See Fig. 10 "Transient Input/Output Reference
Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (High Speed Configuration) for testing
characteristics.
5.
- 32 -
See Fig. 11 "Transient Input/Output Reference
Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
Standby
Device
Address Selection
Data Valid
VIH
Address Stable
ADDRESSES (A)
VIL
tAVAV
VIH
CE# (E)
VIL
OE# (G)
tEHQZ
VIH
tGHQZ
VIL
tELQV
VIH
tGLQV
WE# (W)
VIL
tGLQX
tOH
tELQX
DATA (D/Q)
(DQ0 - DQ15)
VOH
High Z
Valid Output
VOL
tAVQV
VCC
tPHQV
VIH
RP# (P)
VIL
Fig. 13 AC Waveform for Read Operations
- 33 -
High Z
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800SG-L70
LH28F800SGH-L70
SYMBOL
PARAMETER
NOTE
MIN.
MAX.
tAVAV
Write Cycle Time
100
tPHWL
RP# High Recovery to WE# Going Low
2
1
tELWL
CE# Setup to WE# Going Low
10
tWLWH WE# Pulse Width
50
tPHHWH RP# VHH Setup to WE# Going High
2
100
tVPWH VPP Setup to WE# Going High
2
100
tAVWH Address Setup to WE# Going High
3
50
tDVWH Data Setup to WE# Going High
3
50
tWHDX Data Hold from WE# High
5
tWHAX Address Hold from WE# High
5
tWHEH CE# Hold from WE# High
10
tWHWL WE# Pulse Width High
30
tWHRL
WE# High to RY/BY# Going Low
100
tWHGL Write Recovery before Read
0
tQVVL
VPP Hold from Valid SRD, RY/BY# High
2, 4
0
0
RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
tQVPH
VERSIONS
LH28F800SG-L10
LH28F800SGH-L10 UNIT
MIN.
MAX.
120
ns
1
µs
10
ns
50
ns
100
ns
100
ns
50
ns
50
ns
5
ns
5
ns
10
ns
30
ns
100
ns
0
ns
0
ns
0
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800SG-L70
LH28F800SGH-L70
SYMBOL
PARAMETER
NOTE
MIN.
MAX.
tAVAV
Write Cycle Time
85
tPHWL
RP# High Recovery to WE# Going Low
2
1
tELWL
CE# Setup to WE# Going Low
10
tWLWH WE# Pulse Width
50
tPHHWH RP# VHH Setup to WE# Going High
2
100
tVPWH VPP Setup to WE# Going High
2
100
tAVWH Address Setup to WE# Going High
3
50
tDVWH Data Setup to WE# Going High
3
50
tWHDX Data Hold from WE# High
5
tWHAX Address Hold from WE# High
5
tWHEH CE# Hold from WE# High
10
tWHWL WE# Pulse Width High
30
tWHRL
WE# High to RY/BY# Going Low
100
tWHGL Write Recovery before Read
0
tQVVL
VPP Hold from Valid SRD, RY/BY# High
2, 4
0
tQVPH
RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
0
VERSIONS
LH28F800SG-L10
LH28F800SGH-L10 UNIT
MIN.
MAX.
100
ns
1
µs
10
ns
50
ns
100
ns
100
ns
50
ns
50
ns
5
ns
5
ns
10
ns
30
ns
100
ns
0
ns
0
ns
0
ns
NOTES :
1.
2.
Read timing characteristics during block erase, word
write and lock-bit configuration operations are the same
as during read-only operations. Refer to Section 6.2.4
"AC CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
3.
4.
- 34 -
Refer to Table 3 for valid AIN and DIN for block erase,
word write, or lock-bit configuration.
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase,
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.5 AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (contd.) (NOTE 1)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
(NOTE 5)
VERSIONS
VCC±0.25 V LH28F800SG-L70
LH28F800SGH-L70
(NOTE 6)
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHWL
RP# High Recovery to WE#
Going Low
tELWL
CE# Setup to WE# Going Low
NOTE
UNIT
(NOTE 6)
LH28F800SG-L70 LH28F800SG-L10
LH28F800SGH-L70 LH28F800SGH-L10
VCC±0.5 V
MIN.
70
MAX.
MIN.
80
MAX.
MAX.
ns
2
1
10
10
10
ns
tWLWH WE# Pulse Width
tPHHWH RP# VHH Setup to WE# Going High
2
40
100
40
100
40
100
ns
ns
tVPWH
VPP Setup to WE# Going High
2
100
100
100
ns
tAVWH
Address Setup to WE# Going High
3
40
40
40
ns
tDVWH
Data Setup to WE# Going High
3
40
40
40
ns
tWHDX
tWHAX
Data Hold from WE# High
Address Hold from WE# High
5
5
5
5
5
5
ns
ns
tWHEH
tWHWL
CE# Hold from WE# High
WE# Pulse Width High
10
30
10
30
10
30
ns
ns
tWHRL
WE# High to RY/BY# Going Low
tWHGL
Write Recovery before Read
tQVVL
tQVPH
VPP Hold from Valid SRD,
RY/BY# High
RP# VHH Hold from Valid SRD,
RY/BY# High
1
MIN.
100
90
1
90
µs
90
ns
0
0
0
ns
2, 4
0
0
0
ns
2, 4
0
0
0
ns
NOTES :
1.
2.
3.
4.
Read timing characteristics during block erase, word
write and lock-bit configuration operations are the same
as during read-only operations. Refer to Section 6.2.4
"AC CHARACTERISTICS" for read-only operations.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase,
word write, or lock-bit configuration.
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase,
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).
5.
6.
- 35 -
See Fig. 10 "Transient Input/Output Reference
Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (High Speed Configuration) for testing
characteristics.
See Fig. 11 "Transient Input/Output Reference
Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
(NOTE 1)
(NOTE 2)
(NOTE 3)
AIN
AIN
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
ADDRESSES (A)
VIL
tAVWH
tAVAV
tWHAX
VIH
CE# (E)
VIL
tELWL
tWHEH
tWHGL
VIH
OE# (G)
VIL
tWHWL
tWHQV1/2/3/4
VIH
WE# (W)
tWLWH
tDVWH
tWHDX
VIL
VIH
DATA (D/Q)
High Z
VIL
DIN
DIN
tPHWL
Valid
SRD
tWHRL
VOH
RY/BY# (R)
VOL
tSHWH
tQVSL
VIH
WP# (S)
VIL
VIH
RP# (P)
VIL
tVPWH
tQVVL
VPPH1/2/3
VPP (V) VPPLK
VIL
NOTES :
1.
2.
3.
4.
5.
6.
VCC power-up and standby.
Write block erase or word write setup.
Write block erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
Fig. 14 AC Waveform for WE#-Controlled Write Operations
- 36 -
DIN
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800SG-L70
LH28F800SGH-L70
SYMBOL
PARAMETER
NOTE
MIN.
MAX.
tAVAV
Write Cycle Time
100
tPHEL
RP# High Recovery to CE# Going Low
2
1
tWLEL
WE# Setup to CE# Going Low
0
tELEH
CE# Pulse Width
70
tPHHEH RP# VHH Setup to CE# Going High
2
100
tVPEH
VPP Setup to CE# Going High
2
100
tAVEH
Address Setup to CE# Going High
3
50
tDVEH
Data Setup to CE# Going High
3
50
tEHDX
Data Hold from CE# High
5
tEHAX
Address Hold from CE# High
5
tEHWH WE# Hold from CE# High
0
tEHEL
CE# Pulse Width High
25
tEHRL
CE# High to RY/BY# Going Low
100
tEHGL
Write Recovery before Read
0
tQVVL
VPP Hold from Valid SRD, RY/BY# High
2, 4
0
tQVPH
RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
0
VERSIONS
LH28F800SG-L10
LH28F800SGH-L10 UNIT
MIN.
MAX.
120
ns
1
µs
0
ns
70
ns
100
ns
100
ns
50
ns
50
ns
5
ns
5
ns
0
ns
25
ns
100
ns
0
ns
0
ns
0
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
LH28F800SG-L70
LH28F800SGH-L70
SYMBOL
PARAMETER
NOTE
MIN.
MAX.
tAVAV
Write Cycle Time
85
tPHEL
RP# High Recovery to CE# Going Low
2
1
tWLEL
WE# Setup to CE# Going Low
0
tELEH
CE# Pulse Width
70
tPHHEH RP# VHH Setup to CE# Going High
2
100
tVPEH
VPP Setup to CE# Going High
2
100
tAVEH
Address Setup to CE# Going High
3
50
tDVEH
Data Setup to CE# Going High
3
50
tEHDX
Data Hold from CE# High
5
tEHAX
Address Hold from CE# High
5
tEHWH WE# Hold from CE# High
0
tEHEL
CE# Pulse Width High
25
tEHRL
CE# High to RY/BY# Going Low
100
tEHGL
Write Recovery before Read
0
tQVVL
VPP Hold from Valid SRD, RY/BY# High
2, 4
0
RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
0
tQVPH
VERSIONS
LH28F800SG-L10
LH28F800SGH-L10 UNIT
MIN.
MAX.
100
ns
1
µs
0
ns
70
ns
100
ns
100
ns
50
ns
50
ns
5
ns
5
ns
0
ns
25
ns
100
ns
0
ns
0
ns
0
ns
NOTES :
1.
2.
In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
Sampled, not 100% tested.
3.
4.
- 37 -
Refer to Table 3 for valid AIN and DIN for block erase,
word write, or lock-bit configuration.
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase,
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS (contd.)
(NOTE 1)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
(NOTE 5)
VERSIONS
VCC±0.25 V LH28F800SG-L70
LH28F800SGH-L70
(NOTE 6)
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHEL
RP# High Recovery to CE#
Going Low
tWLEL
tELEH
tPHHEH
NOTE
UNIT
(NOTE 6)
LH28F800SG-L70 LH28F800SG-L10
LH28F800SGH-L70 LH28F800SGH-L10
VCC±0.5 V
MIN.
70
MAX.
MIN.
80
MAX.
MAX.
ns
2
1
WE# Setup to CE# Going Low
0
0
0
ns
CE# Pulse Width
RP# VHH Setup to CE# Going High
2
50
100
50
100
50
100
ns
ns
tVPEH
VPP Setup to CE# Going High
2
100
100
100
ns
tAVEH
Address Setup to CE# Going High
3
40
40
40
ns
tDVEH
Data Setup to CE# Going High
3
40
40
40
ns
tEHDX
tEHAX
Data Hold from CE# High
Address Hold from CE# High
5
5
5
5
5
5
ns
ns
tEHWH
tEHEL
WE# Hold from CE# High
CE# Pulse Width High
0
25
0
25
0
25
ns
ns
tEHRL
CE# High to RY/BY# Going Low
tEHGL
Write Recovery before Read
tQVVL
tQVPH
VPP Hold from Valid SRD,
RY/BY# High
RP# VHH Hold from Valid SRD,
RY/BY# High
1
MIN.
100
90
1
90
µs
90
ns
0
0
0
ns
2, 4
0
0
0
ns
2, 4
0
0
0
ns
NOTES :
1.
2.
3.
4.
In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
Sampled, not 100% tested.
Refer to Table 3 for valid AIN and DIN for block erase,
word write, or lock-bit configuration.
VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase,
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).
5.
6.
- 38 -
See Fig. 10 "Transient Input/Output Reference
Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (High Speed Configuration) for testing
characteristics.
See Fig. 11 "Transient Input/Output Reference
Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
(NOTE 1)
(NOTE 2)
(NOTE 3)
AIN
AIN
(NOTE 4)
(NOTE 5)
(NOTE 6)
VIH
ADDRESSES (A)
VIL
tAVEH
tAVAV
tEHAX
VIH
WE# (W)
VIL
tWLEL
tEHWH
tWHGL
VIH
OE# (G)
VIL
tEHEL
tEHQV1/2/3/4
VIH
CE# (E)
tELEH
tDVEH
tEHDX
VIL
VIH
DATA (D/Q)
High Z
VIL
DIN
DIN
tPHEL
Valid
SRD
tEHRL
VOH
RY/BY# (R)
VOL
tSHEH
tQVSL
VIH
WP# (S)
VIL
VIH
RP# (P)
VIL
tVPEH
tQVVL
VPPH1/2/3
VPP (V) VPPLK
VIL
NOTES :
1.
2.
3.
4.
5.
6.
VCC power-up and standby.
Write block erase or word write setup.
Write block erase confirm or valid address and data.
Automated erase or program delay.
Read status register data.
Write Read Array command.
Fig. 15 AC Waveform for CE#-Controlled Write Operations
- 39 -
DIN
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.7 RESET OPERATIONS
VOH
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
tPLPH
(A) Reset During Read Array Mode
VOH
RY/BY# (R)
VOL
tPLRH
VIH
RP# (P)
VIL
tPLPH
(B) Reset During Block Erase, Word Write, or Lock-Bit Configuration
2.7 V/3.3 V/5 V
VCC
VIL
t235VPH
VIH
RP# (P)
VIL
(C) VCC Rising Timing
Fig. 16 AC Waveform for Reset Operation
Reset AC Specifications (NOTE 1)
SYMBOL
PARAMETER
tPLPH
RP# Pulse Low Time (If RP# is tied to VCC,
this specification is not applicable)
tPLRH
RP# Low to Reset during Block Erase,
Word Write or Lock-Bit Configuration
NOTE
VCC = 2.7 to 3.6 V
MIN.
MAX.
100
4
100
MAX.
100
20
28 (2.7 V VCC)
2, 3
VCC 2.7 V to RP# High
t235VPH VCC 3.0 V to RP# High
VCC = 5.0±0.5 V
MIN.
ns
12
100
UNIT
µs
ns
VCC 4.5 V to RP# High
NOTES :
1.
2.
These specifications are valid for all product versions
(packages and speeds).
If RP# is asserted while a block erase, word write, or
lock-bit configuration operation is not executing, the reset
will complete within 100 ns.
3.
4.
- 40 -
A reset time, tPHQV, is required from the latter of RY/BY#
or RP# going high until outputs are valid.
When the device power-up, holding RP#-low minimum
100 ns is required after VCC has been in predefined
range and also has been in stable there.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.8 BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (NOTE 3, 4)
• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or –40 to +85˚C
VPP = 2.7 to 3.0 V
SYMBOL
PARAMETER
NOTE
MIN. TYP.(NOTE 1) MAX.
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
UNIT
tWHQV1
Word Write Time
tEHQV1
2
49
63
20
28
15.4
µs
Block Write Time
2
1.7
2.1
0.7
1.0
0.56
s
Block Erase Time
2
3.0
2.0
1.9
s
tWHQV3
Set Lock-Bit Time
tEHQV3
2
44
28
24.4
µs
tWHQV4 Clear Block Lock-Bits
tEHQV4 Time
2
3.8
2.6
2.3
s
12.6
10.5
10.5
µs
34.1
20.2
20.2
µs
tWHQV2
tEHQV2
tWHRH1 Word Write Suspend
tEHRH1 Latency Time to Read
tWHRH2 Erase Suspend Latency
tEHRH2
Time to Read
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
SYMBOL
tWHQV1
tEHQV1
tWHQV2
tEHQV2
tWHQV3
PARAMETER
VPP = 3.3±0.3 V
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
UNIT
Word Write Time
2
35
45
14
20
11
µs
Block Write Time
2
1.2
1.5
0.5
0.7
0.4
s
Block Erase Time
2
2.1
1.4
1.3
s
2
31
20
17.4
µs
2
2.7
1.8
1.6
s
9
7.5
7.5
µs
24.3
14.4
14.4
µs
Set Lock-Bit Time
tEHQV3
tWHQV4 Clear Block Lock-Bits
tEHQV4 Time
tWHRH1 Word Write Suspend
tEHRH1
NOTE
Latency Time to Read
tWHRH2 Erase Suspend Latency
tEHRH2 Time to Read
NOTES :
1.
2.
Typical values measured at TA = +25˚C and nominal
voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
Excludes system-level overhead.
3.
4.
- 41 -
These performance numbers are valid for all speed
versions.
Sampled, not 100% tested.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.8 BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (contd.) (NOTE 3, 4)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
SYMBOL
PARAMETER
NOTE
VPP = 5.0±0.5 V
VPP = 12.0±0.6 V
MIN. TYP.(NOTE 1) MAX.
MIN. TYP.(NOTE 1) MAX.
UNIT
tWHQV1
Word Write Time
tEHQV1
2
10
14
7.5
µs
Block Write Time
2
0.4
0.5
0.25
s
Block Erase Time
2
1.3
1.2
s
tWHQV3
Set Lock-Bit Time
tEHQV3
2
18
15
µs
tWHQV4
Clear Block Lock-Bits Time
tEHQV4
2
1.6
1.5
s
7.5
6
µs
14.4
14.4
µs
tWHQV2
tEHQV2
tWHRH1
Word Write Suspend Latency Time to Read
tEHRH1
tWHRH2
tEHRH2
Erase Suspend Latency Time to Read
NOTES :
1.
2.
Typical values measured at TA = +25˚C and nominal
voltages. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
Excludes system-level overhead.
3.
4.
- 42 -
These performance numbers are valid for all speed
versions.
Sampled, not 100% tested.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
7 ORDERING INFORMATION
Product line designator for all SHARP Flash products
L H 2 8 F 8 0 0 S G (H) E - L 7 0
Device Density
800 = 8 M-bit
Access Speed (ns)
70 : 70 ns (5.0±0.25 V), 80 ns (5.0±0.5 V),
85 ns (3.3±0.3 V), 100 ns (2.7 to 3.0 V)
10 : 100 ns (5.0±0.5 V), 100 ns (3.3±0.3 V),
120 ns (2.7 to 3.0 V)
Architecture
S = Symmetrical Block
Package
E = 48-pin TSOP (I) (TSOP048-P-1220) Normal bend
R = 48-pin TSOP (I) (TSOP048-P-1220) Reverse bend
B = 48-ball CSP (FBGA048-P-0808)
Power Supply Type
G = SmartVoltage Technology
Operating Temperature
Blank = 0 to +70°C
H = – 40 to +85°C
VALID OPERATIONAL COMBINATIONS
VCC = 2.7 to 3.0 V
50 pF load,
VCC = 3.3±0.3 V
50 pF load,
VCC = 5.0±0.5 V
100 pF load,
VCC = 5.0±0.25 V
30 pF load,
1.5 V I/O Levels
70 ns
OPTION
ORDER CODE
1
LH28F800SGXX-L70
1.35 V I/O Levels
100 ns
1.5 V I/O Levels
85 ns
TTL I/O Levels
80 ns
2
LH28F800SGXX-L10
120 ns
100 ns
100 ns
- 43 -
PACKAGING
48
24
0.1
12.0 ±0.2
0.10
0.5 TYP.
M
1
48 _ 0.2±0.08
48 TSOP (TSOP048-P-1220)
25
1.2MAX.
1.0 ±0.1
0.125
18.4 ±0.2
Package base plane
19.0 ±0.1
0.1±0.1
0.125 ±0.05
20.0±0.3
PACKAGING
48 CSP (FBGA048-P-0808)
A
8.00
+ 0.2
B
1.2MAX.
/ / 0.1 S
∗0.4TYP.
S
∗Land hole diameter
0.35±0.05
for ball mounting
+0.2
8.00
0.1 S
2.0TYP.
0.4TYP.
0.4TYP.
0.8TYP.
C
0.8TYP.
F
D
A
8
1
1.2TYP.
0.45±0.03
0.30
M
S
AB
0.15
M
S
CD