LINER LT1161IN Quad protected high-side mosfet driver Datasheet

LT1161
Quad Protected High-Side
MOSFET Driver
U
FEATURES
■
■
■
■
■
■
■
■
■
■
DESCRIPTIO
8V to 48V Power Supply Range
Protected from – 15V to 60V Supply Transients
Fully Enhances N-Channel MOSFET Switches
Individual Short-Circuit Protection
Individual Automatic Restart Timers
Programmable Current Limit, Delay Time, and
Auto-Restart Period
Voltage-Limited Gate Drive
Defaults to OFF State with Open Input
Flowthrough Input to Output Pinout
Available in 20-Lead DIP or SOL Package
The LT1161 is a quad high-side gate driver allowing the
use of low cost N-channel power MOSFETs for high-side
switching applications. It has four independent switch
channels, each containing a completely self-contained
charge pump to fully enhance an N-channel MOSFET
switch with no external components.
Also included in each switch channel is a drain sense
comparator that is used to sense switch current. When a
preset current level is exceeded, the switch is turned off.
The switch remains off for a period of time set by an
external timing capacitor and then automatically attempts
to restart. If the fault is still present, this cycle repeats until
the fault is removed, thus protecting the MOSFET.
U
APPLICATIO S
■
■
■
■
■
The LT1161 has been specifically designed for harsh
operating environments such as industrial, avionics, and
automotive applications where poor supply regulation
and/or transients may be present. The device will not
sustain damage from supply voltages of –15V to 60V.
Industrial Control
Avionics Systems
Automotive Switches
Stepper Motor and DC Motor Control
Electronic Circuit Breaker
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
24V
+
0.1µF
0.1µF
0.1µF
INPUTS
T1
DS1
RS
0.01Ω
T2
G1
IRFZ34
V+
V+
IN1
IN2
IN3
IN4
GND
GND
0.50
0.45
DS2
T3
T4
Switch Drop vs Load Current
50µF
50V
LT1161
G2
0.01Ω
LOAD
#1
IRFZ34
DS3
0.01Ω
G3
IRFZ34
DS4
0.01Ω
G4
IRFZ34
LOAD
#2
0.40
TOTAL DROP (V)
CT
0.1µF
0.35
0.30
0.25
0.20
0.15
LOAD
#3
0.10
0.05
0
LOAD
#4
0
1
3
2
LOAD CURRENT (A)
4
5
1161 TA01
1161 F01
Figure 1. Protected Quad High-Side Switch
1161fa
1
LT1161
U
W
U
W W
U
W
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
Supply Voltages (Pins 11, 20) ................... – 15V to 60V
Input Voltages (Pins 3, 5, 7, 9) ...... (GND – 0.3V) to 15V
Gate Voltages (Pins 12, 14, 16, 18) ........................ 75V
Sense Voltages (Pins 13, 15, 17, 19) ................. V + ±5V
Current (Any Pin) .................................................. 50mA
Operating Temperature Range
LT1161C ............................................... 0°C to 70°C
LT1161I ............................................ – 40°C to 85°C
Junction Temperature Range (Note 1)
LT1161C .............................................. 0°C to 125°C
LT1161I ......................................... – 40°C to 150°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
GND
1
20 V +
TIMER1
2
19 SENSE 1
INPUT 1
3
18 GATE 1
TIMER 2
4
17 SENSE 2
INPUT 2
5
16 GATE 2
TIMER 3
6
15 SENSE 3
INPUT 3
7
14 GATE 3
TIMER 4
8
13 SENSE 4
INPUT 4
9
12 GATE 4
GND 10
11 V +
N PACKAGE
20-LEAD PLASTIC DIP
SW PACKAGE
20-LEAD PLASTIC SO
LT1161CN
LT1161CSW
LT1161IN
LT1161ISW
θJA = 70°C/ W (N)
θJA = 110°C/ W (S)
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V + = 12V to 48V each channel, unless otherwise noted.
SYMBOL
IS
∆IS(ON)
VINH
VINL
IIN
PARAMETER
Supply Current
Delta Supply Current (ON State)
Input High Voltage
Input Low Voltage
Input Current
CIN
VT(TH)
VT(CL)
IT
VSEN
Input Capacitance
Timer Threshold Voltage
Timer Clamp Voltage
Timer Charge Current
Drain Sense Threshold Voltage
Temperature Coefficient
Drain Sense Input Current
Gate Voltage Above Supply
ISEN
VGATE – V +
tON
tOFF
tOFF(CL)
Turn-ON Time
Turn-OFF Time
Current Limit Turn-OFF Time
CONDITIONS
All Channels OFF (Note 2)
Measure Increase in IS per Channel
MIN
3
●
TYP
4.5
1
2
●
VIN = 2V
VIN = 5V
●
●
15
55
VIN = 2V, Adjust V T
VIN = 0.8V
VIN = V T = 2V
●
2.7
3.2
9
50
V + = 48V, VSEN = 65mV
V + = 8V
V + = 12V
V + = 24V
V + = 48V
V + = 24V, VGATE > 32V, CGATE = 1000pF
V + = 24V, VGATE < 2V, CGATE = 1000pF
V + = 24V, (V + – VSENSE ) → 0.1V, CGATE = 1000pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
●
●
●
MAX
6.5
1.35
4
7
10
10
100
30
110
5
3
3.5
14
65
+0.33
0.5
4.5
8.5
12
12
220
75
25
0.8
50
185
3.3
3.8
20
80
1.5
6
10
14
14
400
200
50
UNITS
mA
mA
V
V
µA
µA
pF
V
V
µA
mV
%/°C
µA
V
V
V
V
µs
µs
µs
Note 2: Both V + pins (11, 20) must be connected together and both
ground pins (1, 10) must be connected together.
1161fa
2
LT1161
U W
TYPICAL PERFORMANCE CHARACTERISTICS
MOSFET Gate Voltage Above V +
20
16
18
14
TJ = 85°C
12
14
TJ = –40°C
VGATE – V +
SUPPLY CURRENT (mA)
16
MOSFET Gate Drive Current
100
GATE DRIVE CURRENT (µA)
Supply Current
12
ALL CHANNELS ON
10
8
ALL CHANNELS OFF
6
10
TJ = 25°C
8
6
4
4
10
30
20
INPUT VOLTAGE (V)
40
0
50
10
20
30
INPUT VOLTAGE (V)
40
12
ALL CHANNELS ON
8
6
ALL CHANNELS OFF
4
2
2.0
1.8
TURN-ON
1.6
1.4
TURN-OFF
1.2
1.0
0.8
0.6
0
–50
–25
25
50
0
TEMPERATURE (°C)
0.4
–50
100
75
–25
25
50
0
TEMPERATURE (°C)
90
80
70
60
50
40
30
20
–25
25
50
0
TEMPERATURE (°C)
75
Turn-ON Time Driving MOSFET
Turn-OFF Time Driving MOSFET
Automatic Restart Period
100
IRFZ34
1000
IRFZ34
90
100
1161 G06
1161 G05
500
16
V + = 24V
100
10
–50
100
75
1161 G04
450
4
8
6
10 12 14
GATE VOLTAGE ABOVE V + (V)
Drain Sense Threshold Voltage
DRAIN SENSE THRESHOLD VOLTAGE (mV)
INPUT THRESHOLD VOLTAGE (V)
SUPPLY CURRENT (mA)
14
2
1161 G03
110
V + = 24V
2.2
16
10
0
Input Threshold Voltage
2.4
V + = 24V
18
50
1161 G02
Supply Current
20
V + = 24V
CT = 3.3µF
80
350
300
250
200
150
70
60
40
30
20
50
10
10
30
20
INPUT VOLTAGE (V)
40
50
1161 G07
NORMAL
50
100
0
RESTART PERIOD (ms)
TURN-OFF TIME (µs)
400
TURN-ON TIME (µs)
V + = 8V
1
0.1
0
0
1161 G01
0
V + = 12V
2
2
0
V + ≥ 24V
10
0
CURRENT LIMIT
CT = 1µF
100
CT = 0.33µF
CT = 0.1µF
0
10
30
20
INPUT VOLTAGE (V)
40
50
10
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1161 G08
1161 G09
1161fa
3
LT1161
U
U
U
PIN FUNCTIONS
Supply Pins: The two supply pins are internally connected
and must also be externally connected. In addition to
providing the operating current for the LT1161, the supply
pins also serve as the Kelvin connection for the current
sense comparators. The supply pins must be connected to
the positive side of the drain sense resistors for proper
operation of the current sense.
Input Pins: The input pins are active high and each pin
activates a separate internal charge pump when switched
ON. The input threshold is TTL/CMOS compatible but may
be taken as high as 15V with or without the supply
powered. Each input has approximately 200mV of hysteresis and an internal 75k pull-down resistor.
Gate Pins: The gate pins drive the power MOSFET gates.
When an input is ON, the corresponding gate pin is
pumped approximately 12V above the supply. These pins
have a relatively high impedance when above the rail (the
equivalent of a few hundred kilohms). Care should be
taken to minimize any loading by parasitic resistance to
ground or supply.
Sense Pins: Each sense pin connects to the input of a
supply-referenced comparator with a 65mV nominal offset. When a sense pin is taken more than 65mV below
W
FUNCTIONAL DIAGRA
supply, the MOSFET gate for that channel is driven low and
the corresponding timing capacitor discharged. Each current-sense comparator operates completely independently.
The 65mV typical threshold has a +0.33%/°C temperature
coefficient, which closely matches the TC of drain sense
resistors formed from copper PC traces.
Some loads require high in-rush currents. An RC time
delay can be added between the drain sense resistor and
the sense pin to ensure that the current-sense comparator
does not false trigger during start-up (see Applications
Information). However, a maximum of 10kΩ can be inserted between a drain sense resistor and the sense pin. If
current sense is not required in any channel, the sense pin
for that channel is tied to supply.
Timer Pins: A timing capacitor CT from each timer pin to
ground sets the restart time following overcurrent detection. CT is rapidly discharged to less than 1V and then
recharged by a 14µA nominal current source back to the
timer threshold, whereupon restart is attempted. If current
sense is not required in any channel, the timer pin for that
channel is left open.
Ground Pins: The two ground pins are internally connected and must also be externally connected.
(Each Channel)
U
U
V+
3V
14µA
+
65mV
+
–
TIMER
–
SENSE
+
–
1.4V
75k
INPUT
1.4V
OSCILLATOR
AND
CHARGE PUMP
GATE
+
–
75k
1161 FD
1161fa
4
LT1161
U
OPERATIO
(Each Channel, Refer to Functional Diagram)
The LT1161 gate pin has two states, OFF and ON. In the
OFF state it is held low, while in the ON state it is pumped
to 12V above supply by a self-contained 750kHz charge
pump. The OFF state is activated when either the input pin
is below 1.4V or the timer pin is below 3V. Conversely, for
the ON state to be activated, both the input and timer pins
must be above their thresholds.
If left open, the input pin is held low by a 75k resistor, while
the timer pin is held a diode drop above 3V by a 14µA pullup current source. Thus the timer pin automatically reverts to the ON state, subject to the input also being high.
The input has approximately 200mV of hysteresis.
The sense pin normally connects to the drain of the power
MOSFET, which returns through a low valued drain sense
resistor to supply. When the gate is ON and the MOSFET
drain current exceeds the level required to generate a
65mV drop across the drain sense resistor, the sense
comparator activates a pull-down NPN which rapidly pulls
the timer pin below 3V. This in turn causes the timer
comparator to override the input pin and activate the gate
pin OFF state, thus protecting the power MOSFET. In order
for the sense comparator to accurately sense MOSFET
drain current, the LT1161 supply pins must be connected
directly to the positive side of the drain sense resistors.
When the MOSFET gate voltage is less than 1.4V, the timer
pin is released. The 14µA current source then slowly
charges the timing capacitor back to 3V where the charge
pump again starts to drive the gate pin high. If a fault still
exists, such as a short circuit, the sense comparator
threshold will again be exceeded and the timer cycle will
repeat until the fault is removed (see Figure 2).
OFF
NORMAL
OVERCURRENT
NORMAL
INPUT
12V
V+
GATE
0V
3V
TIMER
0V
1161 F02
Figure 2. Timing Diagram
U
W
U
U
APPLICATIONS INFORMATION
Input/Supply Sequencing
There are no input/supply sequencing requirements for
the LT1161. The input may be taken up to 15V with the
supply at 0V. When the supply is turned on with an input
high, the MOSFET turn-on will be inhibited until the timing
capacitor charges to 3V (i.e., for one restart cycle). The
two V + pins (11, 20) must always be connected to each
other.
rating, for supply voltages of 12V to 48V over the entire
temperature range. In order to maintain the OFF state, the
opto must have less than 20µA of dark current (leakage)
hot.
12V TO 48V
100k
LOGIC
INPUT
1/4 NEC PS2501-4
2k
IN
Isolating the Inputs
LT1161
51k
Operation in harsh environments may require isolation to
prevent ground transients from damaging control logic.
The LT1161 easily interfaces to low cost opto-isolators.
The network shown in Figure 3 ensures that the input will
be pulled above 2V, but not exceed the absolute maximum
LOGIC
GND
POWER
GROUND
GND
GND
1161 F03
Figure 3. Isolating the Inputs
1161fa
5
LT1161
U
W
U
U
APPLICATIONS INFORMATION
Drain Sense Configuration
Automatic Restart Period
The LT1161 uses supply-referenced current sensing. One
input of each channel’s current-sense comparator is connected to a drain sense pin, while the second input is offset
65mV below the supply bus inside the device. For this
reason, Pins 11 and 20 of the LT1161 must be treated not
only as supply pins, but as the reference inputs for the
current-sense comparators.
The timing capacitor CT shown in Figure 4 determines the
length of time the power MOSFET is held off following a
current limit trip. Curves are given in the Typical Performance Characteristics to show the restart period for
various values of CT. For example, CT = 0.33µF yields a
50ms restart period.
Figure 4 shows the proper drain sense configuration for
the LT1161. Note that the sense pin goes to the drain end
of the sense resistor, while the two V + pins are tied to each
other and connected to supply at the same point as the
positive ends of the sense resistors. Local supply
decoupling at the LT1161 is important at high input
voltages (see Protecting Against Supply Transients).
The drain sense threshold voltage has a positive temperature coefficient, allowing PTC sense resistors to be used
(see Printed Circuit Board Shunts). The selection of RS
should be based on the minimum threshold voltage:
Defeating Automatic Restart
Some applications are required to remain off after a fault
occurs. When the LT1161 is being driven from CMOS
logic, this can be easily implemented by connecting
resistor R1 between the input and timer pins as shown in
Figure 5. R1 supplies the sustaining current for an SCR
which latches the timer pin low. This prevents the MOSFET
gate from turning ON until the input has been recycled.
TIMER
RS =
R1
2k
50mV
ISET
5V
CMOS
LOGIC
Thus the 0.02Ω drain sense resistor in Figure 4 would yield
a minimum trip current of 2.5A. This simple configuration
is appropriate for resistive or inductive loads which do not
generate large current transients at turn-on.
ON = 5V
OFF = 0V
LT1161
INPUT
1161 F05
Figure 5. Latch-Off Input Network (Auto-Restart Defeated)
Inductive vs Capacitive Loads
24V
V+
V+
+
10µF
LT1161
+
100µF
50V
RS
0.02Ω
(PTC)
DS1
1161 F04
T1
CT
1µF
G1
IRFZ34
GND
GND
24V, 2A
SOLENOID
Figure 4. Drain Sense Configuration
Turning on an inductive load produces a relatively benign
ramp in MOSFET current. However, when an inductive
load is turned off, the current stored in the inductor needs
somewhere to decay. A clamp diode connected directly
across each inductive load normally serves this purpose.
If a diode is not employed the LT1161 clamps the MOSFET
gate 0.7V below ground. This causes the MOSFET to
resume conduction during the current decay with (V + +
VGS + 0.7V) across it, resulting in high dissipation peaks.
Capacitive loads exhibit the opposite behavior. Any load
that includes a decoupling capacitor will generate a current equal to CLOAD × (∂V/∂t) during capacitor in-rush.
With large electrolytic capacitors, the resulting current
1161fa
6
LT1161
U
U
W
U
APPLICATIONS INFORMATION
Turn-on ∂V/∂t is controlled by the addition of the simple
network shown in Figure 6. This network takes advantage
of the fact that the MOSFET acts as a source follower
during turn-on. Thus the ∂V/∂t on the source can be
controlled by controlling the ∂V/∂t on the gate:
∂V V + − VTH
=
∂ t 105 × C1
where VTH is the MOSFET gate threshold voltage. Multiplying CLOAD times this ∂V/∂t yields the value of the current
spike. For example, if V + = 24V, VTH = 2V, and C1 = 0.1µF,
∂V/∂t = 2.2V/ms, resulting in a 2.2A turn-on spike into
1000µF. The diode and second resistor in the network
ensure fast current limit turn-off.
When turning off a capacitive load, the source of the
MOSFET can “hang up” if the load resistance does not
discharge CLOAD as fast as the gate is being pulled down.
If this is the case, a diode may have to be added from
source to gate to prevent VGS(MAX) from being exceeded.
CURRENT LIMIT
DELAY NETWORK
V+
V+
24V
+
1N4148
CD
RD (≤10k)
DS
∂V/∂t CONTROL NETWORK
1N4148
LT1161
100k
100k
1RFZ24
G
C1
+
CLOAD
1161 F06
Figure 6. ∂V/∂t Control and Current Limit Delay
Adding Current Limit Delay
When capacitive loads are being switched or in very noisy
environments, it is desirable to add delay in the drain
current-sense path to prevent false tripping (inductive
loads normally do not need delay). This is accomplished
by the current limit delay network shown in Figure 6. RD
and CD delay the overcurrent trip for drain currents up to
approximately 10 × ISET, above which the diode conducts
and provides immediate turn-off (see Figure 7). To ensure
proper operation of the timer, CD must be ≤ CT.
10
TRIP DELAY TIME (1 = RDCD)
spike can play havoc with the power supply and false trip
the current-sense comparator.
1
0.1
0.01
1
10
100
MOSFET DRAIN CURRENT (1 = SET CURRENT)
L1161 F07
Figure 7. Current Limit Delay Time
Printed Circuit Board Shunts
The sheet resistance of 1oz. copper clad is approximately
5 × 10 –4 Ω/square with a temperature coefficient of
+0.39%/°C. Since the LT1161 drain sense threshold has a
similar temperature coefficient (+0.33%/°C), this offers
the possibility of nearly zero TC current sensing using
“free” drain sense resistors made out of PC trace material.
A conservative approach is to use 0.02" of width for each
1A of current for 1oz. copper. Combining the LT1161 drain
sense threshold with the 1oz. copper sheet resistance
results in a simple expression for width and length:
Width (1oz. Cu) = 0.02" × ISET
Length (1oz. Cu) = 2"
The width for 2oz. copper would be halved while the length
would remain the same.
Bends may be incorporated into the resistor to reduce
space; each bend is equivalent to approximately 0.6 ×
width of straight length. Kelvin connections should be
employed by running separate traces from the ends of the
resistors back to the LT1161 V + and sense pins. See
Application Note 53 for further information on printed
circuit board shunts.
1161fa
7
LT1161
U
W
U
U
APPLICATIONS INFORMATION
Low Voltage/Wide Supply Range Operation
When the supply is <12V, the LT1161 charge pumps do
not produce sufficient gate voltage to fully enhance standard N-channel MOSFETs. For these applications, logiclevel MOSFETs can be used to extend operation down to
8V. If the MOSFET has a maximum VGS rating of 15V or
greater, then it can also be used up to the 60V (absolute
maximum) rating of the LT1161. MOSFETs are available
from both Motorola and Siliconix which meet these
criteria.
The second method shown in Figure 8 uses a quad
exclusive-NOR gate to indicate when the output of the
switch has not obeyed the input command (i.e., output low
when it should be high or vice versa). In addition to current
limit, this gives a fault indication if the switch is shorted or
if the load is open.
24V
V+
V+
LT1161
ROL
ADD FOR
OPEN-LOAD
DETECTION
G
FAULT
The LT1161 is 100% tested and guaranteed to be safe
from damage with 60V applied between the V + and ground
pins. However, when this voltage is exceeded, even for a
few microseconds, the result can be a catastrophic failure.
For this reason it is imperative that the LT1161 not be
exposed to supply transients above 60V.
DS
IN
INPUT
Protecting Against Supply Transients
RS
1/4 MM74HC266A
LOAD
100k
1161 F08
Figure 8. Fault Feedback Using Exclusive-NOR Gate
V+
pins are reFor proper current-sense operation, the
quired to be connected to the positive side of the drain
sense resistors (see Drain Sense Configuration). Therefore, the best way to prevent supply transients is to ensure
that the supply is adequately decoupled at the point where
the V + pins and drain sense resistors meet. Several
hundred microfarads may be required with high current
switches.
When operating voltages approach the 60V absolute maximum rating of the LT1161, local supply decoupling between the V + pins (11, 20) and ground pins (1, 10) is highly
recommended. A small ferrite bead between the supply
connection and local capacitor can also be effective in
suppressing transients. Note however, that resistance
should not be added in series with the V + pins because it
will cause an error in the current sense threshold.
Low-Side Driving
Although the LT1161 is primarily targeted at high-side
(grounded load) switch applications, it can also be used
for low-side (supply-connected load), or mixed high- and
low-side switch applications. Figures 9a and 9b illustrate
LT1161 switch channels driving low-side power MOSFETs.
Because the LT1161 charge pump tries to pump the gate
of the N-channel MOSFET above supply, a clamp zener is
required to prevent the VGS (absolute maximum) of the
MOSFET from being exceeded. The LT1161 gate drive is
current limited for this purpose so that no resistance is
needed between the gate pin and zener.
12V TO 48V
V+
V+
Fault Feedback
Two methods can be used to derive switch status. First,
the timer pin voltage can be monitored to indicate when
the switch is turned off due to current limit. During normal
operation (ON or OFF), the timer voltage is 3.5V and only
during current limit does the voltage drop below 3V.
T
1µF
LT1161
+
100µF
RS
0.01Ω
(PTC)
DS
4A
LOAD
IRFZ44
G
15V
1N4744
1161 F09a
Figure 9a. Low-Side Driver with Load Current Sensing
1161fa
8
LT1161
U
U
W
U
APPLICATIONS INFORMATION
supply operating range of the LT1161. This allows the load
to be returned to supply through current-sense resistor
RS, providing normal operation of the LT1161 protection
circuitry.
8V TO 24V
HV
10µF
1N4148
V+
T1
V+
DS1
1µF
51Ω
G1
LT1161
1µF
HV
LOAD
IRF630
If the load cannot be returned to supply through RS, or the
load supply voltage is higher than the LT1161 supply, the
current sense must be moved to the source of the low-side
MOSFET. Figure 9b shows two approaches to source
sensing. On channel 1, current limit occurs when the
voltage across sense resistor RS1 thresholds the VBE of the
NPN transistor, causing the LT1161 drain sense pin to be
pulled down.
2N2222
15V
1N4744
51Ω
T2
HV
LOAD
RS1
0.2Ω
DS2
IRF630
G2
+
2N2222
1/2
LT1013
–
51Ω
15V
1N4744
RS2
0.02Ω
1161 F09b
The channel 2 circuit of Figure 9b uses an operational
amplifier (must common mode to ground) to level shift the
voltage across RS2 up to the drain sense pin. This approach allows the use of a much smaller sense resistor
which could be made from PC trace material. In both
cases, the LT1161 restart timers function the same as in
high-side switch applications.
Figure 9b. Low-Side Drivers with Two Approaches
for Source Current Sensing
Current sensing for protecting low-side drivers can be
done in several different ways. In the Figure 9a circuit, the
supply voltage for the load is assumed to be within the
U
TYPICAL APPLICATIONS
Using an Extra Channel to Do Common Current Limit for Multiple/Paralleled Switches
24V
100k
1
1µF
2
3
4
5
6
INPUTS
(MAY BE PARALLELED)
7
8
9
10
V+
GND
T1
DS1
IN1
G1
T2
DS2
IN2
LT1161
G2
T3
DS3
IN3
G3
20
RS
19
18
10µF
50V
15k
17
16
IRFZ44
15
14
IRFZ44
OUTPUTS
(MAY BE PARALLELED)
13
T4
DS4
IN4
G4
GND
11
V+
12
IRFZ44
1161 TA05
1161fa
9
LT1161
U
TYPICAL APPLICATIONS
Protected Quad 1A Automotive Solenoid Driver with Overvoltage Shutdown
1
1N4148
3
4
0.33µF
1N4148
INPUTS
GND
2
0.33µF
5
1N4148
IN1
G1
T2
DS2
LT1161
G3
T4
9
10
G2
DS3
IN3
8
1N4148
DS1
T3
7
0.33µF
T1
IN2
6
0.33µF
8V TO 28V OPERATING
32V TO 60V SHUTDOWN
20
V+
DS4
19
18
MTD3055EL
17
0.03Ω
16
MTD3055EL
15
0.03Ω
14
MTD3055EL
13
0.03Ω
12
IN4
G4
GND
11
V+
10µF
100V
0.03Ω
MTD3055EL
2N3904
5.1k
10k
30V
1N6011B
1161 TA03
Protected Quad Switch with Mixed Low- and High-Side Driving
10µF
+
24V
0.01Ω
1
0.33µF
2
3
HIGH-SIDE DRIVER
INPUTS
(SEE NOTE 1)
0.33µF
4
5
2k
6
7
LOW-SIDE DRIVER
INPUTS
(SEE NOTE 2)
2k
8
9
10
20
V+
GND
DS1
T1
G1
IN1
DS2
T2
IN2
LT1161
T3
G2
DS3
IN3
G3
T4
DS4
+
100µF
50V
17
MTP36N06E
16
1N4148
24V/3A
LOAD
51Ω
150V/1A
LOAD
15
14
2N2222
GND
15V
1N4744
1N4148
12
11
V+
150V
MTP10N40E
13
G4
NOTE 2: THE LOW-SIDE DRIVER CHANNELS ARE CONFIGURED
TO LATCH OFF FOLLOWING A FAULT. 5V CMOS LOGIC INPUTS
ARE REQUIRED.
24V/3A
LOAD
0.01Ω
18
IN4
NOTE 1: THE HIGH-SIDE DRIVER CHANNELS ARE CONFIGURED
TO AUTOMATICALLY RESTART FOLLOWING A FAULT.
MTP36N06E
19
0.4Ω
150V/1A
LOAD
51Ω
2N2222
15V
1N4744
MTP10N40E
0.4Ω
1161 TA04
1161fa
10
LT1161
U
TYPICAL APPLICATIONS
Protected Quad 2A Industrial Switch with Isolated Inputs and Fault Output
24V
1
NEC PS2501-4
5.1k
2
1µF
3
5.1k
4
1µF
INPUTS
5
5.1k
6
1µF
7
5.1k
1µF
8
9
10
24V
20
V+
GND
T1
DS1
IN1
G1
T2
DS2
IN2
G2
LT1161
T3
DS3
IN3
G3
T4
DS4
IN4
G4
GND
V+
19
18
17
16
15
14
13
12
+
0.015Ω
50µF
50V
RFD16N05
LOAD
#1
0.015Ω
100k
RFD16N05
LOAD
#2
0.015Ω
100k
RFD16N05
LOAD
#3
0.015Ω
100k
RFD16N05
LOAD
#4
11
MM74HC266A
100k
18k
2N3904
1161 TA02
5.6V
1N5994B
4N28
5.1k
FAULT
OUTPUT
0.1µF
2k
U
PACKAGE DESCRIPTION
N Package
20-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
+0.889
8.255
–0.381
)
1.060*
(26.924)
MAX
.045 – .065
(1.143 – 1.651)
.125 – .145
(3.175 – 3.683)
.020
(0.508)
MIN
.065
(1.651)
TYP
.120
(3.048)
MIN
.005
(0.127)
MIN
.100
(2.54)
BSC
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
.255 ± .015*
(6.477 ± 0.381)
.018 ± .003
(0.457 ± 0.076)
N20 0405
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1161fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1161
U
PACKAGE DESCRIPTION
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.496 – .512
(12.598 – 13.005)
NOTE 4
N
20
18
17
16
15
14
13
12
11
N
.325 ±.005
.420
MIN
19
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
.005
(0.127)
RAD MIN
.291 – .299
(7.391 – 7.595)
NOTE 4
.010 – .029 × 45°
(0.254 – 0.737)
.009 – .013
(0.229 – 0.330)
NOTE:
1. DIMENSIONS IN
1
2
3
4
5
6
7
8
9
10
.037 – .045
(0.940 – 1.143)
.093 – .104
(2.362 – 2.642)
0° – 8° TYP
.050
(1.270)
BSC
NOTE 3
.016 – .050
(0.406 – 1.270)
.004 – .012
(0.102 – 0.305)
.014 – .019
(0.356 – 0.482)
TYP
S20 (WIDE) 0502
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1158
Half-Bridge N-Channel Power MOSFET Driver
Single Input, Continuous Current Protection and Internal Charge
Pump for DC Operation
LT1336
Half-Bridge N-Channel Power MOSFET Driver with
Boost Regulator
Onboard Boost Regulator to Supply the High Side Driver
LT1910
Protected High Side MOSFET Driver
VIN = 8V to 48V, Protected from –15V to 60V Transients, Auto
Restart, Fault Indication
LTC1922-1
Synchronous Phase Modulated Full-Bridge Controller
Output Power from 50W to Kilowatts, Adaptive Direct Sense Zero
Voltage Switching Compensates for External Component Tolerances
LTC1923
Full-Bridge Controller for Thermoelectric Coolers
High Efficiency, Adjustabe Slew Rate Reduces EMI
5mm × 5mm QFN and 28-Pin SSOP
1161fa
12
Linear Technology Corporation
LT 0406 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1994