HT32F52220/HT32F52230
Datasheet
32-Bit ARM® Cortex™-M0+ Microcontroller,
up to 32 KB Flash and 4 KB SRAM with 1 MSPS ADC,
USART, UART, SPI, I2C, GPTM, SCTM, BFTM, WDT
Revision: V1.21
Date: April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
Flash Memory Controller – FMC............................................................................................. 7
Reset Control Unit – RSTCU.................................................................................................. 8
Clock Control Unit – CKCU..................................................................................................... 8
Power Management – PWRCU.............................................................................................. 8
External Interrupt/Event Controller – EXTI............................................................................. 9
Analog to Digital Converter – ADC......................................................................................... 9
I/O Ports – GPIO..................................................................................................................... 9
PWM Generation and Capture Timers – GPTM................................................................... 10
Single Channel Generation and Capture Timers – SCTM.................................................... 10
Basic Function Timer – BFTM.............................................................................................. 10
Watchdog Timer – WDT........................................................................................................ 11
Inter-integrated Circuit – I2C................................................................................................. 11
Serial Peripheral Interface – SPI.......................................................................................... 12
Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 12
Universal Asynchronous Receiver Transmitter – UART....................................................... 13
Debug Support...................................................................................................................... 13
Package and Operation Temperature................................................................................... 13
3 Overview................................................................................................................. 14
Device Information................................................................................................................ 14
Block Diagram...................................................................................................................... 15
Memory Map......................................................................................................................... 16
Clock Structure..................................................................................................................... 18
4 Pin Assignment...................................................................................................... 19
5 Electrical Characteristics...................................................................................... 24
Absolute Maximum Ratings.................................................................................................. 24
Recommended DC Operating Conditions............................................................................ 24
On-Chip LDO Voltage Regulator Characteristics.................................................................. 24
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April 11, 2017
Table of Contents
On-chip Memory..................................................................................................................... 7
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Power Consumption............................................................................................................. 25
Reset and Supply Monitor Characteristics............................................................................ 26
External Clock Characteristics.............................................................................................. 27
Internal Clock Characteristics............................................................................................... 28
PLL Characteristics............................................................................................................... 28
I/O Port Characteristics......................................................................................................... 29
ADC Characteristics............................................................................................................. 30
SCTM/GPTM Characteristics............................................................................................... 31
I2C Characteristics................................................................................................................ 32
SPI Characteristics............................................................................................................... 33
6 Package Information............................................................................................. 35
24-pin SSOP (150mil) Outline Dimensions........................................................................... 36
28-pin SSOP (150mil) Outline Dimensions........................................................................... 37
SAW Type 33-pin (4mm×4mm) QFN Outline Dimensions.................................................... 38
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April 11, 2017
Table of Contents
Memory Characteristics........................................................................................................ 28
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
List of Tables
Rev. 1.21
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April 11, 2017
List of Tables
Table 1 Features and Peripheral List........................................................................................................ 14
Table 2 Register Map ............................................................................................................................... 17
Table 3 Series Pin Assignment for 33-pin QFN, 24/28-pin SSOP Package............................................. 22
Table 4 Pin Description............................................................................................................................. 23
Table 5 Absolute Maximum Ratings.......................................................................................................... 24
Table 6 Recommended DC Operating Conditions.................................................................................... 24
Table 7 LDO Characteristics..................................................................................................................... 24
Table 8 Power Consumption Characteristics............................................................................................ 25
Table 9 VDD Power Reset Characteristics................................................................................................. 26
Table 10 LVD/BOD Characteristics........................................................................................................... 26
Table 11 High Speed External Clock (HSE) Characteristics..................................................................... 27
Table 12 High Speed Internal Clock (HSI) Characteristics....................................................................... 28
Table 13 Low Speed Internal Clock (LSI) Characteristics......................................................................... 28
Table 14 PLL Characteristics.................................................................................................................... 28
Table 15 Flash Memory Characteristics.................................................................................................... 28
Table 16 I/O Port Characteristics.............................................................................................................. 29
Table 17 ADC Characteristics................................................................................................................... 30
Table 18 SCTM/GPTM Characteristics..................................................................................................... 31
Table 19 I2C Characteristics...................................................................................................................... 32
Table 20 SPI Characteristics..................................................................................................................... 33
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
List of Figures
Rev. 1.21
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April 11, 2017
List of Figures
Figure 1 Block Diagram............................................................................................................................ 15
Figure 2 Memory Map............................................................................................................................... 16
Figure 3 Clock Structure........................................................................................................................... 18
Figure 4 24-pin SSOP Pin Assignment..................................................................................................... 19
Figure 5 28-pin SSOP Pin Assignment..................................................................................................... 20
Figure 6 33-pin QFN Pin Assignment....................................................................................................... 21
Figure 7 ADC Sampling Network Model................................................................................................... 31
Figure 8 I2C Timing Diagrams................................................................................................................... 32
Figure 9 SPI Timing Diagrams – SPI Master Mode.................................................................................. 34
Figure 10 SPI Timing Diagrams – SPI Slave Mode with CPHA=1............................................................ 34
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
1
General Description
The HOLTEK HT32F52220/52230 devices are high performance, low power consumption 32-bit
microcontrollers based around an ARM® Cortex™-M0+ processor core. The Cortex™-M0+ is a
next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller
(NVIC), SysTick timer, and including advanced debug support.
The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.
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April 11, 2017
General Description
The devices operate at a frequency of up to 40 MHz for HT32F52220/52230 with a Flash
accelerator to obtain maximum efficiency. It provides up to 32 KB of embedded Flash memory for
code/data storage and 4 KB of embedded SRAM memory for system operation and application
program usage. A variety of peripherals, such as ADC, I2C, USART, UART, SPI, GPTM, SCTM,
BFTM, WDT, SW-DP (Serial Wire Debug Port), etc., are also implemented in the device series.
Several power saving modes provide the flexibility for maximum optimization between wakeup
latency and power consumption, an especially important consideration in low power applications.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
2
Features
Core
■■ 32-bit ARM® Cortex™-M0+ processor core
■■ Up to 40 MHz operating frequency
Features
■■ 0.93 DMIPS/MHz (Dhrystone v2.1)
■■ Single-cycle multiplication
■■ Integrated Nested Vectored Interrupt Controller (NVIC)
■■ 24-bit SysTick timer
The Cortex™-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,
low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®
instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
On-chip Memory
■■ Up to 32 KB on-chip Flash memory for instruction/data and options storage
■■ 4 KB on-chip SRAM
■■ Supports multiple boot modes
The ARM® Cortex™-M0+ processor accesses and debug accesses share the single external
interface to external AHB peripherals. The processor accesses take priority over debug accesses.
The maximum address range of the Cortex™-M0+ is 4 GB since it has a 32-bit bus address
width. Additionally, a pre-defined memory map is provided by the Cortex™-M0+ processor to
reduce the software complexity of repeated implementation by different device vendors. However,
some regions are used by the ARM® Cortex™-M0+ system peripherals. Refer to the ARM®
Cortex™-M0+ Technical Reference Manual for more information. Figure 2 shows the memory
map of the HT32F522320/52230 series of devices, including code, SRAM, peripheral, and other
pre-defined regions.
Flash Memory Controller – FMC
■■ Flash accelerator for maximum efficiency
■■ 32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
■■ Flash protection capability to prevent illegal access
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer
for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower
than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution
delays. Flash Memory word program/page erase functions are also provided.
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April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Reset Control Unit – RSTCU
■■ Supply supervisor:
●● Power On Reset / Power Down Reset – POR/PDR
●● Brown-out Detector – BOD
●● Programmable Low Voltage Detector – LVD
Clock Control Unit – CKCU
■■ External 4 to 16 MHz crystal oscillator
■■ Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3V operating voltage and 25°C operating
temperature
■■ Internal 32 kHz RC oscillator
■■ Integrated system clock PLL
■■ Independent clock divider and gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a
Low Speed Internal RC oscillator (LSI), a Phase Lock Loop (PLL), a HSE clock monitor, clock
prescalers, clock multiplexers, APB clock divider and gating circuitry. The AHB, APB and
CortexTM-M0+ clocks are derived from the system clock (CK_SYS) which can come from the HSI,
HSE or PLL. The Watchdog Timer and Real Time Clock (RTC) use the LSI as their clock source.
Power Management – PWRCU
■■ Single VDD power supply: 2.0 V to 3.6 V
■■ Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply
■■ Two power domains: VDD, 1.5 V.
■■ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
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April 11, 2017
Features
The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
External Interrupt/Event Controller – EXTI
■■ Up to 16 EXTI lines with configurable trigger source and type
■■ All GPIO pins can be selected as EXTI trigger source
■■ Source trigger type includes high level, low level, negative edge, positive edge, or both edge
■■ Individual interrupt enable, wakeup enable and status bits for each EXTI line
■■ Integrated deglitch filter for short pulse blocking
The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate
a wake-up event or interrupt requests independently. Each EXTI line can also be masked
independently.
Analog to Digital Converter – ADC
■■ 12-bit SAR ADC engine
■■ Up to 1 Msps conversion rate
■■ Up to 8 external analog input channels
A 12-bit multi-channel ADC is integrated in the device. There are multiplexed channels, which
include 8 external analog signal channels and 2 internal channels which can be measured. If the
input voltage is required to remain within a specific threshold window, an Analog Watchdog
function will monitor and detect these signals. An interrupt will then be generated to inform the
device that the input voltage is not within the preset threshold levels. There are three conversion
modes to convert an analog signal to digital data. The ADC can be operated in one shot, continuous
and discontinuous conversion modes.
I/O Ports – GPIO
■■ Up to 23 GPIOs
■■ Port A, B are mapped as 16 external interrupts – EXTI
■■ Almost all I/O pins have a configurable output driving current.
There are up to 23 General Purpose I/O pins, GPIO, named Port A and Port B for the
implementation of logic input/output functions. Each of the GPIO ports has a series of related
control and configuration registers to maximize flexibility and to meet the requirements of a wide
range of applications.
The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins. The external
interrupts on the GPIO pins of the device have related control and configuration registers in the
External Interrupt Control Unit, EXTI.
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Features
■■ Software interrupt trigger mode for each EXTI line
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
PWM Generation and Capture Timers – GPTM
■■ One 16-bit up, down, up/down auto-reload counter
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
■■ Single Pulse Mode Output
■■ Encoder interface controller with two inputs using quadrature decoder
The General Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare
Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.
They can be used for a variety of purposes including general time measurement, input signal pulse
width measurement, output waveform generation such as single pulse generation, or PWM output
generation. The GPTM supports an Encoder Interface using a decoder with two inputs.
Single Channel Generation and Capture Timers – SCTM
■■ One 16-bit up and auto-reload counter
■■ One channel for each timer
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ Compare Match Output
■■ PWM waveform generation with Edge-aligned
■■ Single Pulse Mode Output
The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register
(CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be
used for a variety of purposes including general timer, input signal pulse width measurement or
output waveform generation such as single pulse generation or PWM output.
Basic Function Timer – BFTM
■■ One 32-bit compare/match count-up counter – no I/O control features
■■ One shot mode – counting stops after a match condition
■■ Repetitive mode – restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.
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Features
■■ Compare Match Output
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Watchdog Timer – WDT
■■ 12-bit down counter with 3-bit prescaler
■■ Reset event for the system
■■ Programmable watchdog timer window function
■■ Register write protection function
Inter-integrated Circuit – I2C
■■ Supports both master and slave modes with a frequency of up to 1 MHz
■■ Provide an arbitration function and clock synchronization
■■ Supports 7-bit and 10-bit addressing modes and general call addressing
■■ Supports slave multi-addressing mode with maskable address
The I2C is an internal circuit allowing communication with an external I2C interface which is an
industry standard two line serial interface used for connection to external hardware. These two
serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I 2C module
provides three data transfer rates: (1) 100 kHz in the Standard mode, (2) 400 kHz in the Fast mode
and (3) 1 MHz in the Fast plus mode. The SCL period generation register is used to setup different
kinds of duty cycle implementations for the SCL pulse.
The SDA line which is connected directly to the I2C bus is a bi-directional data line between the
master and slave devices and is used for data transmission and reception. The I 2C also has an
arbitration detect function and clock synchronization to prevent situations where more than one
master attempts to transmit data to the I2C bus at the same time.
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Features
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due
to software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT delta value
register, WDT operation control circuitry and a WDT protection mechanism. If the software does
not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated
when the counter underflows. In addition, a reset is also generated if the software reloads the
counter when the counter value is greater than the WDT delta value. This means the counter must
be reloaded within a limited timing window using a specific method. The Watchdog Timer counter
can be stopped while the processor is in the debug mode. There is a register write protect function
which can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Serial Peripheral Interface – SPI
■■ Supports both master and slave mode
■■ Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode
■■ FIFO Depth: 8 levels
■■ Multi-master and multi-slave operation
Universal Synchronous Asynchronous Receiver Transmitter – USART
■■ Supports both asynchronous and clocked synchronous serial communication modes
■■ Asynchronous operating baud rate up to (fPCLK/16) MHz and synchronous operating rate up to
(fPCLK/8) MHz
■■ Full duplex communication
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun and frame error
■■ Auto hardware flow control mode – RTS, CTS
■■ IrDA SIR encoder and decoder
■■ RS485 mode with output enable control
■■ FIFO Depth: 8 × 9 bits for both receiver and transmitter
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full
duplex data exchange using synchronous or asynchronous data transfer. The USART is used to
translate data between parallel and serial interfaces, and is commonly used for RS232 standard
communication. The USART peripheral function supports four types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt
and Time Out Interrupt. The USART module includes a transmitter FIFO, (TX_FIFO) and receiver
FIFO (RX_FIFO). The software can detect a USART error status by reading the Line Status
Register, LSR. The status includes the type and the condition of transfer operations as well as
several error conditions resulting from Parity, Overrun, Framing and Break events.
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April 11, 2017
Features
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried out in a similar way but in a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Universal Asynchronous Receiver Transmitter – UART
■■ Asynchronous serial communication operating baud-rate up to (fPCLK/16) MHz
■■ Full duplex communication
Features
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun and frame error
The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data
exchange using asynchronous transfer. The UART is used to translate data between parallel and
serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral
function supports Line Status Interrupt. The software can detect a UART error status by reading
the Line Status Register, LSR. The status includes the type and the condition of transfer operations
as well as several error conditions resulting from Parity, Overrun, Framing and Break events.
Debug Support
■■ Serial Wire Debug Port – SW-DP
■■ 4 comparators for hardware breakpoint or code / literal patch
■■ 2 comparators for hardware watchpoints
Package and Operation Temperature
■■ 24/28-pin SSOP, 33-pin QFN package
■■ Operation temperature range: -40°C to +85°C
Rev. 1.21
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April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
3
Overview
Device Information
Table 1 Features and Peripheral List
HT32F52220
16
Option Bytes Flash (KB)
1
1
SRAM (KB)
4
4
Timers
Communication
GPTM
1
SCTM
2
BFTM
1
WDT
1
SPI
1
USART
1
UART
1
I2C
1
EXTI
16
1
12-bit ADC
Number of channels
8 Channels
GPIO
Up to 23
CPU frequency
Up to 40 MHz
Operating voltage
2.0 V ~ 3.6 V
Operating temperature
-40°C ~ +85°C
Package
Rev. 1.21
HT32F52230
31
24/28-pin SSOP, 33-pin QFN
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April 11, 2017
Overview
Peripherals
Main Flash (KB)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Block Diagram
PA; PB
SWCLK SWDIO
BOOT
AF
AF
Powered by VDD15
FMC
Control Registers
HSI
SRAM
CLDO
LDO
CAP.
1.5 V
Interrupt request
BOD
LVD
Powered by VDD
PLL
AF
MOSI, MISO
SCK, SEL
I2C
AF
SDA
SCL
GPTM
AF
UART
WDT
SPI
AFIO
APB
EXTI
Power control
USART
AF
TX, RX
SRAM
Controller
XTALIN
XTALOUT
8 MHz
CKCU/RSTCU
Control Registers
AHB to APB
Bridge
AF
TX, RX
RTS/TXE
CTS/SCK
AHB
Peripherals
HSE
4 ~ 16 MHz
Clock and reset control
Bus Matrix
System
NVIC
IO Port
CortexTM-M0+
Processor
GPIO
VSS
CH3 ~ CH0
BFTM
AF
SCTM0 ~ 1
SCTM0 ~
SCTM1
VDD
AF
ADC_IN0
...
ADC
PWRCU
VDDA
VSSA
Power supply:
Bus:
Control signal:
Alternate function:
Powered by VDDA
Powered by VDD15
Powered by VDD
LSI
32 kHz
VSS
AF
ADC_IN7
12-bit
SAR ADC
WAKEUP
nRST
AF
Figure 1 Block Diagram
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April 11, 2017
Overview
SW-DP
Flash
Memory
AF
Flash Memory
Interface
VDD
POR
/PDR
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Memory Map
0xFFFF_FFFF
Reserved
0xE010_0000
0x400F_FFFF
Private peripheral bus
0x400B_4000
0x400B_0000
0x4008_A000
0x4008_8000
0x4008_2000
0x4008_0000
Reserved
0x4010_0000
Peripheral
0x4008_0000
0x4000_0000
AHB peripherals
512 KB
APB peripherals
512 KB
Reserved
SRAM
0x2000_1000
4 KB on-chip SRAM
4 KB
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_0800
Code
0x1F00_0000
0x000_8000
Reserved
Option byte alias
0x4007_7000
0x4007_6000
0x4007_5000
0x4007_4000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_A000
0x4006_9000
0x4006_8000
0x4004_9000
0x4004_8000
0x4003_5000
0x4003_4000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4001_1000
0x4001_0000
0x4000_5000
0x4000_4000
0x4000_2000
0x4000_1000
0x4000_0000
Reserved
GPIO A ～ B
Reserved
CKCU/RSTCU
Reserved
FMC
Reserved
BFTM
Reserved
SCTM1
Reserved
GPTM
Reserved
PWRCU
Reserved
WDT
Reserved
I2C
Reserved
SCTM0
Reserved
EXTI
Reserved
AFIO
Reserved
ADC
Reserved
SPI
Reserved
UART
USART
AHB
APB
1 KB
Reserved
Boot loader
2 KB
Reserved
Up to
32 KB on-chip Flash
Up to
32 KB
0x0000_0000
Figure 2 Memory Map
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April 11, 2017
Overview
0xE000_0000
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Table 2 Register Map
End Address
0x4000_0FFF
Peripheral
USART
0x4000_1000
0x4000_1FFF
UART
0x4000_2000
0x4000_3FFF
Reserved
0x4000_4000
0x4000_4FFF
SPI
0x4000_5000
0x4001_9FFF
Reserved
0x4001_0000
0x4001_0FFF
ADC
Reserved
0x4001_1000
0x4002_1FFF
0x4002_2000
0x4002_2FFF
AFIO
0x4002_3000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
EXTI
0x4002_5000
0x4003_3FFF
Reserved
0x4003_4000
0x4003_4FFF
SCTM0
0x4003_5000
0x4004_7FFF
Reserved
0x4004_8000
0x4004_8FFF
I 2C
Reserved
0x4004_9000
0x4006_7FFF
0x4006_8000
0x4006_8FFF
WDT
0x4006_9000
0x4006_9FFF
Reserved
0x4006_A000
0x4006_AFFF
RTC/PWRCU
0x4006_B000
0x4006_DFFF
Reserved
0x4006_E000
0x4006_EFFF
GPTM
0x4006_F000
0x4007_3FFF
Reserved
0x4007_4000
0x4007_4FFF
SCTM1
Reserved
0x4007_5000
0x4007_5FFF
0x4007_6000
0x4007_6FFF
BFTM
0x4007_7000
0x4007_FFFF
Reserved
0x4008_0000
0x4008_1FFF
FMC
0x4008_2000
0x4008_7FFF
Reserved
0x4008_8000
0x4008_9FFF
CKCU/RSTCU
0x4008_A000
0x400A_FFFF
Reserved
0x400B_0000
0x400B_1FFF
GPIOA
0x400B_2000
0x400B_3FFF
GPIOB
0x400B_4000
0x400F_FFFF
Reserved
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Bus
Overview
Rev. 1.21
Start Address
0x4000_0000
APB
AHB
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Clock Structure
Prescaler
1 ~ 32
HSIEN
f CK_PLL,max = 40 MHz (Recommended)
PLL
0
STCLK
(to SysTick)
8
CK_PLL
SW[2:0]
CK_GPIO
( to GPIO port)
GPIOAEN
4-16 MHz
HSE XTAL
00x
CK_HSI
GPIOBEN
fCK_SYS,max = 40 MHz
FCLK
( Free running clock)
011
HSEEN
Overview
1
PLLEN
CK_REF
CKREFPRE
CKREFEN
PLLSRC
8 MHz
HSI RC
Divider
CK_HSE
010
CK_SYS AHB Prescaler
1,2,4,8,16,32
HCLKC
( to CortexTM-M0+)
CM0PEN
(control by HW)
111
CK_AHB
110
Clock
Monitor
HCLKF
( to Flash)
CM0PEN
FMCEN
HCLKS
( to SRAM)
CM0PEN
Reserved
1
CK_WDT
0
32 kHz
LSI RC
SRAMEN
WDTSRC
CK_LSI
WDTEN
HCLKBM
( to Bus Matrix)
CM0PEN
BMEN
LSIEN
HCLKAPB
( to APB Bridge)
CM0PEN
APBEN
CKOUTSRC[2:0]
CKOUT
PCLK
000
CK_REF
001
010
CK_AHB/16
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
Reserved
110
CK_LSI
Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSI = Low Speed Internal clock
Peripherals
Clock
Prescaler
1,2,4,8
00
PCLK/2
01
PCLK/4
10
PCLK/8
11
PCLK ( AFIO, ADC,
SPI, USART, UART,
I2C, GPTM, SCTMx,
BFTM, EXTI, WDT)
SPIEN
EXTIEN
ADC
Prescaler
1,2,3,4,8...
CK_ADC IP
ADCEN
Figure 3 Clock Structure
Rev. 1.21
18 of 39
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
4
Pin Assignment
HT32F52220/HT32F52230
24 SSOP-A
PB7
1
33V
PB8
2
33V
VDDA
3
AP
PA0
4
33V
PA1
5
33V
PA2
6
33V
P33
3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15
1.5 V Power Pad
33V
3.3 V Digital & Analog IO Pad
AF1
Pin Assignment
AF0
(Default)
AF0
(Default)
33V
24
PB4
33V
23
PB3
33V
22
PB2
33V
21
PB1
33V
20
PB0
33V
19
SWDIO
PA13
33V
18
SWCLK
PA12
33V
17
PA9_BOOT
PA3
7
33V
PA4
8
33V
PA5
9
33V
33V
16
XTALOUT
PB14
CLDO
10
P15
33V
15
XTALIN
PB13
VDD
11
P33
33V
14
PB12
VSS
12
P33
33V
13
nRST
33V
3.3 V Digital I/O Pad
Figure 4 24-pin SSOP Pin Assignment
Rev. 1.21
19 of 39
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
HT32F52220/HT32F52230
28 SSOP-A
AF0
(Default)
AF0
(Default)
1
33V
PB8
2
33V
VDDA
3
AP
PA0
4
33V
PA1
5
33V
PA2
6
33V
P33
3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15
1.5 V Power Pad
33V
3.3 V Digital & Analog IO Pad
33V
28
PB4
33V
27
PB3
33V
26
PB2
33V
25
PB1
33V
24
PB0
33V
23
PA15
33V
22
PA14
33V
21
SWDIO
PA13
PA12
Pin Assignment
PB7
AF1
PA3
7
33V
PA4
8
33V
PA5
9
33V
33V
20
SWCLK
PA6
10
33V
33V
19
PA9_BOOT
PA7
11
33V
33V
18
XTALOUT
PB14
CLDO
12
P15
33V
17
XTALIN
PB13
VDD
13
P33
33V
16
PB12
VSS
14
P33
33V
15
nRST
33V
3.3 V Digital I/O Pad
Figure 5 28-pin SSOP Pin Assignment
Rev. 1.21
20 of 39
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
HT32F52220/HT32F52230
33 QFN-A
PB4
PB3
PB2
31
30
29
28
27
26
25
AP
AP
33V
33V
33V
33V
33V
33V
33V
P33
3.3 V Digital Power Pad
AP
3.3 V Analog Power Pad
P15
1.5 V Power Pad
33V
AF0
(Default)
33V
24
PB1
33V
23
PB0
33V
22
PA15
33V
21
PA14
AF1
PA2
3
33V
PA3
4
33V
PA4
5
33V
33V
3.3 V Digital & Analog IO Pad
33V
20
SWDIO
PA13
PA5
6
33V
33V
3.3 V Digital I/O Pad
33V
19
SWCLK
PA12
33V
18
PA9_
BOOT
33V
17
XTALOUT
PA6
7
33V
PA7
8
33V
VDD VDD Domain Pad
33 VSS
P15
P33
P33
9
10
11
12
13
14
15
16
CLDO
VDD
VSS
nRST
N.C.
N.C.
PB12
XTALIN
AF0
(Default)
PB13
AF1
VDD VDD VDD VDD
33V 33V 33V 33V
Pin Assignment
N.C.
32
AF0
(Default)
PB7
2
PB8
PA1
1
VDDA
PA0
VSSA
AF0
(Default)
PB14
33V
Figure 6 33-pin QFN Pin Assignment
Rev. 1.21
21 of 39
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Table 3 Series Pin Assignment for 33-pin QFN, 24/28-pin SSOP Package
Alternate Function Mapping
Package
33QFN 28SSOP 24SSOP
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
System
Default
GPIO
ADC
N/A
GPTM
SPI
USART
/UART
I2C
N/A
N/A
N/A
N/A
N/A
SCTM
N/A
System
Other
4
4
PA0
ADC_IN0
GT_CH0
SPI_SCK
USR_
RTS
I2C_SCL
2
5
5
PA1
ADC_IN1
GT_CH1 SPI_MOSI
USR_
CTS
I2C_SDA
3
6
6
PA2
ADC_IN2
GT_CH2 SPI_MISO
USR_TX
4
7
7
PA3
ADC_IN3
GT_CH3
SPI_SEL
USR_RX
5
8
8
PA4
ADC_IN4
GT_CH0
SPI_SCK
UR_TX
I2C_SCL
6
9
9
PA5
ADC_IN5
GT_CH1 SPI_MOSI
UR_RX
I2C_SDA
7
10
PA6
ADC_IN6
GT_CH2 SPI_MISO
8
11
PA7
ADC_IN7
GT_CH3
9
12
10
11
12
10
CLDO
13
11
VDD
14
12
VSS
15
13
nRST
13
Pin Assignment
1
SPI_SEL
N.C.
14
N.C.
15
16
14
PB12
16
17
15
XTALIN
PB13
17
18
16
XTALOUT
PB14
18
19
17
PA9_BOOT
19
20
18
SWCLK
PA12
20
21
19
SWDIO
PA13
21
22
PA14
SPI_MISO
UR_RX
SCTM0
UR_TX
I2C_SCL
UR_RX
I2C_SDA
SPI_MOSI
GT_CH0
SCTM1
SPI_SEL
USR_
RTS
I2C_SCL
SPI_SCK
USR_
CTS
I2C_SDA
22
23
PA15
GT_CH0
23
24
20
PB0
GT_CH1 SPI_MOSI
USR_TX
I2C_SCL
24
25
21
PB1
GT_CH1 SPI_MISO USR_RX
I2C_SDA
25
26
22
PB2
GT_CH2
26
27
23
PB3
GT_CH2
27
28
24
PB4
28
WAKEUP
CKOUT
SCTM1
SCTM0
SPI_SEL
UR_TX
SPI_SCK
UR_RX
SCTM1
SPI_MOSI
UR_TX
SCTM0
N.C.
29
1
1
PB7
GT_CH3 SPI_MISO
UR_TX
I2C_SCL
30
2
2
PB8
GT_CH3
UR_RX
I2C_SDA
31
3
3
VDDA
32
VSSA
33
VSS
Rev. 1.21
SPI_SEL
22 of 39
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Table 4 Pin Description
Pin number
33QFN 28SSOP 24SSOP
Pin
Name
Type
(Note1)
IO
Structure
(Note2)
Description
Output
Driving
Default function (AF0)
29
1
1
PB7
AI/O
33V
4/8/12/16 mA PB7
30
2
2
PB8
AI/O
33V
4/8/12/16 mA PB8
31
3
3
VDDA
P
—
—
Analog voltage for ADC
VSSA
P
—
—
Analog ground for ADC
32
1
4
4
VSS
P
PA0
AI/O
Ground reference for digital I/O
33V
Pin Assignment
33
4/8/12/16 mA PA0
2
5
5
PA1
AI/O
33V
4/8/12/16 mA PA1
3
6
6
PA2
AI/O
33V
4/8/12/16 mA PA2
4
7
7
PA3
AI/O
33V
4/8/12/16 mA PA3
5
8
8
PA4
AI/O
33V
4/8/12/16 mA PA4
9
6
9
PA5
AI/O
33V
4/8/12/16 mA PA5
7
10
PA6
AI/O
33V
4/8/12/16 mA PA6
8
11
PA7
AI/O
33V
4/8/12/16 mA PA7
9
12
10
CLDO
P
—
—
Core power LDO 1.5 V output
It is recommended to connect a 1 μF to 2.2 μF capacitor as
close as possible between this pin and VSS pin.
10
13
11
VDD
P
—
—
Voltage for digital I/O
11
14
12
VSS
P
—
—
Ground reference for digital I/O
12
15
13
I (VDD)
33V_PU
—
External reset pin and external wakeup pin in the PowerDown mode
nRST
Note 3
13
N.C.
—
—
—
—
14
N.C.
—
—
—
—
15
16
14
PB12 Note 3
I/O (VDD)
33V
4/8/12/16 mA
16
17
15
PB13
AI/O
33V
4/8/12/16 mA XTALIN
17
18
16
PB14
AI/O
33V
18
19
17
PA9
I/O
33V_PU
PB12
4/8/12/16 mA XTALOUT
4/8/12/16 mA PA9_BOOT
19
20
18
PA12
I/O
33V_PU
4/8/12/16 mA SWCLK
20
21
19
PA13
I/O
33V_PU
4/8/12/16 mA SWDIO
21
22
PA14
I/O
33V
4/8/12/16 mA PA14
22
23
PA15
I/O
33V
4/8/12/16 mA PA15
4/8/12/16 mA PB0
23
24
20
PB0
I/O
33V
24
25
21
PB1
I/O
33V
4/8/12/16 mA PB1
25
26
22
PB2
I/O
33V
4/8/12/16 mA PB2
26
27
23
PB3
I/O
33V
4/8/12/16 mA PB3
27
28
24
PB4
I/O
33V
4/8/12/16 mA PB4
N.C.
—
—
28
—
—
Note: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, VDD = VDD Power
2. 33V = 3.3 V tolerant.
3. These pins are located at the VDD power domain.
Rev. 1.21
23 of 39
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
5
Electrical Characteristics
Absolute Maximum Ratings
Table 5 Absolute Maximum Ratings
Min
Max
Unit
VDD
Symbol
External Main Supply Voltage
Parameter
VSS - 0.3
VSS + 3.6
V
VDDA
External Analog Supply Voltage
VSSA - 0.3
VSSA + 3.6
V
VIN
Input Voltage On I/O
VSS - 0.3
VSS + 0.3
V
TA
Ambient Operating Temperature Range
-40
+85
°C
TSTG
Storage Temperature Range
-55
+150
°C
TJ
Maximum Junction Temperature
—
125
°C
PD
Total Power Dissipation
—
500
mW
VESD
Electrostatic Discharge Voltage – Human Body Mode
-4000
+4000
V
Recommended DC Operating Conditions
Table 6 Recommended DC Operating Conditions
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
VDD
I/O OPerating Voltage
—
2.0
3.3
3.6
V
VDDA
Analog Operating Voltage
—
2.5
3.3
3.6
V
On-Chip LDO Voltage Regulator Characteristics
Table 7 LDO Characteristics
Symbol
Rev. 1.21
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Unit
VLDO
Internal Regulator Output
Voltage
VDD ≥ 2.0 V Regulator input @
ILDO = 35 mA and voltage vari- 1.425
ant = ±5 %, After trimming.
1.5
1.57
V
ILDO
Output Current
VDD = 2.0 V Regulator input @
VLDO = 1.5 V
—
30
35
mA
CLDO
External Filter Capacitor
The capacitor value is depenValue for Internal Core Power dent on the core power curSupply
rent consumption
—
1
—
μF
24 of 39
April 11, 2017
Electrical Characteristics
The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the
absolute maximum rating conditions for extended periods may affect device reliability.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Power Consumption
Table 8 Power Consumption Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min Typ Max Unit
VDD = 3.3 V, HSE = 8 MHz, PLL = 40 MHz,
fHCLK = 40 MHz, fPCLK = 40 MHz,
— 10.5 — mA
All peripherals enabled
—
6.8
—
mA
VDD = 3.3 V, HSE off, PLL off, LSI on,
fHCLK = 32 kHz, fPCLK = 32 kHz,
All peripherals enabled
—
44
—
μA
VDD = 3.3 V, HSE off, PLL off, LSI on,
fHCLK = 32 kHz, fPCLK = 32 kHz,
All peripherals disabled
—
41
—
μA
VDD = 3.3 V, HSE = 8 MHz, PLL = 40 MHz,
fHCLK = 0 MHz, fPCLK = 40 MHz,
All peripherals enabled
—
5.8
—
mA
VDD = 3.3 V, HSE = 8 MHz, PLL = 40 MHz,
fHCLK = 0 MHz, fPCLK = 40 MHz,
All peripherals disabled
—
2.0
—
mA
Supply Current
VDD = 3.3 V, All clock off (HSE/PLL/fHCLK),
(Deep-Sleep1 Mode) LDO in low power mode, LSI on
—
34
—
μA
Supply Current
VDD = 3.3 V, All clock off (HSE/PLL/fHCLK),
(Deep-Sleep2 Mode) LDO off DMOS on, LSI on.
—
4.8
—
μA
Supply Current
(Power-Down Mode)
—
1.3
—
μA
Supply Current
(Run Mode)
IDD
Supply Current
(Sleep Mode)
VDD = 3.3 V, LDO off, DMOS off, LSI on.
Note: 1. HSE means high speed external oscillator. HSI means 8 MHz high speed internal oscillator.
2. Code = while (1) { 208 NOP } executed in Flash.
Rev. 1.21
25 of 39
April 11, 2017
Electrical Characteristics
VDD = 3.3 V, HSE = 8 MHz, PLL = 40 MHz,
fHCLK = 40 MHz, fPCLK = 40 MHz,
All peripherals disabled
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Reset and Supply Monitor Characteristics
Table 9 VDD Power Reset Characteristics
Symbol
VPOR
Parameter
Power on reset threshold
(Rising Voltage on VDD)
TA = 25°C, unless otherwise specified.
Conditions
Power down reset threshold
(Falling Voltage on VDD)
VPORHYST
POR hysteresis
tPOR
Reset delay time
Typ
Max
Unit
1.66
1.79
1.90
V
1.49
1.64
1.78
V
—
150
—
mV
—
0.1
0.2
ms
TA = -40°C ~ +85°C
—
VDD = 3.3 V
Note: 1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
3. If the LDO is turned on, the VDD POR has to be in the de-assertion condition. When the
VDD POR is in the assertion state then the LDO will be turned off.
Table 10 LVD/BOD Characteristics
Symbol
VBOD
VLVD
Parameter
TA = 25°C, unless otherwise specified.
Min
Typ
Max
Unit
2.02
2.1
2.18
V
LVDS = 000
2.17
2.25
2.33
V
LVDS = 001
2.32
2.4
2.48
V
LVDS = 010
2.47
2.55
2.63
V
Voltage of Low Voltage TA = -40°C ~ 85°C LVDS = 011
Detection
(VDD Falling edge) LVDS = 100
2.62
2.7
2.78
V
2.77
2.85
2.93
V
Voltage of Brown Out
Detection
Conditions
TA = -40°C ~ 85°C
After factory-trimmed
(VDD Falling edge)
LVDS = 101
2.92
3.0
3.08
V
LVDS = 110
3.07
3.15
3.23
V
LVDS = 111
3.22
3.3
3.38
V
VLVDHTST
Lvd Hysteresis
VDD = 3.3 V
—
—
100
—
mV
tsuLVD
Lvd Setup Time
VDD = 3.3 V
—
—
—
5
μs
tatLVD
Lvd Active Delay Time VDD = 3.3 V
—
—
—
—
μs
IDDLVD
Operation Current Note3 VDD = 3.3 V
—
—
5
15
μA
Note: 1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
3. Bandgap current is not included.
4. LVDS field is in the PWRCU LVDCSR register
Rev. 1.21
26 of 39
April 11, 2017
Electrical Characteristics
VPDR
Min
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
External Clock Characteristics
Table 11 High Speed External Clock (HSE) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Operation Range
VDD
High Speed External Oscillator
Frequency (HSE)
CLHSE
Load Capacitance
RFHSE
Internal Feedback Resistor
Between XTALIN and XTALOUT
pins
Min
2.0
Typ
—
Max
3.6
Unit
V
—
4
—
16
MHz
VDD = 3.3 V,
RESR = 100 Ω
@ 16 MHz
—
—
22
pF
—
—
1
—
MΩ
—
—
160
Ω
40
—
60
%
VDD = 3.3 V, CL = 12 pF
@ 16 MHz, HSEDR = 0
RESR
Equivalent Series Resistance*
DHSE
Hse Oscillator Duty Cycle
IDDHSE
Hse Oscillator Current
Consumption
VDD = 3.3 V @ 16 MHz
—
TBD
—
mA
IPWDHSE
Hse Oscillator Power Down
Current
VDD = 3.3 V
—
—
0.01
μA
tSUHSE
Hse Oscillator STartup Time
VDD = 3.3 V
—
—
4
ms
VDD = 2.4 V, CL = 12 pF
@ 16 MHz, HSEDR = 1
—
Note: The following guidelines are recommended to increase the stability of the crystal circuit of the
HSE clock in the PCB layout:
■■ The crystal oscillator should be located as close as possible to the MCU to keep the trace
lengths as short as possible to reduce any parasitic capacitance.
■■ Shield lines in the vicinity of the crystal by using a ground plane to isolate signals and
reduce noise.
■■ Keep any high frequency signal lines away from the crystal area to prevent any crosstalk
adverse effects.
Rev. 1.21
27 of 39
April 11, 2017
Electrical Characteristics
fHSE
Conditions
—
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Internal Clock Characteristics
Table 12 High Speed Internal Clock (HSI) Characteristics
TA = 25°C, unless otherwise specified.
Parameter
Operation Range
fHSI
Hsi Frequency
ACCHSI
Factory Calibrated Hsi
Oscillator FRequency
Accuracy
Duty Cycle
Duty
IDDHSI
tsuHSI
Conditions
—
Oscillator Supply Current
Min
2.0
Typ
—
Max
3.6
Unit
V
VDD = 3.3 V @ 25°C
—
8
—
MHz
VDD = 3.3 V, TA = 25°C
-2
—
2
%
VDD = 2.5 V ~ 3.6 V,
TA = -40°C ~ +85°C
-3
—
3
%
VDD = 2.0 V ~ 3.6 V
TA = -40°C ~ +85°C
-4
—
4
%
fHSI = 8 MHz
35
—
65
%
—
300
500
μA
—
—
0.05
μA
-—
—
10
μs
fHSI = 8 MHz
Power Down Current
Startup Time
fHSI = 8 MHz
Table 13 Low Speed Internal Clock (LSI) Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Low Speed Internal Oscillator
Frequency (LSI)
Conditions
VDD = 3.3 V,
TA = -40°C ~ +85°C
Min
Typ
Max
Unit
21
32
43
kHz
ACCLSI
Lsi Frequency Accuracy
After factory-trimmed,
VDD = 3.3 V, TA = 25°C
-10
—
+10
%
IDDLSI
Lsi Oscillator Operating Current VDD = 3.3 V, TA = 25°C
—
0.4
0.8
μA
tSULSI
Lsi Oscillator STartup Time
—
—
100
μs
fLSI
VDD = 3.3 V, TA = 25°C
PLL Characteristics
Table 14 PLL Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
PLL input clock
fPLLIN
Conditions
—
Min
4
Typ
—
Max
16
Unit
MHz
fCK_PLL
PLL output clock
—
16
—
48
MHz
tLOCK
PLL lock time
—
—
200
—
μs
Memory Characteristics
Table 15 Flash Memory Characteristics
Symbol
Rev. 1.21
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
TA = -40°C ~ +85°C
10
—
—
K cycles
Data retention time
TA = -40°C ~ +85°C
10
—
—
Years
tPROG
Word programming time
TA = -40°C ~ +85°C
20
—
—
μs
tERASE
Page erase time
TA = -40°C ~ +85°C
2
—
—
ms
tMERASE
Mass erase time
TA = -40°C ~ +85°C
10
—
—
ms
NENDU
Number of guaranteed
program/erase cycles before
failure. (Endurance)
tRET
28 of 39
April 11, 2017
Electrical Characteristics
Symbol
VDD
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
I/O Port Characteristics
Table 16 I/O Port Characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
—
—
3
μA
—
—
3
μA
—
—
3
μA
—
—
3
μA
3.3 V IO
- 0.5
—
VDD ×
0.35
V
Reset pin
- 0.5
—
VDD ×
0.35
V
3.3 V IO
VDD ×
0.65
—
VDD +
0.5
V
Reset pin
VDD ×
0.65
—
VDD +
0.5
V
3.3 V IO
—
0.12
× VDD
—
mV
Reset pin
—
0.12
× VDD
—
mV
3.3 V IO 4 mA drive, VOL = 0.4 V
4
—
—
mA
3.3 V IO 8 mA drive, VOL = 0.4 V
8
—
—
mA
3.3 V IO 12 mA drive, VOL = 0.4 V
12
—
—
mA
3.3 V IO 16 mA drive, VOL = 0.4 V
16
—
—
mA
4
—
—
mA
8
—
—
mA
12
—
—
mA
IIL
Reset pin
IIH
High Level Input
Current
Reset pin
VIL
Low Level Input
Voltage
VHYS
IOL
IOH
VOL
VOH
High Level Input
Voltage
Schmitt Trigger Input
Voltage Hysteresis
Low Level Output
Current
(GPIO Sink current)
3.3 V IO
VI = VSS, On-chip pull-up
resister disabled.
VI = VDD, On-chip pulldown resister disabled.
3.3 V I/O 4 mA drive, VOH = VDD - 0.4 V
High Level Output
3.3 V I/O 8 mA drive, VOH = VDD - 0.4 V
Current
(GPIO Source current) 3.3 V I/O 12 mA drive, VOH = VDD - 0.4 V
3.3 V I/O 16 mA drive, VOH = VDD - 0.4 V
Low Level Output
Voltage
High Level Output
Voltage
16
—
—
mA
3.3 V 4 mA drive IO, IOL = 4 mA
—
—
0.4
V
3.3 V 8 mA drive IO, IOL = 8 mA
—
—
0.4
V
3.3 V 12 mA drive IO, IOL = 12 mA
—
—
0.4
V
3.3 V 16 mA drive IO, IOL = 16 mA
—
—
0.4
V
3.3 V 4 mA drive IO, IOH = 4 mA
VDD 0.4
—
—
V
3.3 V 8 mA drive IO, IOH = 8 mA
VDD 0.4
—
—
V
3.3 V 12 mA drive IO, IOH = 12 mA
VDD 0.4
—
—
V
3.3 V 16 mA drive IO, IOH = 16 mA
VDD 0.4
—
—
V
RPU
Internal Pull-up
Resistor
3.3 V I/O
—
46
—
kΩ
RPD
Internal Pull-down
Resistor
3.3 V I/O
—
46
—
kΩ
29 of 39
April 11, 2017
Electrical Characteristics
Min
3.3 V IO
Low Level Input
Current
VIH
Rev. 1.21
TA = 25°C, unless otherwise specified.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
ADC Characteristics
Table 17 ADC Characteristics
TA = 25°C, unless otherwise specified.
Symbol
Parameter
Operating Voltage
VDDA
Conditions
—
Min
2.5
Typ
3.3
Max
3.6
Unit
V
A/D Converter Input Voltage
Range
—
0
—
VREF+
V
VREF+
A/D Converter Reference
Voltage
—
—
VDDA
VDDA
V
IADC
Current Consumption
VDDA = 3.3 V
—
1
TBD
mA
IADC_DN
Power Down Current
Consumption
VDDA = 3.3 V
—
—
0.1
μA
fADC
A/D Converter Clock
—
0.7
—
16
MHz
fS
Sampling Rate
—
0.05
—
1
MHz
tDL
Data Latency
—
—
12.5
—
1/fADC
Cycles
tS&H
Sampling & Hold Time
—
—
3.5
—
1/fADC
Cycles
tADCCONV
A/D Converter Conversion
Time
—
—
16
—
1/fADC
Cycles
RI
Input Sampling Switch
Resistance
—
—
—
1
kΩ
CI
Input Sampling Capacitance
—
16
—
pF
tSU
Startup Up Time
—
—
1
μs
N
Resolution
—
—
12
—
bits
INL
Integral Non-Linearity Error
fS = 750 kHz, VDDA = 3.3 V
—
±2
±5
LSB
DNL
Differential Non-Linearity Error fS = 750 kHz, VDDA = 3.3 V
—
±1
—
LSB
EO
Offset Error
—
—
—
±10
LSB
EG
Gain Error
—
—
—
±10
LSB
No pin/pad capacitance
included
—
Note: 1. Guaranteed by design, not tested in production.
2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input
stage where CI is the storage capacitor, RI is the resistance of the sampling switch and RS
is the output impedance of the signal source VS. Normally the sampling phase duration is
approximately, 3.5/fADC. The capacitance, CI, must be charged within this time frame and it
must be ensured that the voltage at its terminals becomes sufficiently close to VS for accuracy. To guarantee this, RS is not allowed to have an arbitrarily large value.
Rev. 1.21
30 of 39
April 11, 2017
Electrical Characteristics
VADCIN
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
SAR ADC
sample
RS
CI
RI
Figure 7 ADC Sampling Network Model
The worst case occurs when the extremities of the input range (0V and V REF ) are sampled
consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following
equation:
RS
3. 5
RI
f ADCC I ln( 2 N 2 )
Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, RS may be larger than the value indicated by the equation
above.
SCTM/GPTM Characteristics
Table 18 SCTM/GPTM Characteristics
Symbol
Parameter
Timer clock source for GPTM
fTM
Rev. 1.21
Conditions
—
Min
—
Typ
—
Max
48
Unit
MHz
tRES
Timer resolution time
—
—
—
—
fTM
fEXT
External signal frequency on
channel 1 ~ 4
—
—
—
1/2
fTM
RES
Timer resolution
—
—
—
16
bits
31 of 39
April 11, 2017
Electrical Characteristics
VS
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
I2C Characteristics
Table 19 I2C Characteristics
Symbol
Parameter
Standard Mode
Fast Mode
Fast Mode Plus
Max
100
Min
—
Max
400
Min
—
Max
1000
Unit
fSCL
Scl Clock Frequency
Min
—
tSCL(H)
Scl Clock High Time
4.5
—
1.125
—
0.45
—
μs
tSCL(L)
Scl Clock Low Time
4.5
—
1.125
—
0.45
—
μs
tFALL
Scl And Sda Fall Time
—
1.3
—
0.34
—
0.135
μs
tRISE
Scl And Sda Rise Time
—
1.3
—
0.34
—
0.135
μs
tSU(SDA)
Sda Data Setup Time
500
—
125
—
50
—
ns
tH(SDA)
Sda Data Hold Time
tSU(STA)
Start Condition Setup Time
tH(STA)
Start Condition Hold Time
0
—
0
—
0
—
ns
tSU(STO)
Stop Condition Setup Time
500
—
125
—
50
—
ns
kHz
—
0
—
0
—
ns
—
125
—
50
—
ns
Note: 1. Guaranteed by design, not tested in production.
2. To achieve 100 kHz standard mode, the peripheral clock frequency must be higher than 2
MHz.
3. To achieve 400 kHz fast mode, the peripheral clock frequency must be higher than 8 MHz.
4. To achieve 1 MHz fast mode plus, the peripheral clock frequency must be higher than 20
MHz.
5. The above characteristic parameters of the I2C bus timing are based on: SEQ_FILTER = 01
and COMB_FILTER_En is disabled.
tFALL
tRISE
SCL
tSCL(L)
tH(STA)
tSCL(H)
tH(SDA)
tSU(SDA)
tSU(STO)
SDA
tSU(STA)
Figure 8 I2C Timing Diagrams
Rev. 1.21
32 of 39
April 11, 2017
Electrical Characteristics
0
500
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
SPI Characteristics
Table 20 SPI Characteristics
Symbol
Parameter
SPI Master mode
Conditions
Min
Typ
Max
Unit
SPI master output SCK
clock frequency
SPI peripheral clock frequency fPCLK
—
—
fPCLK/2 MHz
tSCK(H)
tSCK(L)
SCK clock high and low
time
—
tSCK/2
-2
—
tSCK/2
+1
tV(MO)
Data output valid time
—
-
—
5
ns
tH(MO)
Data output hold time
—
2
—
—
ns
tSU(MI)
Data input setup time
—
5
—
—
ns
tH(MI)
Data input hold time
—
5
—
—
ns
ns
SPI Slave mode
fSCK
SPI slave input SCK clock
SPI peripheral clock frequency fPCLK
frequency
—
—
DutySCK
SPI slave input SCK clock
duty cycle
—
30
—
70
%
fPCLK/3 MHz
tSU(SEL)
SEL enable setup time
—
3 tPCLK
—
—
ns
tH(SEL)
SEL enable hold time
—
2 tPCLK
—
—
ns
tA(SO)
Data output access time
—
—
—
3 tPCLK
ns
tDIS(SO)
Data output disable time
—
—
—
10
ns
tV(SO)
Data output valid time
—
—
—
25
ns
tH(SO)
Data output hold time
—
15
—
—
ns
tSU(SI)
Data input setup time
—
5
—
—
ns
tH(SI)
Data input hold time
—
4
—
—
ns
Note: 1. fSCK is SPI output/input clock frequency and tSCK = 1/fSCK.
2. fPCLK is SPI peripheral clock frequency and tPCLK = 1/fPCLK.
Rev. 1.21
33 of 39
April 11, 2017
Electrical Characteristics
fSCK
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
tSCK
SCK (CPOL = 0)
tSCK(H)
tSCK(L)
SCK (CPOL = 1)
MOSI
DATA VALID
tSU(MI )
MISO
MOSI
MISO
DATA VALID
DATA VALID
tH(MI )
CPHA = 1
DATA VALID
DATA VALID
tV(MO)
tH(MO)
DATA VALID
DATA VALID
tSU(MI )
tH(MO)
DATA VALID
DATA VALID
tH(MI )
CPHA = 0
DATA VALID
DATA VALID
DATA VALID
Figure 9 SPI Timing Diagrams – SPI Master Mode
SEL
tSU(SEL)
tH(SEL)
tSCK
SCK
(CPOL=0)
tSCK(H)
tSCK(L)
SCK
(CPOL=1)
tSU(SI)
MOSI
MSB/LSB IN
tA(SO)
MISO
tH(SI)
tV(SO)
LSB/MSB IN
tH(SO)
MSB/LSB OUT
tDIS(SO)
LSB/MSB OUT
Figure 10 SPI Timing Diagrams – SPI Slave Mode with CPHA=1
Rev. 1.21
34 of 39
April 11, 2017
Electrical Characteristics
tV(MO)
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
6
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
for the latest version of the Package/Carton Information.
• Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• The Operation Instruction of Packing Materials
• Carton information
Rev. 1.21
35 of 39
April 11, 2017
Package Information
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
24-pin SSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.008
—
0.012
C’
—
0.341 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.21
Dimensions in mm
Min.
Nom.
Max.
—
A
—
6.000 BSC
B
—
3.900 BSC
—
C
0.200
—
0.300
C’
0.200
—
0.300
D
—
—
1.750
E
—
0.635 BSC
—
F
0.100
—
0.250
G
0.410
—
1.270
H
0.100
—
0.250
α
0°
—
8°
36 of 39
April 11, 2017
Package Information
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
28-pin SSOP (150mil) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.008
—
0.012
C’
—
0.390 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
F
0.004
—
0.0098
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.21
Dimensions in mm
Min.
Nom.
Max.
—
A
—
6.000 BSC
B
—
3.900 BSC
—
C
0.200
—
0.300
C’
—
9.900 BSC
—
D
—
—
1.750
E
—
0.635 BSC
—
F
0.100
—
0.250
G
0.410
—
1.270
H
0.100
—
0.250
α
0°
—
8°
37 of 39
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
SAW Type 33-pin (4mm×4mm) QFN Outline Dimensions
Package Information
33
Symbol
Nom.
Max.
A
0.028
0.030
0.031
A1
0.000
0.001
0.002
A3
—
0.008 BSC
—
b
0.006
0.008
0.010
D
—
0.157 BSC
—
E
—
0.157 BSC
—
e
—
0.016 BSC
—
D2
0.104
0.106
0.108
E2
0.104
0.106
0.108
L
0.014
0.016
0.018
K
0.008
—
—
Symbol
Rev. 1.21
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
0.700
0.750
0.800
A1
0.000
0.020
0.050
A3
—
0.203 BSC
—
b
0.150
0.200
0.250
D
—
4.000 BSC
—
E
—
4.000 BSC
—
e
—
0.400 BSC
—
D2
2.650
2.700
2.750
E2
2.650
2.700
2.750
L
0.350
0.400
0.450
K
0.200
—
—
38 of 39
April 11, 2017
32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Package Information
Copyright© 2017 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw/en/home.
Rev. 1.21
39 of 39
April 11, 2017