AD AD8651AR-REEL 50 mhz, precision, low distortion, low noise cmos amplifier Datasheet

50 MHz, Precision, Low Distortion,
Low Noise CMOS Amplifiers
AD8651/AD8652
–IN 2
+IN 3
V–
4
Optical communications
Laser source drivers/controllers
Broadband communications
High speed ADCs and DACs
Microwave link interface
Cell phone PA control
Video line drivers
Audio
GENERAL DESCRIPTION
The AD865x family consists of high precision, low noise, low
distortion, rail-to-rail CMOS operational amplifiers that run
from a single-supply voltage of 2.7 V to 5.5 V.
The AD865x family is made up of rail-to-rail input and output
amplifiers with a gain bandwidth of 50 MHz and a typical
voltage offset of 100 μV across common mode from a 5 V
supply. It also features low noise—4.5 nV/√Hz.
The AD865x family can be used in communications
applications, such as cell phone transmission power control, fiber
optic networking, wireless networking, and video line drivers.
TOP VIEW
(Not to Scale)
8
NC
OUT A 1
7
V+
–IN A 2
6
OUT
+IN A 3
5
NC
NC = NO CONNECT
Figure 1. 8-Lead MSOP (RM-8)
NC 1
–IN 2
APPLICATIONS
AD8651
AD8651
8
NC
7
V+
6 OUT
TOP VIEW
V– 4 (Not to Scale) 5 NC
TOP VIEW
(Not to Scale)
8
V+
7
OUT B
6
–IN B
5
+IN B
Figure 2. 8-Lead MSOP (RM-8)
OUT A 1
–IN A 2
+IN 3
NC = NO CONNECT
V– 4
AD8652
AD8652
8
V+
7
OUT B
+IN A 3
Figure 3. 8-Lead SOIC_N (R-8)
6 –IN B
TOP VIEW
V– 4 (Not to Scale) 5 +IN B
03301-004
NC 1
03301-003
PIN CONFIGURATIONS
03301-002
Bandwidth: 50 MHz @ 5 V
Low noise: 4.5 nV/√Hz
Offset voltage: 100 μV typical, specified over
entire common-mode range
Slew rate: 41 V/μs
Rail-to-rail input and output swing
Input bias current: 1 pA
Single-supply operation: 2.7 V to 5.5 V
Space-saving MSOP and SOIC_N packaging
03301-001
FEATURES
Figure 4. 8-Lead SOIC_N (R-8)
The AD865x family features the newest generation of DigiTrim®
in-package trimming. This new generation measures and
corrects the offset over the entire input common-mode range,
providing less distortion from VOS variation than is typical of
other rail-to-rail amplifiers. Offset voltage and CMRR are both
specified and guaranteed over the entire common-mode range
as well as over the extended industrial temperature range.
The AD865x family is offered in the narrow 8-lead SOIC
package and the 8-lead MSOP package. The amplifiers are
specified over the extended industrial temperature range
(−40°C to +125°C).
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8651/AD8652
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Protection ..................................................................... 15
Applications....................................................................................... 1
Overdrive Recovery ............................................................... 15
Pin Configurations ........................................................................... 1
Layout, Grounding, and Bypassing Considerations .............. 15
General Description ......................................................................... 1
Power Supply Bypassing........................................................ 15
Specifications..................................................................................... 3
Grounding............................................................................... 15
Electrical Characteristics............................................................. 3
Leakage Currents.................................................................... 15
Absolute Maximum Ratings............................................................ 5
Input Capacitance .................................................................. 16
Thermal Resistance ...................................................................... 5
Output Capacitance ............................................................... 16
ESD Caution.................................................................................. 5
Settling Time........................................................................... 16
Typical Performance Characteristics ............................................. 6
THD Readings vs. Common-Mode Voltage ...................... 16
Applications..................................................................................... 14
Driving a 16-Bit ADC............................................................ 17
Theory of Operation .................................................................. 14
Outline Dimensions ....................................................................... 18
Rail-to-Rail Output Stage...................................................... 14
Ordering Guide .......................................................................... 19
Rail-to-Rail Input Stage ......................................................... 14
REVISION HISTORY
8/06—Rev. B. to Rev. C
Changes to Figure 1 to Figure 4 ...................................................... 1
Changes to Figure 7 and Figure 9................................................... 6
Changes to Figure 23........................................................................ 9
Changes to Figure 53...................................................................... 14
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
9/04—Rev. A to Rev. B
Added AD8652 ....................................................................Universal
Change to General Description ....................................................... 1
Changes to Electrical Characteristics ............................................. 3
Changes to Absolute Maximum Ratings ........................................ 5
Change to Figure 23 .......................................................................... 9
Change to Figure 26 .......................................................................... 9
Change to Figure 36 ........................................................................ 11
Change to Figure 42 ........................................................................ 12
Change to Figure 49 ........................................................................ 13
Change to Figure 51 ........................................................................ 13
Inserted Figure 52............................................................................ 13
Change to Theory of Operation section....................................... 14
Change to Input Protection section .............................................. 15
Changes to Ordering Guide ........................................................... 20
6/04—Rev. 0 to Rev. A
Change to Figure 18 .............................................................................8
Change to Figure 21 .............................................................................9
Change to Figure 29 .............................................................................10
Change to Figure 30 .............................................................................10
Change to Figure 43 .............................................................................12
Change to Figure 44 .............................................................................12
Change to Figure 47 .............................................................................13
Change to Figure 57 .............................................................................17
10/03 Revision 0: Initial Version
Rev. C | Page 2 of 20
AD8651/AD8652
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V+ = 2.7 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified.
Table 1.
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
AD8651
VOS
Min
0 V ≤ VCM ≤ 2.7 V
–40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 2.7 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V
0 V ≤ VCM ≤ 2.7 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 2.7 V
AD8652
Offset Voltage Drift
Input Bias Current
Conditions
Typ
Max
Unit
100
350
1.4
1.6
300
1.3
μV
mV
mV
μV
mV
μV/°C
pA
pA
pA
pA
pA
V
90
0.4
4
1
TCVOS
IB
–40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
1
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
AD8651
VCM
CMRR
AD8652
Large Signal Voltage Gain
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current
AD8651
AVO
VOH
VOL
ISC
Current Noise Density
V+ = 2.7 V, –0.1 V < VCM < +2.8 V
–40°C ≤ TA ≤ +85°C, –0.1 V < VCM < +2.8 V
–40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V
V+ = 2.7 V, –0.1 V < VCM < +2.8 V
–40°C ≤ TA ≤ +125°C, –0.1 V < VCM < +2.8 V
RL = 1 kΩ, 200 mV < VO < 2.5 V
RL = 1 kΩ, 200 mV < VO < 2.5 V, TA = 85°C
RL = 1 kΩ, 200 mV < VO < 2.5 V, TA = 125°C
75
70
65
77
73
100
100
95
IL = 250 μA, –40°C ≤ TA ≤ +125°C
IL = 250 μA, –40°C ≤ TA ≤ +125°C
Sourcing
Sinking
2.67
PSRR
VS = 2.7 V to 5.5 V, VCM = 0 V
–40°C ≤ TA ≤ +125°C
76
74
95
88
85
95
90
115
114
108
dB
dB
dB
dB
dB
dB
dB
dB
80
80
40
V
mV
mA
mA
mA
94
93
dB
dB
30
IO
ISY
IO = 0
–40°C ≤ TA ≤ +125°C
IO = 0
–40°C ≤ TA ≤ +125°C
AD8652
INPUT CAPACITANCE
Differential
Common Mode
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Settling Time, 0.01%
Overload Recovery Time
Total Harmonic Distortion + Noise
NOISE PERFORMANCE
Voltage Noise Density
–0.1
10
600
10
30
600
+2.8
9
17.5
12
14.5
19.5
22.5
mA
mA
mA
mA
CIN
SR
GBP
THD + N
en
in
6
9
pF
pF
G = 1, RL = 10 kΩ
G=1
G = ±1, 2 V step
VIN × G = 1.48 V+
G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p
41
50
0.2
0.1
0.0006
V/μs
MHz
μs
μs
%
f = 10 kHz
f = 100 kHz
f = 10 kHz
5
4.5
4
nV/√Hz
nV/√Hz
fA/√Hz
Rev. C | Page 3 of 20
AD8651/AD8652
V+ = 5 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
AD8651
VOS
Min
0 V ≤ VCM ≤ 5 V
–40°C ≤ TA ≤ +85°C, 0 V ≤ VCM ≤ 5 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V
0 V ≤ VCM ≤ 5 V
–40°C ≤ TA ≤ +125°C, 0 V ≤ VCM ≤ 5 V
AD8652
Offset Voltage Drift
Input Bias Current
Conditions
Typ
Max
Unit
100
350
1.4
1.7
300
1.4
μV
mV
mV
μV
mV
μV/°C
pA
pA
pA
pA
pA
pA
V
90
0.4
4
1
TCVOS
IB
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
1
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
AD8651
VCM
CMRR
AD8652
Large Signal Voltage Gain
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current
AD8651
AVO
VOH
VOL
ISC
Current Noise Density
0.1 V < VCM < 5.1 V
–40°C ≤ TA ≤ +85°C, 0.1 V < VCM < 5.1 V
–40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V
0.1 V < VCM < 5.1 V
–40°C ≤ TA ≤ +125°C, 0.1 V < VCM < 5.1 V
RL = 1 kΩ, 200 mV < VO < 4.8 V
RL = 1 kΩ, 200 mV < VO < 4.8 V, TA = 85°C
RL = 1 kΩ, 200 mV < VO < 4.8 V, TA = 125°C
80
75
70
84
76
100
98
95
IL = 250 μA, –40°C ≤ TA ≤ +125°C
IL = 250 μA, –40°C ≤ TA ≤ +125°C
Sourcing
Sinking
4.97
PSRR
VS = 2.7 V to 5.5 V, VCM = 0 V
–40°C ≤ TA ≤ +125°C
76
74
95
94
90
100
95
115
114
111
dB
dB
dB
dB
dB
dB
dB
dB
80
80
40
V
mV
mA
mA
mA
94
93
dB
dB
30
IO
ISY
IO = 0
–40°C ≤ TA ≤ +125°C
IO = 0
–40°C ≤ TA ≤ +125°C
AD8652
INPUT CAPACITANCE
Differential
Common Mode
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Settling Time, 0.01%
Overload Recovery Time
Total Harmonic Distortion + Noise
NOISE PERFORMANCE
Voltage Noise Density
–0.1
10
30
600
10
30
600
+5.1
9.5
17.5
14.0
15
20.0
23.5
mA
mA
mA
mA
CIN
SR
GBP
THD + N
en
in
6
9
pF
pF
G = 1, RL = 10 kΩ
G=1
G = ±1, 2 V step
VIN × G = 1.2 V+
G = 1, RL = 600 Ω, f = 1 kHz, VIN = 2 V p-p
41
50
0.2
0.1
0.0006
V/μs
MHz
μs
μs
%
f = 10 kHz
f = 100 kHz
f = 10 kHz
5
4.5
4
nV/√Hz
nV/√Hz
fA/√Hz
Rev. C | Page 4 of 20
AD8651/AD8652
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration to GND
Electrostatic Discharge (HBM)
Storage Temperature Range
RM, R Package
Operating Temperature Range
Junction Temperature Range
RM, R Package
Lead Temperature (Soldering, 10 sec)
THERMAL RESISTANCE
Rating
6.0 V
GND to VS + 0.3 V
±6.0 V
Indefinite
4000 V
JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
8-Lead MSOP (RM)
8-Lead SOIC_N (R)
θJA
210
158
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 5 of 20
θJC
45
43
Unit
°C/W
°C/W
AD8651/AD8652
TYPICAL PERFORMANCE CHARACTERISTICS
60
100
VS = 5V
80
40
60
30
40
03301-005
200
160
120
–120
80
–20
40
0
0
0
–40
10
–80
20
–160
20
VOS (µV)
Figure 5. Input Offset Voltage Distribution
0
6
VS = ±2.5V
200
0
–100
–200
0
50
TEMPERATURE (°C)
100
150
200
100
0
03301-006
–300
–50
300
0
Figure 6. Input Offset Voltage vs. Temperature
20
40
60
80
100
TEMPERATURE (°C)
120
140
03301-009
INPUT BIAS CURRENT (pA)
400
100
Figure 9. Input Bias Current vs. Temperature
60
10
VS = ±2.5V
VCM = 0V
TA: –40°C TO +125°C
8
SUPPLY CURRENT (mA)
50
40
30
20
6
4
2
10
1
2
3
4
5
6
7
TCVOS (µV/°C)
8
9
10
11
0
03301-007
0
Figure 7. TCVOS Distribution
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
Figure 10. Supply Current vs. Supply Voltage
Rev. C | Page 6 of 20
6
03301-010
VOS (µV)
5
500
VS = ±2.5V
VCM = 0V
NUMBER OF AMPLIFIERS
2
3
4
COMMON-MODE VOLTAGE (V)
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
300
0
1
03301-008
VOS (µV)
50
–200
NUMBER OF AMPLIFIERS
VS = ±2.5V
VCM = 0V
AD8651/AD8652
12
2.50
VS = 5V
IL = 250µA
VS = ±2.5V
2.00
10
9
8
7
0
50
TEMPERATURE (°C)
100
150
1.00
0.50
0
–50
03301-011
6
–50
1.50
0
50
TEMPERATURE (°C)
100
Figure 14. Output Voltage Swing Low vs. Temperature
Figure 11. Supply Current vs. Temperature
500
100
VS = ±2.5V
VS = ±2.5V
80
300
CMRR (dB)
VOH
200
60
40
VOL
0
20
40
60
CURRENT LOAD (mA)
80
100
0
10
03301-012
0
Figure 12. Output Voltage to Supply Rail vs. Load Current
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
03301-015
20
100
Figure 15. CMRR vs. Frequency
4.997
110
VS = ±2.5V
VS = 5V
IL = 250µA
4.996
105
4.995
CMRR (dB)
4.994
4.993
4.992
100
95
4.990
–50
0
50
TEMPERATURE (°C)
100
150
03301-013
4.991
Figure 13. Output Voltage Swing High vs. Temperature
90
–50
0
50
TEMPERATURE (°C)
100
Figure 16. CMRR vs. Temperature
Rev. C | Page 7 of 20
150
03301-016
(VSY – VOUT) (mV)
400
OUTPUT SWING HIGH (V)
150
03301-014
OUTPUT SWING LOW (mV)
SUPPLY CURRENT (mA)
11
AD8651/AD8652
100
100
VS = ±2.5V
91
88
82
–50
0
50
TEMPERATURE (°C)
100
150
1
10
03301-017
85
10
Figure 17. CMRR vs. Temperature
100
1k
FREQUENCY (Hz)
10k
Figure 20. Voltage Noise Density vs. Frequency
100
80
VS = ±2.5V
CURRENT NOISE DENSITY (fA/√Hz)
VS = ±2.5V
80
PSRR (dB)
+PSRR
60
–PSRR
40
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
60
40
20
0
100
03301-018
20
0
100k
1k
10k
100k
FREQUENCY (Hz)
Figure 18. PSRR vs. Frequency
03301-021
CMRR (dB)
94
03301-020
VOLTAGE NOISE DENSITY (nV/√Hz)
97
Figure 21. Current Noise Density vs. Frequency
100
VS = ±2.5V
VIN = 6.4V
VS = ±2.5V
VIN
VOLTAGE (1V/DIV)
90
VOUT
0
80
–50
0
50
TEMPERATURE (°C)
100
150
TIME (200µs/DIV)
Figure 22. No Phase Reversal
Figure 19. PSRR vs. Temperature
Rev. C | Page 8 of 20
03301-022
85
03301-019
PSRR (dB)
95
AD8651/AD8652
140
60
0
VS = ±2.5V
RL = 1MΩ
CL = 47pF
VS = ±2.5V
120
OPEN-LOOP GAIN (dB)
–45
60
PHASE (Degrees)
80
–90
40
20
–135
CLOSED-LOOP GAIN (dB)
40
100
G = 100
20
G = 10
0
G=1
–20
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
–180
100M
–40
5k
03301-023
–20
10
Figure 23. Open-Loop Gain and Phase vs. Frequency
50k
500k
5M
FREQUENCY (Hz)
50M
300M
03301-026
0
Figure 26. Closed-Loop Gain vs. Frequency
6
117
VS = ±2.5V
RL = 1kΩ
5
115
114
112
–50
0
50
TEMPERATURE (°C)
100
150
4
3
VS = 2.7V
2
1
0
100k
03301-024
113
VS = 5V
Figure 24. Open-Loop Gain vs. Temperature
1M
10M
FREQUENCY (Hz)
VS = ±2.5V
CL = 47pF
AV = 1
VS = ±2.5V
IL = 250µA
IL = 2.5mA
120
VOLTAGE (1V/DIV)
IL = 4.2mA
110
100
90
80
60
0
100
150
200
50
OUTPUT VOLTAGE SWING FROM THE RAILS (mV)
250
TIME (100µs/DIV)
Figure 28. Large Signal Response
Figure 25. Open-Loop Gain vs. Output Voltage Swing
Rev. C | Page 9 of 20
03301-028
70
03301-025
OPEN-LOOP GAIN (dB)
100M
Figure 27. Maximum Output Swing vs. Frequency
140
130
03301-027
MAXIMUM OUTPUT SWING (V)
OPEN-LOOP GAIN (dB)
116
AD8651/AD8652
VS = ±2.5V
VIN = 200mV
AV = 1
VS = ±2.5V
VIN = 200mV
GAIN = –15
0V
VOLTAGE (100mV/DIV)
OUTPUT
–2.5V
200mV
INPUT
TIME (10µs/DIV)
TIME (200ns/DIV)
Figure 32. Positive Overload Recovery Time
Figure 29. Small Signal Response
40
VS = ±2.5V
OUTPUT IMPEDANCE (Ω)
VS = ±2.5V
VIN = 200mV
AV = 1
20
–OS
15
+OS
10
30
20
GAIN = 10
GAIN = 1
10
5
20
30
40
CAPACITANCE (pF)
50
60
70
0
10
100
Figure 30. Small Signal Overshoot vs. Load Capacitance
10k
100k
Figure 33. Output Impedance vs. Frequency
60
VS = ±2.5V
VIN = 200mV
GAIN = –15
VS = ±1.35V
VCM = 0V
50
NUMBER OF AMPLIFIERS
2.5V
1k
FREQUENCY (Hz)
03301-033
10
0V
0V
–200mV
40
30
20
Figure 31. Negative Overload Recovery Time
Figure 34. Input Offset Voltage Distribution
Rev. C | Page 10 of 20
03301-034
VOS (µV)
200
160
120
80
40
0
–40
–80
0
–200
TIME (200ns/DIV)
03301-031
10
–120
0
–160
0
GAIN = 100
03301-030
SMALL SIGNAL OVERSHOOT (%)
30
25
03301-032
03301-029
0V
AD8651/AD8652
300
500
VS = ±1.35V
VS = ±1.35V
VCM = 0V
200
400
(VSY – VOUT) (mV)
0
–100
300
VOH
200
VOL
100
–200
0
50
TEMPERATURE (°C)
100
150
0
03301-035
–300
–50
Figure 35. Input Offset Voltage vs. Temperature
80
0
20
40
60
CURRENT LOAD (mA)
80
Figure 38. Output Voltage to Supply Rail vs. Load Current
2.697
VS = 2.7V
VS = 2.7V
IL = 250µA
2.696
60
OUTPUT SWING HIGH (V)
INPUT OFFSET VOLTAGE (µV)
100
03301-038
VOS (µV)
100
40
20
2.695
2.694
2.693
2.692
0
1
2
INPUT COMMON-MODE VOLTAGE (V)
3
2.690
–50
Figure 36. Input Offset Voltage vs. Common-Mode Voltage
0
50
TEMPERATURE (°C)
100
Figure 39. Output Voltage Swing High vs. Temperature
11
3.00
VS = ±1.35V
VS = 2.7V
IL = 250µA
2.50
OUTPUT SWING LOW (mV)
9
8
7
2.00
1.50
1.00
0.50
0
50
TEMPERATURE (°C)
100
150
03301-037
SUPPLY CURRENT (mA)
10
6
–50
150
Figure 37. Supply Current vs. Temperature
0
–50
0
50
TEMPERATURE (°C)
100
Figure 40. Output Voltage Swing Low vs. Temperature
Rev. C | Page 11 of 20
150
03301-040
0
03301-036
–20
03301-039
2.691
AD8651/AD8652
30
20
15
Figure 41. No Phase Reversal
–OS
10
+OS
5
0
10
20
30
40
CAPACITANCE (pF)
50
60
70
03301-044
TIME (200µs/DIV)
VS = ±1.35V
VIN = 200mV
25
0
03301-041
VOLTAGE (1V/DIV)
SMALL SIGNAL OVERSHOOT (%)
VS = ±1.35V
AV = 1
Figure 44. Small Signal Overshoot vs. Load Capacitance
VS = ±1.35V
CL = 47pF
AV = 1
VS = ±1.35V
VIN = 200mV
GAIN = –10
VOLTAGE (500mV/DIV)
1.35V
0V
0V
TIME (100µs/DIV)
03301-045
03301-042
–200mV
TIME (200ns/DIV)
Figure 42. Large Signal Response
Figure 45. Negative Overload Recovery Time
VS = ±1.35V
VIN = 200mV
CL = 47pF
AV = 1
VS = ±1.35V
VIN = 200mV
GAIN = –10
VOLTAGE (100mV/DIV)
0V
–1.35V
200mV
Figure 43. Small Signal Response
TIME (200ns/DIV)
Figure 46. Positive Overload Recovery Time
Rev. C | Page 12 of 20
03301-046
TIME (10µs/DIV)
03301-043
0V
AD8651/AD8652
100
120
VS = ±1.35V
VS = ±1.35V
RL = 1kΩ
118
80
116
AVO (dB)
CMRR (dB)
60
40
114
112
20
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
108
–50
03301-047
0
10
Figure 47. CMRR vs. Frequency
40
–PSRR
40
20
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
0
G = 100
G = 10
G=1
–20
–40
5k
03301-048
1
20
VS = ±1.35V
RL = 1MΩ
CL = 47pF
Figure 48. PSRR vs. Frequency
50k
500k
5M
FREQUENCY (Hz)
50M
300M
Figure 51. Closed-Loop Gain vs. Frequency
140
0
0
VS = ±1.35V
120
CHANNEL SEPARATION (dB)
–20
–45
80
60
–90
40
20
PHASE (Degrees)
100
–135
VIN
–40
R1
10kΩ
+2.5V
28mV p-p
–60
V+
V–
R2
100Ω
V–
VOUT
V+
–2.5V
–80
–100
–120
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
–180
Figure 49. Open-Loop Gain and Phase vs. Frequency
–140
100
VS = ±2.5V
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 52. Channel Separation vs. Frequency.
Rev. C | Page 13 of 20
10M
03301-052
100
03301-049
0
03301-051
CLOSED-LOOP GAIN (dB)
60
PSRR (dB)
150
60
+PSRR
OPEN-LOOP GAIN (dB)
100
VS = ±1.35V
80
–20
10
50
TEMPERATURE (°C)
Figure 50. Open-Loop Gain vs. Temperature
100
0
0
03301-050
110
AD8651/AD8652
APPLICATIONS
The AD865x family is available in standard op amp pinouts,
making DigiTrim completely transparent to the user. The input
stage of the amplifiers is a true rail-to-rail architecture, allowing
the input common-mode voltage range of the op amp to extend
to both positive and negative supply rails. The open-loop gain
of the AD865x with a load of 1 kΩ is typically 115 dB.
The AD865x can be used in any precision op amp application.
The amplifiers do not exhibit phase reversal for common-mode
voltages within the power supply. With voltage noise of
4.5 nV/√Hz and –105 dB distortion for 10 kHz, 2 V p-p signals,
the AD865x is a great choice for high resolution data
acquisition systems. Their low noise, sub-pA input bias current,
precision offset, and high speed make them superb preamps for
fast photodiode applications. The speed and output drive
capabilities of the AD865x also make the amplifiers useful in
video applications.
The NMOS and PMOS input stages are separately trimmed
using DigiTrim to minimize the offset voltage in both differential pairs. Both NMOS and PMOS input differential pairs are
active in a 500 mV transition region when the input commonmode voltage is approximately 1.5 V below the positive supply
voltage. A special design technique improves the input offset
voltage in the transition region that traditionally exhibits a
slight VOS variation. As a result, the common-mode rejection
ratio is improved within this transition band. Compared to the
Burr Brown OPA350 amplifier, shown in Figure 53, the
AD865x, shown in Figure 54, exhibits much lower offset voltage
shift across the entire input common-mode range, including the
transition region.
600
400
200
0
–200
–400
–600
0
1
2
3
4
COMMON-MODE VOLTAGE (V)
5
6
03301-053
The AD865x family consists of voltage feedback, rail-to-rail
input and output precision CMOS amplifiers that operate from
2.7 V to 5.5 V of power supply voltage. These amplifiers use
Analog Devices, Inc. DigiTrim technology to achieve a higher
degree of precision than is available from most CMOS
amplifiers. DigiTrim technology, used in a number of Analog
Devices amplifiers, is a method of trimming the offset voltage of
the amplifier after it has been assembled. The advantage of
post-package trimming is that it corrects any offset voltages
caused by the mechanical stresses of assembly.
VOS (µV)
THEORY OF OPERATION
Figure 53. Input Offset Distribution over Common-Mode
Voltage for the OPA350
Rail-to-Rail Output Stage
600
400
200
VOS (µV)
The voltage swing of the output stage is rail-to-rail and is
achieved by using an NMOS and PMOS transistor pair connected in a common source configuration. The maximum
output voltage swing is proportional to the output current, and
larger currents will limit how close the output voltage can get to
the proximity of the output voltage to the supply rail. This is a
characteristic of all rail-to-rail output amplifiers. With 40 mA of
output current, the output voltage can reach within 5 mV of the
positive and negative rails. At light loads of >100 kΩ, the output
swings within ~1 mV of the supplies.
0
–200
The input common-mode voltage range of the AD865x extends
to both positive and negative supply voltages. This maximizes
the usable voltage range of the amplifier, an important feature
for single-supply and low voltage applications. This rail-to-rail
input range is achieved by using two input differential pairs, one
NMOS and one PMOS, placed in parallel. The NMOS pair is active
at the upper end of the common-mode voltage range, and the
PMOS pair is active at the lower end of the common-mode range.
Rev. C | Page 14 of 20
–600
0
1
2
3
4
COMMON-MODE VOLTAGE (V)
5
Figure 54. Input Offset Distribution over Common-Mode
Input Protection for the AD865x
6
03301-061
–400
Rail-to-Rail Input Stage
AD8651/AD8652
Input Protection
As with any semiconductor device, if a condition exists for the
input voltage to exceed the power supply, the device input
overvoltage characteristic must be considered. The inputs of the
AD865x family are protected with ESD diodes to either power
supply. Excess input voltage energizes internal PN junctions in
the AD865x, allowing current to flow from the input to the
supplies. This results in an input stage with picoamps of input
current that can withstand up to 4000 V ESD events (human
body model) with no degradation.
Excessive power dissipation through the protection devices
destroys or degrades the performance of any amplifier. Differential
voltages greater than 7 V result in an input current of approximately
(| VCC – VEE | – 0.7 V)/RI, where RI is the resistance in series with
the inputs. For input voltages beyond the positive supply, the
input current is approximately (VIN – VCC – 0.7)/RI. For input
voltages beyond the negative supply, the input current is about
(VIN – VEE + 0.7)/RI. If the inputs of the amplifier sustain
differential voltages greater than 7 V or input voltages beyond
the amplifier power supply, limit the input current to 10 mA by
using an appropriately sized input resistor (RI), as shown in
Figure 55.
(| VCC – VEE | – 0.7V)
FOR LARGE | VCC – VEE |
+
AD865x
– VIN +
(VIN – VEE – 0.7V)
RI >
30mA
–
30mA
(VIN – VEE + 0.7V)
RI >
30mA
FOR VIN BEYOND
SUPPLY VOLTAGES
RI
Grounding
A ground plane layer is important for densely packed PC
boards to spread the current-minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and, therefore, the high
frequency impedance of the path. High speed currents in an
inductive ground return create an unwanted voltage noise.
The length of the high frequency bypass capacitor leads is
critical. A parasitic inductance in the bypass grounding works
against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location. Because load currents also flow from the
supplies, the ground for the load impedance should be at the
same physical location as the bypass capacitor grounds. For the
larger value capacitors, intended to be effective at lower
frequencies, the current return path distance is less critical.
Leakage Currents
+ VO
03301-054
RI >
Bypassing schemes are designed to minimize the supply
impedance at all frequencies with a parallel combination of
capacitors of 0.1 μF and 4.7 μF. Chip capacitors of 0.1 μF (X7R
or NPO) are critical and should be as close as possible to the
amplifier package. The 4.7 μF tantalum capacitor is less critical
for high frequency bypassing, and, in most cases, only one is
needed per board at the supply inputs.
Figure 55. Input Protection Method
Overdrive Recovery
Overdrive recovery is defined as the time it takes for the output
of an amplifier to come off the supply rail after an overload signal is
initiated. This is usually tested by placing the amplifier in a closedloop gain of 15 with an input square wave of 200 mV p-p while the
amplifier is powered from either 5 V or 3 V. The AD865x family
has excellent recovery time from overload conditions (see Figure 31
and Figure 32). The output recovers from the positive supply rail
within 200 ns at all supply voltages. Recovery from the negative rail
is within 100 ns at 5 V supply.
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Power Supply Bypassing
Power supply pins can act as inputs for noise, so care must be
taken that a noise-free, stable dc voltage is applied. The purpose
of bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise.
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than the
input bias current of the AD865x family. Any voltage differential
between the inputs and nearby traces sets up leakage currents
through the PC board insulator, for example 1 V/100 G = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem).
To significantly reduce leakages, put a guard ring (shield)
around the inputs and the input leads that are driven to the
same voltage potential as the inputs. This ensures that there is
no voltage potential between the inputs and the surrounding
area to set up any leakage currents. To be effective, the guard
ring must be driven by a relatively low impedance source and
should completely surround the input leads on all sides, above
and below, using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the
amount of material between the input leads and the guard
ring helps to reduce the absorption. Also, low absorption
materials, such as Teflon® or ceramic, may be necessary in
some instances.
Rev. C | Page 15 of 20
AD8651/AD8652
•
Input Capacitance
Another way to stabilize an op amp driving a large capacitive
load is to use a snubber network, as shown in Figure 57. Because
there is not any isolation resistor in the signal path, this method
has the significant advantage of not reducing the output swing.
The exact values of RS and CS are derived experimentally. In
Figure 57, an optimum RS and CS combination for a capacitive
load drive ranging from 50 pF to 1 nF was chosen. For this,
RS = 3 Ω and CS = 10 nF were chosen.
Along with bypassing and grounding, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at high
frequencies, which in turn increases the amplifier gain, causing
peaking in the frequency response or oscillations. With the
AD865x, additional input damping is required for stability with
capacitive loads greater than 47 pF with direct input to output
feedback (see the Output Capacitance section).
V+
+
When using high speed amplifiers, it is important to consider
the effects of the capacitive loading on amplifier stability.
Capacitive loading interacts with the output impedance of the
amplifier, causing reduction of the BW as well as peaking and
ringing of the frequency response. To reduce the effects of the
capacitive loading and allow higher capacitive loads, there are
two commonly used methods.
As shown in Figure 56, place a small value resistor (RS) in
series with the output to isolate the load capacitor from the
amplifier output. Heavy capacitive loads can reduce the
phase margin of an amplifier and cause the amplifier
response to peak or become unstable. The AD865x is able
to drive up to 47 pF in a unity gain buffer configuration
without oscillation or external compensation. However, if
an application requires a higher capacitive load drive when
the AD865x is in unity gain, the use of external isolation
networks can be used. The effect produced by this resistor
is to isolate the op amp output from the capacitive load.
The required amount of series resistance has been
tabulated in Table 5 for different capacitive loads. While
this technique improves the overall capacitive load drive
for the amplifier, its biggest drawback is that it reduces the
output swing of the overall circuit.
VCC
U1
2
V+
AD865x
–
0
RL
Settling Time
The settling time of an amplifier is defined as the time it takes
for the output to respond to a step change of input and enter
and remain within a defined error band, as measured relative to
the 50% point of the input pulse. This parameter is especially
important in measurements and control circuits where amplifiers are used to buffer A/D inputs or DAC outputs. The design of
the AD865x family combines a high slew rate and a wide gain
bandwidth product to produce an amplifier with very fast
settling time. The AD865x is configured in the noninverting
gain of 1 with a 2 V p-p step applied to its input. The AD865x
family has a settling time of about 130 ns to 0.01% (2 mV). The
output is monitored with a 10×, 10 M, 11.2 pF scope probe.
THD Readings vs. Common-Mode Voltage
Total harmonic distortion of the AD865x family is well below
0.0004% with any load down to 600 Ω. The distortion is a
function of the circuit configuration, the voltage applied, and
the layout, in addition to other factors. The AD865x family
outperforms its competitor for distortion, especially at
frequencies below 20 kHz, as shown in Figure 58.
0.1
VSY = +3.5V/–1.5V
VOUT = 2.0V p-p
0.05
RL
0
CL
Figure 57. Snubber Network
V–
CL
CS
V–
VOUT
RS
0
0.02
0.01
Figure 56. Driving Large Capacitive Loads
Table 5. Optimum Values for Driving Large Capacitive Loads
CL
100 pF
500 pF
1.0 nF
–
RS
50 Ω
35 Ω
25 Ω
0.005
0.002
OPA350
0.001
0.0005
AD8651
0.0002
0.0001
20
50
100
500
1k
2k
FREQUENCY (Hz)
5k
Figure 58. Total Harmonic Distortion
Rev. C | Page 16 of 20
20k
03301-057
+
03301-055
3
VIN
VOUT
RS
V–
200mV
THD + NOISE (%)
•
V+
AD865x
03301-056
Output Capacitance
AD8651/AD8652
5V
+3.5V
10kΩ
AD865x
–
600Ω
47pF
1µF
03301-058
VIN
2V p-p
–1.5V
10kΩ
The AD865x is configured in an inverting gain of 1 with a 5 V
single supply. Input of 45 kHz is applied, and the ADC samples
at 250 kSPS. The results of this solution are listed in Table 6.
The advantage of this circuit is that the amplifier and ADC can
be powered with the same power supply. For the case of
a noninverting gain of 1, the input common-mode voltage
encompasses both supplies.
Parameter
THD + N
SFDR
2nd Harmonics
3rd Harmonics
fSAMPLE = 250kSPS
fIN = 45kHz
INPUT RANGE = 0V TO 5V
–60
–80
–100
–120
–140
10
20
30 40
50 60 70 80
FREQUENCY (kHz)
90
100 110 120
03301-059
AMPLITUDE (dB of Full Scale)
–40
0
1kΩ
IN
Figure 60. Frequency Response of AD865x Driving a 16-Bit ADC
Rev. C | Page 17 of 20
AD7685
2.7nF
Table 6. Data Acquisition Solution of Figure 60
For more information about the AD7685 data converter, go to
http://www.analog.com/Analog_Root/productPage/productHome/0%2C21
21%2CAD7685%2C00.html
–160
–
– V
VCC
33Ω
1kΩ
The AD865x family is an excellent choice for driving high
speed, high precision ADCs. The driver amplifier for this type
of application needs low THD + N as well as quick settling time.
Figure 61 shows a complete single-supply data acquisition
solution. The AD865x family drives the AD7685, a 250 kSPS,
16-bit data converter. 1
–20
V+
Figure 61. AD865x Driving a 16-Bit ADC
Driving a 16-Bit ADC
0
U1
+
AD865x
2
VIN
0V TO 5V
fIN = 45kHz
Figure 59. THD + N Test Circuit
1
3
VOUT
03301-060
+
Reading (dB)
105.2
106.6
107.7
113.6
AD8651/AD8652
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.80
0.60
0.40
8°
0°
0.23
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 62. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 63. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. C | Page 18 of 20
060506-A
4.00 (0.1574)
3.80 (0.1497)
AD8651/AD8652
ORDERING GUIDE
Model
AD8651ARM-REEL
AD8651ARM-R2
AD8651ARMZ-REEL1
AD8651ARMZ-R21
AD8651AR
AD8651AR-REEL
AD8651AR-REEL7
AD8651ARZ1
AD8651ARZ-REEL1
AD8651ARZ-REEL71
AD8652ARMZ-R21
AD8652ARMZ-REEL1
AD8652ARZ1
AD8652ARZ-REEL1
AD8652ARZ-REEL71
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Z = Pb-free part; # denotes lead-free product may be top or bottom marked.
Rev. C | Page 19 of 20
Package Option
RM-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
R-8
R-8
R-8
Branding
BEA
BEA
BEA#
BEA#
A05
A05
AD8651/AD8652
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03301-0-8/06(C)
Rev. C | Page 20 of 20