AD AD9215 10-bit, 65/80/105 msps, 3v a/d converter Datasheet

10-Bit, 65/80/105 MSPS,
3 V A/D Converter
AD9215
FEATURES
APPLICATIONS
AVDD
DRVDD
VIN+
PIPELINE
ADC CORE
SHA
VIN–
REFT
AD9215
REFB
CORRECTION LOGIC
10
OR
OUTPUT BUFFERS
D9 (MSB)
D0
VREF
CLOCK
DUTY CYCLE
STABLIZER
SENSE
Ultrasound equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
REF
SELECT
MODE
SELECT
0.5V
AGND
CLK
PDWN
MODE DGND
02874-A-001
Single 3 V supply operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist)
SFDR = 77 dBc (to Nyquist)
Low power ADC core: 96 mW at 65 MSPS, 104 mW
@ 80 MSPS, 120 mW at 105 MSPS
Differential input with 300 MHz bandwidth
On-chip reference and sample-and-hold amplifier
DNL = ±0.25 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
PRODUCT DESCRIPTION
The AD9215 is a family of monolithic, single 3 V supply, 10-bit,
65/80/105 MSPS analog-to-digital converters (ADC). This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9215 uses a multistage differential
pipelined architecture with output error correction logic to provide 10-bit accuracy at 105 MSPS data rates and to guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential sample-and-hold amplifier (SHA) allows for a variety of user-selectable input ranges
and offsets including single-ended applications. It is suitable for
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling single-channel inputs at
frequencies well beyond the Nyquist rate. Combined with
power and cost savings over previously available ADCs, the
AD9215 is suitable for applications in communications, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer compensates for wide variations in the
clock duty cycle while maintaining excellent performance. The digital
output data is presented in straight binary or twos complement formats. An out-of-range signal indicates an overflow condition, which
can be used with the MSB to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9215 is available in both a 28-lead surface-mount plastic package and a
32-lead chip scale package and is specified over the industrial
temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
The AD9215 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families.
Operating at 105 MSPS, the AD9215 core ADC consumes
a low 120 mW; at 80 MSPS, the power dissipation is 104
mW; and at 65 MSPS, the power dissipation is 96 mW.
The patented SHA input maintains excellent performance
for input frequencies up to 200 MHz and can be configured for single-ended or differential operation.
The AD9215 is part of several pin compatible 10-, 12-, and
14-bit low power ADCs. This allows a simplified upgrade
from 10 bits to 12 bits for systems up to 80 MSPS.
The clock duty cycle stabilizer maintains converter performance over a wide range of clock pulse widths.
The out of range (OR) output bit indicates when the signal
is beyond the selected input range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9215
TABLE OF CONTENTS
Specifications..................................................................................... 3
REVISION HISTORY
Absolute Maximum Ratings............................................................ 6
2/04—Data Sheet Changed from a REV. 0 to a REV. A
Explanation of Test Levels ........................................................... 6
Renumbered Figures and Tables ..............................UNIVERSAL
ESD Caution.................................................................................. 6
Changes to Product Title................................................................ 1
Pin Configurations and Function Descriptions ........................... 7
Changes to Features ........................................................................ 1
Equivalent Circuits....................................................................... 8
Changes to Product Description ................................................... 1
Definitions of Specifications ....................................................... 8
Changes to Product Highlights ..................................................... 1
Typical Performance Characteristics ........................................... 10
Changes to Specifications............................................................... 2
Applying the AD9215 Theory of Operation............................... 14
Changes to Figure 2......................................................................... 4
Clock Input and Considerations .............................................. 15
Changes to Figures 9 to 11 ........................................................... 10
Evaluation Board ........................................................................ 18
Added Figure 14 ............................................................................ 10
Outline Dimensions ....................................................................... 33
Added Figures 16 and 18 .............................................................. 11
Ordering Guide........................................................................... 34
Changes to Figures 21 to 24 and 25 to 26................................... 12
Deleted Figure 25........................................................................... 12
Changes to Figures 28 and 29 ...................................................... 13
Changes to Figure 31..................................................................... 14
Changes t0 Figure 35..................................................................... 16
Changes to Figures 50 through 58............................................... 26
Added Table 11 .............................................................................. 31
Updated Outline Dimensions...................................................... 32
Changes to Ordering Guide ......................................................... 33
5/03—Revision 0: Initial Version
Rev. A | Page 2 of 36
AD9215
SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise
noted.
Table 1. DC Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error1
Gain Error
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error1
Reference Voltage (1 V Mode)
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
IDRVDD
PSRR
POWER CONSUMPTION
Sine Wave Input
IAVDD
IDRVDD
Standby Power4
1
2
1
2
2
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Temp
Full
Test
Level
VI
Min
10
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
Guaranteed
±0.3
±2.0
0
+1.5
+4.0
−1.0 ±0.5
+1.0
±0.5
±1.2
Guaranteed
±0.3
±2.0
+1.5
+4.0
−1.0 ±0.5
+1.0
±0.5
±1.2
Guaranteed
±0.3
±2.0
+1.5
+4.0
−1.0
±0.6
+1.2
±0.65 ±1.2
Full
Full
Full
V
V
V
+15
+30
±230
+15
+30
±230
+15
+30
±230
Full
Full
Full
Full
VI
V
V
V
±2
0.2
±1
0.2
25°C
25°C
V
V
0.8
0.4
0.8
0.4
0.8
0.4
LSB rms
LSB rms
Full
Full
Full
Full
IV
IV
V
V
1
2
2
7
1
2
2
7
1
2
2
7
V p-p
V p-p
pF
kΩ
Full
Full
IV
IV
Full
25°C
Full
Full
25°C
25°C
2.7
2.25
Typ
Max
Min
10
±35
3.0
2.5
3.3
3.6
VI
V
V
32
7.0
± 0.1
35
VI
V
V
96
18
1.0
Typ
±2
0.2
±1
0.2
2.7
2.25
Max
Min
10
±35
3.0
2.5
3.3
3.6
34.5
8.6
± 0.1
39
Typ
±2
0.2
±1
0.2
2.7
2.25
Max
Unit
Bits
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
±35
mV
mV
mV
mV
3.0
2.5
3.3
3.6
V
V
40
11.3
± 0.1
44
mA
mA
% FSR
2
2
2
1
104
20
1.0
120
25
1.0
mW
mW
mW
With a 1.0 V internal reference.
Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
4
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
2
Rev. A | Page 3 of 36
AD9215
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference,
AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted.
Table 2. AC Specifications
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = Nyquist
1
fIN = 70 MHz
fIN = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = Nyquist
1
fIN = 70 MHz
fIN = 100 MHz
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz
fIN = Nyquist
1
fIN = 70 MHz
fIN = 100 MHz
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz
fIN = Nyquist
1
fIN = 70 MHz
fIN = 100 MHz
TWO-TONE SFDR (AIN = –7 dBFS)
fIN1 = 70.3 MHz, fIN2 = 71.3 MHz
fIN1 = 100.3 MHz, fIN2 = 101.3 MHz
ANALOG BANDWIDTH
1
AD9215BRU-65/
AD9215BCP-65
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Min
Typ
Min
Typ
Min
Temp
Test
Level
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
56.0
57.0
56.0
56.5
58.5
59.0
58.0
58.5
56.0
57.0
56.0
56.5
58.5
59.0
58.0
58.5
58.0
57.5
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
55.8
56.5
55.8
56.3
58.5
59.0
58.0
58.5
55.7
56.8
55.5
56.3
58.5
58.5
58.0
58.5
56.0
55.5
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
9.1
9.2
9.1
9.1
9.5
9.6
9.4
9.5
9.0
9.3
9.0
9.0
9.5
9.5
9.4
9.5
9.1
9.0
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
−78
−80
−77
−78
−64
−65
−64
−65
−78
−80
−76
−78
−70
−70
−64
−65
−63
−65
−78
−84
−74
−75
−75
−74
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
−77
−78
−77
−78
−67
−68
−67
−68
−77
−77
−77
−77
−80
−80
−66
−68
−66
−68
−73
−75
−71
−75
-75
−75
25°C
25°C
25°C
V
V
V
300
Tested at fIN = 35 MHz for AD9215-65; fIN = 39 MHz for AD9215-80; and fIN = 50 MHz for AD9215-105.
Rev. A | Page 4 of 36
Max
75
74
300
Max
56.6
56.4
56.5
56.1
9.2
9.1
Typ
Max
Unit
57.5
58.5
57.5
58.0
57.8
57.7
dB
dB
dB
dB
dB
dB
57.6
58.2
57.3
57.8
57.7
57.4
dB
dB
dB
dB
dB
dB
9.3
9.5
9.4
9.4
9.4
9.3
Bits
Bits
Bits
Bits
Bits
Bits
75
74
300
−70
−61
−66
−63
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
AD9215
Table 3. Digital Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS1
DRVDD = 2.5 V
High Level Output Voltage
Low Level Output Voltage
1
Temp
Test
Level
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
Full
Full
IV
IV
Min
Typ
AD9215BRU-80/
AD9215BCP-80
Max
Min
2.0
Typ
AD9215BRU-105/
AD9215BCP-105
Max
Min
2.0
0.8
+10
+10
−650
−70
Typ
Unit
0.8
+10
+10
V
V
µA
µA
pF
2.0
0.8
+10
+10
−650
−70
2
−650
−70
2
2.45
Max
2
2.45
2.45
0.05
0.05
V
V
0.05
Output voltage levels measured with a 5 pF load on each output.
Table 4. Switching Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLOCK Period
DATA OUTPUT PARAMETERS
Output Delay1 (tOD)
Pipeline Delay (Latency)
Aperture Delay
Aperture Uncertainty (Jitter)
Wake-Up Time2
OUT-OF-RANGE RECOVERY TIME
Temp
Test
Level
Full
Full
Full
VI
V
V
Full
Full
25°C
25°C
25°C
25°C
VI
V
V
V
V
V
AD9215BRU-105/
AD9215BCP-105
Unit
Min
Typ
Max
65
Min
Typ
Max
Min
80
5
15.4
4.8
5
2.4
0.5
7
1
6.5
2.5
9.5
4.8
5
2.4
0.5
7
1
6.5
2.5
4.8
5
2.4
0.5
7
1
N+1
N+2
N–1
N+8
N+3
tA
N+7
N+4
N+5
N+6
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
tPD
N+2
02874-A-002
CLK
DATA
OUT
Figure 2. Timing Diagram
1
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Rev. A | Page 5 of 36
Max
5
12.5
2.5
Typ
105
5
N
ANALOG
INPUT
AD9215BRU-80/
AD9215BCP-80
6.5
MSPS
MSPS
ns
ns
Cycles
ns
ps rms
ms
Cycles
AD9215
ABSOLUTE MAXIMUM RATINGS1
Table 5.
EXPLANATION OF TEST LEVELS
With
Respect to
Mnemonic
ELECTRICAL
AVDD
AGND
DRVDD
DRGND
AGND
DRGND
AVDD
DRVDD
Digital Outputs
DRGND
CLK, MODE
AGND
VIN+, VIN−
AGND
VREF
AGND
SENSE
AGND
REFB, REFT
AGND
PDWN
AGND
ENVIRONMENTAL2
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
Min
Max
Unit
−0.3
−0.3
−0.3
−3.9
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
+3.9
+3.9
+0.3
+3.9
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
V
V
V
V
V
V
V
V
V
V
V
−40
+85
150
300
+150
°C
°C
°C
°C
−65
Test Level
I
100% production tested.
II
100% production tested at 25°C and sample tested at
specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI
100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for military devices.
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances 28-lead TSSOP: θJA = 67.7°C/W, 32-lead LFCSP:
θJA = 32.7°C/W; heat sink soldered down to ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 36
AD9215
25 REFB
26 REFT
DNC 1
24 VREF
CLK 2
23 SENSE
22 MODE
DNC 3
23 DRGND
AD9215
PDWN 4
TOP VIEW 22 D5
AVDD 7
(Not to Scale)
21 D4
AGND 8
DNC 5
21 OR
20 D9 (MSB)
TOP VIEW
(Not to Scale)
DNC 6
19 D8
AVDD 12
17 D0 (LSB)
16 DNC
PDWN 14
15 DNC
DNC = DO NOT CONNECT
02874-A-003
CLK 13
DRVDD 16
18 D1
DRGND 15
17 D6
AGND 11
D5 14
DNC 8
D4 13
19 D2
D3 12
18 D7
VIN– 10
D2 11
DNC 7
D1 10
20 D3
(LSB) D0 9
VIN+ 9
02874-A-004
AD9215
27 AVDD
24 DRVDD
28 AGND
25 D6
REFB 5
29 VIN+
26 D7
VREF 4
30 VIN–
27 D8
SENSE 3
31 AGND
28 D9 (MSB)
OR 1
MODE 2
REFT 6
32 AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DNC = DO NOT CONNECT
Figure 4. LFCSP (CP-32)
Figure 3. TSSOP (RU-28)
Table 6. Pin Function Descriptions
TSSOP Pin No.
1
2
3
4
5
6
7, 12
8, 11
9
10
13
14
15 to 16
17 to 22,
25 to 28
23
24
LFCSP Pin No.
21
22
23
24
25
26
27, 32
28, 31
29
30
2
4
1, 3, 5 to 8
9 to 14,
17 to 20
15
16
Mnemonic
OR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
VIN−
CLK
PDWN
DNC
D0 (LSB) to
D9 (MSB)
DRGND
DRVDD
Description
Out-of-Range Indicator.
Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.
Reference Mode Selection.
Voltage Reference Input/Output.
Differential Reference (Negative).
Differential Reference (Positive).
Analog Power Supply.
Analog Ground.
Analog Input Pin (+).
Analog Input Pin (−).
Clock Input Pin.
Power-Down Function Selection (Active High).
Do not connect, recommend floating this pin.
Data Output Bits.
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DRGND with a
minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.
Rev. A | Page 7 of 36
AD9215
EQUIVALENT CIRCUITS
fications define an acceptable clock duty cycle.
AVDD
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicate that all 1024
codes, respectively, must be present over all operating ranges.
02874-A-005
MODE
Effective Number of Bits (ENOB)
Figure 5. Equivalent Analog Input Circuit
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to obtain a
measure of performance expressed as N, the effective number of
bits
AVDD
MODE
N = (SINAD – 1.76)/6.02
02874-A-006
20kΩ
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
Figure 6. Equivalent MODE Input Circuit
Gain Error
DRVDD
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur at
an analog value 1 1/2 LSB below the positive full scale. Gain
error is the deviation of the actual difference between the first
and last code transitions and the ideal difference between the
first and last code transitions.
02874-A-007
D9–D0,
OR
Figure 7. Equivalent Digital Output Circuit
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
AVDD
2.6kΩ
2.6kΩ
02874-A-008
CLK
Maximum Conversion Rate
Figure 8. Equivalent Digital Input Circuit
The clock rate at which parametric testing is performed.
Minimum Conversion Rate
DEFINITIONS OF SPECIFICATIONS
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as frequency-dependent noise
on the input to the ADC.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these speci-
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Offset Error
The major carry transition should occur for an analog value 1/2
LSB below VIN+ = VIN−. Zero error is defined as the deviation
of the actual transition from that point.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Output Propagation Delay
The delay between the clock logic threshold and the time when
Rev. A | Page 8 of 36
AD9215
all bits are within valid logic levels.
Spurious-Free Dynamic Range (SFDR)
Power Supply Rejection
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Signal-to-Noise and Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for SINAD is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It may be reported in dBc
(i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full scale).
Rev. A | Page 9 of 36
AD9215
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V with DCS enabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V, unless
otherwise noted.
80
0
–20
70
–40
1V p-p SFDR (dBc)
65
–100
55
0
6.56
13.13
19.69 26.25 32.81
FREQUENCY (MHz)
39.38
45.94
1V p-p SNR (dB)
50
52.50
5
35
45
55
ENCODE (MSPS)
2V p-p SFDR (dBc)
AIN = –0.5dBFS
SNR = 57.8
ENOB = 9.4 BITS
SFDR = 75.0dB
dB
–60
–100
55
02874-A-063
60
19.69 26.25 32.81
FREQUENCY (MHz)
AIN = –0.5dBFS
65
–80
13.13
85
1V p-p SFDR (dBc)
70
6.56
75
75
–40
0
65
39.38
45.94
2V p-p SNR (dB)
02874-A-013
–20
1V p-p SNR (dB)
50
5
52.50
15
25
35
45
ENCODE (MSPS)
55
65
Figure 13. AD9215-65 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
Figure 10. Single-Tone 32k FFT with fIN = 70.3 MHz, fSAMPLE = 105 MSPS
85
0
2V p-p SFDR
AIN = –0.5dBFS
SNR = 57.7
ENOB = 9.3 BITS
SFDR = 75dB
–20
80
75
dB
–40
–60
70
65
–100
60
02874-A-065
–80
–120
25
80
0
–120
15
Figure 12. AD9215-80 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
Figure 9. Single-Tone 32k FFT with fIN = 10.3 MHZ, fSAMPLE = 105 MSPS
AMPLITUDE (dBFS)
2V p-p SNR (dB)
0
6.56
13.13
19.69 26.25 32.81
FREQUENCY (MHz)
39.38
45.94
02874-A-066
–120
02874-A-062
60
02874-A-012
–60
–80
AMPLITUDE (dBFS)
AIN = –0.5dBFS
75
dB
AMPLITUDE (dBFS)
2V p-p SFDR (dBc)
AIN = –0.5dBFS
SNR = 58.0
ENOB = 9.4 BITS
SFDR = 75.5dB
2V p-p SNR
55
0
52.50
20
40
60
80
100
fSAMPLE (MSPS)
Figure 11. Single-Tone 32k FFT with fIN = 100.3 MHz, fSAMPLE = 105 MSPS
Rev. A | Page 10 of 36
Figure 14. AD9215-105 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
AD9215
80
80
70
75
SFDR
60
70
1V p-p SFDR (dBc)
dB
dB
50
80dB REFERENCE LINE
40
65
2V p-p SNR (dB)
30
60
1V p-p SNR (dB)
–45
–40
–35 –30 –25 –20 –15
ANALOG INPUT LEVEL
–10
–5
50
0
02874-A-072
0
–50
SNR
2V p-p SFDR (dBc)
10
55
02874-A-014
20
0
Figure 15. AD9215-80 SNR/SFDR vs.
Analog Input Drive Level, fSAMPLE = 80 MSPS, fIN = 39.1 MHz
50
100
150
200
FREQUENCY (MHz)
250
300
Figure 18. AD9215-105 SNR/SFDR vs.
fIN, AIN = −0.5 dBFS, fSAMPLE = 105 MSPS
85
80
80
70
75
50
70
dB
dB
2 SFDR dBc
60
40
30
2V p-p SFDR (dBc)
65
–70dBFS
REFERENCE LINE
60
1V p-p SFDR (dBc)
20
2V p-p SNR (dB)
02874-A-067
10
2V p-p
SNR
0
–90
–80
–70
–60
–50
–40
–30
–20
ANALOG INPUT LEVEL (–dBFS)
–10
02874-A-016
55
1V p-p SNR
50
0
0
50
100
150
200
250
300
250
300
fIN (MHz)
Figure 19. AD9215-80 SNR/SFDR vs.
fIN, AIN = −0.5 dBFS, fSAMPLE = 80 MSPS
Figure 16. AD9215-105 SNR/SFDR vs.
Analog Input Drive Level, fSAMPLE = 105 MSPS, fIN = 50.3 MHz
80
80
1V p-p SFDR (dBc)
70
75
2V p-p SFDR (dBc)
60
80dB REFERENCE LINE
dB
40
30
65
1V p-p SNR (dB)
60
20
2V p-p SFDR (dBc)
2V p-p SNR (dB)
–45
–40
–35 –30 –25 –20 –15
ANALOG INPUT LEVEL
–10
–5
02874-A-017
10
0
–50
55
02874-A-015
dB
70
2V p-p SNR (dB)
50
50
0
0
50
100
150
200
ANALOG INPUT (MHz)
Figure 20. AD9215-65 SNR/SFDR vs.
fIN, AIN = −0.5 dBFS, fSAMPLE = 65 MSPS
Figure 17. AD9215-65 SNR/SFDR vs.
Analog Input Drive Level, fSAMPLE = 65 MSPS, fIN = 30.3 MHz
Rev. A | Page 11 of 36
AD9215
80
0
AIN1, AIN2 = –7dBFS
SFDR = 74dBc
70
–20
60
SFDR
–40
dB
dB
50
–60
40
80dBFS REFERENCE LINE
30
–80
02874-A-060
–120
0
13.125
26.250
FREQUENCY (MHz)
39.375
10
0
–60
52.500
Figure 21. Two-Tone 32k FFT with fIN1 = 70.1 MHz,
and fIN2 = 71.1 MHz, fSAMPLE = 105 MSPS
02874-A-073
20
–100
–55
–50
–45
–40
–35 –30 –25
AIN (dBFS)
–20
–15
–10
–5
Figure 24. AD9215-80 Two-Tone SFDR vs. AIN, fIN1 = 100.3 MHz, and fIN2 =
101.3 MHz, fSAMPLE = 105 MSPS
80
0
AIN1, AIN2 = –7dBFS
SFDR = 74dBc
SFDR DCS ON
75
–20
70
SFDR DCS OFF
65
–40
SNR DCS ON
dB
dB
60
–60
55
50
–80
45
SNR DCS OFF
02874-A-061
–120
0
13.125
26.250
FREQUENCY (MHz)
39.375
02874-A-069
40
–100
35
30
20
52.500
Figure 22. Two-Tone 32k FFT with fIN1 = 100.3 MHz,
and fIN2 = 101.3 MHz, fSAMPLE = 105 MSPS
30
40
50
60
CLOCK DUTY CYCLE HIGH (%)
70
80
Figure 25. SINAD, SFDR vs.
Clock Duty Cycle, fSAMPLE = 105 MSPS, fIN = 50.3 MH
80
80
2V p-p SFDR (dBc)
70
75
60
70
dBc
SFDR
40
1V p-p SFDR (dBc)
65
80dBFS REFERENCE LINE
30
60
2V p-p SINAD
20
–55
–45
–35
–25
AIN1, AIN2 (dBFS)
–15
02874-A-070
10
0
–65
55
02874-A-068
dB
50
1V p-p SINAD
50
–5
Figure 23. AD9215-105 Two-Tone SFDR vs. AIN,
fIN1 = 70.1 MHz, and fIN2 = 71.1 MHz, fSAMPLE = 105 MSPS
–40
–20
0
20
40
TEMPERATURE (°C)
60
Figure 26. SINAD, SFDR vs. Temperature,
fSAMPLE = 105 MSPS, fIN = 50 MHz
Rev. A | Page 12 of 36
80
AD9215
0.6
40
30
0.2
10
INL (LSB)
GAIN ERROR (ppm/°C)
0.4
20
0
0
–10
–0.2
–20
–20
0
20
40
TEMPERATURE (°C)
60
–0.6
80
Figure 27. Gain vs. Temperature External 1 V Reference
0.4
0.3
DNL (LSB)
0.2
0.1
0
–0.1
–0.2
02874-A-064
–0.3
–0.5
0
128
256
384
512
CODE
640
768
896
0
128
256
384
512
CODE
640
768
896
1024
Figure 29. AD9215-105 Typical INL, fSAMPLE = 105 MSPS, fIN = 2.3 MHz
0.5
–0.4
02874-A-074
–40
–40
–0.4
02874-A-025
–30
1024
Figure 28. AD9215-105 Typical DNL, fSAMPLE = 105 MSPS, fIN = 2.3 MHz
Rev. A | Page 13 of 36
AD9215
APPLYING THE AD9215 THEORY OF OPERATION
The input stage contains a differential SHA that can be configured as ac-coupled or dc-coupled in differential or single-ended
modes. Each stage of the pipeline, excluding the last, consists of
a low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipeline. Redundancy is used in each one of the stages to facilitate
digital correction of flash errors.
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance, they would limit the input bandwidth.
The analog inputs of the AD9215 are not internally dc biased.
In ac-coupled applications, the user must provide this bias externally. VCM = AVDD/2 is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 31).
85
80
2V p-p SFDR
75
70
65
dB
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
60
2V p-p SNR
55
50
02874-A-071
The AD9215 architecture consists of a front-end SHA followed
by a pipelined switched capacitor ADC. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new
input sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
45
Analog Input and Reference Overview
The analog input to the AD9215 is a differential switched
capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input
can support a wide common-mode range and maintain excellent performance, as shown in Figure 31. An input commonmode voltage of midsupply minimizes signal-dependent errors
and provides optimum performance.
40
0.25
0.75
1.25
1.75
2.25
ANALOG INPUT COMMON-MODE VOLTAGE (V)
2.75
Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
H
T
0.5pF
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as
T
VIN+
CPAR
T
REFT = 1/2 (AVDD + VREF)
0.5pF
CPAR
02874-A-028
VIN–
T
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
H
Figure 30. Switched-Capacitor SHA Input
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 30). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum
Rev. A | Page 14 of 36
AD9215
2V p-p
AVDD
C
VIN–
AGND
1kΩ
0.1µF
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN−.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN−. The
AD9215 then accepts a signal varying between 2 V and 0 V. In
the single-ended configuration, distortion performance may
degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large
input common-mode swing. However, if the source impedances
on each input are kept matched, there should be little effect on
SNR performance. Figure 34 details a typical single-ended input
configuration.
10µF
Differential Input Configurations
1kΩ
As previously detailed, optimum performance is achieved while
driving the AD9215 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen Key filter
topology to provide band limiting of the input signal.
2V p-p
49.9Ω
R
0.1µF 1kΩ
AVDD
C
R
1kΩ
10µF
0.1µF
C
AVDD
VIN+
AD9215
VIN–
AGND
1kΩ
02874-A-032
The minimum common-mode input level allows the AD9215 to
accommodate ground-referenced inputs.
Figure 34. Single-Ended Input Configuration
CLOCK INPUT AND CONSIDERATIONS
1kΩ
499Ω
AVDD
R
523Ω
VIN+
C
AD8138
AD9215
R
499Ω
499Ω
C
VIN–
AGND
02874-A-030
VCM
49.9Ω
AD9215
Figure 33. Differential Transformer-Coupled Configuration
VCMMAX = (AVDD + VREF)/2
1V p-p
C
49.9Ω
1kΩ
VCMMIN = VREF/2
1kΩ
VIN+
R
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels
are defined as
0.1µF
AVDD
R
02874-A-031
SNR performance is achieved with the AD9215 set to the largest
input span of 2 V p-p. The relative SNR degradation is 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
Figure 32. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9215. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor is dependant on the input
frequency and source impedance and should be reduced or removed. An example of this is shown in Figure 33.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance characteristics. The AD9215 contains a clock duty cycle stabilizer
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9215. As shown in Figure 25, noise and distortion performance are nearly flat over a 50% range of duty cycle. For best
ac performance, enabling the duty cycle stabilizer is recommended for all applications.
The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow
the DLL to acquire and lock to the new rate.
Rev. A | Page 15 of 36
AD9215
Table 7. Reference Configuration Summary
Selected Mode
Externally Supplied Reference
Internal 0.5 V Reference
Programmed Variable
Reference
Internally Programmed 1 V
Reference
External SENSE
Connection
AVDD
VREF
External Divider
Internal Op Amp
Configuration
N/A
Voltage Follower (G = 1)
Noninverting (1 < G < 2)
Resulting VREF
(V)
N/A
0.5
0.5 × (1 + R2/R1)
Resulting Differential Span
(V p-p)
2 × External Reference
1.0
2 × VREF
AGND to 0.2 V
Internal Divider
1.0
2.0
Table 8. Digital Output Coding
VIN+ − VIN− Input Span =
1 V p-p (V)
0.500
0
−0.000978
−0.5000
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tA) can be
calculated with the following equation
SNR Degradation = 20 × log10 [2 × π × fINPUT × tA]
Digital Output Offset Binary
(D9••••••D0)
11 1111 1111
10 0000 0000
01 1111 1111
00 0000 0000
ber of output bits switching, which are determined by the encode
rate and the characteristics of the analog input signal.
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 35 was taken with a 5 pF load on each output driver.
AD9215-105 IAVDD
13
35
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
where N is the number of output bits, 10 in the case of the
AD9215. This maximum current is for the condition of every
output bit switching on every clock cycle, which can only occur
for a full-scale square wave at the Nyquist frequency, fCLOCK/2. In
practice, the DRVDD current is established by the average num-
11
IAVDD (mA)
AD9215-65/80 IAVDD
9
30
7
25
5
3
20
IDRVDD
1
15
5
Power Dissipation and Standby Mode
As shown in Figure 35, the power dissipated by the AD9215 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
15
40
In the equation, the rms aperture jitter, tA, represents the rootsum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9215. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
Digital Output Twos
Complement (D9••••••D0)
01 1111 1111
00 0000 0000
11 1111 1111
10 0000 0000
IDRVDD
1023
512
511
0
VIN+ − VIN− Input Span =
2 V p-p (V)
1.000
0
−0.00195
−1.00
15
25
35
45
55
65
fSAMPLE (MSPS)
75
85
95
–1
105
02874-A-075
Code
Figure 35. Supply Current vs. fSAMPLE for fIN = 10.3 MHz
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
By asserting the PDWN pin high, the AD9215 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9215 into its normal operational mode.
Rev. A | Page 16 of 36
AD9215
⎛ R2 ⎞
VREF = 0.5 × ⎜1 +
⎟
⎝ R1 ⎠
In standby mode, low power dissipation is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately one second to fully discharge
the reference buffer decoupling capacitors and 7 ms to restore
full operation.
VIN+
VIN–
The AD9215 provides latched data outputs with a pipeline delay
of five clock cycles. Data outputs are available one propagation
delay (tOD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
0.1µF
10µF
REFB
0.1µF
VREF
+
7kΩ
0.1µF
0.5V
SELECT
LOGIC
The AD9215 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
Timing
0.1µF
ADC
CORE
10µF
SENSE
7kΩ
02874-A-034
Digital Outputs
REFT
AD9215
Figure 36. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the ADC
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
VIN+
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9215;
these transients can detract from the converter’s dynamic performance.
REFT
0.1µF
ADC
CORE
0.1µF
10µF
REFB
0.1µF
VREF
10µF
+
0.1µF
R2
Voltage Reference
0.5V
SELECT
LOGIC
SENSE
A stable and accurate 0.5 V voltage reference is built into the
AD9215. The input range can be adjusted by varying the reference voltage applied to the AD9215, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
R1
AD9215
02874-A-035
The lowest typical conversion rate of the AD9215 is 5 MSPS. At
clock rates below 5 MSPS, dynamic performance may degrade.
VIN–
Figure 37. Programmable Reference Configuration
Internal Reference Connection
A comparator within the AD9215 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 1 If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor divider (see Figure 36), setting VREF to 1 V. Connecting the
SENSE pin to the VREF pin switches the amplifier output to the
SENSE pin, configuring the internal op amp circuit as a voltage
follower and providing a 0.5 V reference output. If an external
resistor divider is connected as shown in Figure 37, the switch is
again set to the SENSE pin. This puts the reference amplifier in a
noninverting mode with the VREF output defined as
If the internal reference of the AD9215 is used to drive multiple
converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts how the internal reference voltage is affected by loading.
Rev. A | Page 17 of 36
AD9215
0.05
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
0
Operational Mode Selection
As discussed earlier, the AD9215 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock duty cycle stabilizer (DCS). The
MODE pin is a multilevel input that controls the data format
and DCS state. For best ac performance, enabling the duty cycle
stabilizer is recommended for all applications. The input
threshold values and corresponding mode selections are outlined in Table 9.
–0.10
VREF = 1.0V
–0.15
02874-A-036
–0.20
–0.25
0
0.5
1.0
1.5
ILOAD (mA)
2.0
2.5
3.0
As detailed in Table 9, the data format can be selected for either
offset binary or twos complement.
Figure 38. VREF Accuracy vs. Load
External Reference Operation
Table 9. Mode Selection
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 39 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.
MODE Voltage
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
EVALUATION BOARD
The AD9215 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially
through an AD8351 driver, a transformer, or single-ended.
Separate power pins are provided to isolate the DUT from the
support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 40 shows the typical bench characterization setup used
to evaluate the ac performance of the AD9215. It is critical that
signal sources with very low phase noise (<1 ps rms jitter) be
used to realize the ultimate performance of the converter.
Proper filtering of the input signal, to remove harmonics and
lower the integrated noise at the input, is also necessary to
achieve the specified noise performance.
0.5
VREF = 0.5V
VREF ERROR (%)
Duty Cycle Stabilizer
Disabled
Enabled
Enabled
Disabled
The MODE pin is internally pulled down to AGND by a 20 kΩ
resistor.
0.6
0.4
0.3
VREF = 1.0V
0.2
02874-A-037
0.1
0
–40
Data Format
Twos Complement
Twos Complement
Offset Binary
Offset Binary
–20
0
20
40
TEMPERATURE (°C)
60
80
Figure 39. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
Complete schematics and layout plots follow that demonstrate
the proper routing and grounding techniques that should be
applied at the system level.
–
3.0V
+
2.5V
–
2.5V
+
–
+
AVDD GND DRVDD GND VDL
REFIN
R AND S SMG, 2V p-p
SIGNAL SYNTHESIZER
BAND-PASS
FILTER
R AND S SMG, 2V p-p
SIGNAL SYNTHESIZER
VAMP
XFMR
INPUT
AD9215
10MHz
REFOUT
5.0V
–
+
EVALUATION BOARD
CLK
Figure 40. Evaluation Board Connections
Rev. A | Page 18 of 36
P12
DATA
CAPTURE
AND
PROCESSING
02874-A-038
VREF ERROR (%)
VREF = 0.5V
–0.05
Figure 41. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
L1 100
PRI SEC
PRI SEC
R10
36Ω
E 45
XOUT
R3, R17, R18
ONLY ONE SHOULD BE
ON BOARD AT A TIME
XOUTB
GND
R11
36Ω
R2
XX
C18
0.10µF
GND
GND
AVDD
C11
0.1µF
C22
10µF
R15
33Ω
R26
1kΩ
R13
1kΩ
C23
SELECT
GND
OR L1
FOR FILTER
P4
P3
R25
1kΩ
GND
AVDD
3
2
4
P1
AVDD
GND
VIN+
VIN–
R6
1kΩ
R7
1kΩ
R5
1kΩ
GND
GND
GND
C21
SELECT
AVDD
C19
10pF
R4
33Ω
R36
1kΩ
GND GND
C13
0.10µF
R SINGLE ENDED
GND
R18
25Ω
AMPINB
R3
0Ω
C5
0.1µF
C26
10pF
P10
D
C29
10µF
C7
0.1µF
GND
R12
0Ω
GND
E
C
AVDD
GND
P11
P9 P8
P7 A B
C9
0.10µF
AMPIN
C16
0.1µF
R42
0Ω
6
2 CT
4
T1
ADT1–1WT
XFRIN1 1
5
NC
3
GND
C6
0.1µF
GND
C12
0.1µF
OPTIONAL XFR
T2
FT C1–1–13
5
1
XOUT
X FRIN
2
CT
3
4
GND
XOUTB
C15
AMP 0.1µF
02874-A-039
GND
J1
GND
R9
10kΩ
R1
10kΩ
P6
MODE
2
P5
31 AGND
32 AVDD
28 AGND
29 VIN+
30 VIN–
25 REFB
26 REFT
27 AVDD
GND
GND
P14
CLK
AVDD
C8
0.1µF
U4
AD9215
P13
R8
1kΩ
14
15
16
GND
D1 10
D0 9
13
D3 12
D2 11
DRVDD
DGND
D5
D4
1
AVDD
5
4
3
2
GND
6
11
10
9
6
12
7
8
13
5
15
14
4
16
1
10
9
2
3
11
6
12
7
8
13
5
15
14
4
16
MODE PIN SOLDERABLE JUMPER:
5 TO 1: TWOS COMPLEMENT/DCS OFF
5 TO 2: TWOS COMPLEMENT/DCS ON
5 TO 3: OFFSET BINARY/DCS ON
5 TO 4: OFFSET BINARY/DCS OFF
D0X
D1X
D2X
D4X
D3X
D6X
D5X
D8X
D7X
D9X
D10X
D12X
D11X
ORX
D13X
H4
MTHOLE6
H3
MTHOLE6
H2
MTHOLE6
H1
MTHOLE6
2
3
RP1 220Ω
RP2 220Ω
GND
1
P2
SENSE PIN SOLDERABLE JUMPER:
E TO A: EXTERNAL VOLTAGE DIVIDER
E TO B: INTERNAL 1V REFERENCE (DEFAULT)
E TO C: EXTERNAL REFERENCE
E TO D: INTERNAL 0.5V REFERENCE
(LSB)
DRVDD
GND
(MSB)
OVERRANGE BIT
3.0V
1
D8 19
D7 18
D6 17
2.5V DRVDD
2.5V
AVDD
VREF 24
SENSE 23
MODE 22
OR 21
D9 20
1 DNC
2 CLK
Rev. A | Page 19 of 36
3 DNC
4 PDWN
5 DNC
6 DNC
7 DNC
8 DNC
VDL
GND
VAMP
5.0V
EXTREF
1V MAX E1
AD9215
Figure 42. LFCSP Evaluation Board, Digital Path
Rev. A | Page 20 of 36
D11X
GND
D12X
DRX
D13X
47
48
46
45
44
42
43
41
39
40
38
37
36
34
35
33
31
32
30
28
29
27
26
25
GND
R19
50Ω
AMP
AMP IN
CLKLAT/DAC
GND
D0X
DRVDD
D2X
D1X
D4X
D3X
GND
D5X
D7X
D6X
GND
D8X
D10X
D9X
DRVDD
02874-A-040
LSB
MSB
CLKAT/DAC
2Q7
GND
2Q6
2Q5
VCC
2D5
1Q7
1Q3
GND
1Q2
1Q1
1OE
OUT
1D3
GND
1D2
1D1
1CLK 1
IN
2
1
3
4
5
7
6
8
10
9
GND
R35
25Ω
R40
10kΩ
GND
C35
0.10µF
C28
0.1µF
R41
10kΩ
VAMP
R33
25Ω
R38
1kΩ
R39
1kΩ
GND
DR
DRY
GND
20
22
18
12
14
16
8
10
6
4
2
RPG2 5
6 COMM
7 OPLO
INLO 4
10 VOCM
C44
0.1µF
9 VPOS
8 OPHI
R34
1.2kΩ
U3
AD8351
GND
INHI 3
RGP1 2
PWDN 1
GND
GND
DRVDD
GND
R14
25Ω
VAMP
C45
0.1µF
C24
10µF
R17
0Ω
R16
0Ω
GND
GND
C17
0.1µF
C27
0.1µF
GND
AMPIN
AMPINB
40
38
36
34
30
32
28
26
MSB
GND
11
VAMP
DRY
24
GND
GND
DRVDD
GND
GND
12
13
15
14
16
18
17
19
20
21
23
22
24
POWER DOWN
USE R40 OR R41
1Q4
VCC
1D4
1Q5
VCC
GND
1Q6
1D7
GND
1D6
1D5
2Q1
1Q8
2Q2
2D2
2D1
1D8
GND
2Q3
2D3
GND
2Q4
VCC
2D4
2D6
2QB
2DB
2OE
2D7
GND
2CLK
U1
74LVTH162374
40
36
38
34
30
32
28
26
24
20
22
18
14
16
12
10
8
4
6
2
P12
HEADER 40
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
1
GND
AD9215
C4
10µF
C3
10µF
Figure 43. LFCSP Evaluation Board Schematic, Clock Input
Rev. A | Page 21 of 36
02874-A-041
GND
R29
50Ω
C43
0.1µF
ENC
ENCX
GND
ENCODE
J2
GND
C25
10µF
AVDD
GND
R30
1kΩ
R31
1kΩ
VDL
R27
0Ω
R28
0Ω
VDL
VDL
E43
E44
E35
E51
E52
VDL
E31
VDL
E50
CLK
ENC
C33
C14
0.1µF 0.001µF
ANALOG BYPASSING
C32
0.001µF
CLOCK TIMING ADJUSTMENTS
FOR A BUFFERED ENCODE USE R28
FOR A DIRECT ENCODE USE R27
DRVDD AVDD
GND
DUT BYPASSING
C10
22µF
VDL
R20
1kΩ
GND
GND
R24
1kΩ
GND
R21
1kΩ
GND
E53
GND
R32
1kΩ
C41
0.1µF
DRVDD
C30
0.001µF
5
9
10
12
13
3A
3B
4A
4B
2B
1 1A
2 1B
4 2A
C31
0.1µF
U5
4Y
3Y
2Y
1Y
74VCX86
DIGITAL BYPASSING
C2
22µF
PWR
GND
14
8
11
6
7
3
C34
0.1µF
VDL
GND
ENCX
C36
0.1µF
C39
C1
0.001µF 0.1µF
LATCH BYPASSING
C47
0.1µF
R23
0Ω
CLKLAT/DAC
R37
25Ω
Rx
DNP
SCHEMATIC SHOWS TWO-GATE DELAY SETUP.
FOR ONE DELAY REMOVE R22 AND R37
ATTACH Rx (Rx = 0Ω)
C38
0.001µF
C48
0.001µF
DR
GND
C49
0.001µF
VDL
R22
0Ω
GND
VAMP
C20
10µF
C46
10µF
C37
0.1µF
C40
0.001µF
AD9215
Figure 44. LFCSP Evaluation Board Layout, Primary Side
02874-A-043
02874-A-042
AD9215
Figure 45. LFCSP Evaluation Board Layout, Secondary Side
Rev. A | Page 22 of 36
02874-A-044
02874-A-045
AD9215
Figure 47. LFCSP Evaluation Board Layout, Power Plane
Figure 46. LFCSP Evaluation Board Layout, Ground Plane
Rev. A | Page 23 of 36
Figure 48. LFCSP Evaluation Board Layout, Primary Silkscreen
02874-A-047
02874-A-046
AD9215
Figure 49. LFCSP Evaluation Board Layout, Secondary Silkscreen
Rev. A | Page 24 of 36
AD9215
Table 10. LFCSP Evaluation Board Bill of Materials (BOM)
Omit1
2
8
3
8
4
5
6
1
2
1
9
7
8
2
1
Reference Designator
C1, C5, C7, C8, C9, C11,
C12, C13, C15, C16, C31, C33,
C34, C36, C37, C41, C43, C47
C6, C18, C27, C17,
C28, C35, C45, C44
C2, C3, C4, C10,
C20, C22, C25, C29
C46, C24,
C14, C30, C32, C38,
C39 C40, C48, C49
C19
C21, C23
C26
E31, E35, E43, E44,
E50, E51, E52, E53
E1, E45
J1, J2
L1
9
1
P2
Terminal Block
TB6
10
1
P12
HEADER40
11
5
Header Dual 20-Pin RT
Angle
Chip Resistor
0603
0Ω
Chip Resistor
Chip Resistor
0603
0603
33 Ω
1Ω
Chip Resistor
Chip Resistor
0603
0603
36 Ω
50 Ω
Resistor Pack
R_742
220 Ω
ADT1-1WT
74LVTH162374 CMOS
Register
AD9215BCP ADC (DUT)
74VCX86M
AD9XXBCP/PCB
AD8351 Op Amp
MACOM Transformer
Chip Resistor
Chip Resistor
Chip Resistor
Chip Resistor
Chip Resistor
AWT1-T1
TSSOP-48
Item
1
Qty
18
8
2
2
12
13
2
14
14
15
2
1
16
2
R3, R12, R23, R18, RX
R37, R22, R42, R16, R17, R27
R4, R15
R5, R6, R7, R8, R13, R20, R21, R24,
R25, R26, R30, R31, R32, R36
R10, R11
R29
R19
RP1, RR2
17
18
1
1
T1
U1
19
20
21
22
23
24
25
26
27
28
1
1
1
U4
U5
PCB
U3
T2
R9, R1, R2, R38, R39
R18, R14, R35
R40, R41
R34
R33
6
1
1
1
1
5
3
2
1
1
Device
Chip Capacitor
Package
0603
Value
0.1 µF
Tantalum Capacitor
TAJD
10 µF
Chip Capacitor
0603
Chip Capacitor
0603
0.001
µF
10 pF
Chip Capacitor
Header
0603
EHOLE
SMA Connector/50 Ω
Inductor
SMA
0603
These items are included in the PCB design but are omitted at assembly.
Rev. A | Page 25 of 36
CSP-32
SOIC-14
PCB
MSOP-8
ETC1-1-13
0603
0603
0603
Recommended Vendor/
Part Number
10 pF
Jumper Blocks
10 nH
1-1 TX
Select
25 Ω
10 kΩ
1.2 kΩ
110 Ω
Coilcraft/0603CS10NXGBU
Wieland/25.602.2653.0
z5-530-0625-0
Digi-Key S2131-20-ND
Digi-Key
CTS/742C163220JTR
Mini-Circuits
Analog Devices, Inc.
Fairchild
Analog Devices, Inc.
Analog Devices, Inc.
MACOM/ETC1-1-13
Rev. A | Page 26 of 36
GND
GND
R15
10kΩ
A
GND
J1
Figure 50. TSSOPP Evaluation Board Schematic, Analog Inputs and DUT
GND
E32
GND
R3
5kΩ
GND
C14
0.1µF
1
5
3
B
C12
0.1µF
GND
T1
6
2
4
PRI SEC
GND
L1
10nH
OPTIONAL
C32
0.1µF
AVDD
R7
50Ω
R1
10Ω
OPTIONAL
AMP
DIFFERENTIAL
INPUT
SINGLE-ENDED INPUT OPERATION
1. PLACE R7( 50Ω), R5( 0Ω) AND R46 (25Ω)
2. PLACE C23 (0.1µF), C9 (0.1µF)
3. REMOVE C33, C1, R34, R6, C32
C18
0.1µF
E16
E17
R33
36Ω
R34
0Ω
C6
0.1µF
AMPIN
R32
36Ω
E12
R6
0Ω
GND
R25
25Ω
+
R16
XX
R24
1kΩ
R21
33Ω
C11
0.1µF
R29
1kΩ
C5
10pF
C8
10pF
GND
GND
E4 E8
H
E3 E2
G
E1 E5
F
GND
GND
R9
1kΩ
R10
1kΩ
R8
1kΩ
R45
1kΩ
GND
AVDD
AIN
AIN
GND
E26
E25
E24
E27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D9
D8
D7
D6
DRVDD
DRGND
D5
D4
D3
D2
D1
D0
DNC
DNC
R11
1kΩ
GND
DEVICE = AD9215
U1
PARTS = 1
OR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
VIN–
AGND
AVDD
CLK
PWDN
OR1
(LSB)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(MSB)
AVDD VDL VCLK
E28
E29
OVERRANGE BIT
E11
CLK
GND
AVDD
AVDD
GND
E9
AVDD
C15
0.1µF
ANALOG INPUT OPTIONS
1. R6, R34 FOR DIFFERENTIAL OPERATION
2. C1, C33 FOR OP AMP OPERATION
3. R7, R46, R5, C9, C23 FOR SINGLE-ENDED OPERATION
C23
0.1µF
R44
1kΩ
C17
0.1µF
R19
33Ω
AVDD
AVDD
GND
GND
R5
0Ω
C13
0.1µF
C7
0.001µF
AMPIN
GND
C52
10µF
GND
SENSE
C16
0.1µF
C29
10µF
GND
+
COMMON MODE
PLEASE JUMPER E45 TO E32 DC VOLTAGE ADJUST
OR JUMPER E45 TO E12 CAPACITOR TO GROUND
E45
D
GND
COM
C9
0.1µF
C
GND AVDD
E22
E19
R4
10kΩ
E18
E23
C30
0.1µF
DRVDD
DRVDD
GND
1
2
3
4
5
6
7
8
1
1
2
3
4
5
6
7
8
3
2
1
4
3
2
GND
AVDD
3.0V
E6 E7
E
2.5V DRVDD
MODE SELECT
GND
VREF
VCLK
RP1 220Ω
RP2 220Ω
3.0V
MODE SELECT CONFIGURATION
E:2C/DCS OFF
F:2C/DCS ON
G:OB/DCS ON
H:OB/DCS OFF
VDL
GND
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
3.0V
OPTIONAL
E21
E20
4
VAMP
D4X
D3X
D2X
D1X
D0X
NCX
NC2X
ORX
D9X
D8X
D7X
D6X
D5X
5.0V
02874-A-048
REFERENCE CONFIGURATION
A: EXTERNAL VOLTAGE DIVIDER REFERENCE
B: INTERNAL 1V REFERENCE
C: EXTERNAL REFERENCE
D: INTERNAL 0.5V REFERENCE 1V MAX
AD9215
P2
Rev. A | Page 27 of 36
GND
GND
GND
D3X
LSB D2X
D1X
D0X
NCX
NC2X
GND
OE
X0
X1
X2
X3
X4
X5
X6
X7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CP
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
OE
X0
X1
X2
X3
X4
X5
X6
X7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CP
20
19
18
17
16
15
14
13
12
11
U3
74LVT574
DEVICE = 74LVT574A
1
2
3
4
5
6
7
8
9
10
Figure 51. TSSOP Evaluation Board, Digital Path
C31
10pF
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
C45
0.1µF
C44
0.1µF
GND
R51
25Ω
R50
25Ω
CLKLAT/DAC
VDL
CLKLAT/DAC
GND
R36
25Ω
AMP
R23
100Ω
R20
150Ω
VDL
GND
GND
GND
VDL
R31
100Ω
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
R47
10kΩ
1
2
3
4
5
PWUP
RGP1
INHI
INLO
RGP2
R49
1kΩ
VOCM
VPOS
OPHI
OPLO
COMM
R48
1kΩ
R30
1.2kΩ
10
9
8
7
6
C41
0.1µF
E13
U6
DEVICE = AD8351
GND VAMP VAMP
R22
10kΩ
RP4
220Ω
RP3
220Ω
MSB
GND
GND
R28
0Ω
GND
GND
VAMP
E14
E30
R27
0Ω
R17
0Ω
C43
0.001µF
C42
0.1µF
C47
10µF
C1
0.1µF
C33
0.1µF
GND
GND
GND
DRX
GND
OUT OF RANGE BIT
STRAP THIS AT ASSEMBLY
+
U4
74LVT574
DEVICE = 74LVT574A
AMPIN
AMPIN
P40
P38
P36
P34
P32
P30
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
P6
P4
P2
U2
P39
P37
P35
P33
P31
P29
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P5
P3
P1
GND
02874-A-049
ORX
MSB D9X
D8X
D7X
D6X
D5X
D4X
GND
GND
GND
AD9215
C10 +
22µF
+
C27 +
10µF
C24
0.1µF
U3/U4 BYPASSING
C25
10µF
C3
22µF
GND
C4 +
10µF
GND
DUT BYPASSING
C2 +
22µF
DRVDD AVDD
J3
Figure 52. TSSOP Evaluation Board Schematic, Clock Input
Rev. A | Page 28 of 36
E35
GND
VCLK
GND
R40
50Ω
ENCODE
GND
VCLK
GND
E43 E44
R26
1kΩ
GND
R41
1kΩ
ENC
C48
0.1µF
C34
0.1µF
VCLK
GND
GND
VCLK
CLK
GND
R43
1kΩ
E50 E51
R35
0Ω
C20
10µF
1
2
4
5
9
10
12
13
C51
0.1µF
4B
4A
3B
3A
2B
2A
1B
1A
C46
0.1µF
R38
0Ω
J4
C19
0.001µF
R18
0Ω
R25
0Ω
GND
GND
C28
R14 0.1µF
50Ω
DRX
DRX
DRX
R52
0Ω
CLKLAT/DAC
SCHEMATIC SHOWS 1-GATE DELAY SETUP
FOR TWO-GATE DELAY REMOVE RESISTOR R52
ADD RESISTORS R38 AND R18
EXTERNAL DATA READY
OPTIONAL
VCLK
GND
C21
0.1µF
GND
DUT DRVDD BYPASSING
DRVDD
ENCX
3
6
2Y 7
8 GND
3Y 11
14
PWR
4Y
1Y
C39
0.001µF
U5
74VCX86
C36
0.1µF
C49
0.001µF
AVDD
U5 BYPASSING
+
GND
C35
0.001µF
VCLK
R37
0Ω
C38
0.001µF
R2
1kΩ
E52 E53
ENC
ENCX
C37
0.001µF
AVDD BYPASSING
C50
10µF
C26
0.1µF
+
R39
1kΩ
E36
C40
0.1µF
R42
1kΩ
AVDD
ENCODE FROM XOR
FOR A BUFFERED ENCODE USE R37
FOR A DIRECT ENCODE USE R35
GND
VDL
+
VDL
02874-A-050
VCLK
AD9215
02874-A-051
02874-A-053
AD9215
02874-A-054
Figure 55. TSSOP Evaluation Board Layout, Ground Plane
02874-A-052
Figure 53. TSSOP Evaluation Board Layout, Primary Side
Figure 56. TSSOP Evaluation Board Layout, Power Plane
Figure 54. TSSOP Evaluation Board Layout, Secondary Side
Rev. A | Page 29 of 36
Figure 57. TSSOP Evaluation Board Layout, Primary Silkscreen
02874-A-056
02874-A-055
AD9215
Figure 58. TSSOP Evaluation Board Layout, Secondary Silkscreen
Rev. A | Page 30 of 36
AD9215
Table 11. TSSOP Evaluation Board Bill of Materials (BOM)
Item
Qty.
1
11
Omit
Reference Designator
Device
Package
Value
C2 to C4, C10, C20,
C25, C27, C29,
C47, C50, C52
Tantalum Capacitor
TAJD
10 µF
Chip Capacitor
0603
10 pF
C6, C9, C13,
C15 to C18, C21, C24,
C26, C30, C32, C34, C36,
C40, C46, C48, C51
Chip Capacitor
0603
0.1 µF
C12, C14, C23, C28
Chip Capacitor
0603
Select
C7, C19, C35, C19,
C37 to C39, C49
Chip Capacitor
0603
0.001 µF
C47
2
2
C5,C8
1
3
15
4
5
3
8
C31
6
6
C1,C33, C41 to C42,
C44 to C5
BCAP0402
0402
0.1 µF
7
1
C43
BCAP0402
0402
0.001 µF
8
1
C11
BCAP0603
0603
Select
R2, R8 to R11, R24,
R26, R29, R39, R41 to R45
BRES603
0603A
1 kΩ
BRES603
0603A
0Ω
BRES603
0603A
50 Ω
9
11
2
10
4
R6, R25, R34, R37
8
11
R48, R49
2
R5, R35, R17 to R18,
R27 to R28, R38, R52
R7, R40
1
R14
12
2
R19, R21
BRES603
0603A
33 Ω
13
2
R32, R33
RES0603
0603A
36 Ω
14
1
R16
BRES603
0603
Select
15
2
R4, R15,
BRES603
0603
10 kΩ
16
4
R20, R22 to R23, R47
BRES603
0603A
Select
17
2
R48, R49
BRES603
0603
1 kΩ
18
4
R36, R46, R50 to R51
BRES603
0603
25 Ω
19
1
R31
BRES603
0603
100 Ω
20
1
R30
BRES603
0603
1.2 kΩ
21
1
R3
BRES603
0603
5 kΩ
22
1
R1
Potentiometer
RJ24FW
10 kΩ
RP1 to RP4
Resister Pack
220•
742C163221
23
4
Rev. A | Page 31 of 36
Recommended
Vendor/Part No.
AD9215
Item
Qty.
24
Recommended
Vendor/Part No.
Reference Designator
Device
Package
Value
1
L1
Chip Inductor
0603
10 nH
25
1
T1
1:1 RF Transformer
CD542
Mini-Circuits
AWT1-1T
26
1
U1
ADC
28TSSOP
Analog Devices, Inc.
AD9215
27
1
U2
Right Angle 40-Pin Header
Samtec
TSW-120-08-T-D-RA
28
2
U3, U4
Octal D-Type Flip-Flop
Fairchild 74LVT57MSA
29
1
U5
Quad XOR Gate
SO14
Fairchild 74VCX86M
U6
High Speed Amplifier
SOMB10
Analog Devices, Inc.
AD8351ARM
J1, J3
SMB Connecter
SMBP
PTMICRO4
30
31
Omit
1
2
1
J4
32
2
P1, P2
Power Connector
33
26
E1/E5, E2/E3, E4/E8,
E9/E11, E6/E7, E16/E17,
E19/E22, E18/E23, E21/20,
E35/E51, E36/E50, E43/E53,
E44/E52
Headers/Jumper Blocks
E24/E27, E25/E26, E28/E29,
E13/E14/E30, E12/E32/E45
Wirehole
34
12
Coilcraft/0603CS10NXGBU
Rev. A | Page 32 of 36
Weiland
Z5.531.3425.0 Posts
25.602.5453.0 Top
TSW-120-07-G-S
SMT-100-BK-G
AD9215
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
SEATING
PLANE
8°
0°
0.20
0.09
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 59. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
TOP
VIEW
32
25
24
0.50
0.40
0.30
1
3.25
3.10 SQ
2.95
BOTTOM
VIEW
17
16
9
8
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
0.30
0.23
0.18
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
NOTE:
IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED
TO THE GROUND PLANE FOR THE LFCSP PACKAGE. THERE IS AN
INCREASED RELIABILITY OF THE SOLDER JOINTS, AND THE MAXIMUM
THERMAL CAPABILITY OF THE PACKAGE IS ACHIEVED WITH THE
EXPOSED PADDLE SOLDERED TO THE CUSTOMER BOARD.
Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
Rev. A | Page 33 of 36
AD9215
ORDERING GUIDE
Model
AD9215BRU-65
AD9215BRU-80
AD9215BRU-105
AD9215BRURL7-65
AD9215BRURL7-80
AD9215BRURL7-105
AD9215BRU-65EB
AD9215BRU-80EB
AD9215BRU-105EB
AD9215BCP-65
AD9215BCP-80
AD9215BCP-105
AD9215BCPZ-651
AD9215BCPZ-801
AD9215BCPZ-1051
AD9215BCP-65EB
AD9215BCP-80EB
AD9215BCP-105EB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
AD9215BRU-65 Evaluation Board (TSSOP)
AD9215BRU-80 Evaluation Board (TSSOP)
AD9215BRU-105 Evaluation Board (TSSOP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
AD9215BCP-65 Evaluation Board (LFCSP)
AD9215BCP-80 Evaluation Board (LFCSP)
AD9215BCP-105 Evaluation Board (LFCSP)
Z = Pb-free part.
Rev. A | Page 34 of 36
Package Option
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
CP-32
CP-32
CP-32
CP-32
CP-32
CP-32
CP-32
CP-32
CP-32
AD9215
NOTES
Rev. A | Page 35 of 36
AD9215
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
C02874-0-2/04(A)
Rev. A | Page 36 of 36