CS8421
32-bit, 192 kHz Asynchronous Sample Rate Converter
Features
! 175 dB Dynamic Range
! Bypass Mode
! –140 dB THD+N
! Time Division Multiplexing (TDM) Mode
! No Programming Required
! Attenuates Clock Jitter
! No External Master Clock Required
! Multiple Part Outputs are Phase-Matched
! Supports Sample Rates up to 211 kHz
! Linear Phase FIR Filter
! Input/Output Sample Rate Ratios from 7.5:1 to
! Automatic Soft Mute/Unmute
1:8
! +2.5 V Digital Supply (VD)
! Master Clock Support for 128 x Fs, 256 x Fs,
! +3.3 V or 5.0 V Digital Interface (VL)
384 x Fs, and 512 x Fs (Master Mode)
! Space-Saving 20-Pin TSSOP and QFN
! 16, 20, 24, or 32-bit Data I/O
Packages
! 32-bit Internal Signal Processing
The CS8421 supports sample rates up to 211 kHz and
is available in 20-pin TSSOP and QFN packages in both
Commercial (-10° to +70°C) and Automotive (-40° to
+85°C) grades. The CDB8421 Customer Demonstration board is also available for device evaluation and
implementation suggestions. Please see “Ordering Information” on page 36 for complete details.
! Dither Automatically Applied and Scaled to
Output Resolution
! Flexible 3-Wire Serial Digital Audio Input and
Output Ports
! Master and Slave Modes for Both Input and
Output
BYPASS
RST
ISCLK
ILRCK
Level Translators
SDIN
MS_SEL
Serial
Audio
Input
Data
Sync Info
Time
Varying
Digital
Filters
Data
Sync Info
Digital
PLL
SAOF
3.3 V or 5.0 V (VL)
Clock
Generator
http://www.cirrus.com
2.5 V (VD)
TDM_IN
SDOUT
OSCLK
OLRCK
SRC_UNLOCK
Serial
Port
Mode
Decoder
SAIF
Serial
Data Audio
Output
Level Translators
Level Translators
GND
XTI
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
MCLK_OUT
XTO
JULY '06
DS641F1
CS8421
General Description
The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter.
Digital audio inputs and outputs can be 32, 24, 20, or 16-bits. Input and output data can be completely asynchronous, synchronous to an external data clock, or the part can operate without any external clock by using an
integrated oscillator.
Audio data is input and output through configurable 3-wire input/output ports. The CS8421 does not require any software control via a control port.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mixing consoles, high-quality D/A, effects processors, computer audio systems, and automotive audio systems.
The CS8412 is available in a
The CS8421 is also suitable for use as an asynchronous decimation or interpolation filter. See Cirrus Logic Application Note AN270, “Audio A/D Conversion with an Asynchronous Decimation Filter”, available at www.cirrus.com
for more details.
2
DS641F1
CS8421
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................ 6
1.1 TSSOP Pin Descriptions ................................................................................................................ 6
1.2 QFN Pin Descriptions ..................................................................................................................... 8
2. CHARACTERISTICS AND SPECIFICATIONS ................................................................................... 10
SPECIFIED OPERATING CONDITIONS ............................................................................................ 10
ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 10
PERFORMANCE SPECIFICATIONS.................................................................................................. 11
DIGITAL FILTER CHARACTERISTICS .............................................................................................. 12
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 12
DIGITAL INPUT CHARACTERISTICS ................................................................................................ 13
DIGITAL INTERFACE SPECIFICATIONS .......................................................................................... 13
SWITCHING SPECIFICATIONS ......................................................................................................... 13
3. TYPICAL CONNECTION DIAGRAMS ................................................................................................ 15
4. APPLICATIONS .................................................................................................................................. 17
4.1 Three-Wire Serial input/Output Audio Port ................................................................................... 17
4.2 Mode Selection ............................................................................................................................. 18
4.3 Sample Rate Converter (SRC) ..................................................................................................... 20
4.3.1 Data Resolution and Dither .............................................................................................. 20
4.3.2 SRC Locking and Varispeed ............................................................................................ 20
4.3.3 Bypass Mode ................................................................................................................... 20
4.3.4 Muting .............................................................................................................................. 21
4.3.5 Group Delay and Phase Matching Between Multiple CS8421 Parts ............................... 21
4.3.6 Master Clock .................................................................................................................... 21
4.3.7 Clocking ........................................................................................................................... 22
4.4 Time Division Multiplexing (TDM) Mode ....................................................................................... 23
4.5 Reset, Power-Down, and Start-Up ............................................................................................... 24
4.6 Power Supply, Grounding, and PCB Layout ................................................................................ 24
5. PERFORMANCE PLOTS
................................................................................................................ 25
6. PACKAGE DIMENSIONS ................................................................................................................... 34
TSSOP THERMAL CHARACTERISTICS ........................................................................................... 34
QFN THERMAL CHARACTERISTICS ................................................................................................ 35
7. ORDERING INFORMATION ............................................................................................................... 36
8. REVISION HISTORY .......................................................................................................................... 36
DS641F1
3
CS8421
LIST OF FIGURES
Figure 1. Non-TDM Slave Mode Timing..................................................................................................... 14
Figure 2. TDM Slave Mode Timing ............................................................................................................ 14
Figure 3. Non-TDM Master Mode Timing................................................................................................... 14
Figure 4. TDM Master Mode Timing .......................................................................................................... 14
Figure 5. Typical Connection Diagram, No External Master Clock ............................................................ 15
Figure 6. Typical Connection Diagram, Master and Slave Modes ............................................................. 16
Figure 7. Serial Audio Interface Format - I²S ............................................................................................. 18
Figure 8. Serial Audio Interface Format - Left-Justified.............................................................................. 18
Figure 9. Serial Audio Interface Format - Right-Justified ........................................................................... 18
Figure 10. Typical Connection Diagram for Crystal Circuit ........................................................................ 22
Figure 11. TDM Slave Mode Timing Diagram............................................................................................ 23
Figure 12. TDM Master Mode Timing Diagram.......................................................................................... 23
Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)....................................................... 24
Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave) .................... 24
Figure 15. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz ..................................... 25
Figure 16. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz ................................ 25
Figure 17. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz .................................. 25
Figure 18. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz .................................. 25
Figure 19. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:96 kHz ..................................... 25
Figure 20. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 96 kHz:48 kHz ..................................... 25
Figure 21. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz ................................... 26
Figure 22. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:96 kHz.................................. 26
Figure 23. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:48 kHz.................................. 26
Figure 24. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz............................. 26
Figure 25. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz............................... 26
Figure 26. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz............................... 26
Figure 27. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 96 kHz:48 kHz.................................. 27
Figure 28. IMD, 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz ................................................................... 27
Figure 29. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 192 kHz:48 kHz................................ 27
Figure 30. IMD, 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz ................................................................ 27
Figure 31. IMD, 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz ................................................................ 27
Figure 32. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz ................................ 27
Figure 33. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone, 192 kHz:192 kHz ............................... 28
Figure 34. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:96 kHz ................................... 28
Figure 35. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:48 kHz ................................... 28
Figure 36. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 96 kHz:48 kHz ................................... 28
Figure 37. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz ................................ 28
Figure 38. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 192 kHz ..................................... 28
Figure 39. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 48 kHz ....................................... 29
Figure 40. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 96 kHz ....................................... 29
Figure 41. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 44.1 kHz .................................... 29
Figure 42. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 192 kHz .................... 29
Figure 43. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 32 kHz ....................................... 29
Figure 44. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 32 kHz ...................... 29
Figure 45. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 96 kHz ...................... 30
Figure 46. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz ................... 30
Figure 47. Frequency Response with 0 dBFS Input .................................................................................. 30
Figure 48. Passband Ripple, 192 kHz:48 kHz ........................................................................................... 30
Figure 49. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 48 kHz ...................... 30
Figure 50. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz ........................................ 30
Figure 51. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz ..................................... 31
Figure 52. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz ........................................ 31
4
DS641F1
CS8421
Figure 53. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz ........................................ 31
Figure 54. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz ................................... 31
Figure 55. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz ..................................... 31
Figure 56. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz ................................... 31
Figure 57. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:44.1 kHz ..................................................... 32
Figure 58. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:96 kHz ........................................................ 32
Figure 59. THD+N vs. Input Amplitude, 1 kHz Tone, 96 kHz:48 kHz ........................................................ 32
Figure 60. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:192 kHz ................................................... 32
Figure 61. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:48 kHz ..................................................... 32
Figure 62. THD+N vs. Input Amplitude, 1 kHz Tone, 192 kHz:48 kHz ...................................................... 32
Figure 63. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz ........................................................... 33
Figure 64. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:96 kHz .............................................................. 33
Figure 65. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz ........................................................... 33
Figure 66. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz .............................................................. 33
LIST OF TABLES
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL) ................. 19
Table 2. Serial Audio Input Port Start-Up Options (SAIF) .......................................................................... 19
Table 3. Serial Audio Output Port Start-Up Options (SAOF) ..................................................................... 19
DS641F1
5
CS8421
1. PIN DESCRIPTIONS
1.1
TSSOP PIN DESCRIPTIONS
XTO
1
20
SRC_UNLOCK
XTI
2
19
SAIF
VD
3
18
SAOF
GND
4
17
VL
RST
5
16
GND
BYPASS
6
7
8
9
10
15
14
13
12
MS_SEL
11
TDM_IN
ILRCK
ISCLK
SDIN
MCLK_OUT
6
OLRCK
OSCLK
SDOUT
DS641F1
CS8421
Pin Name
#
XTO
1
Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 21.
XTI
2
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock”
on page 21.
VD
3
Digital Power (Input) - Digital core power supply. Typically +2.5 V.
GND
4
Ground (Input) - Ground for I/O and core logic.
RST
5
Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are
reset. On initial power-up, RST must be held low until the power supply is stable and all input
clocks are stable in frequency and phase.
BYPASS
6
Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample rate converter will
be bypassed, and any data input through the serial audio input port will be directly output on the
serial audio output port. When BYPASS is low, the sample rate converter will operate normally.
ILRCK
7
Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDIN pin.
ISCLK
8
Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin.
SDIN
9
Serial Audio Input Data Port (Input) - Audio data serial input pin.
MCLK_OUT
10
Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 kΩ resistor to turn the output off. See
“Master Clock” on page 21.
TDM_IN
11
Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See “Time Division Multiplexing (TDM) Mode” on page 23.
SDOUT
12
Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally this pin may be
pulled low through a 47 kΩ resistor, but should not be pulled high.
OSCLK
13
Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDOUT pin.
OLRCK
14
Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDOUT pin.
MS_SEL
15
Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 19 for settings.
GND
16
Ground (Input) - Ground for I/O and core logic.
VL
17
Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF
18
Serial Audio Output Format Select (Input) - Used to select the serial audio output format at startup and reset. See Table 3 on page 19 for format settings.
SAIF
19
Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup
and reset. See Table 2 on page 19 for format settings.
SRC_UNLOCK
20
SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and
Varispeed” on page 20.
DS641F1
Pin Description
7
CS8421
8
XTI
XTO
SRC_UNLOC
SAIF
SAOF
QFN PIN DESCRIPTIONS
20
19
18
17
16
GND
2
14
GND
RST
3
Thermal Pad
13
MS_SEL
BYPASS
4
Top-Down View
20-pin QFN Package
12
OLRCK
ILRCK
5
11
OSCLK
6
7
8
9
10
SDOUT
VL
TDM_IN
15
MCLK_OUT
1
SDIN
VD
ISCLK
1.2
DS641F1
CS8421
Pin Name
#
Pin Description
VD
1
Digital Power (Input) - Digital core power supply. Typically +2.5 V.
GND
2
Ground (Input) - Ground for I/O and core logic.
RST
3
Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are
reset. On initial power-up, RST must be held low until the power supply is stable and all input clocks
are stable in frequency and phase.
BYPASS
4
Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample-rate converter will be
bypassed, and any data input through the serial audio input port will be directly output on the serial
audio output port. When BYPASS is low, the sample rate converter will operate normally.
ILRCK
5
Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDIN pin.
ISCLK
6
Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin.
SDIN
7
Serial Audio Input Data Port (Input) - Audio data serial input pin.
MCLK_OUT
8
Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 kΩ resistor to turn the output off. See
“Master Clock” on page 21.
TDM_IN
9
Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See “Time Division Multiplexing (TDM) Mode” on page 23.
SDOUT
10
Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally this pin may be
pulled low through a 47 kΩ resistor, but should not be pulled high.
OSCLK
11
Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin.
OLRCK
12
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin.
MS_SEL
13
Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 19 for settings.
GND
14
Ground (Input) - Ground for I/O and core logic.
VL
15
Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF
16
Serial Audio Output Format Select (Input) - Used to select the serial audio output format at startup and reset. See Table 3 on page 19 for format settings.
SAIF
17
Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup
and reset. See Table 2 on page 19 for format settings.
SRC_UNLOCK
18
SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and
Varispeed” on page 20.
XTO
19
Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 21.
XTI
20
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock” on
page 21.
THERMAL PAD
-
DS641F1
Thermal Pad - Thermal relief pad for optimized heat dissipation.
9
CS8421
2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V)
Parameter
Power Supply Voltage
Ambient Operating Temperature:
‘-CZ’
‘-CNZ’
‘-DZ’
Symbol
Min
Nominal
Max
Units
VD
VL
2.38
3.14
2.5
3.3 or 5.0
2.62
5.25
V
V
TA
-10
-10
-40
-
+70
+70
+85
°C
°C
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the
device. Normal operation is not guaranteed at these extremes.)
Parameter
Power Supply Voltage
Input Current, Any Pin Except Supplies
Min
Max
Units
VD
VL
-0.3
-0.3
3.5
6.0
V
V
Iin
-
±10
mA
Vin
-0.3
VL+0.4
V
Ambient Operating Temperature (power applied)
TA
-55
+125
°C
Storage Temperature
Tstg
-65
+150
°C
Input Voltage
(Note 1)
Symbol
Notes:
1. Transient currents of up to 100 mA will not cause SCR latch-up.
2. Numbers separated by a colon indicate input and output sample rates. For example, 48 kHz:96 kHz indicates that Fsi = 48 khz and Fso = 96 kHz.
10
DS641F1
CS8421
PERFORMANCE SPECIFICATIONS
(XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS, Measurement Bandwidth = 20 to Fso/2 Hz, and Word
Width = 32-Bits, unless otherwise stated.)
Parameter
Min
Typ
Max
Units
16
-
32
bits
7.2
53
-
207
211
kHz
kHz
-
XTI/130
XTI/128
kHz
kHz
12
-
96
kHz
Sample Rate Ratio - Upsampling
-
-
1:8
Sample Rate Ratio - Downsampling
-
-
7.5:1
Interchannel Gain Mismatch
-
0.0
-
dB
Interchannel Phase Deviation
-
0.0
-
Degrees
Peak Idle Channel Noise Component (32-bit operation)
-
-
-192
dBFS
Resolution
Sample Rate with XTI = 27.000 MHz
Slave
Master
Sample Rate with other XTI clocks
Slave XTI/3750
Master XTI/512
Sample Rate with ring oscillator (XTI to GND or VL, XTO floating)
Dynamic Range (20 Hz to Fso/2, 1 kHz, -60 dBFS Input)
44.1 kHz:48 kHz
A-Weighted
Unweighted
-
180
177
-
dB
dB
44.1 kHz:192 kHz
A-Weighted
Unweighted
-
175
172
-
dB
dB
48 kHz:44.1 kHz
A-Weighted
Unweighted
-
180
177
-
dB
dB
48 kHz:96 kHz
A-Weighted
Unweighted
-
179
176
-
dB
dB
96 kHz:48 kHz
A-Weighted
Unweighted
-
176
173
-
dB
dB
192 kHz:32 kHz
A-Weighted
Unweighted
-
175
172
-
dB
dB
-
-161
-
dB
Total Harmonic Distortion + Noise (20 Hz to Fso/2, 1 kHz, 0 dBFS Input)
32 kHz:48 kHz
44.1 kHz:48 kHz
-
-171
-
dB
44.1 kHz:192 kHz
-
-130
-
dB
48 kHz:44.1 kHz
-
-160
-
dB
48 kHz:96 kHz
-
-148
-
dB
96 kHz:48 kHz
-
-168
-
dB
192 kHz:32 kHz
-
-173
-
dB
DS641F1
11
CS8421
DIGITAL FILTER CHARACTERISTICS
Parameter
Min
Typ
Max
Units
Passband (Upsampling or Downsampling)
-
-
0.4535*Fso
Hz
Passband Ripple
-
-
±0.007
dB
0.5465*Fso
-
-
Hz
125
-
-
dB
Stopband
Stopband Attenuation
Group Delay
(Note 3)
ms
3. The equation for the group delay through the sample-rate converter is (56.581 / Fsi) + (55.658 / Fso).
For example, if the input sample rate is 192 kHz and the output sample rate is 96 kHz, the group delay
through the sample-rate converter is (56.581/192,000) + (55.658/96,000) =.875 milliseconds.
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
Min
Typ
Max
Units
Power-Down Mode (Note 4)
Supply Current in power-down
(Oscillator attached to XTI-XTO)
VD
VL = 3.3 V
VL = 5.0 V
50
100
200
µA
µA
µA
Supply Current in power-down
(Crystal attached to XTI-XTO)
VD
VL = 3.3 V
VL = 5.0 V
100
1.5
4
µA
mA
mA
Supply Current at 48 kHz Fsi and Fso
(Oscillator attached to XTI-XTO)
VD
VL = 3.3 V
VL = 5.0 V
24
2.5
4
mA
mA
mA
Supply Current at 192 kHz Fsi and Fso
(Oscillator attached to XTI-XTO)
VD
VL = 3.3 V
VL = 5.0 V
80
8
13
mA
mA
mA
Supply Current at 48 kHz Fsi and Fso
(Crystal attached to XTI-XTO)
VD
VL = 3.3 V
VL = 5.0 V
24
3
7
mA
mA
mA
Supply Current at 192 kHz Fsi and Fso
(Crystal attached to XTI-XTO)
VD
VL = 3.3 V
VL = 5.0 V
80
4
6.5
mA
mA
mA
Normal Operation (Note 5)
4. Power Down Mode is defined as RST = LOW with all clocks and data lines held static, except when a
crystal is attached across XTI-XTO, in which case the crystal will begin oscillating.
5. Normal operation is defined as RST = HI.
12
DS641F1
CS8421
DIGITAL INPUT CHARACTERISTICS
Symbol
Min
Typ
Max
Units
Input Leakage Current
Parameters
Iin
-
-
±10
µA
Input Capacitance
Iin
-
8
-
pF
-
250
-
mV
Input Hysteresis
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
Min
Max
Units
High-Level Output Voltage, except MCLK_OUT and SDOUT (IOH=-4 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, except MCLK_OUT and SDOUT (IOL=4 mA)
VOL
-
.6
V
High-Level Output Voltage, MCLK_OUT
(IOH=-6 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, MCLK_OUT
(IOL=6 mA)
VOL
-
.6
V
High-Level Output Voltage, SDOUT
(IOH=-8 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, SDOUT
(IOL=8 mA)
VOL
-
.65
V
High-Level Input Voltage
VIH
0.6xVL
VL+0.3
V
Low-Level Input Voltage
VIL
-0.3
0.8
V
SWITCHING SPECIFICATIONS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameters
Symbol
RST pin Low Pulse Width
XTI Frequency (Note 7)
(Note 6)
Crystal
Digital Clock Source
XTI Pulse Width High/Low
MCLK_OUT Duty Cycle
Min
Max
Units
1
-
ms
16.384
1.024
27.000
27.000
MHz
MHz
14.8
-
ns
45
55
%
Slave Mode
I/OSCLK Frequency
-
24.576
MHz
tlrckh
326
-
ns
I/OSCLK High Time
tsckh
9
-
ns
I/OSCLK Low Time
tsckl
9
-
ns
I/OLRCK Edge to I/OSCLK Rising
tlcks
6
-
ns
OLRCK Rising Edge to OSCLK Rising Edge (TDM)
tfss
5
-
ns
I/OSCLK Rising Edge to I/OLRCK Edge
tlckd
5
-
ns
OSCLK Rising Edge to OLRCK Falling Edge (TDM)
tfsh
5
-
ns
OLRCK High Time
(Note 8)
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid
tdpd
-
18
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
3.5
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
5
-
ns
DS641F1
13
CS8421
Parameters
Symbol
Min
Max
Units
Master Mode (Note 9)
I/OSCLK Frequency (non-TDM)
64*Fsi/o
MHz
OSCLK Frequency (TDM)
256*Fso
MHz
I/OLRCK Duty Cycle
45
55
%
I/OSCLK Duty Cycle
45
55
%
I/OSCLK Falling Edge to I/OLRCK Edge
tlcks
-
5
ns
OSCLK Falling Edge to OLRCK Edge (TDM)
tfss
-
5
ns
OSCLK Falling Edge to SDOUT Output Valid
tdpd
-
7
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
3
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
5
-
ns
tlrckh
I/OLRCK
(input)
tlckd
tlcks
tsckh
tsckl
OLRCK
(input)
tfss
tfsh
tsckh
tsckl
I/OSCLK
(input)
tds
OSCLK
tdh
(input)
tds
SDIN
MSB
tdh
MSB-1
(input)
TDM_IN
tdpd
(input)
MSB
MSB-1
MSB
MSB-1
tdpd
SDOUT
MSB
(output)
MSB-1
SDOUT
(output)
Figure 1. Non-TDM Slave Mode Timing
Figure 2. TDM Slave Mode Timing
6. After powering up the CS8421, RST should be held low until the power supplies and clocks are settled.
7. The maximum possible sample rate is XTI/128.
8. OLRCK must remain high for at least 8 OSCLK periods in TDM Mode.
9. Only the input or the output serial port can be set as master at a given time.
I/OLRCK
(output)
tlcks
OLRCK
(output)
tfss
I/OSCLK
(output)
OSCLK
tds
SDIN
(output)
tdh
tds
MSB
MSB-1
(input)
TDM_IN
(output)
MSB
Figure 3. Non-TDM Master Mode Timing
14
MSB-1
MSB
MSB-1
tdpd
SDOUT
(output)
MSB
(input)
tdpd
SDOUT
tdh
MSB-1
Figure 4. TDM Master Mode Timing
DS641F1
CS8421
3. TYPICAL CONNECTION DIAGRAMS
+2.5 V
+3.3 V or +5.0 V
0.1 µF
0.1 µF
VD
Serial
Audio
Source
VL
ILRCK
OLRCK
ISCLK
OSCLK
SDIN
SDOUT
Serial
Audio
Input
Device
TDM_IN
MS_SEL
CS8421
SAIF
XTI
1 kΩ *
SAOF
SRC_UNLOCK
BYPASS
**
RST
GND
GND
Hardware Control
Settings
Figure 5. Typical Connection Diagram, No External Master Clock
* When no external master clock is supplied to the part, both input and output must be set to Slave Mode for the
part to operate properly. This is done by connecting the MS_SEL pin to ground through a resistance of 0 Ω to 1 kΩ
+ 1% as stated in Table 1, “Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL),”
on page 19.
** The connection (VL or GND) and value of these two resistors determines the mode of operation for the input
and output serial ports as described in Table 2 on page 19 and Table 3 on page 19.
DS641F1
15
CS8421
+2.5 V
+3.3 V or +5.0 V
0.1 µF
0.1 µF
VD
Serial
Audio
Source
VL
ILRCK
OLRCK
ISCLK
OSCLK
SDIN
SDOUT
Serial
Audio
Input
Device
TDM_IN
MS_SEL
CS8421
SAIF
XTI
Crystal /Clock
Source
SAOF
XTO
SRC_UNLOCK
BYPASS
MCLK_OUT
RST
*
47 kΩ
GND
**
GND
To external
hardware
Hardware Control
Settings
Figure 6. Typical Connection Diagram, Master and Slave Modes
* The connection (VL or GND) and value of these three resistors determines the mode of operation for the input
and output serial ports as described in Table 1 Serial Audio Port Master/Slave and Clock Ratio Select Start-Up
Options (MS_SEL), and Table 2, “Serial Audio Input Port Start-Up Options (SAIF),” on page 19 and Table 3,
“Serial Audio Output Port Start-Up Options (SAOF),” on page 19.
** MCLK_OUT pin should be pulled high through a 47 kΩ resistor if an MCLK output is not needed.
16
DS641F1
CS8421
4. APPLICATIONS
The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter.
The digital audio data is input and output through configurable 3-wire serial ports. The digital audio input/output ports
offer Left-Justified, Right-Justified, and I²S serial audio formats. The CS8421 also supports a TDM Mode which allows multiple channels of digital audio data on one serial line. A Bypass Mode allows the data to be passed directly
to the output port without sample rate conversion.
The CS8421 does not require a control port interface, helping to speed design time by not requiring the user to develop software to configure the part. Pins that are sensed after reset allow the part to be configured. See “Reset,
Power-Down, and Start-Up” on page 24.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mixing consoles, high quality D/A, effects processors and computer audio systems.
Figure 5 and 6 show the supply and external connections to the CS8421.
4.1
Three-Wire Serial input/Output Audio Port
A 3-wire serial audio input/output port is provided. The interface format should be chosen to suit the attached device
through the MS_SEL, SAIF, and SAOF pins. Tables 1, 2, and 3 show the pin functions and their corresponding settings. The following parameters are adjustable:
•
Master or Slave
•
Master clock (MCLK) frequencies of 128*Fsi/o, 256*Fsi/o, 384*Fsi/o, and 512*Fsi/o (Master Mode)
•
Audio data resolution of 16-, 20-, 24-, or 32-bits
•
Left- or Right-Justification of the data relative to left/right clock (LRCK) as well as I²S
Figures 7, 8, and 9 show the input/output formats available.
In Master Mode, the left/right clock and the serial bit clock are outputs, derived from the XTI input pin master clock.
In Slave Mode, the left/right clock and the serial bit clock are inputs and may be asynchronous to the XTI master
clock. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are
present in each phase to clock all of the data bits.
ISCLK is always set to 64*Fsi when the input is set to master. In normal operation, OSCLK is set to 64*Fso. In TDM
Slave Mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421’s connected together. In TDM
Master Mode, OSCLK is set to 256*Fso
For more information about serial audio formats, refer to the Cirrus Logic applications note AN282, “The 2-Channel
Serial Audio Interface: A Tutorial”, available at www.cirrus.com.
DS641F1
17
CS8421
I/OLRCK
Channel A
Channel B
I/OSCLK
SDIN
SDOUT
M SB
MSB
LSB
MSB
LSB
Figure 7. Serial Audio Interface Format - I²S
I/OLRCK
Channel A
Channel B
I/OSCLK
SDIN
SDOUT
M SB
MSB
LSB
MSB
LSB
Figure 8. Serial Audio Interface Format - Left-Justified
I/OLRCK
Channel A
Channel B
I/OSCLK
SDIN
SDOUT
MSB Extended
MSB
LSB
MSB
LSB
MSB Extended
MSB
LSB
MSB
LSB
Figure 9. Serial Audio Interface Format - Right-Justified
4.2
Mode Selection
The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes of operation.
After reset, the resistor value and condition (VL or GND) are sensed. This operation will take approximately 4 µs to
complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be muted until the mode detection sequence has completed. After this, if all clocks are stable, SRC_UNLOCK will be brought low when audio output is
valid and normal operation will occur. Tables 1, 2, and 3 show the pin functions and their corresponding settings. If
the 1.0 kΩ option is selected for MS_SEL, SAIF, or SAOF, the resistor connected to that pin may be replaced by a
direct connection to VL or GND as appropriate.
The resistor attached to each mode-selection pin should be placed physically close to the CS8421. The end of the
resistor not connected to the mode selection pins should be connected as close as possible to VL and GND to minimize noise. Tables 1, 2, and 3 show the pin functions and their corresponding settings.
18
DS641F1
CS8421
MS_SEL pin
Input M/S
Output M/S
1.0 kΩ ± 1% to GND
Slave
Slave
1.96 kΩ ± 1% to GND
Slave
Master (128 x Fso)
4.02 kΩ ± 1% to GND
Slave
Master (256 x Fso)
8.06 kΩ ± 1% to GND
Slave
Master (384 x Fso)
16.2 kΩ ± 1% to GND
Slave
Master (512 x Fso)
1.0 kΩ ± 1% to VL
Slave
Master (128 x Fsi)
1.96 kΩ ± 1% to VL
Slave
Master (256 x Fsi)
Slave
4.02 kΩ ± 1% to VL
Master (384 x Fsi)
Slave
8.06 kΩ ± 1% to VL
Master (512 x Fsi)
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL)
SAIF pin
Input Port Configuration
1.0 kΩ ± 1% to GND
I²S up to 32-bit data
1.96 kΩ ± 1% to GND
Left-Justified up to 32-bit data
4.02 kΩ ± 1% to GND
Right-Justified 16-bit data
1.0 kΩ ± 1% to VL
Right-Justified 20-bit data
1.96 kΩ ± 1% to VL
Right-Justified 24-bit data
4.02 kΩ ± 1% to VL
Right-Justified 32-bit data
Table 2. Serial Audio Input Port Start-Up Options (SAIF)
SAOF pin
Output Port Configuration
1.0 kΩ ± 1% to GND
I²S 16-bit data
1.96 kΩ ± 1% to GND
I²S 20-bit data
4.02 kΩ ± 1% to GND
I²S 24-bit data
8.06 kΩ ± 1% to GND
I²S 32-bit data
16.2 kΩ ± 1% to GND
Left-Justified 16-bit data
32.4 kΩ ± 1% to GND
Left-Justified 20-bit data
63.4 kΩ ± 1% to GND
Left-Justified 24-bit data
127.0 kΩ ± 1% to GND
Left-Justified 32-bit data
1.0 kΩ ± 1% to VL
Right-Justified 16-bit data
1.96 kΩ ± 1% to VL
Right-Justified 20-bit data
4.02 kΩ ± 1% to VL
Right-Justified 24-bit data
8.06 kΩ ± 1% to VL
Right-Justified 32-bit data
16.2 kΩ ± 1% to VL
TDM Mode 16-bit data
32.4 kΩ ± 1% to VL
TDM Mode 20-bit data
63.4 kΩ ± 1% to VL
TDM Mode 24-bit data
127.0 kΩ ± 1% to VL
TDM Mode 32-bit data
Table 3. Serial Audio Output Port Start-Up Options (SAOF)
DS641F1
19
CS8421
4.3
Sample Rate Converter (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very
high rate and then downsample to the outgoing rate. The internal data path is 32-bits wide even if a lower
bit depth is selected at the output. The filtering is designed so that a full input audio bandwidth of 20 kHz is
preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz. When the output sample rate becomes less than the input sample rate, the input is automatically band-limited to avoid
aliasing products in the output. Careful design ensures minimum ripple and distortion products are added
to the incoming signal. The SRC also determines the ratio between the incoming and outgoing sample rates
and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little impact on the
dynamic performance of the rate converter and has no influence on the output clock.
4.3.1
Data Resolution and Dither
When using the serial audio input port in Left-Justified and I²S Modes, all input data is treated as 32-bits
wide. Any truncation that has been done prior to the CS8421 to less than 32-bits should have been done
using an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input
data will be truncated to the bit depth set by SAIF pin setting. If the SAIF bit depth is set to 16-, 20-, or 24bits, and the input data is 32-bits wide, truncation distortion will occur. Similarly, in any serial audio input
port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks), the input
words will be truncated, causing truncation distortion at low levels. In summary, there is no dithering
mechanism on the input side of the CS8421, and care must be taken to ensure that no truncation occurs.
Dithering is used internally where appropriate inside the SRC block.
The output side of the SRC can be set to 16-, 20-, 24-, or 32-bits. Dithering is applied and is automatically
scaled to the selected output word length. This dither is not correlated between left and right channels.
4.3.2
SRC Locking and Varispeed
The SRC calculates the ratio between the input sample rate and the output sample rate and uses this information to set up various parameters inside the SRC block. The SRC takes some time to make this calculation, approximately 4200/Fso (8.75 ms at Fso of 48 kHz).
If Fsi is changing, as in a varispeed application, the SRC will track the incoming sample rate. During this
tracking mode, the SRC will still rate convert the audio data, but at increased distortion levels. Once the
incoming sample rate is stable, the SRC will return to normal levels of audio quality. The data buffer in the
SRC can overflow if the input sample rate changes at greater than 10%/sec. There is no provision for
varispeed applications where Fso is changing.
The SRC_UNLOCK pin is used to indicate when the SRC is not locked. When RST is asserted, or if there
is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high
until the SRC has reacquired lock and settled, at which point it will transition low. When the
SRC_UNLOCK pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to
unmute its output.
4.3.3
Bypass Mode
When the BYPASS pin is set high, the input data bypasses the sample rate converter and is sent directly
to the serial audio output port. No dithering is performed on the output data. This mode is ideal for passing
non-audio data through without a sample-rate conversion. ILRCK and OLRCK should be the same sample rate and synchronous in this mode.
20
DS641F1
CS8421
4.3.4
Muting
The SDOUT pin is set to all zero output (full mute) immediately after the RST pin is set high. When the
output from the SRC becomes valid, though the SRC may not have reached full performance, SDOUT is
unmuted over a period of approximately 4096 OLRCK cycles (soft unmuted). When the output becomes
invalid, depending on the condition, SDOUT is either immediately set to all zero output (hard muted) or
SDOUT is muted over a period of approximately 4096 OLRCK cycles until it reaches full mute (soft muted). The SRC will soft mute SDOUT if there is an illegal ratio between ILRCK and the XTI master clock.
Conditions that will cause the SRC to hard mute SDOUT include removing OLRCK, the RST pin being
set low, or illegal ratios between OLRCK and the XTI master clock. After all invalid states have been
cleared, the SRC will soft unmute SDOUT.
4.3.5
Group Delay and Phase Matching Between Multiple CS8421 Parts
The equation for the group delay through the sample rate converter is shown in “Digital Filter Characteristics” on page 12. This phase delay is equal across multiple parts. Therefore, when multiple parts operate
at the same Fsi and Fso and use a common XTI/XTO clock, their output data is phase matched.
4.3.6
Master Clock
The CS8421 uses the clock signal supplied through XTI as its master clock (MCLK). MCLK can be supplied from a digital clock source, a crystal oscillator, or a fundamental mode crystal. Figure 10 shows the
typical connection diagram for using a fundamental mode crystal. Please refer to the crystal manufacturer’s specifications for the external capacitor recommendations. If XTO is not used, such as with a digital
clock source or crystal oscillator, XTO should be left unconnected or pulled low through a 47 kΩ resistor
to GND.
If either serial audio port is set as master, MCLK will be used to supply the sub-clocks to the master SCLK
and LRCK. In this case, MCLK will be synchronous to the master serial audio port. If both serial audio
ports are set as slave, MCLK can be asynchronous to either or both ports. If the user needs to change the
clock source to XTI while the CS8421 is still powered on and running, a RESET must be issued once the
XTI clock source is present and valid to ensure proper operation.
When both serial ports are configured as slave and operating at sample rates less than 96 kHz, the
CS8421 has the ability to operate without a master clock input through XTI. This benefits the design by
not requiring extra external clock components (lowering production cost) and not requiring a master clock
to be routed to the CS8421, resulting in lowered noise contribution in the system. In this mode, an internal
oscillator provides the clock to run all of the internal logic. To enable the internal oscillator, simply tie XTI
to GND or VL. In this mode, XTO should be left unconnected.
The CS8421 can also provide a buffered MCLK output through the MCLK_OUT pin. This pin can be used
to supply MCLK to other system components that operate synchronously to MCLK. If MCLK_OUT is not
needed, the output of the pin can be disabled by pulling the pin high through a 47 kΩ resistor to VL.
MCLK_OUT is also disabled when using the internal oscillator mode. The MCLK_OUT pin will be set low
when disabled by using the internal oscillator mode.
DS641F1
21
CS8421
4.3.7
Clocking
In order to ensure proper operation of the CS8421, the clock or crystal attached to XTI must simultaneously satisfy the requirements of LRCK for both the input and output as follows:
•
If the input is set to master, Fsi ≤ XTI/128 and Fso ≤ XTI/130.
•
If the output is set to master, Fso ≤ XTI/128 and Fsi ≤ XTI/130.
•
If both input and output are set to slave, XTI ≥ 130*[maximum(Fsi,Fso)], XTI/Fsi < 3750, and XTI/Fso <
3750.
XTI
XTO
R
C
C
Figure 10. Typical Connection Diagram for Crystal Circuit
22
DS641F1
CS8421
4.4
Time Division Multiplexing (TDM) Mode
TDM Mode allows several CS8421 to be serially connected together allowing their corresponding SDOUT
data to be multiplexed onto one line for input into a DSP or other TDM-capable multichannel device.
The CS8421 can operate in two TDM modes. The first mode consists of all of the CS8421’s output ports set
to slave, as shown in Figure 13. The second mode consists of one CS8421 output port set to master and
the remaining CS8421’s output ports set to slave, as shown in Figure 14.
The TDM_IN pin is used to input the data, while the SDOUT pin is used to output the data. The first CS8421
in the chain should have its TDM_IN set to GND. Data is transmitted from SDOUT most significant bit first
on the first OSCLK falling edge after an OLRCK transition and is valid on the rising edge of OSCLK.
In TDM Slave Mode, the number of channels that can by multiplexed to one serial data line depends on the
output sampling rate. For Slave Mode, OSCLK must operate at N*64*Fso, where N is the number of
CS8421’s connected together. The maximum allowable OSCLK frequency is 24.576 MHz, so for Fso =
48 kHz, N = 8 (16 channels of serial audio data).
In TDM Master Mode, OSCLK operates at 256*Fso, which is equivalent to N = 4, so a maximum of 8 channels of digital audio can be multiplexed together. Note that for TDM Master Mode, MCLK must be at least
256*Fso, where Fso ≤ 96 kHz. OLRCK identifies the start of a new frame. Each time-slot is 32-bits wide,
with the valid data sample left-justified within the time-slot. Valid data lengths are 16-, 20-, 24- or 32-bits.
Figures 11 and 12 show the interface format for Master and Slave TDM Modes with a 32-bit word-length.
OLRCK
OSCLK
SDOUT/
TDM_IN
MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB
SDOUT 4, ch A
SDOUT 4, ch B
SDOUT 3, ch A
SDOUT 3, ch B
SDOUT 2, ch A
SDOUT 2, ch B
SDOUT 1, ch A
SDOUT 1, ch B
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Figure 11. TDM Slave Mode Timing Diagram
256 OSCLKs
OLRCK
OSCLK
SDOUT/
TDM_IN
MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB
SDOUT 4, ch A
SDOUT 4, ch B
SDOUT 3, ch A
SDOUT 3, ch B
SDOUT 2, ch A
SDOUT 2, ch B
SDOUT 1, ch A
SDOUT 1, ch B
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Figure 12. TDM Master Mode Timing Diagram
DS641F1
23
CS8421
Output
Clock
Source
LRCK
SCLK
CS84211
CS84212
OLRCK
OSCLK
TDM_IN
TDM_IN
TDM_IN
SDOUT
OLRCK
OSCLK
TDM_IN
SDOUT
OLRCK
OSCLK
LRCK
OSCLK
SCLK
SDOUT
SDIN
ISCLK
Slave
Slave
SDIN
PCM Source 2
DSP
OLRCK
ILRCK
ISCLK
Slave
SDIN
PCM Source 1
SDOUT
ILRCK
ISCLK
Slave
SDIN
OSCLK
OSCLK
SDOUT
ILRCK
ISCLK
CS84214
OLRCK
OSCLK
SDOUT
ILRCK
OLRCK
CS84213
OLRCK
Slave
SDIN
SDOUT
OLRCK
PCM Source 3
OSCLK
SDOUT
PCM Source 4
Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)
CS84211
CS84212
OLRCK
OSCLK
TDM_IN
TDM_IN
SDOUT
PCM Source 1
TDM_IN
OSCLK
SDOUT
PCM Source 2
TDM_IN
OSCLK
SDOUT
PCM Source 3
LRCK
OSCLK
SCLK
SDOUT
SDIN
ISCLK
Slave
Slave
SDIN
OLRCK
DSP
OLRCK
ILRCK
ISCLK
Slave
SDIN
OLRCK
SDOUT
ILRCK
ISCLK
Master
SDIN
OSCLK
OSCLK
SDOUT
ILRCK
ISCLK
CS84214
OLRCK
OSCLK
SDOUT
ILRCK
OLRCK
CS84213
OLRCK
Slave
SDIN
OLRCK
OSCLK
SDOUT
PCM Source 4
Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave)
4.5
Reset, Power-Down, and Start-Up
When RST is low, the CS8421 enters a low-power mode, all internal states are reset, and the outputs are
disabled. After RST transitions from low to high, the part senses the resistor value on the configuration pins
(MS_SEL, SAIF, and SAOF) and sets the appropriate mode of operation. After the mode has been set (approximately 4 µs), the part is set to normal operation and all outputs are functional.
4.6
Power Supply, Grounding, and PCB Layout
The CS8421 operates from a VD = +2.5 V and VL = +3.3 V or +5.0 V supply. These supplies may be set
independently. Follow normal supply decoupling practices; see Figure 6.
Extensive use of power and ground planes, ground-plane fill in unused areas, and surface-mount decoupling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the
board as the CS8421 to minimize inductance effects, and all decoupling capacitors should be as close to
the CS8421 as possible. The pin of the configuration resistors not connected to MS_SEL, SAIF, and SAOF
should be connected as close as possible to VL or GND.
24
DS641F1
CS8421
5. PERFORMANCE PLOTS
d
B
F
S
+0
+0
-20
-20
-40
-40
-60
-60
-80
d
B
F
S
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
-200
5k
10k
15k
-200
20k
20k
40k
Figure 15. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 48 kHz:48 kHz
d
B
F
S
+0
+0
-20
-40
-40
-60
-60
-80
d
B
F
S
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
5k
10k
15k
-200
20k
2.5k
5k
7.5k
10k
Hz
+0
+0
-20
-40
-40
-60
-60
-80
d
B
F
S
-100
-120
-120
-160
-160
-180
-180
-200
30k
40k
Hz
Figure 19. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 48 kHz:96 kHz
DS641F1
20k
-80
-140
20k
17.5k
-100
-140
10k
15k
Figure 18. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 48 kHz:44.1 kHz
-20
-200
12.5k
Hz
Figure 17. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 44.1 kHz:48 kHz
d
B
F
S
80k
Figure 16. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 44.1 kHz:192 kHz
-20
-200
60k
Hz
Hz
5k
10k
15k
20k
Hz
Figure 20. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 96 kHz:48 kHz
25
CS8421
+0
-60
-20
-40
-80
-60
d
B
F
S
-100
-80
d
B
F
S
-100
-120
-140
-120
-140
-160
-160
-180
-180
-200
5k
10k
15k
-200
20k
10k
20k
Figure 21. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz
Tone, 192 kHz:48 kHz
d
B
F
S
-60
-80
-80
-100
-100
d
B
F
S
-120
-140
-120
-140
-160
-160
-180
-180
5k
10k
15k
-200
20k
20k
40k
Hz
-60
-80
-80
-100
-100
d
B
F
S
-120
-140
-140
-160
-180
-180
10k
15k
20k
Hz
Figure 25. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 44.1 kHz:48 kHz
26
-120
-160
5k
80k
Figure 24. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 44.1 kHz:192 kHz
-60
-200
60k
Hz
Figure 23. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 48 kHz:48 kHz
d
B
F
S
40k
Figure 22. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 48 kHz:96 kHz
-60
-200
30k
Hz
Hz
-200
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
20k
Hz
Figure 26. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 48 kHz:44.1 kHz
DS641F1
CS8421
+0
-60
-20
-80
-40
-60
-100
d
B
F
S
d
B
F
S
-120
-140
-80
-100
-120
-140
-160
-160
-180
-200
-180
5k
10k
15k
-200
20k
5k
10k
Hz
15k
20k
Hz
Figure 27. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 96 kHz:48 kHz
Figure 28. IMD, 10 kHz and 11 kHz -7 dBFS,
96 kHz:48 kHz
+0
-60
-20
-40
-80
-60
-100
d
B
F
S
d
B
F
S
-120
-140
-80
-100
-120
-140
-160
-160
-180
-200
-180
5k
10k
15k
-200
20k
2.5k
5k
7.5k
10k
Figure 29. Wideband FFT Plot (16k Points) -60 dBFS
1 kHz Tone, 192 kHz:48 kHz
d
B
F
S
+0
+0
-20
-40
-40
-60
-60
-80
d
B
F
S
-100
-120
-120
-160
-160
-180
-180
15k
20k
Hz
Figure 31. IMD, 10 kHz and 11 kHz -7 dBFS,
44.1 kHz:48 kHz
DS641F1
20k
-80
-140
10k
17.5k
-100
-140
5k
15k
Figure 30. IMD, 10 kHz and 11 kHz -7 dBFS,
48 kHz:44.1 kHz
-20
-200
12.5k
Hz
Hz
-200
5k
10k
15k
20k
Hz
Figure 32. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 44.1 kHz:48 kHz
27
CS8421
d
B
F
S
+0
+0
-20
-20
-40
-40
-60
-60
-80
d
B
F
S
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
-200
20k
40k
60k
-200
80k
10k
20k
Figure 33. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz
Tone, 192 kHz:192 kHz
d
B
F
S
+0
-20
-20
-40
-40
-60
-60
-80
d
B
F
S
-100
-120
-80
-100
-120
-140
-140
-160
-160
-180
-180
5k
10k
40k
Figure 34. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 48 kHz:96 kHz
+0
-200
30k
Hz
Hz
15k
-200
20k
5k
10k
Hz
15k
20k
Hz
Figure 35. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 48 kHz:48 kHz
Figure 36. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 96 kHz:48 kHz
-120
+0
-122.5
-20
-125
-40
-127.5
-60
d
B
F
S
-130
-80
d
B
F
S
-100
-120
-132.5
-135
-137.5
-140
-140
-142.5
-160
-145
-180
-200
-147.5
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
20k
Hz
Figure 37. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz
Tone, 48 kHz:44.1 kHz
28
-150
50k
75k
100k
125k
150k
175k
Hz
Figure 38. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 192 kHz
DS641F1
CS8421
-120
-120
-122.5
-122.5
-125
-125
-127.5
-127.5
-130
d
B
F
S
-130
-132.5
d
B
F
S
-135
-137.5
-132.5
-135
-137.5
-140
-140
-142.5
-142.5
-145
-145
-147.5
-147.5
-150
50k
75k
100k
125k
150k
-150
175k
50k
75k
100k
125k
150k
175k
Hz
Hz
Figure 39. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 48 kHz
Figure 40. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 96 kHz
-120
-135
-122.5
-136
-125
-137
-127.5
-138
-130
d
B
F
S
-132.5
d
B
F
S
-135
-137.5
-140
-139
-140
-141
-142
-142.5
-143
-145
-144
-147.5
-150
50k
75k
100k
125k
150k
-145
175k
50k
75k
100k
Hz
Figure 41. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 44.1 kHz
-120
-120
-122.5
-122.5
-125
-125
-127.5
-127.5
d
B
F
S
-135
-137.5
-132.5
-135
-137.5
-140
-140
-142.5
-142.5
-145
-145
-147.5
-147.5
-150
50k
75k
100k
125k
150k
175k
Hz
Figure 43. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
Tone, Fsi = 32 kHz
DS641F1
175k
-130
-132.5
-150
150k
Figure 42. Dynamic Range vs. Output Sample Rate, 60 dBFS 1 kHz Tone, Fsi = 192 kHz
-130
d
B
F
S
125k
Hz
50k
75k
100k
125k
150k
175k
Hz
Figure 44. Dynamic Range vs. Output Sample Rate, 60 dBFS 1 kHz Tone, Fsi = 32 kHz
29
CS8421
-120
-120
-122.5
-122.5
-125
-125
-127.5
-127.5
-130
d
B
F
S
-130
-132.5
d
B
F
S
-135
-137.5
-132.5
-135
-137.5
-140
-140
-142.5
-142.5
-145
-145
-147.5
-147.5
-150
50k
75k
100k
125k
150k
-150
175k
50k
75k
100k
Hz
125k
150k
175k
Hz
Figure 45. Dynamic Range vs. Output Sample Rate, 60 dBFS 1 kHz Tone, Fsi = 96 kHz
Figure 46. Dynamic Range vs. Output Sample Rate, 60 dBFS 1 kHz Tone, Fsi = 44.1 kHz
+0
+0
-0.02
-20
-0.04
-40
d
B
F
S
-0.06
192 kHz:48 kHz
-60
d
B
F
S
192 kHz:96 kHz
-80
-100
-0.08
-0.1
-0.12
-0.14
192 kHz:32 kHz
-0.16
-120
-0.18
-140
0
10k
20k
30k
40k
50k
-0.2
0
60k
5k
10k
15k
20k
25k
Hz
Hz
Figure 47. Frequency Response with 0 dBFS Input
Figure 48. Passband Ripple, 192 kHz:48 kHz
-120
+0
-122.5
d
B
F
S
-10
-125
-20
-127.5
-30
-130
-40
-50
-132.5
d
B
F
S
-135
-137.5
-60
-70
-80
-90
-140
-100
-142.5
-110
-145
-120
-147.5
-150
-130
50k
75k
100k
125k
150k
175k
Hz
Figure 49. Dynamic Range vs. Output Sample Rate, 60 dBFS 1 kHz Tone, Fsi = 48 kHz
30
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 50. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 48 kHz:48 kHz
DS641F1
CS8421
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
d
B
F
S
d
B
F
S
-60
-70
-80
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
-120
-100
-80
-60
-40
-20
-140
-140
+0
-120
-100
-80
Figure 51. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 48 kHz:44.1 kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-70
-80
-70
-80
-90
-100
-100
-110
-110
-120
-120
-130
-120
-100
-80
-60
-40
-20
-140
-140
+0
-120
-100
-80
dBFS
-40
-20
+0
Figure 54. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 44.1 kHz:192 kHz
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
d
B
F
S
-60
-70
-80
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 55. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 44.1 kHz:48 kHz
DS641F1
-60
dBFS
Figure 53. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 96 kHz:48 kHz
-140
-140
+0
-60
-90
-130
d
B
F
S
-20
-50
d
B
F
S
-60
-140
-140
-40
Figure 52. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 48 kHz:96 kHz
-50
d
B
F
S
-60
dBFS
dBFS
-140
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 56. Linearity Error, 0 to -140 dBFS Input, 200 Hz
Tone, 192 kHz:44.1 kHz
31
CS8421
-110
-110
-115
-115
-120
-120
-125
-125
-130
-130
-135
-135
d
B
F
S
-140
d
B
F
S
-145
-150
-140
-145
-150
-155
-155
-160
-160
-165
-165
-170
-170
-175
-175
-180
-140
-120
-100
-80
-60
-40
-20
-180
-140
+0
-120
-100
-80
dBFS
Figure 57. THD+N vs. Input Amplitude, 1 kHz Tone,
48 kHz:44.1 kHz
-110
-110
-115
-115
-120
-120
-125
-125
-130
-130
d
B
F
S
-145
-150
-145
-150
-155
-155
-160
-160
-165
-165
-170
-170
-175
-175
-120
-100
-80
-60
-40
-20
-180
-140
+0
-120
-100
-80
-40
-20
+0
Figure 60. THD+N vs. Input Amplitude, 1 kHz Tone,
44.1 kHz:192 kHz
-110
-110
-115
-115
-120
-120
-125
-125
-130
-130
-135
-135
-140
d
B
F
S
-145
-150
-140
-145
-150
-155
-155
-160
-160
-165
-165
-170
-170
-175
-175
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 61. THD+N vs. Input Amplitude, 1 kHz Tone,
44.1 kHz:48 kHz
32
-60
dBFS
Figure 59. THD+N vs. Input Amplitude, 1 kHz Tone,
96 kHz:48 kHz
-180
-140
+0
-140
dBFS
d
B
F
S
-20
-135
-140
-180
-140
-40
Figure 58. THD+N vs. Input Amplitude, 1 kHz Tone,
48 kHz:96 kHz
-135
d
B
F
S
-60
dBFS
-180
-140
-120
-100
-80
-60
-40
-20
+0
dBFS
Figure 62. THD+N vs. Input Amplitude, 1 kHz Tone,
192 kHz:48 kHz
DS641F1
CS8421
-110
-110
-115
-115
-120
-120
-125
-125
-130
-130
-135
-135
-140
d
B
F
S
d
B
F
S
-145
-150
-140
-145
-150
-155
-155
-160
-160
-165
-165
-170
-170
-175
-175
-180
0
-180
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
20k
-140
-120
-100
Figure 63. THD+N vs. Frequency Input, 0 dBFS,
48 kHz:44.1 kHz
-110
-110
-115
-115
-120
-120
-125
-125
-130
-130
-40
-20
+0
-135
-140
d
B
F
S
-145
-150
-140
-145
-150
-155
-155
-160
-160
-165
-165
-170
-170
-175
-175
-180
0
-60
Figure 64. THD+N vs. Frequency Input, 0 dBFS,
48 kHz:96 kHz
-135
d
B
F
S
-80
dBFS
Hz
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
20k
Hz
Figure 65. THD+N vs. Frequency Input, 0 dBFS,
44.1 kHz:48 kHz
-180
0
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
20k
Hz
Figure 66. THD+N vs. Frequency Input, 0 dBFS,
96 kHz:48 kHz
All performance plots represent typical performance. Measurements for all performance plots were taken under the
following conditions, unless otherwise stated:
•
VD = 2.5 V, VL = 3.3 V
•
Serial Audio Input port set to slave
•
Serial Audio Output port set to slave
•
Input and output clocks and data are asynchronous
•
XTI/XTO = 27 MHz
•
Input signal = 1.000 kHz, 0 dBFS
•
Measurement Bandwidth = 20 to (Fso/2) Hz
•
Word Width = 24 Bits
DS641F1
33
CS8421
6. PACKAGE DIMENSIONS
20L TSSOP (4.4 MM BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
A1
b2
END VIEW
L
SIDE VIEW
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
DIM
A
A1
A2
b
D
E
E1
e
L
µ
MIN
-0.002
0.03346
0.00748
0.252
0.248
0.169
-0.020
0°
NOM
-0.004
0.0354
0.0096
0.256
0.2519
0.1732
-0.024
4°
MILLIMETERS
MAX
0.043
0.006
0.037
0.012
0.259
0.256
0.177
0.026
0.028
8°
MIN
-0.05
0.85
0.19
6.40
6.30
4.30
-0.50
0°
NOM
--0.90
0.245
6.50
6.40
4.40
-0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
6.60
6.50
4.50
0.65
0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
TSSOP THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance
34
2 Layer Board
4 Layer Board
Symbol
Min
Typ
Max
Units
θJA
-
48
38
-
°C/Watt
°C/Watt
DS641F1
CS8421
20-PIN QFN (5 × 5 MM BODY) PACKAGE DRAWING
b
D
Pin #1 Corner
e
Pin #1 Corner
E2
E
A1
D2
L
A
Top View
Side View
DIM
MIN
A
A1
b
D
D2
E
E2
e
L
-0.0000
0.0091
0.1201
0.1202
0.0197
INCHES
NOM
--0.0110
0.1969 BSC
0.1220
0.1969 BSC
0.1221
0.0256 BSC
0.0236
Bottom View
MAX
MIN
0.0394
0.0020
0.0130
-0.00
0.23
0.1240
3.05
0.1241
3.05
0.0276
0.50
MILLIMETERS
NOM
--0.28
5.00 BSC
3.10
5.00 BSC
3.10
0.65 BSC
0.60
NOTE
MAX
1.00
0.05
0.33
3.15
3.15
0.70
1
1
1, 2
1
1
1
1
1
1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.23mm and 0.33mm
from the terminal tip.
QFN THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance
DS641F1
2 Layer Board
4 Layer Board
Symbol
Min
Typ
Max
Units
θJA
-
128
35
-
°C/Watt
°C/Watt
35
CS8421
7. ORDERING INFORMATION
ORDERING INFORMATION
Product
Description
Package
Pb-Free Temp Range
20-TSSOP
-10° to +70°C
CS8421
32-bit Asynchronous Sample Rate
Converter
20-QFN
YES
20-TSSOP
CDB8421
Evaluation Board for CS8421
-40° to +85°C
-
-
Container
Order#
Rail
CS8421-CZZ
Tape and Reel
CS8421-CZZR
Rail
CS8421-CNZ
Tape and Reel
CS8421-CNZR
Rail
CS8421-DZZ
Tape and Reel
CS8421-DZZR
-
CDB8421
8. REVISION HISTORY
Release
A1
PP1
-Updated “Features” on page 1.
-Updated “Sample Rate with other XTI clocks” on page 11.
-Updated “DC Electrical Characteristics” on page 12.
-Updated “Digital Input Characteristics” on page 13.
-Updated “Digital Interface Specifications” on page 13
-Updated Figure 6. “Typical Connection Diagram, Master and Slave Modes” on page 16.
-Added Figure 5. “Typical Connection Diagram, No External Master Clock” on page 15.
-Corrected reference to Bypass Mode to output only data on page 17.
-Added Section 4.3.7 “Clocking” on page 22.
-Updated “Master Clock” on page 21.
-Updated “Time Division Multiplexing (TDM) Mode” on page 23.
-Added Thermal Pad label “Pin Descriptions” on page 6.
-Added Thermal Pad pin description to “QFN Pin Descriptions” on page 8.
-Updated “Performance Plots” on page 25.
PP2
-Updated “Characteristics and Specifications” on page 10.
-Corrected Section 4.3.7 “Clocking” on page 22.
-Corrected “QFN Thermal Characteristics” on page 35.
PP3
-Updated “Digital Interface Specifications” on page 13.
-Updated “Switching Specifications” on page 13.
F1
36
Changes
Initial Advance Release
Final Release
DS641F1
CS8421
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
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