GS1535A / GS9065A HD-LINX® II Multi-Rate SDI Automatic Reclocker GS1535A / GS9065A Data Sheet Features GS1535A • • • • • • • • • • • • • • • SMPTE 292M, 259M and 344M compliant Supports data rates of 143, 177, 270, 360, 540, 1483.5, 1485 Mb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Footprint compatible with the GS1535, GS9065 and GS9065A Automatic Reclockers Auto and Manual Modes for rate selection Standards indication in Auto Mode 4:1 input multiplexer Lock Detect Output On-chip Input and Output Termination Differential 50Ω inputs and outputs Mute, Bypass and Autobypass functions SD/HD indication output to control GS1528A Dual Slew-Rate Cable Driver Single 3.3V power supply Operating temperature range: 0°C to 70°C GS9065A • • • • • • • • • • • • • • SMPTE 259M and 344M compliant Supports data rates of 143, 177, 270, 360, and 540Mb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Footprint compatible with the GS1535, GS9065 and GS1535A Automatic Reclockers Auto and Manual Modes for rate selection Standards indication in Auto Mode 4:1 input multiplexer Lock Detect Output On-chip Input and Output Termination Differential 50Ω inputs and outputs Mute, Bypass and Autobypass functions Single 3.3V power supply Operating temperature range: 0°C to 70°C Applications GS1535A • SMPTE 292M, SMPTE 259M and SMPTE 344M Serial Digital Interfaces GS9065A • SMPTE 259M and SMPTE 344M Serial Digital Interfaces. Description The GS1535A/9065A is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The GS1535A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal. The GS9065A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 259M or SMPTE 344M compliant digital video signal. The GS1535A/9065A removes the high frequency jitter components from the bit-serial stream. Input termination is on-chip for seamless matching to 50Ω transmission lines. An LVPECL compliant output interfaces seamlessly to the GS1528A/9068A Cable Driver. The GS1535A/9065A can operate in either auto or manual rate selection mode. In Auto mode the device will automatically detect and lock onto incoming SMPTE SDI data signals at any supported rate. For single rate data systems, the GS1535A/9065A can be configured to operate in Manual mode. In both modes, the device requires only one external crystal to set the VCO frequency when not locked and provides adjustment free operation. In systems which require passing of non-SMPTE data rates, the GS1535A/9065A can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. The ASI/177 input pin allows for manual selection of support of either 177Mb/s or DVB-ASI inputs. The GS1535A/9065A is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS Compliant). 31497 - 3 November 2005 1 of 27 www.gennum.com GS1535A / GS9065A Data Sheet XTAL+ XTAL- XTAL XTAL OUT+ OUT- XTAL OSC LF+ LF- KBB BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE DDI 0 DDI 1 DDI 2 PHASE FREQUENCY DETECTOR D A T A CHARGE PUMP M U X VCO PHASE DETECTOR M U X DIVIDE BY 2,4,6,8,12,16 DIVIDE BY 152, 160, 208 DDI 3 BYPASS LOGIC CONTROL LOGIC DDI_SEL[1:0] SS[2:0] ASI/177 AUTO/MAN LD SD/HD AUTOBYPASS BYPASS GS1535A Functional Block Diagram XTAL+ XTAL- XTAL XTAL OUT+ OUT- XTAL OSC LF+ LF- KBB BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE DDI 0 DDI 1 DDI 2 DDI 3 PHASE FREQUENCY DETECTOR D A T A CHARGE PUMP M U X VCO PHASE DETECTOR M U X DIVIDE BY 2,4,6,8,12 DIVIDE BY 152, 160 BYPASS LOGIC CONTROL LOGIC DDI_SEL[1:0] SS[2:0] ASI/177 AUTO/MAN SD LD AUTOBYPASS BYPASS GS9065A Functional Block Diagram 31497 - 3 November 2005 2 of 27 GS1535A / GS9065A Data Sheet Contents Features ........................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................4 1.1 GS1535A Pin Assignment ..............................................................................4 1.2 GS9065A Pin Assignment ..............................................................................5 1.3 GS1535A / GS9065A Pin Descriptions ...........................................................6 2. Electrical Characteristics ...........................................................................................9 2.1 Absolute Maximum Ratings ............................................................................9 2.2 DC Electrical Characteristics ..........................................................................9 2.3 AC Electrical Characteristics .........................................................................10 2.4 Solder Reflow Profiles ...................................................................................12 3. Input / Output Circuits .............................................................................................13 4. Detailed Description ................................................................................................17 4.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................17 4.2 VCO ..............................................................................................................18 4.3 Charge Pump ................................................................................................18 4.4 Frequency Acquisition Loop — The Phase-Frequency Detector ..................19 4.5 Phase Acquisition Loop — The Phase Detector ...........................................19 4.6 4:1 Input Mux ................................................................................................20 4.7 Automatic and Manual Data Rate Selection .................................................20 4.8 Bypass Mode ................................................................................................21 4.9 DVB-ASI Operation .......................................................................................21 4.10 Lock ............................................................................................................22 4.11 Output Drivers .............................................................................................22 4.12 Output Mute ................................................................................................22 5. Typical Application Circuits .....................................................................................23 6. Package & Ordering Information .............................................................................25 6.1 Package Dimensions ....................................................................................25 6.2 Packaging Data .............................................................................................26 6.3 Ordering Information .....................................................................................26 7. Revision History ......................................................................................................27 31497 - 3 November 2005 3 of 27 GS1535A / GS9065A Data Sheet 1. Pin Out RSVD RSVD 58 57 56 GND RSVD 59 XTAL_OUT+ RSVD 60 XTAL_OUT- VEE_CP 61 XTAL+ VCC_CP 62 XTAL- LF+ 63 RSVD LF- 64 RSVD GND 1.1 GS1535A Pin Assignment 55 54 53 52 51 50 49 DDI0 1 48 VEE_DDO DDI0_VTT 2 47 VCC_DDO DDI0 3 46 DDO GND 4 45 DDO_VTT DDI1 5 44 DDO DDI1_VTT 6 43 GND DDI1 7 42 RSVD GS1535A (TOP VIEW) GND 8 41 RSVD DDI2 9 40 RSVD DDI2_VTT 10 39 RSVD DDI2 11 38 RSVD GND 12 37 GND DDI3 13 36 DDO_MUTE DDI3_VTT 14 35 RSVD DDI3 15 34 KBB GND 16 33 SD/HD 24 25 DDI_SEL1 BYPASS AUTOBYPASS AUTO/MAN VCC_VCO VEE_VCO SS0 SS1 26 27 28 29 30 31 32 GND 23 VEE_DIG 22 VCC_DIG 21 LD 20 RSVD 19 SS2 18 ASI/177 17 DDI_SEL0 P Figure 1-1: 64-Pin LQFP 31497 - 3 November 2005 4 of 27 GS1535A / GS9065A Data Sheet RSVD RSVD 58 57 56 GND RSVD 59 XTAL_OUT+ RSVD 60 XTAL_OUT- VEE_CP 61 XTAL+ VCC_CP 62 XTAL- LF+ 63 RSVD LF- 64 RSVD GND 1.2 GS9065A Pin Assignment 55 54 53 52 51 50 49 DDI0 1 48 VEE_DDO DDI0_VTT 2 47 VCC_DDO DDI0 3 46 DDO GND 4 45 DDO_VTT DDI1 5 44 DDO DDI1_VTT 6 43 GND DDI1 7 42 RSVD GS9065A (TOP VIEW) GND 8 41 RSVD DDI2 9 40 RSVD DDI2_VTT 10 39 RSVD DDI2 11 38 RSVD GND 12 37 GND DDI3 13 36 DDO_MUTE DDI3_VTT 14 35 RSVD DDI3 15 34 KBB GND 16 33 SD 24 25 DDI_SEL1 BYPASS AUTOBYPASS AUTO/MAN VCC_VCO VEE_VCO SS0 SS1 26 27 28 29 30 31 32 GND 23 VEE_DIG 22 VCC_DIG 21 LD 20 RSVD 19 SS2 18 ASI/177 17 DDI_SEL0 P Figure 1-2: 64-Pin LQFP 31497 - 3 November 2005 5 of 27 GS1535A / GS9065A Data Sheet 1.3 GS1535A / GS9065A Pin Descriptions Table 1-1: GS1535A / GS9065A Pin Descriptions Pin Number Name Type Description 1, 3 DDI0, DDI0 Input Serial digital differential input 0. 2 DDI0_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI0 and DDI0. GND Passive Recommended connect to GND. 5, 7 DDI1,DDI1 Input Serial digital differential input 1. 6 DDI1_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI1 and DDI1. 9, 11 DDI2, DDI2 Input Serial digital differential input 2. 10 DDI2_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI2 and DDI2. 13, 15 DDI3, DDI3 Input Serial digital differential input 3. 14 DDI3_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI3 and DDI3. DDI_SEL[1:0] Logic Input Serial digital input select. 4, 8, 12,16, 32, 37, 43, 49, 64 17, 18 19 BYPASS Logic Input DDI_SEL1 DDI_SEL0 INPUT SELECTED 0 0 DDI0 0 1 DDI1 1 0 DDI2 1 1 DDI3 Bypass the reclocker stage. When BYPASS is HIGH, it overwrites the AUTOBYPASS setting. 20 AUTOBYPASS Logic Input Automatically bypasses the reclocker stage when the PLL is not locked This pin is ignored when BYPASS is HIGH. 21 AUTO/MAN Logic Input Auto/Manual select. When set HIGH, the standard is automatically detected from the input data rate. When set LOW, the user must program the input standard using the SS[2:0] pins. 22 VCC_VCO Power Most positive power supply connection for the internal VCO section. Connect to 3.3V. 23 VEE_VCO Power Most negative power supply connection for the internal VCO section. Connect to GND. 31497 - 3 November 2005 6 of 27 GS1535A / GS9065A Data Sheet Table 1-1: GS1535A / GS9065A Pin Descriptions (Continued) Pin Number Name Type Description 24, 25, 26 SS[2:0] Bi-directional When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to which the PLL has locked. When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a selected data rate . SS2 SS1 SS0 DATA RATE SELECTED/FORCED (Mb/s) 0 0 0 143 0 0 1 177 0 1 0 270 0 1 1 360 1 0 0 540 1 0 1 1483.5/1485* *Only applies to the GS1535A. For the GS9065A, when AUTO/MAN is LOW, the pin settings SS[0:2] = 101 will be ignored by the device. 27 ASI/177 Logic Input When set HIGH, the device disables the 177Mb/s data rate in the data rate detection circuit. This prevents a false lock to 177Mb/s when using DVB-ASI. When set LOW, 177Mb/s lock is possible, however, if a 270Mb/s ASI signal is applied, the device could false lock to the 177MHz signal. 28 LD Output Lock Detect. This pin is set HIGH by the device when the PLL is locked. 29 RSVD Reserved Do not connect. 30 VCC_DIG Power Most positive power supply connection for the internal glue logic. Connect to 3.3V. 31 VEE_DIG Power Most negative power supply connection for the internal glue logic. Connect to GND. 33 SD/HD Output GS1535A: This signal will be set LOW by the device when the reclocker has locked to 1.485Gbps or 1.485/1.001Gbps, or when a non-SMPTE standard is applied (i.e. the device is not locked). It will be set HIGH when the reclocker has locked to 143Mbps, 177Mbps, 270Mbps, 360Mbps, or 540Mbps. GS9065A: This signal will go HIGH when the reclocker has locked to the input SD signal. It will be LOW otherwise. 34 KBB Analog Input Controls the loop bandwidth of the PLL. Leave this pin floating for serial reclocking applications. 35, 38 - 42 36 RSVD Reserved Do not connect. DDO_MUTE Logic Input Mutes the DDO/DDO outputs, when not in bypass mode. 31497 - 3 November 2005 7 of 27 GS1535A / GS9065A Data Sheet Table 1-1: GS1535A / GS9065A Pin Descriptions (Continued) Pin Number Name Type Description 43 GND_DRV Passive Recommended connect to GND. 44, 46 DDO, DDO Output Differential Serial Digital Outputs. 45 DDO_VTT Passive Do not connect. NOTE: This pin is not connected internally. Previous external application circuitry from the original GS1535/9065 may remain in order to maintain footprint compatibility. 47 VCC_DDO Power Most positive power supply connection for the DDO/DDO output driver. Connect to 3.3V. 48 VEE_DDO Power Most negative power supply connection for the DDO/DDO output driver. Connect to GND. 50, 51 XTAL_OUT+, XTAL_OUT- Output Differential outputs of the reference oscillator used for monitoring or test purposes. 52, 53 XTAL+, XTAL- Input Reference crystal input. Connect to the GO1535. 54 - 59 RSVD Reserved Do Not Connect. NOTE: These pins are not connected internally. Previous external application circuitry from the original GS1535/9065 may remain in order to maintain footprint compatibility. 60 VEE_CP Power Most negative power supply connection for the internal charge pump. Connect to GND. 61 VCC_CP Power Most positive power supply connection for the internal charge pump. Connect to 3.3V. 62, 63 LF+, LF- Passive 31497 - 3 Loop filter capacitor connection. (CLF = 47nF). November 2005 8 of 27 GS1535A / GS9065A Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Value Supply Voltage +3.6 VDC Input ESD Voltage 2kV Storage Temperature Range -50°C < Ts < 125°C Input Voltage Vcc + 0.5V Operating Temperature Range 0°C to 70°C 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VCC = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Test Levels Supply Voltage VCC Operating Range 3.1 3.3 3.5 V 3 Supply Current ICC TA=25°C – 195 230 mA 1 Power Consumption – TA=25°C – 645 – mW 5 Logic Inputs VIH High 2.0 – – V 3 DDI_SEL[1:0], BYPASS, AUTOBYPASS, AUTO/MAN, ASI/177, DDO_MUTE VIL Low – – 0.8 V 3 Logic Outputs VOH 250uA Load 2.4 – – V 3 VOL 250uA Load – – 0.4 V 3 VIH High 2.0 – – V 3 VIL Low – – 0.8 V 3 VOH High, 250uA Load 2.4 – – V 1 VOL Low, 250uA Load – – 0.4 V 1 VOH High – VCC – V 7 VOL Low – VCC - 0.285 – V 7 – Common Mode 1.65 + (VSID/2) – VCC -(VSID/2) V 1 SD/HD, LD, and LOS Bi-Directional Pins (Manual Mode) SS[2:0], AUTO/MAN = 0 Bi-Directional Pins (Auto Mode) SS[2:0], AUTO/MAN = 1 XTAL_OUT+, XTAL_OUT- Serial Input Voltage 31497 - 3 November 2005 9 of 27 GS1535A / GS9065A Data Sheet Table 2-1: DC Electrical Characteristics (Continued) VCC = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Symbol Conditions Output Voltage, DDO/DDO – Common Mode Min Typ Max Units Test Levels – VCC - (VOD/2) – V 1 TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2 or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VCC = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Test Levels Serial Input Data Rate – GS1535A 143 – 1485 Mb/s 3 – GS9065A 143 – 540 Mb/s 3 – Worst case modulation (e.g. square wave modulation) 0.8 – – UI 1 Serial Input Jitter Tolerance 143, 270, 360, 1485 Mb/s PLL Lock Time Asynchronous t ALOCK – – – 10 ms 6,7 GS1535A PLL Lock Time Synchronous t SLOCK CLF=47nF, SD/HD=0 – – 10 us 6,7 t SLOCK CLF=47nF, SD/HD=1 – – 39 us 6,7 GS9065A PLL Lock Time Synchronous t SLOCK CLF=47nF – – 39 us 6,7 Serial Output Rise/Fall Time (20% - 80%) trDDO 50Ω load (on chip) – 114 – ps 6,7 tfDDO 50Ω load (on chip) – 106 – ps 6,7 Serial Input Swing VSID 100Ω load (on chip) 100 – 800 mVp-p 6,7 Serial Output Swing VOD 100Ω load differential 1400 1600 2200 mVp-p 6,7 31497 - 3 November 2005 10 of 27 GS1535A / GS9065A Data Sheet Table 2-2: AC Electrical Characteristics (Continued) VCC = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Symbol Conditions Serial Output Jitter tOJ KBB = Float PRN, 223-1 Measurement is output jitter that includes input jitter from BERT. Loop Bandwidth Min Typ Max Units Test Levels 143 Mb/s – 0.02 – UI 1 tOJ 177 Mb/s – 0.02 – UI 1 tOJ 270 Mb/s – 0.02 0.09 UI 1 tOJ 360 Mb/s – 0.03 – UI 1 tOJ 540 Mb/s – 0.03 0.09 UI 1 tOJ 1485 Mb/s (GS1535A only) – 0.06 0.13 UI 1 tOJ Bypass – 0.06 0.13 UI 1 BWLOOP 1.485 Gb/s, KBB = FLOAT – 1.75 – MHz 6,7 – 3.2 – MHz 6,7 (GS1535A only) BWLOOP 1.485 Gb/s, KBB = GND, <0.1dB Peaking (GS1535A only) BWLOOP 270 Mb/s, KBB = FLOAT – 520 – KHz 6,7 BWLOOP 270 Mb/s, KBB = GND – 1000 – KHz 6,7 TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2 or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 31497 - 3 November 2005 11 of 27 GS1535A / GS9065A Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-1. The recommended standard Pb reflow profile is shown in Figure 2-2. Temperature 60-150 sec. 20-40 sec. 260˚C 250˚C 3˚C/sec max 217˚C 6˚C/sec max 200˚C 150˚C 25˚C Time 60-180 sec. max 8 min. max Figure 2-1: Maximum Pb-free Solder Reflow Profile (Preferred) 60-150 sec. Temperature 10-20 sec. 230˚C 220˚C 3˚C/sec max 183˚C 6˚C/sec max 150˚C 100˚C 25˚C Time 120 sec. max 6 min. max Figure 2-2: Standard Pb Solder Reflow Profile (Pb-free package) 31497 - 3 November 2005 12 of 27 GS1535A / GS9065A Data Sheet 3. Input / Output Circuits VREF Figure 3-1: DDO_MUTE, BYPASS 8k VREF Figure 3-2: DDI_SEL[1:0], AUTOBYPASS, AUTO/MAN, ASI/177 LF+ LF- Figure 3-3: Loop Filter 31497 - 3 November 2005 13 of 27 GS1535A / GS9065A Data Sheet 250R 250R 10p 5K 5K XTAL+ XTAL- Figure 3-4: Crystal Input 1K 1K XTAL OUT- XTAL OUT+ Figure 3-5: Crystal Output Buffer 50 50 SDO SDO Figure 3-6: Serial Data Outputs 31497 - 3 November 2005 14 of 27 GS1535A / GS9065A Data Sheet V REF KBB 500R Figure 3-7: KBB Figure 3-8: Indicator Outputs: SD/HD, LD 24k vREF SS[2:0] Figure 3-9: Standard Select/Indication Bi-directional Pins 31497 - 3 November 2005 15 of 27 GS1535A / GS9065A Data Sheet DDI[3:0] 50 1k 1k DDI_VTT 50 DDI[3:0] Figure 3-10: Serial Data Inputs 31497 - 3 November 2005 16 of 27 GS1535A / GS9065A Data Sheet 4. Detailed Description The GS1535A/9065A is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The GS1535A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal. The GS9065A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 259M or SMPTE 344M compliant digital video signal. Using the functional block diagram (page 2) as a guide, Slew Rate Phase Lock Loop (S-PLL) on page 17 to Output Mute on page 22 describes each aspect of the GS1535A/9065A in detail. 4.1 Slew Rate Phase Lock Loop (S-PLL) The term “slew” refers to the output phase of the PLL in response to a step change at the input. Linear PLLs have an output phase response characterized by an exponential response whereas an S-PLL’s output is a ramp response (see Figure 4-1). Because of this non-linear response characteristic, traditional small signal analysis is not possible with an S-PLL. PHASE (UI) 0.2 INPUT 0.1 OUTPUT 0.0 SLEW PLL RESPONSE PHASE (UI) 0.2 INPUT 0.1 OUTPUT 0.0 LINEAR (CONVENTIONAL) PLL RESPONSE Figure 4-1: PLL Characteristics 31497 - 3 November 2005 17 of 27 GS1535A / GS9065A Data Sheet The S-PLL offers several advantages over the linear PLL. The Loop Bandwidth of an S-PLL is independent of the transition density of the input data. Pseudo-random data has a transition density of 0.5 verses a pathological signal which has a transition density of 0.05. The loop bandwidth of a linear PLL will change proportionally with this change in transition density. With an S-PLL, the loop bandwidth is defined by the jitter at the data input. This translates to infinite loop bandwidth with a zero jitter input signal. This allows the loop to correct for small variations in the input jitter quickly, resulting in very low output jitter. The loop bandwidth of the GS1535A/9065A’s PLL is defined at 0.2UI of input jitter. The PLL consists of two acquisition loops. First is the Frequency Acquisition (FA) loop. This loop is active when the device is not locked and is used to achieve lock to the supported data rates. Second is the phase acquisition (PA) loop. Once locked, the PA loop tracks the incoming data and makes phased corrections to produce a re-clocked output. 4.2 VCO The internal VCO of the GS1535A/9065A is a ring oscillator. It is trimmed at the time of manufacture to capture all data rates over temperature and operation voltage ranges. Integrated into the VCO is a series of programmable dividers used to achieve all serial data rates, as well as additional dividers for the frequency acquisition loop. 4.3 Charge Pump A common charge pump is used for the PLL of the GS1535A/9065A. During frequency acquisition, the charge pump has two states, “pump-up” and “pump-down,” which is produced by a leading or lagging phase difference between the input and the VCO frequency. During phase acquisition, there are two levels of “pump-up” and two levels of “pump down” produced for leading and lagging phase difference between the input and VCO frequency. This is to allow for greater precision of VCO control. The charge pump produces these signals by holding the integrated frequency information on the external loop-filter capacitor, CLF. The instantaneous frequency information is the result of the current flowing through an internal resistor connected to the loop-filter capacitor. 31497 - 3 November 2005 18 of 27 GS1535A / GS9065A Data Sheet 4.4 Frequency Acquisition Loop — The Phase-Frequency Detector An external crystal of 14.140 MHz is used as a reference to keep the VCO centered at the last known data rate. This allows the device to achieve a fast synchronous lock, especially in cases where a known data rate is interrupted. The crystal reference is also used to clock internal timers and counters. To keep the optimal performance of the reclocker over all operating conditions, the crystal frequency must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is available from GENNUM. The VCO is divided by a selected ratio which is dependant on the input data rate. The resultant is then compared to the crystal frequency. If the divided VCO frequency and the crystal frequency are within 1% of each other, the PLL is considered to be locked to the input data rate. 4.5 Phase Acquisition Loop — The Phase Detector The phase detector is a digital quadrature phase detector. It indicates whether the input data is leading or lagging with respect to a clock that is in phase with the VCO (I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop) is locked, the input data transition is aligned to the falling edge of I-clk and the output data is re-timed on the rising edge of I-clk. During high input jitter conditions (>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the VCO. i-PHASE ALIGNMENT EDGE DATA RE-TIMING EDGE I-clk q-clk q-PHASE ALIGNMENT EDGE INPUT DATA WITH JITTER 0.25UI 0.8UI RE-TIMED OUTPUT DATA Figure 4-2: Phase Detector Characteristics When the PA loop is active, the crystal frequency and the incoming data rate are compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the system jumps to the FA loop. 31497 - 3 November 2005 19 of 27 GS1535A / GS9065A Data Sheet 4.6 4:1 Input Mux The 4:1 input mux allows the connection of four independent streams of video/data. There are four differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be selected via the DDI_SEL[1:0] pins. Table 4-1 shows the input selected for a given state at DDI_SEL[1:0]. Table 4-1: Bit Pattern for Input Select DDI_SEL[1:0] Selected Input 00 DDI0 01 DDI1 10 DDI2 11 DDI3 The DDI inputs are designed to be DC interfaced with the output of the GS1524A/9064A Cable Equalizer. There are on chip 50Ω termination resistors which come to a common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and connect the other end of the capacitor to ground. This terminates the transmission line at the inputs for optimum performance. If only one input pair is used, connect the unused positive inputs to +3.3V and leave the unused negative inputs floating. This helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 Automatic and Manual Data Rate Selection The GS1535A/9065A can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The AUTO/MAN pin selects automatic data rate detection mode (Auto mode) when HIGH and manual data rate selection mode (Manual mode) when LOW. In Auto mode, the SS[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the PLL is locked to (or previously locked to). The "search algorithm" cycles through the data rates and starts over if that data rate is not found (see Figure 4-3). POWER-UP 143 Mb\s 177 Mb\s 270Mb\s 360 Mb\s 1.485Mb\s (GS1535A only) 540 Mb\s Figure 4-3: Data Rate Search Pattern 31497 - 3 November 2005 20 of 27 GS1535A / GS9065A Data Sheet In Manual mode, the SS[2:0] pins become inputs and the data rate can be programmed by the application layer. In this mode, the search algorithm is disabled and the PLL will only lock to the data rate selected. Table 4-2 shows the SS[2:0] pin settings for either the data rate selected (in Manual mode) or the data rate that the PLL has locked to (in Auto mode). Table 4-2: Data Rate Indication/Selection Bit Pattern SS[2:0] Data Rate (Mb/s) 000 143 001 177 010 270 011 360 100 540 101* 1485/1483.5 * This setting only applies to the GS1535A. For the GS9065A, when AUTO/MAN is LOW, the pin settings SS[0:2] = 101 will be ignored by the device. 4.8 Bypass Mode In Bypass mode, the GS1535A/9065A passes the data at the inputs directly to the outputs. There are two pins that control the bypass function: BYPASS and AUTOBYPASS. When BYPASS is set HIGH by the application layer, the GS1535A/9065A will be in Bypass mode. When AUTOBYPASS is set HIGH by the application layer, the GS1535A/9065A will be configured to enter Bypass mode only when the PLL has not locked to a data rate. When BYPASS is set HIGH, AUTOBYPASS will be ignored. When the PLL is not locked, and both BYPASS and AUTOBYPASS are set LOW, the serial digital output DDO/DDO will produce invalid data. 4.9 DVB-ASI Operation The GS1535A/9065A will also re-clock DVB-ASI at 270 Mb/s. When reclocking DVB-ASI data set the ASI/177 pin HIGH to prevent a false lock to 177Mb/s. If ASI/177 is not set HIGH, a false lock may occur since there is a harmonic present in idle patterns (K28.5) which is very close the 177 Mb/s data rate (EIC 1179). Note that setting the ASI/177 pin HIGH will disable the 177 Mb/s search when the device is in Auto mode, consequently the GS1535A/9065A will not lock to that data rate. 31497 - 3 November 2005 21 of 27 GS1535A / GS9065A Data Sheet 4.10 Lock The LOCK DETECT signal, LD, is an active high output which indicates when the PLL is locked. The internal lock logic of the GS1535A/9065A includes a system which monitors the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect harmonic lock. 4.11 Output Drivers The device’s serial digital data outputs (DDO/DDO) have a nominal voltage of 800mv single ended or 1600mV differential when terminated into a 50Ω load. 4.12 Output Mute The DDO_MUTE pin is provided to allow muting of the re-timed output. When the PLL is locked and the device is reclocking, setting DDO_MUTE = LOW will force the serial digital outputs DDO/DDO to mute. However, if the GS1535A/9065A is in Bypass mode, (AUTOBYPASS = HIGH and/or BYPASS = HIGH), DDO_MUTE will have no effect on the output. 31497 - 3 November 2005 22 of 27 GS1535A / GS9065A Data Sheet 5. Typical Application Circuits No te : P in s 4 5 , 5 4 , 5 5 , a n d 57 are not connected i nternal l y. A ny previ ous ci rcui try from th e o r ig in a l GS 1 5 3 5 m a y remai n connected i n order to mai ntai n footpri nt compati bi l i ty. GO1535 (14.140MH z) 47n 3 .3 V 100 10n 3 49 GN D 53 X TAL- 55 54 NC NC 56 NC 57 NC 58 NC NC 61 60 59 VEE_CP 62 5 DDI1 DDO 6 DDI1 _V T GND 7 DDI1 8 GND 9 DDI2 R SVD DDI2 _V T R SVD DDI2 R SVD 46 45 Zo = 50 DATA OUTPUT 44 43 42 39 38 37 36 S D O_ M U TE 35 34 DDI3 KBB 3.3V DDI_S E L 0 DDI_S E L 1 S D /H D GND VEE_D IG 33 32 VC C _D IG 31 30 LD A SI/177 R SVD 29 28 SS2 10n 27 SS1 26 SS0 25 VC C _VC O VEE_VC 0 24 17 SD/HD 23 GND D D I_SEL0 16 R SVD DDI3 _V T 22 15 GND D D O_MU TE A U TO/MA N 10n 3.3V 40 DDI3 21 14 10n 47 R SVD GND A U TOB YPA SS 13 48 41 GS 1 5 3 5 A 20 12 R SVD B YPA SS 10 10n Z o = 50 VCC_CP D D O_VTT 11 D A TA INPUT 3 63 GND 10n Z o = 50 LF- DDO D D I_SEL1 D A TA INPUT 2 Z o = 50 VC C _D D O DDI0 4 D AT A INPUT 1 VEE_D D O DDI0 _V T 19 Z o = 50 DDI0 18 D ATA INPUT 0 2 X TAL+ 5 2 51 X TAL_ OU T50 X TAL_ OU T+ 1 LF+ GND 64 10n 10n 3.3V AS I_1 7 7 LD Note: All resistors in ohms and all capacitors in Farads. Figure 5-1: GS1535A Typical Application Circuit 31497 - 3 November 2005 23 of 27 GS1535A / GS9065A Data Sheet Note: Pins 45, 54, 55, and 5 7 a r e n o t c o n n e c t e d in t e r n a lly. A n y p r e vio u s c ir c u it r y f r o m the original GS9065 may r e ma in c o n n e c t e d in o r d e r t o ma in t a in f o o t p r in t c o mp a t ib ilit y. GO1 5 3 5 ( 1 4 . 1 4 0 MH z) 47n 3.3V 100 10n 3 49 G ND 53 X TA L- 55 54 NC NC 56 NC 57 NC 58 NC NC 61 60 59 V E E _ CP DDI1 DDO 6 DDI1_ VT GN D 7 DDI1 8 GND RSVD GND GN D DDI3 D D O_MU T E RSVD DDI3_ VT 46 45 Zo = 50 DATA OUTPUT 44 43 42 39 38 37 36 SDO _ MUTE 35 34 DDI3 KBB 3.3V DDI_ SEL0 DDI_ SEL1 SD GN D V E E _D I G 33 32 V C C _D I G 31 30 LD ASI/177 RSVD 29 28 SS2 10n 27 SS1 26 SS0 25 V C C _V C O V E E _V C 0 24 17 SD 23 GND D D I _S E L 0 16 DDI2 22 15 RSVD A U T O/ MA N 10n 3.3V 40 DDI2_ VT 21 14 1 0n 47 RSVD RSVD A U T OB Y P A S S 13 48 41 GS9065A DDI2 20 12 RSVD BYPASS 10 10n Zo = 50 62 5 11 DAT A IN PU T 3 V CC_ CP D D O_V T T 10n Z o = 50 63 GND 9 DAT A IN PU T 2 LF- DDO D D I _S E L 1 Zo = 50 V C C _D D O DDI0 4 DA T A IN PU T 1 V E E _D D O DDI0_ VT 19 Zo = 50 DDI0 18 DAT A IN PU T 0 2 X TA L+ 52 51 X TA L_ O UT50 X TA L_ O UT+ 1 LF+ G ND 64 10n 10n 3.3V ASI_ 177 LD Note: All resistors in ohms and all capacitors in Farads. Figure 5-2: GS9065A Typical Application Circuit 31497 - 3 November 2005 24 of 27 GS1535A / GS9065A Data Sheet 6. Package & Ordering Information 6.1 Package Dimensions Table X 0 0 0 0 NOTE: Diagram shown is representative only. Table X is fixed for all pin sizes, and Table Y is specific to the 64-pin package. Table Y SYMBOL 64L MILLIMETER b MIN NOM MAX 0.17 0.20 0.27 I NCH MIN NO M MAX 0. 007 0. 008 0. 011 e 0.50 BSC D2 7.50 0. 295 E2 7.50 0. 295 0. 020 B S C TOLERANCES OF FORM AND POSITION 31497 - 3 November 2005 aaa 0.20 0. 008 bbb 0.20 0. 008 ccc 0.08 0. 003 25 of 27 GS1535A / GS9065A Data Sheet 6.2 Packaging Data Parameter Value Package Type 10mm x 10mm 64-pin LQFP Package Drawing Reference ASE 64-06-280-1384 Moisture Saturation Level 3 Junction to Case Thermal Resistance, θj-c 18.1°C/W Junction to Air Thermal Resistance, θj-a (at zero airflow) 47.8°C/W Psi 1.1°C/W Pb-free and RoHS Compliant Yes 6.3 Ordering Information Part Number Package Temperature Range GS1535A GS1535ACFUE3 Pb-free 64-pin LQFP 0°C to 70°C GS9065A GS9065ACFUE3 Pb-free 64-pin LQFP 0°C to 70°C 31497 - 3 November 2005 26 of 27 GS1535A / GS9065A Data Sheet 7. Revision History Version ECR PCN Date Changes and/or Modifications A 133493 – April 2004 New Document. 0 134398 – September 2004 Convert to Preliminary Data Sheet. Updated pin descriptions. Updated Electrical Characteristics. Added Packaging Data section detailing package information. Corrected minor typing errors in pin description table and typical application circuits. 1 135364 – February 2005 Corrected block diagrams and pin description table to reflect mute functionality of the device. 2 136782 – May 2005 Removed all references to the Serial Clock Output. Updated all ‘Green’ references to ‘RoHS Compliant’. Updated TTL input circuit and Standard Selection/Indication circuit diagrams. Corrected minor typing errors in electrical characteristics tables. 3 138505 37280 November 2005 Converted to Data Sheet. Revised maximum output swing to 2200 mV in AC Electrical Characteristics on page 10. CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2004 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 31497 - 3 November 2005 27 of 27 27