ITF87072DK8T
TM
Data Sheet
6A, 20V, 0.037 Ohm, Dual P-Channel,
2.5V Specified Power MOSFET
Packaging
SO8 (JEDEC MS-012AA)
BRANDING DASH
5
1
2
3
March 2000
File Number
4812.3
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.037Ω, VGS = −4.5V
- rDS(ON) = 0.039Ω, VGS = −4.0V
- rDS(ON) = 0.059Ω, VGS = −2.5V
• Gate to Source Protection Diode
• Simulation Models
- Temperature Compensated PSPICE™ and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
4
• Transient Thermal Impedance Curve vs Board Mounting
Area
Symbol
DRAIN1(8)
DRAIN1(7)
• Switching Time vs RGS Curve
Ordering Information
SOURCE1(1)
GATE1(2)
PART NUMBER
DRAIN2(6)
ITF87072DK8T
PACKAGE
SO8
BRAND
87072
DRAIN2(5)
NOTE: When ordering, use the entire part number. ITF87072DK8T
is available only in tape and reel.
SOURCE2(3)
GATE2(4)
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TA = 25oC, VGS = -4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 25oC, VGS = -4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 100oC, VGS = -4.0V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA = 100oC, VGS = -2.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Technical Brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
ITF87072DK8T
-20
-20
±12
UNITS
V
V
V
6.0
6.0
1.5
1.5
Figure 4
2.5
20
-55 to 150
A
A
A
A
W
mW/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.14 in2 (90.3 mm2) copper pad at 1 second.
3. 228oC/W measured using FR-4 board with 0.006 in2 (3.9 mm2) copper pad at 1000 second.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
SABER© is a Copyright of Analogy Inc. , PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
ITF87072DK8T
TA = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-20
-
-
V
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V Figure 11
Zero Gate Voltage Drain Current
IDSS
VDS = -20V, VGS = 0V
-
-
-1
µA
Gate to Source Leakage Current
IGSS
VGS = ±12V
-
-
±10
uA
-0.5
-
-1.5
V
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA Figure 10
Drain to Source On Resistance
rDS(ON)
ID = 6.0A, VGS = -4.5V Figures 8, 9
-
0.028
0.037
Ω
ID = 1.5A, VGS = -4.0V Figure 8
-
0.030
0.039
Ω
ID = 1.5A, VGS = -2.5V Figure 8
-
0.044
0.059
Ω
Pad Area = 0.14 in2 (90.3 mm2) (Note 2)
-
-
50
oC/W
Pad Area = 0.027 in2 (17.4 mm2) Figure 20
-
-
191
oC/W
Pad Area = 0.006 in2 (3.9 mm2) Figure 20
-
-
228
oC/W
VDD = -10V, ID = 1.5A
VGS = -2.5V,
RGS = 10Ω
Figures 14, 18, 19
-
13
-
ns
-
85
-
ns
-
55
-
ns
-
62
-
ns
-
9
-
ns
-
72
-
ns
-
81
-
ns
-
82
-
ns
-
12
-
nC
-
6
-
nC
-
0.7
-
nC
THERMAL SPECIFICATIONS
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = -2.5V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
SWITCHING SPECIFICATIONS (VGS = -4.5V)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
VDD = -10V, ID = 6.0A
VGS = -4.5V,
RGS = 10Ω
Figures 15, 18, 19
tf
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to -4.5V
Gate Charge at -2V
Qg(-2)
VGS = 0V to -2V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -0.5V
VDD = -10V,
ID = 6.0A,
Ig(REF) = 1.0mA
Figures 13, 16, 17
Gate to Source Gate Charge
Qgs
-
2.5
-
nC
Gate to Drain “Miller” Charge
Qgd
-
3.5
-
nC
-
1200
-
pF
-
325
-
pF
-
130
-
pF
MIN
TYP
MAX
UNITS
ISD = -6.0A
-
-0.85
-
V
trr
ISD = -6.0A, dISD/dt = 100A/µs
-
24
-
ns
QRR
ISD = -6.0A, dISD/dt = 100A/µs
-
17
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = -10V, VGS = 0V,
f = 1MHz
Figure 12
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
ITF87072DK8T
Typical Performance Curves
-8
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
-6
VGS = -4.5V, RθJA = 50oC/W
-4
-2
0.2
0
VGS = -2.5V, RθJA = 228oC/W
0
0
25
50
75
100
125
25
150
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
2
THERMAL IMPEDANCE
ZθJA, NORMALIZED
1
0.1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 228oC/W
PDM
0.01
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
103
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-400
IDM, PEAK CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
RθJA = 228oC/W
-100
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
150 - TA
125
VGS = -2.5V
-10
VGS = -4.5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-1
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
101
102
103
ITF87072DK8T
Typical Performance Curves
(Continued)
-200
ID, DRAIN CURRENT (A)
-100
ID, DRAIN CURRENT (A)
-25
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
RθJA = 228oC/W
100µs
-10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
-1
-1
-50
-10
-20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
-15
-10
TJ = 150oC
-5
TJ = 25oC
-0
-1.0
-1.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
-2.5
-3.0
FIGURE 6. TRANSFER CHARACTERISTICS
80
TA = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID, DRAIN CURRENT (A)
-2.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
-25
TJ = -55oC
-20
VGS = -4.5V
VGS = -2.5V
-15
VGS = -3V
-10
VGS = -2V
-5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = -1.5A
60
ID = -6A
40
VGS = -1.5V
20
-1
0
0
-0.5
-1.0
-1.5
-2.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
-3
-4
-5
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
1.4
1.6
VGS = VDS, ID = -250µA
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.4
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
-2
VGS, GATE TO SOURCE VOLTAGE (V)
1.2
VGS = -4.5V, ID = -6A
1.0
0.8
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
160
1.2
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
ITF87072DK8T
Typical Performance Curves
(Continued)
2000
1.2
CISS = CGS + CGD
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = -250µA
1.1
1.0
0.9
-80
-40
0
40
80
120
1000
COSS ≅ CDS + CGD
CRSS = CGD
100
-0.1
160
VGS = 0V, f = 1MHz
-1
TJ , JUNCTION TEMPERATURE (oC)
-20
-10
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VDD = -10V
200
-4
VGS = -2.5V, VDD = -10V, ID = -1.5A
tr
SWITCHING TIME (ns)
VGS , GATE TO SOURCE VOLTAGE (V)
-5
-3
-2
WAVEFORMS IN
DESCENDING ORDER:
ID = -6A
ID = -1.5A
-1
150
100
tf
td(OFF)
50
td(ON)
0
0
3
6
9
12
15
0
Qg, GATE CHARGE (nC)
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
200
SWITCHING TIME (ns)
VGS = -4.5V, VDD = -10V, ID = -6A
td(OFF)
150
tf
100
tr
50
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
50
50
ITF87072DK8T
Test Circuits and Waveforms
Qgs
VDS
RL
Qgd
VDS
Qg(TH)
0
VGS= -0.5V
VGS
VGS= -2V
-VGS
VDD
Qg(-2)
+
VGS= -4.5V
VDD
DUT
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
tON
tOFF
td(OFF)
td(ON)
RL
VDS
-
VDS
0V
DUT
0
90%
90%
10%
-VGS
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
6
10%
10%
+
VGS
RGS
tf
tr
0
50%
PULSE WIDTH
90%
FIGURE 19. SWITCHING TIME WAVEFORM
ITF87072DK8T
Thermal Resistance vs Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient temperature,
TA (oC), and thermal resistance RθJA (oC/W) must be
reviewed to ensure that TJM is never exceeded. Equation 1
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
RθJA = 103.2 - 24.3
250
Rθβ, RθJA (oC/W)
( T JM – T A )
P DM = ------------------------------R θJA
300
* ln(AREA)
228 oC/W - 0.006in2
200
191 oC/W - 0.027in2
150
100
(EQ. 1)
50
Rθβ = 46.4 - 21.7 * ln(AREA)
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
0
0.001
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 20 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
1
While Equation 2 describes the thermal resistance of a
single die, several devices are offered with two die in the
SO8 package. The dual die SO8 package introduces an
additional thermal component, thermal coupling resistance,
Rθβ. Equation 3 describes Rθβ as a function of the top
copper mounting pad area.
Rθβ
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
0.1
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD
AREA
4. The use of thermal vias.
5. Air flow and board orientation.
0.01
AREA, TOP COPPER AREA (in2) PER DIE
= 46.4 – 21.7 ×
ln ( Area )
(EQ. 3)
The thermal coupling resistance vs copper area is also
graphically depicted in Figure 20. It is important to note the
thermal resistance (RθJA) and thermal coupling resistance
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
RθJA1 = RθJA2 = 159oC/W
Rθβ1 = Rθβ2 = 97oC/W
TJ1 and TJ2 define the junction temperature of the
respective die. Similarly, P1 and P2 define the power
dissipated in each die. The steady state junction
temperature can be calculated using Equation 4 for die 1
and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70oC and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calculate TJ1 and Equation 5 to calculate
TJ2.
.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
R θJA = 103.2 – 24.3 ×
ln ( Area )
(EQ. 2)
T J1 = P 1 R θJA + P 2 R θβ + T A
TJ1 = (0 Watts)(159˚C/W) + (0.5 Watts)(97˚C/W) + 70˚C
TJ1 = 119˚C
T J2 = P 2 R θJA + P 1 R θβ + T A
(EQ. 5)
TJ2 = (0.5 Watts)(159˚C/W) + (0 Watts)(97˚C/W) + 70˚C
TJ2 = 150˚C
7
(EQ. 4)
ITF87072DK8T
The transient thermal impedance (ZθJA) is also affected by
varied top copper board area. Figure 21 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
ZθJA, THERMAL
IMPEDANCE (oC/W)
160
120
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
COPPER BOARD AREA - DESCENDING ORDER
0.020 in2
0.140 in2
0.257 in2
0.380 in2
0.493 in2
80
40
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 21. THERMAL RESISTANCE vs MOUNTING PAD AREA
8
102
103
ITF87072DK8T
PSPICE Electrical Model
.SUBCKT ITF87072DK8 2 1 3 ;
REV Dec 1999
CA 12 8 1.15e-9
CB 15 14 1.2e-9
CIN 6 8 1.09e-9
LDRAIN
ESG
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 6 DPLCAPMOD
DRAIN
2
5
+
8
6
RLDRAIN
RSLC1
51
+
RSLC2
5
51
EBREAK 5 11 17 18 -29.6
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
EBREAK
-
ESLC
9
-
20
DBODY
RDRAIN
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
21
16
MWEAK
6
18 +
22
DBREAK
MSTRO
DESD1
91
DESD2
11
MMED
RLGATE
LDRAIN 2 5 1.0e-9
LGATE 1 9 3.6e-9
LSOURCE 3 7 4.3e-9
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.8e-3
RGATE 9 20 16.1
RLDRAIN 2 5 10
RLGATE 1 9 36
RLSOURCE 3 7 43
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.1e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
-
IT
14
+
+
S1A
S1B
S2A
S2B
+
17
18
50
DPLCAP
LGATE
IT 8 17 1
-
10
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),2.1))}
.MODEL DBODYMOD D (IS = 1.7e-10 IKF = 3 N = 1.18 RS = 1.05e-2 TRS1 = 1.75e-3 TRS2 = 5.08e-6 CJO = 6e-10 TT = 5.1e-9 M = 0.47)
.MODEL DBREAKMOD D (RS = 4e-1 TRS1 = 1e-3 TRS2 = -2e-5)
.MODEL DESD1MOD D (BV = 9.5 TBV1 = -2.9e-3 N = 12 RS = 35)
.MODEL DESD2MOD D (BV = 10.2 TBV1 = -2.5e-3 N = 13 RS = 35)
.MODEL DPLCAPMOD D (CJO = 4.7e-10 IS = 1e-30 N = 10 M = 0.4 VJ = 0.45)
.MODEL MMEDMOD PMOS (VTO = -1.15 KP = 23 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 16.1 RS = 0.1)
.MODEL MSTROMOD PMOS (VTO = -1.35 KP = 30 LAMBDA = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD PMOS (VTO = -0.82 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 161 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9e-4 TC2 = 1e-6)
.MODEL RDRAINMOD RES (TC1 = 1.2e-2 TC2 = 1.2e-6)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 5e-6)
.MODEL RVTHRESMOD RES (TC1 = 1.3e-3 TC2 = 2.3e-6)
.MODEL RVTEMPMOD RES (TC1 = -4e-4 TC2 = -1e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = 2.5 VOFF= 1.5)
VON = 1.5 VOFF= 2.5)
VON = 0.75 VOFF= -0.5)
VON = -0.5 VOFF= 0.75)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9
ITF87072DK8T
SABER Electrical Model
REV Dec 1999
template itf87072dk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.7e-10, ikf = 3, nl = 1.18, cjo = 6e-10, tt = 5.1e-9, m = 0.47, rs = 1.05e-2, trs1 = 1.75e-3, trs2 = 5.08e-6)
dp..model dbreakmod = (rs = 4e-1, trs1 = 1e-3, trs2 = -2e-5)
dp..model desd1mod = (bv = 9.5, tbv1 = -2.9e-3, nl = 12, rs = 35)
dp..model desd2mod = (bv = 10.2, tb1 = -2.5e-3, nl = 13, rs = 35)
dp..model dplcapmod = (cjo = 4.7e-10, isl = 10e-30, nl = 10, m = 0.4, vj = 0.45)
m..model mmedmod = (type=_p, vto = -1.15, kp = 23, is = 1e-30, tox = 1, rs = 0.1)
m..model mstrongmod = (type=_p, vto = -1.35, kp = 30, lambda = 0.05, is = 1e-30, tox = 1)
m..model mweakmod = (type=_p, vto = -0.82, kp = 0.06, is = 1e-30, tox = 1, rs = 0.1)
LDRAIN
ESG
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 2.5, voff = 1.5)
5
- 8 +
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 1.5, voff = 2.5)
6
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.75, voff = -0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.75)
RLDRAIN
+
10
RSLC1
51
c.ca n12 n8 = 1.15e-9
c.cb n15 n14 = 1.2e-9
c.cin n6 n8 = 1.09e-9
DRAIN
2
EBREAK 17
18
RSLC2
-
ISCL
11
dp.dbody n5 n7 = model=dbodymod
dp.dbreak n7 n11 = model=dbreakmod
dp.desd1 n91 n9 = model=desd1mod
dp.desd2 n91 n7 = model=desd2mod
dp.dplcap n10 n6 = model=dplcapmod
DBREAK
RDRAIN
LGATE
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 3.6e-9
l.lsource n3 n7 = 4.3e-9
RLGATE
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
i.it n8 n17 = 1
50
DPLCAP
-
20
9
16
21
MWEAK
6
18 +
22
MSTRO
DESD1
LSOURCE
CIN
91
8
DESD2
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9e-4, tc2 = 1e-6
res.rdrain n50 n16 = 5.8e-3, tc1 = 1.2e-2, tc2 = 1.2e-6
res.rgate n9 n20 = 16.1
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 36
res.rlsource n3 n7 = 43
res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.1e-2, tc1 = 0, tc2 = 5e-6
res.rvtemp n18 n19 = 1, tc1 = -4e-4, tc2 = -1e-7
res.rvthres n22 n8 = 1, tc1 = 1.3e-3, tc2 = 2.3e-6
DBODY
MMED
7
RSOURCE
RLSOURCE
S1A
12
CA
S2A
RBREAK
13
8
15
14
13
S1B
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n5 n11 n17 n18 = -29.6
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n5 n10 n8 n6 = 1
spe.evtemp n6 n20 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/100))** 2.1))
}
}
10
SOURCE
3
ITF87072DK8T
SPICE Thermal Model
REV April 1999
ITF87072DK8
Copper Area = 0.02 in2
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 9.0e-2
CTHERM7 3 2 4.0e-1
CTHERM8 2 tl 1.4
th
JUNCTION
CTHERM1
RTHERM1
8
CTHERM2
RTHERM2
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 39
RTHERM7 3 2 42
RTHERM8 2 tl 48
7
CTHERM3
RTHERM3
6
RTHERM4
CTHERM4
5
SABER Thermal Model
Copper Area = 0.02 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 9.0e-2
ctherm.ctherm7 3 2 = 4.0e-1
ctherm.ctherm8 2 tl = 1.4
CTHERM5
RTHERM5
4
RTHERM6
CTHERM6
3
CTHERM7
RTHERM7
2
rtherm.rtherm1 th 8 = 3.5e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 2
rtherm.rtherm4 6 5 = 8
rtherm.rtherm5 5 4 = 18
rtherm.rtherm6 4 3 = 39
rtherm.rtherm7 3 2 = 42
rtherm.rtherm8 2 tl = 48
}
CTHERM8
RTHERM8
tl
AMBIENT
TABLE 1. THERMAL MODELS
0.02 in2
0.14 in2
0.257 in2
0.38 in2
0.493 in2
CTHERM6
9.0e-2
1.3e-1
1.5e-1
1.5e-1
1.5e-1
CTHERM7
4.0e-1
6.0e-1
4.5e-1
6.5e-1
7.5e-1
CTHERM8
1.4
2.5
2.2
3
3
RTHERM6
39
26
20
20
20
RTHERM7
42
32
31
29
23
RTHERM8
48
35
38
31
25
COMPONENT
11
ITF87072DK8T
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E
E1
INCHES
A
A1
1
e
2
6
D
5
b
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.004
0.0098
0.10
0.25
-
b
0.013
0.020
0.33
0.51
-
c
0.0075
0.0098
0.19
0.25
-
D
0.189
0.1968
4.80
5.00
2
E
0.2284
0.244
5.80
6.20
-
E1
0.1497
0.1574
3.80
4.00
3
e
h x 45o
c
0.004 IN
0.10 mm
L
0o-8o
0.060
1.52
0.050
1.27
0.024
0.6
0.155
4.0
0.275
7.0
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
MILLIMETERS
0.050 BSC
1.27 BSC
-
H
0.0099
0.0196
0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
4.0mm
2.0mm
USER DIRECTION OF FEED
1.75mm
CL
MS-012AA
12mm
12mm TAPE AND REEL
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
COVER TAPE
13mm
330mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
12
50mm
12.4mm
ITF87072DK8T
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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Intersil Corporation
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TEL: (321) 724-7000
FAX: (321) 724-7240
13
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