8XC196MD PROCESS INFORMATION Table 2. 8XC196MD Memory Map This device is manufactured on PX29.5, a CHMOS III-E process. Additional process and reliability information is available in the Intel® Quality System Handbook. Description External Memory or I/O Address 0FFFFH 06000H Internal ROM/EPROM or External Memory (Determined by EA) 5FFFH 2080H Reserved. Must contain FFH. (Note 5) 207FH 205EH PTS Vectors 205DH 2040H Upper Interrupt Vectors 203FH 2030H ROM/EPROM Security Key 202FH 2020H Reserved. Must contain FFH. (Note 5) 201FH 201CH Reserved. Must Contain 20H (Note 5) 201BH NOTE: EPROMs are available as One Time Programmable (OTPROM) only. CCB1 201AH Reserved. Must Contain 20H (Note 5) 2019H Figure 2. The 8XC196MD Family Nomenclature CCB0 2018H Reserved. Must contain FFH. (Note 5) 2017H 2014H Lower Interrupt Vectors 2013H 2000H SFR’s 1FFFH 1F00H External Memory 1EFFH 0200H 488 Bytes Register RAM (Note 1) 01FFH 0018H CPU SFR’s (Notes 1. 3) 0017H 0000H x x 272323 – 2 Table 1. Thermal Characteristics Package Type θ ja θ jc PLCC 35°C/W 13 °C/W QFP 56°C/W 12 °C/W All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology. NOTES: 1. Code executed in locations 0000H to 01FFH will be forced external. 2. Reserved memory locations must contain 0FFH unless noted. 3. Reserved SFR bit locations must contain 0. 4. Refer to 8XC196MC for SFR descriptions. 5. WARNING: Reserved memory locations must not be written or read. The contents and/or function of these locations may change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly. 3 8XC196MD 8XC196MC AND 8XC196MD DIFFERENCES PIÐMASK and PIÐPEND Registers INTÐMASK1/INTÐPEND1 Registers There are some differences between the 8XC196MC and 8XC196MD INTÐMASK1/ INTÐPEND1 registers. The 8XC196MD interrupt mask and pending registers are shown below. Notice that the CAPCOM5, COMP4, and CAPCOM4 bits are reserved bits on the 8XC196MC. The PI bit of the INTÐPEND1 register will be set when a Waveform Generator or Compare Module 5 event occurs and the corresponding bit in the PIÐMASK register is set. The PI interrupt vector can be taken when the PI bit in the INTÐMASK1 register is set. The 8XC196MC User’s Manual should be referenced for details about the interrupts. INTÐMASK1 (0031H) and INTÐPEND1 (0012H) 7 6 5 RSV EXTINT PI 4 3 2 1 The PIÐMASK/PIÐPEND registers contain the bits for the Compare Module 5 (COMP5) Waveform Generator (WG), Timer 1 Overflow (TFI), and Timer 2 Overflow (TF2) mask/status flag. The diagram below shows the registers. Notice that the COMP5 bit is a reserved bit on the 8XC196MC. The 8XC196MC User’s Manual should be referenced for details about the Waveform Generator, Compare Modules, and Timers. PIÐMASK (1FBEH) and PIÐPEND (1FBCH, Read Only) 7 6 5 4 3 2 1 0 RSV COMP5* RSV WG RSV TF2 RSV TF1 RSV e RESERVED BIT. MUST WRITE AS 0, READ AS 1. * e THIS BIT RESERVED ON 8XC196MC. Figure 5. Peripheral Interrupt Mask and Status Registers 0 CAPCOM5* COMP4* CAPCOM4* COMP3 CAPCOM3 RSV e RESERVED BIT. MUST WRITE AS 0 * e THIS BIT RESERVED ON 8XC196MC. Figure 3. Interrupt Mask and Status Registers The PI bit in the INTÐPEND1 register is set if a Waveform Generator event or Compare Module 5 event occurs and the corresponding PIÐMASK bit is set. For either of these events to cause an interrupt, the PI bit in the INTÐMASK1 register and the corresponding event bit in the PIÐMASK register must be set. PTSSRV and PTSSEL Register Similarly, there are differences between 8XC196MC and 8XC196MD PTS registers. The 8XC196MD PTS registers are shown below. Notice the CAPCOM5, COMP4, and CAPCOM4 bits are reserved bits on the 8XC196MC. The PI bit in the PTSSRV will be set when a Waveform Generator or Compare Module 5 end of PTS interrupt occurs and the corresponding bit in the PIÐMASK register is set. The PI PTS vector can be used when the PI bit in the PTSSEL register is set. The 8XC196MC User’s Manual should be referenced for details about the PTS. PTSSEL (0004H) and PTSSRV (0006H) 15 14 13 RSV EXTINT PI 7 6 12 11 10 9 8 CAPCOM5* COMP4* CAPCOM4* COMP3 CAPCOM3 5 4 3 2 1 0 COMP2 CAPCOM2 COMP1 CAPCOM1 COMP0 CAPCOM0 ADÐDONE TOVF RSV e RESERVED BIT. MUST WRITE AS 0 * e THIS BIT RESERVED ON 8XC196MC. Figure 4. PTS Select and Service Registers 4 Similarly, the TOVF bit in the INTÐPEND register is set if Timer 1 or Timer 2 overflow and the corresponding bit in the PIÐMASK register is set. For either of these two events to cause an interrupt, the TOVF bit in the INTÐMASK register and the corresponding event bit in the PIÐMASK must be set. Upon a PI and/or a TOVF interrupt, it may be necessary to check if the Compare Module 5, the Waveform Generator, Timer 1, or Timer 2 event caused the interrupt. The PIÐPEND will give this information. However, it should be noted that reading the PIÐPEND register will clear the register. So the individual bits in the PIÐPEND register must be read by loading PIÐPEND into another ‘‘shadow’’ register, then checking the ‘‘shadow’’ register to see what event occurred. 8XC196MD Table 3. Interrupt Sources, Vectors and Priorities Interrupt Service PTS Service Interrupt Source Symbol Name Vector Priority Name Vector Priority Capture/Compare5 CAPCOMP5 INT12 2038H 12 PTS12 2058H 27 COMP4 INT11 2036H 11 PTS11 2056H 26 CAPCOMP4 INT10 2034H 10 PTS10 2054H 25 Compare4 Capture/Compare4 Interrupt and PTS Vectors Port 7 The 8XC196MD has three new interrupt and PTS vectors which are Capture/Compare5, Compare 4, and Capture/Compare4. Table 3 shows these interrupt vectors and priorities. These are shown as reserved vectors in the 8XC196MC User’s Manual. Port 7 is an additional bidirectional port that was not available on the 8XC196MC device. Port 7 can be used as I/O or some of the pins have special functions. The pins are listed below followed by their special functions. Table 4. Port 7 Special Function Pins Frequency Generator The Frequency Generator (FG) Peripheral which was not available on the 8XC196MC device, is available on the 8XC196MD device. The FG outputs a programmable-frequency 50% duty cycle waveform on the FREQOUT pin (P7.7). There are two 8-bit registers which control the FG peripheral: Ð Frequency Generator Control Register (FGÐCON) at 1FB8h Ð Frequency Generator Period Count Register (FGÐCOUNT) at 1FBAh. The FGÐCON can be read or written. This register is loaded with a value which determines the number of counts necessary for toggling the output. The following equation should be used to calculate the FGÐCON value: FGÐCON value e FXTAL b1 16 * (FG Frequency) Pin Special Function P7.0 CAPCOMP4 P7.1 CAPCOMP5 P7.2 CAPCOMP4 P7.3 CAPCOMP5 P7.4 P7.5 P7.6 P7.7 FREQOUT The special functions of the pins are selected in the Port 7 SFRs. The Port 2 I/O Port section of the 8XC196MC User’s Manual can be referenced when setting up the Port 7 SFRs. Port 7 SFRs are located in the following locations: Table 5. Port 7 Special Function Registers where FG Frequency is from 4 kHz to 1 MHz. The FGÐCOUNT is loaded with the FGÐCON register value. The FGÐCOUNT register is decremented every eighth state time. When it reaches 00h, the FGÐCOUNT register will send a signal to toggle the output pin and reload the FGÐCOUNT register with the value in the FGÐCON register. The FGÐCOUNT can only be read, not written. SFR Address P7ÐMODE 1FD1h P7ÐDIR 1FD3h P7ÐREG 1FD5h P7ÐPIN 1FD7h The FREQOUT pin (P7.7) must be configured for a special function to use it for the Frequency Generator feature. 5 8XC196MD Port 1 There are three additional Port 1 input pins (P1.5 – P1.7) that were not available on the 8XC196MC. These pins are listed below followed by their function: Table 6. New 8XC196MD Port 1 Pins 6 Pin Description P1.5 Digital or Analog Input P1.6 Digital Input P1.7 Digital Input NOTE: P1.5 was a VSS pin on the 8XC196MC device. If P1.5 and P1.6 are not being used these pins can remain connected to VSS. 8XC196MD 272323 – 3 NOTE: NC means No Connect. Do not connect these pins. Figure 6. 84-Lead PLCC Package 7 8XC196MD 272323 – 4 Figure 7. 80-Lead Shrink EIAJQFP (Quad Flat Pack) 8 8XC196MD PIN DESCRIPTIONS (Alphabetically Ordered) Symbol Function ACH0–ACH13 (P0.0–P0.7, P1.0–P1.5) Analog inputs to the on-chip A/D converter. ACH0 – 7 share the input pins with P0.0–7 and ACH8 – 13 share pins with P1.0 – 5. If the A/D is not used, the port pins can be used as standard input ports. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. ALE/ADV(P5.0) Address Latch Enable or Address Valid output, as selected by CCR. Both options allow a latch to demultiplex the address/data bus on the signal’s falling edge. When the pin is ADV, it goes inactive (high) at the end of the bus cycle. ALE/ADV is active only during external memory accesses. Can be used as standard I/O when not used as ALE/ADV. BHE/WRH (P5.5) Byte High Enable or Write High output, as selected by the CCR. BHE will go low for external writes to the high byte of the data bus. WRH will go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. BUSWIDTH (P5.7) Input for bus width selection. If CCR bits 1 and 2 e 1, this pin dynamically controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an 8-bit cycle occurs. If it is high, a 16-bit cycle occurs. This pin can be used as standard I/O when not used as BUSWIDTH. CAPCOMP0–CAPCOMP5 (P2.0–P2.3, P7.0–P7.1) The EPA Capture/Compare pins. CAPCOMP0 – 3 share the pins with P2.0–P2.3. CAPCOMP4 – 5 share the pins with P7.0 – P7.1. If not used for the EPA, they can be configured as standard I/O pins. CLKOUT Output of the internal clock generator. The frequency is (/2 of the oscillator frequency. It has a 50% duty cycle. COMPARE0–COMPARE5 (P2.4–P2.7, P7.2–P7.3) The EPA Compare pins. COMPARE0 – 3 share the pins with P2.4 – P2.7. COMPARE4–5 share the pins with P7.2 – P7.3. If not used for the EPA, they can be configured as standard I/O pins. EA External Access enable pin. EA e 0 causes all memory accesses to be external to the chip. EA e 1 causes memory accesses from location 2000H to 5FFFH to be from the on-chip OTPROM/ROM. EA e 12.5V causes execution to begin in the programming mode. EA is latched at reset. EXTINT A programmable input on this pin causes a maskable interrupt vector through memory location 203CH. The input may be selected to be a positive/negative edge or a high/low level using WGÐPROTECT (1FCEH). FREQOUT Programmable frequency output pin. The frequency can vary from 4 KHz to 1 MHz (16 MHz input clock). It has a 50% duty cycle. Pin may be configured as standard I/O if FREQOUT is not used. INST (P5.1) INST is high during the instruction fetch from the external memory and throughout the bus cycle. It is low otherwise. This pin can be configured as standard I/O if not used as INST. NMI A positive transition on this pin causes a non-maskable interrupt which vectors to memory location 203EH. If not used, it should be tied to VSS. May be used by Intel Evaluation boards. PORT0 8-bit high impedance input-only port. Also used as A/D converter inputs. Port0 pins should not be left floating. These pins also used to select programming modes in the OTPROM devices. PORT1 8-bit high impedance input-only port. P1.0 – P1.5 are also used as A/D converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock input and direction select respectively. P1.6 – P1.7 can be used as input-only pins. 9 8XC196MD PIN DESCRIPTIONS (Alphabetically Ordered) (Continued) Symbol Function PORT2 8-bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O pins (CAPCOMP0 – 3 and COMPARE0 – 3). PORT3 PORT4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which uses strong internal pullups. PORT5 8-bit bidirectional I/O port. 7 of the pins are shared with bus control signals (ALE, INST, WR, RD, BHE, READY, BUSWIDTH). Can be used as standard I/O. PORT6 8-bit output port. P6.6 and P6.7 output PWM, the others are used as the Wave Form Generator outputs. Can be used as standard output ports. PORT7 8-bit bidirectional I/O port. P7.0 – P7.3 can be used as EPA I/O pins (CAPCOMP4–5 and COMPARE4 – 5). P7.7 can be used as FREQOUT output pin. P7.4–P7.6 are standard I/O pins. PWM0, PWM1 (P6.6, P6.7) Programmable duty cycle, Programmable frequency Pulse Width Modulator pins. The duty cycle has a resolution of 256 steps, and the frequency can vary from 122 Hz to 31 KHz (16 MHz input clock). Pins may be configured as standard output if PWM is not used. RD (P5.3) Read signal output to external memory. RD is low only during external memory reads. Can be used as standard I/O when not used as RD. READY (P5.6) Ready input to lengthen external memory cycles. If READY e 0, the memory controller inserts wait states until the next positive transition of CLKOUT occurs with READY e 1. Can be used as standard I/O when not used as READY. RESET Reset input to and open-drain output from the chip. Held low for at least 16 state times to reset the chip. Input high for normal operation. RESET has an Ohmic internal pullup resistor. T1CLK (P1.2) Timer 1 Clock input. This pin has two other alternate functions: ACH10 and P1.2. T1DIR (P1.3) Timer 1 Direction input. This pin has two other alternate functions: ACH11 and P1.3. VPP The programming voltage is applied to this pin. It is also the timing pin for the return from Power Down circuit. Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC. If the Power Down feature is not used, connect the pin to VCC. WG1–WG3/WG1 –WG3 (P6.0–P6.5) 3 phase output signals and their complements used in motor control applications. The pins can also be configured as standard output pins. WR/WRL (P5.2) Write and Write Low output to external memory. WR will go low every external write. WRL will go low only for external writes to an even byte. Can be used as standard I/O when not used as WR/WRL. XTAL1 Input of the oscillator inverter and the internal clock generator. This pin should be used when using an external clock source. XTAL2 Output of the oscillator inverter. PMODE (P0.4–7) Determines the EPROM programming mode. PACT (P2.5) A low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete. 10 8XC196MD PIN DESCRIPTIONS Symbol (Alphabetically Ordered) (Continued) Function PALE (P2.1) A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). PROG (P2.2) A falling edge in Slave Programming Mode begins programming. A rising edge ends programming. PVER (P2.0) A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. CPVER (P2.6) Cumulative Program Verification. Pin is high if all locations since entering a programming mode have programmed correctly. AINC (P2.4) Auto Increment. Active low input enables the auto increment mode. Auto increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write. 11 8XC196MD ABSOLUTE MAXIMUM RATINGS NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. Ambient Temperature Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C Voltage from EA or VPP to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 13.00V Voltage on Any Other Pin to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 7.0V(1) Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W(2) *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. NOTES: 1. This includes VPP and EA on ROM or CPU only devices. 2. Power dissipation is based on package heat transfer limitations, not device power consumption. OPERATING CONDITIONS Description Min Max Units TA Symbol Ambient Temperature Under Bias b 40 a 85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V FOSC Oscillator Frequency 8 16 MHz NOTE: ANGND and VSS should be nominally at the same potential. Also VSS and VSS1 must be at the same potential. DC ELECTRICAL CHARACTERISTICS Symbol Parameter (Over Specified Operating Conditions) Min Max Units Test Conditions VIL Input Low Voltage b 0.5 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC a 0.5 V VOL Output Low Voltage Port 2, 5, and 7, P6.6, P6.7, CLKOUT 0.3 0.45 1.5 V V V IOL e 200 mA IOL e 3.2 mA IOL e 7 mA VOL1 Output Low Voltage on Port 3/4 1.0 V IOL e 15 mA VOL2 Output Low Voltage on Port 6.0–6.5 0.45 V IOL e 10 mA VOH Output High Voltage VCC b 0.3 VCC b 0.7 VCC b 1.5 V V V IOH e b 200 mA IOH e b 3.2 mA IOH e b 7 mA Vth a –Vthb Hysteresis Voltage Width on RESET 0.2 V Typical 12 8XC196MD DC ELECTRICAL CHARACTERISTICS Symbol Parameter ILI Input Leakage Current on All Input Only Pins ILI1 (Over Specified Operating Conditions) (Continued) Min Typ Max Units Test Conditions g 10 mA 0V k VIN k VCC – 0.3V (in RESET) Input Leakage Current on Port0 and Port1 g3 mA 0V k VIN k VREF IIL Input Low Current on BD Ports (Note 1) b 70 mA VIN e 0.3 VCC IIL1 Input Low Current on P5.4 and P2.6 during Reset (Note 3) b 10 mA 0.2 VCC IOH Output High Current on P5.4 and P2.6 during Reset (Note 4) mA 0.7 VCC ICC Active Mode Current in Reset 70 mA IREF A/D Conversion Reference Current 2 5 mA XTAL1 e 16 MHz, VCC e VPP e VREF e 5.5V IIDL Idle Mode Current 15 30 mA IPD Power-Down Mode Current RRST RESET Pin Pullup Resistor CS Pin Capacitance (Any Pin to VSS) b2 50 5 6k 50 mA 65k X 10 pF VCC e VPP e VREF e 5.5V FTEST e 1.0 MHz NOTES: 1. BD (Bidirectional ports) include: P2.0 – P2.7, except P2.6 P3.0 – P3.7 P4.0 – P4.7 P5.0 – P5.3 P5.5 – P5.7 P7.0 – P7.7 2. During normal (non-transient) conditions, the following total current limits apply: IOH: 28 mA P6.0 – P6.5 IOL: 40 mA IOH: 42 mA P3 IOL: 90 mA IOH: 42 mA P4 IOL: 90 mA IOH: 35 mA P5, CLKOUT IOL: 35 mA IOH: 63 mA P2, P6.6, P6.7, P7 IOL: 63 mA 3. Maximum current that must be sunk by external device to ensure test mode entry. 4. Do not exceed minimum current or device may enter test mode. 13 8XC196MD EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: Signals: H Ð High A Ð Address L Ð Low V Ð Valid B Ð BHE C Ð CLKOUT X Z D Ð DATA G Ð Buswidth Ð No Longer Valid Ð Floating L Ð ALE/ADV BR Ð BREQ R Ð RD W Ð WR/WRH/WRL X H Ð HOLD Ð XTAL1 Y Ð READY Q Ð Data Out HA Ð HLDA AC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz. The system must meet the following specifications to work with the 87C196MD: Symbol Parameter FXTAL Frequency on XTAL1 TOSC 1/FXTAL TAVYV Address Valid to READY Setup TLLYV ALE Low to READY Setup TYLYH Not READY Time TCLYX READY Hold after CLKOUT Low TLLYX READY Hold after ALE Low TAVGV Address Valid to BUSWIDTH Setup TLLGV ALE Low to BUSWIDTH Setup TCLGX Buswidth Hold after CLKOUT Low TAVDV Address Valid to Input Data Valid TRLDV Min Max Units Notes 8 16 MHz 3 62.5 125 ns 2 TOSC b 75 ns TOSC b 70 ns No Upper Limit 4 ns 0 TOSC b 30 ns 1 TOSC b 15 2 TOSC b 40 ns 1 2 TOSC b 75 ns TOSC b 60 0 ns 4 ns 3 TOSC b 55 ns 2 RD Active to Input Data Valid TOSC b 22 ns 2 TCLDV CLKOUT Low to Input Data Valid TOSC b 50 ns TRHDZ End of RD to Input Data Float TOSC ns TRXDX Data Hold after RD Inactive 0 ns NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC * N, where N e number of wait states. 3. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 4. These timings are included for compatibility with older b90 and BH products. They should not be used for newer highspeed designs. 14 8XC196MD AC ELECTRICAL CHARACTERISTICS (Continued) Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz. The 87C196MD will meet the following timing specifications: Symbol Parameter Min 30 Max Units 110 ns TXHCH XTAL1 to CLKOUT High or Low TCLCL CLKOUT Cycle Time TCHCL CLKOUT High Period TOSC b 10 TOSC a 15 ns TCLLH CLKOUT Falling Edge to ALE Rising b5 15 ns TLLCH ALE Falling Edge to CLKOUT Rising b 20 15 ns TLHLH ALE Cycle Time 2 TOSC ns 4 TOSC ns TLHLL ALE High Period TOSC b 10 TAVLL Address Setup to ALE Falling Edge TOSC b 15 ns TLLAX Address Hold after ALE Falling TOSC b 40 ns TLLRL ALE Falling Edge to RD Falling TOSC b 30 ns TRLCL RD Low to CLKOUT Falling Edge TRLRH RD Low Period TRHLH RD Rising Edge to ALE Rising Edge TRLAZ RD Low to Address Float TLLWL ALE Falling Edge to WR Falling TCLWL CLKOUT Low to WR Falling Edge TQVWH Data Stable to WR Rising Edge TCHWH CLKOUT High to WR Rising Edge Notes TOSC a 10 3 ns 4 30 ns TOSC b 5 TOSC a 25 ns 3 TOSC TOSC a 25 ns 1 5 ns TOSC b 10 0 ns 25 TOSC b 23 b 10 ns ns 15 ns TWLWH WR Low Period TOSC b 30 TWHQX Data Hold after WR Rising Edge TOSC b 25 TWHLH WR Rising Edge to ALE Rising Edge TOSC b 10 TWHBX BHE, INST Hold after WR Rising TOSC b 10 ns TWHAX AD8–15 Hold after WR Rising TOSC b 30 ns TRHBX BHE, INST Hold after RD Rising TOSC b 10 ns TRHAX AD8–15 Hold after RD Rising TOSC b 30 ns TOSC a 15 ns ns ns 3 1 2 2 NOTES: 1. Assuming back to back cycles. 2. 8-bit bus only. 3. If wait states are used, add 2 TOSC*N, where N e number of wait states. 15 8XC196MD SYSTEM BUS TIMINGS 272323 – 5 16 8XC196MD READY TIMINGS (One Wait State) 272323 – 6 BUSWIDTH TIMINGS 272323 – 7 17 8XC196MD EXTERNAL CLOCK DRIVE Symbol Parameter 1/TXLXL Oscillator Frequency TXLXL Oscillator Period TXHXX High Time 22 ns TXLXX Low Time 22 ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CRYSTAL CONNECTIONS Min Max Units 8 16.0 MHz 62.5 125 ns EXTERNAL CLOCK CONNECTIONS 272323 – 8 NOTE: Keep oscillator components close to chip and use short, direct traces to XTAL1, XTAL2 and VSS. When using crystals, C1 e 20 pF, C2 e 20 pF. When using ceramic resonators, consult manufacturer for recommended circuitry. 272323 – 9 * Required if TTL driver used. Not needed if CMOS driver is used. EXTERNAL CLOCK DRIVE WAVEFORMS 272323 – 10 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF. AC TESTING INPUT, OUTPUT WAVEFORMS 272323 – 11 AC Testing inputs are driven at 3.5V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at 2.0V for a Logic ‘‘1’’ and 0.8V for a Logic ‘‘0’’. 18 FLOAT WAVEFORMS 272323 – 12 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs and Begins to Float when a 100 mV change from the Loaded VOH/VOL Level occurs IOL/IOH e g 15 mA. 8XC196MD A TO D CHARACTERISTICS The sample and conversion time of the A/D converter in the 8-bit or 10-bit modes is programmed by loading a byte into the ADÐTIME Special Function Register. This allows optimizing the A/D operation for specific applications. The ADÐTIME register is functional for all possible values, but the accuracy of the A/D converter is only guaranteed for the times specificed in the operating conditions table. The value loaded into ADÐTIME bits 5, 6, 7 determines the sample time, TSAM, and is calculated using the following formula: SAM e (TSAM c FOSC) b 2 8 TSAM e Sample time, ms FOSC e Processor frequency, MHz SAM e Value loaded into ADÐTIME bits 5, 6, 7 SAM must be in the range 1 through 7. The value loaded into ADÐTIME bits 0–5 determines the conversion time, TCONV, and is calculated using the following formula: CONV e TCONV e Conversion time, ms FOSC e Processor frequency, MHz B e 8 for 8-bit conversion B e 10 for 10-bit conversion CONV e Value loaded into ADÐTIME bits 0 – 5 CONV must be in the range 2 through 31. The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF. VREF must be close to VCC since it supplies both the resistor ladder and the analog portion of the converter and input port pins. There is also an ADÐTEST SFR that allows for conversion on ANGND and VREF as well as adjusting the zero offset. The absolute error listed is WITHOUT doing any adjustments. A/D CONVERTER SPECIFICATION The specifications given assume adherence to the operating conditions section of this data sheet. Testing is performed with VREF e 5.12V and 16.0 MHz operating frequency. After a conversion is started, the device is placed in the IDLE mode until the conversion is complete. (TCONV c FOSC) b 3 b1 2B 19 8XC196MD 10-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature b 40 a 85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V(1) TSAM Sample Time 1.0 TCONV Conversion Time 10.0 20.0 ms(2) FOSC Oscillator Frequency 8.0 16.0 MHz ms(2) NOTES: ANGND and VSS should nominally be at the same potential. 1. VREF must be within 0.5V of VCC. 2. The value of ADÐTIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS Parameter Typical(1) Resolution Absolute Error Full Scale Error 0.25 g 0.5 Zero Offset Error 0.25 g 0.5 Non-Linearity 1.0 g 2.0 Differential Non-Linearity (Over Specified Operating Conditions) Min Max Units* 1024 10 1024 10 Levels Bits 0 g4 LSBs LSBs LSBs g4 LSBs l b1 a2 LSBs g 0.1 0 g 1.0 LSBs Repeatability g 0.25 0 Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.009 0.009 0.009 Channel-to-Channel Matching Off Isolation Feedthrough VCC Power Supply Rejection b 60 Input Series Resistance Voltage on Analog Input Pin DC Input Leakage LSB/C LSB/C LSB/C dB(2, 3) b 60 b 60 Sampling Capacitor LSBs dB(2) dB(2) 750 2K X(4) ANGND b 0.5 VREF a 0.5 V(5, 6) 3 g1 pF 0 g 3.0 mA NOTES: *An ‘‘LSB’’, as used here has a value of approximately 5 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25§ C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g 2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode. 20 8XC196MD 8-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature b 40 a 85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V(1) TSAM Sample Time 1.0 TCONV Conversion Time 7.0 20.0 ms(2) FOSC Oscillator Frequency 8.0 16.0 MHz ms(2) NOTES: ANGND and VSS should nominally be at the same potential. 1. VREF must be within 0.5V of VCC. 2. The value of ADÐTIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS Parameter Typical(1) Resolution Absolute Error Full Scale Error g 0.5 Zero Offset Error g 0.5 Non-Linearity Differential Non-Linearity Channel-to-Channel Matching (Over the Above Operating Conditions) Min Max Units* 256 8 256 8 Level Bits 0 g1 LSBs LSBs LSBs 0 g1 LSBs l b1 a1 LSBs 0 g 1.0 LSBs Repeatability g 0.25 LSBs Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.003 0.003 0.003 LSB/C LSB/C LSB/C Off Isolation Feedthrough VCC Power Supply Rejection b 60 Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage dB(2, 3) b 60 b 60 dB(2) dB(2) 750 2K X(4) VSS b 0.5 VREF a 0.5 V(5, 6) 3 g1 pF 0 g 3.0 mA NOTES: *An ‘‘LSB’’ as used here, has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25§ C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g 2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode. 21 8XC196MD EPROM SPECIFICATIONS OPERATING CONDITIONS DURING PROGRAMMING Min Max Units TA Symbol Ambient Temperature during Programming Description 20 30 §C VCC Supply Voltage during Programming 4.5 5.5 V(1) VREF Reference Supply Voltage during Programming 4.5 5.5 V(1) VPP Programming Voltage 12.25 12.75 V(2) VEA EA Pin Voltage 12.25 12.75 V(2) FOSC Oscillator Frequency during Auto and Slave Mode Programming 6.0 8.0 MHz TOSC Oscillator Frequency during Run-Time Programming 6.0 12.0 MHz NOTES: 1. VCC and VREF should nominally be at the same voltage during programming. 2. VPP and VEA must never exceed the maximum specification, or the device may be damaged. 3. VSS and ANGND should nominally be at the same potential (0V). 4. Load capacitance during Auto and Slave Mode programming e 150 pF. AC EPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) Symbol Parameter Min Max Units TSHLL Reset High to First PALE Low TLLLH PALE Pulse Width 1100 TOSC 50 TOSC TAVLL TLLAX Address Setup Time 0 TOSC Address Hold Time 100 TOSC TPLDV PROG Low to Word Dump Valid 50 TOSC TPHDX Word Dump Data Hold 50 TOSC TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TPLPH(1) PROG Pulse Width 50 TOSC TPHLL PROG High to Next PALE Low 220 TOSC TLHPL PALE High to PROG Low 220 TOSC TPHPL PROG High to Next PROG Low 220 TOSC TPHIL PROG High to AINC Low 0 TOSC TILIH AINC Pulse Width 240 TOSC TILVH PVER Hold after AINC Low 50 TOSC TILPL AINC Low to PROG Low 170 TPHVL PROG High to PVER Valid TOSC 220 TOSC NOTE: 1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. 22 8XC196MD DC EPROM PROGRAMMING CHARACTERISTICS Symbol IPP Parameter VPP Supply Current (When Programming) Min Max Units 100 mA NOTE: Do not apply VPP until VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 2723231 – 13 NOTE: P3.0 must be high (‘‘1’’) 23 8XC196MD SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT 272323 – 14 NOTE: P3.0 must be low (‘‘0’’) SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT 272323 – 15 24 8XC196MD 87C196MD DESIGN CONSIDERATIONS When an indirect shift during divide occurs the upper 3 bits of the shift count are not masked completely. If the shift count register has the value 32 * n where n e 1, 3, 5 or 7. the operand will be shifted 32 times. This should have resulted in no shift taking place. 8XC196MC to 8XC196MD Design Considerations 8XC196MC and 8XC196MD are pin compatible. However, there were several pins that were not connected (NC) on the 8XC196MC that are I/O pins on the 8XC196MD. Port 7 is a bidirectional port added to the 8XC196MD. Port 1 has one additional analog or digital input that was connected to V SS on the 8XC196MC. Port 1 also has two additional digital inputs. See 8XC196MC and 8XC196MD Differences Section of this data sheet. DATA SHEET REVISION HISTORY Document 272323-003 was updated due to changes required for the lead free initiative. To address the fact that many of the package prefix variables have changed, all package prefix variables in the document are now indicated with an "x". 25