ON NCP348 Positive overvoltage protection controller with internal low r on nmos fet and status flag Datasheet

NCP348
Positive Overvoltage
Protection Controller with
Internal Low RON NMOS FET
and Status FLAG
The NCP348 is able to disconnect the systems from its output pin
in case wrong input operating conditions are detected. The system is
positive overvoltage protected up to +28 V.
Due to this device using internal NMOS, no external device is
necessary, reducing the system cost and the PCB area of the
application board.
The NCP348 is able to instantaneously disconnect the output from
the input, due to integrated Low RON Power NMOS (65 mW), if the
input voltage exceeds the overvoltage threshold (6.4 V) or
undervoltage threshold, of 3.25 V (UVLO).
At powerup (EN pin = low level), the Vout turns on 50 ms after the
Vin exceeds the undervoltage threshold.
The NCP348 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1.0 mF or larger capacitor.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Overvoltage Protection up to 28 V
On−Chip Low RDS(on) NMOS Transistor: 65 mW
Internal Charge Pump
Overvoltage Lockout (OVLO)
Undervoltage Lockout (UVLO)
Internal 50 ms Startup Delay
Alert FLAG Output
Shutdown EN Input
Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
ESD Ratings: Machine Model = B
Human Body Model = 3
10 Lead WDFN 2.5x2 mm Package
This is a Pb−Free Device
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MARKING
DIAGRAM
BAIM
G
WDFN10
MT SUFFIX
CASE 516AA
BAI = Specific Device Code
M = Date Code
G
= Pb−Free Package
PIN CONNECTIONS
IN
1
GND
2
FLAG
3
IN
4
IN
5
10 EN
PAD1
GND
PAD2
IN
9
NC
8
NC
7
OUT
6
OUT
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
NCP348MTTBG WDFN−10
(Pb−Free)
3000 / Tape & Reel
NCP348MTTXG WDFN−10
(Pb−Free)
10000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
•
•
•
•
•
Cell Phones
Camera Phones
Digital Still Cameras
Personal Digital Applications
MP3 Players
QFN−16
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 2
1
Publication Order Number:
NCP348/D
NCP348
VBat VBat
D3
7011X/SM
NCP1835B
GND
1 mF
6
7
8
9
ISEL
8 4
270 K
4.7 mF
VBat
3
TIMER
NCP348
1
IN
OUT
4
IN
OUT
5 IN
NC
10
NC
EN
FLAG
ENABLE /
2
Microprocessor
Wall Adapter − AC/DC
3
EN
CFLG
2
FAULT V2P8
VSNS
1
VCC
BAT
1M
6
7
9
10
GND
5
ENABLE / Microprocessor
V2P8
VBat
100 nF
Lithium BATTERY
15 pF
0
0
Figure 1. Typical Application Circuit
INPUT
OUTPUT
60 mA
Output Impedance = 200 k
ESD
Protection
Core
Negative
Protection
Gate
Driver
Charge
Pump
Delay
Generator
ESD
Protection
200 kHz
Oscillator
LDO
VREG
Power
ON
10 V
EN
EN
Block
VREG
UVLO
VREF
VREF
UVLO
OVLO
VREF
OVLO
DISABLE
Figure 2. Functional Block Diagram
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2
FLAG
ESD
Protection
NCP348
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
Description
1
4
5
IN
POWER
Input Voltage Pin.
This pin is connected to the power supply.
The device system core is supplied by this input.
A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND.
The three IN pins must be hardwired to common supply.
2
GND
POWER
Ground
3
FLAG
OUTPUT
Fault Indication Pin.
This pin allows an external system to detect a fault on IN pin.
The FLAG pin goes low when input voltage exceeds OVLO threshold or drop below UVLO threshold.
Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added.
6
7
OUT
OUTPUT
Output Voltage Pin.
This pin follows IN pin when “no fault” is detected.
The output is disconnected from the Vin power supply when the input voltage is under the UVLO
threshold or above OVLO threshold.
The two OUT pins must be hardwired to common supply.
8
NC
OPEN
No Connect
9
NC
OPEN
No Connect
10
EN
INPUT
Enable Pin.
The device enters in shutdown mode when this pin is tied to a high level. In this case the output is
disconnected from the input.
To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin.
This pin does not have an impact on the fault detection.
PAD1
PAD1, under the device. See PCB recommendations page 10.
Can be shorted to GND.
PAD2
The PAD2 is electrically connected to the internal NMOS drain and connected to Pins 4 and 5.
See PCB recommendations page 10.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vminin
−0.3
V
Vmin
−0.3
V
Vmaxin
30
V
Maximum Voltage (All others to GND)
Vmax
7.0
V
Maximum Current (UVLO<VIN<OVLO)
Imax
2.0
A
Thermal Resistance, Junction−to−Air (Note 1)
Minimum Voltage (IN to GND)
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
RqJA
280
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Junction Operating Temperature
TJ
150
°C
ESD Withstand Voltage (IEC 61000−4−2) (input only) when bypassed with 1.0 mF capacitor
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd
15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity
MSL
Level 1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The RqJA is highly dependent on the PCB heat sink area (connected to pad 2). As example RqJA is 268 °C/W with 30 mm2 (copper 35 mm) and
189 °C/W with 400 mm2.
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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3
NCP348
ELECTRICAL CHARACTERISTICS (Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C,
unless otherwise noted.)
Characteristic
Input Voltage Range
Undervoltage Lockout Threshold (Note 4)
Symbol
Conditions
Min
Typ
Max
Unit
Vin
−
1.2
−
28
V
UVLO
−
3.00
3.25
3.5
V
UVLOhyst
−
20
50
100
mV
OVLO
Vin rises up OVLO threshold
6.00
6.4
6.8
V
OVLOhyst
−
50
100
150
mV
Vin versus Vout Resistance
RDS(on)
Vin = 5.0 V, EN = GND,
Load connected to Vout
−
65
120
mW
Disable Quiescent Current
Idddis
Vin = 5.0 V, EN = 1.2 V,
Load connected to Vout
−
6.0
20
mA
Supply Quiescent Current
Idd
No load. EN = 5.0 V
−
90
150
mA
No load. EN = Gnd
−
170
250
mA
Undervoltage Lockout Hysteresis
Overvoltage Lockout Threshold (Note 4)
Overvoltage Lockout Hysteresis
UVLO Supply Current
Idduvlo
VIN = 2.9 V
−
70
100
mA
FLAG Output Low Voltage
Volflag
1.2 V < VIN < UVLO
Sink 50 mA on/FLAG pin
−
20
400
mV
VIN > OVLO
Sink 1.0 mA on FLAG pin
−
−
400
mV
FLAGleak
FLAG level = 5.0 V
−
1.0
−
nA
EN Voltage High
Vih
−
1.2
−
−
V
EN Voltage Low
Vol
−
−
−
0.4
V
ENleak
EN = 5.0 V or GND
−
1.0
−
nA
ton
From Vin > UVLO to Vout =
0.3 V (See Figures 3 & 7)
30
55
70
ms
FLAG Going Up Delay
tstart
From Vout = 0.3 V to FLAG =
1.2 V (See Figures 3 & 9)
30
50
70
ms
Output Turn Off Time
toff
From Vin > OVLO to Vout < =
0.3 V (See Figures 4 & 8)
Vin increasing from 5.0 V to
8.0 V at 3.0 V/ms
Rload connected on Vout
−
1.5
5.0
ms
Alert Delay
tstop
From Vin > OVLO to FLAG < =
0.4 V (See Figures 4 & 10)
Vin increasing from 5.0 V to
8.0 V at 3.0 V/ms
Rload connected on Vout
−
1.0
−
ms
Disable Time
tdis
From EN > = 1.2 V to
Vout < 0.3 V
Rload = 5.0 W
(See Figures 5 & 12)
−
1.0
5.0
ms
FLAG Leakage Current
EN Leakage Current
TIMINGS
Startup Delay
NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature.
4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor
representative for availability.
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4
NCP348
TIMING DIAGRAMS
<OVLO
UVLO
Vin
ton
Vout
Vin − (RDS(on)
0.3 V
OVLO
Vin
Vout
I)
Vin − (RDS(on)
toff
I)
0.3 V
tstart
FLAG
tstop
1.2 V
FLAG
0.4 V
Figure 3. Startup
Figure 4. Shutdown on Overvoltage Detection
1.2 V
EN
1.2 V
EN
Vout
Vin − (RDS(on)
Vin
OVLO
tdis
UVLO
I)
FLAG
0.3 V
100 ms
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
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NCP348
TYPICAL OPERATING CHARACTERISTICS
Figure 7. Startup
Vin = Ch1, Vout = Ch3
Figure 8. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 9. FLAG Going Up Delay
Vout = Ch3, FLAG = Ch2
Figure 10. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 11. Initial Overvoltage Delay
Vin = Ch1, Vout = Ch2, FLAG = Ch3
Figure 12. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
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NCP348
TYPICAL OPERATING CHARACTERISTICS
Figure 13. Inrush Current with Cout = 100 mF,
I charge = 1 A, Output Wall Adaptor Inductance 1 mH
Figure 14. Output Short Circuit
Figure 15. Output Short Circuit (Zoom Fig. 14)
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NCP348
CONDITIONS
IN
OUT
VIN > OVLO
0 < VIN < UVLO
And/Or
VOLTAGE DETECTION
/EN = 1
Figure 16. Simplified Diagram
CONDITIONS
IN
OUT
/EN = 0
&
UVLO < VIN < OVLO
VOLTAGE DETECTION
Figure 17. Simplified Diagram
Operation
overtaking undervoltage UVLO (Figure 3). The NCP348
provides a FLAG output, which alerts the system that a fault
has occurred. A 50 ms additional delay, regarding
available output (Figure 3) is added between output signal
rising up and to FLAG signal rising up. FLAG pin is an open
drain output.
The NCP348 provides overvoltage protection for
positive voltage, up to 28 V. A Low RDS(on) NMOS FET
protects the systems (i.e.: charger) connected on the Vout
pin, against positive overvoltage. At powerup, with EN pin
= low, the output is rising up 50 ms after the input
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NCP348
Vout = 0
FLAG = Low
Reset Timer
Vin < UVLO or
Vin > OVLO
Vout = 0
FLAG = Low
Timer Count
OVLO > Vin > UVLO
T < 50 ms
Timer Check
T = 50 ms
Reset Timer
Vin < UVLO or
Vin > OVLO
Check Vin
FLAG = Low
Timer Count
UVLO < Vin < OVLO
EN = 1
EN = 0
Check EN
Vout = Open
Vin < UVLO or
Vin > OVLO
Vout = Vin
T < 50 ms
Timer Check
T = 50 ms
Check EN
UVLO < Vin < OVLO
EN = 1
UVLO < Vin < OVLO
EN = 0
Vout = Vin
FLAG = High
Check Vin
Vout = Open
FLAG = High
Check Vin
Vin < UVLO or
Vin > OVLO
Figure 18. State Machine
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NCP348
As example: Rload = 8.0 W, Vin = 5.0 V
Typical RDS(on) = 65 mW, Iout = 618 mA
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built−in undervoltage lockout (UVLO) circuit.
During Vin positive going slope, the output remains
disconnected from input until Vin voltage is below 3.25 V,
plus hysteresis, nominal. The FLAG output is tied to low as
long as Vin does not reach UVLO threshold. This circuit has
a 50 mV hysteresis to provide noise immunity to transient
condition. Additional UVLO thresholds ranging from
UVLO can be manufactured. Contact your ON
Semiconductor representative for availability.
Vout = 8 x 0.618 = 4.95 V
NMOS losses = RDS(on) x Iout2 = 0.065 x 0.6182 = 25 mW
ESD Tests
The NCP348 input pin fully supports the IEC61000−4−2.
1.0 mF (minimum) must be connected between Vin and
GND, close to the device.
That means, in Air condition, Vin has a "15 kV ESD
protected input. In Contact condition, Vin has "8.0 kV
ESD protected input.
Please refer to Figure 19 to see the IEC 61000−4−2
electrostatic discharge waveform.
Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from
overvoltage, the device has a built−in overvoltage lockout
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds 6.4 V
typical. Additional OVLO thresholds ranging from OVLO
can be manufactured. Contact your ON Semiconductor
representative for availability.
FLAG output is tied to low until Vin is higher than OVLO.
This circuit has a 100 mV hysteresis to provide noise
immunity to transient conditions.
FLAG Output
The NCP348 provides a FLAG output, which alerts
external systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded or when the Vin level is below the UVLO
threshold. When Vin level recovers normal condition,
FLAG is held high, keeping in mind that an additional
50 ms delay has been added between available output and
FLAG = high. The pin is an open drain output, thus a pull
up resistor (typically 1 MW, minimum 10 kW) must be
added to Vbat. Minimum Vbat supply must be 2.5 V. The
FLAG level will always reflects Vin status, even if the
device is turned off (EN = 1).
Figure 19. Electrostatic Discharge Waveform
PCB Recommendations
The NCP348 integrates a 2 amperes rated NMOS FET,
and the PCB rules must be respected to properly evacuate
the heat out of the silicon. The PAD1 is internally isolated
from the active silicon and should preferably be connected
to ground. The PAD2 of the NCP348 package is connected
to the internal NMOS drain and can be used to increase the
heat transfer if necessary from an applications standpoint.
Depending upon the power dissipated in the application,
one can either use the PCB tracks connected to Pins 4 and
5 to evacuate heat, or make profit of the PAD2 area to add
extra copper surface to reduce the junction temperature
(See Figure 20). Of course, in any case, this pad shall be not
connected to any other potential. Figure 20 shows copper
area according to RqJA and allows the design of the heat
transfer plane connected to PAD2.
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal NMOS FET
The NCP348 includes an internal Low RDS(on) NMOS
FET to protect the systems, connected on OUT pin, from
positive overvoltage. Regarding electrical characteristics,
the RDS(on), during normal operation, will create low losses
on Vout pin.
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NCP348
310
290
1 oz C.F.
270
1 oz Sim
2 oz C.F.
qJA (°C/W)
250
2 oz Sim
230
1
210
190
2
175
150
0 25 50 75 100 125 150 175 200 225 250 275 300 325350
COPPER HEAT SPREADING AREA (mm2)
Figure 21. Demo Board Layout
Figure 20.
INPUT
1 mF 25 V X5R 0603
Murata GRM188R61E105KA12D
OUTPUT
C1
1
IN
4
IN
5
IN
10
EN_Power
EN
6
OUT
7
OUT
NCP348
8
NC
9
NC
EN
FLAG
3
C2
100 nF 50 V X7R 0805 not necessary
FLAG Power
FLAG
GND
2
R1
1M
EN_State
R2
100 k
3 2 1
J2
R3
2
1
100 k
1
GND
FLAG_State
Figure 22. Demo Board Schematic
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11
F1 F2 F3 F4
2
NCP348
PACKAGE DIMENSIONS
WDFN10, 2.5x2, 0.5P
CASE 516AA−01
ISSUE A
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
ÍÍÍ
ÍÍÍ
E
PIN ONE
REFERENCE
DIM
A
A1
A3
b
D
D2
D3
e
E
E2
G
G1
K
L
0.10 C
2X
0.10 C
2X
A3
0.10 C
A
10X
0.08 C
A1
C
0.10 C A
B G1
2.50
D2
1
1.18
0.78
1.00
−−−
0.40
10X
0.95
K
5
E2
1.13
10
0.10 C A
0.30
0.58
L
8X
MAX
0.80
0.05
SOLDERING FOOTPRINT*
D3
0.05 C
10X
SEATING
PLANE
MILLIMETERS
MIN
NOM
0.70
0.75
0.00
−−−
0.20 REF
0.20
0.25
2.50 BSC
0.97
1.08
0.57
0.68
0.50 BSC
2.00 BSC
0.80
0.90
3.75 BSC
3.50 BSC
0.20
−−−
0.20
0.30
b
B
10X
G
0.05 C
0.60
0.50
PITCH
6
e
10X
0.10 C A
0.05 C
0.05
B
NOTE 3
1.45
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
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may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
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NCP348/D
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