TI1 LP3941 Cellular phone power management unit Datasheet

LP3941
LP3941A Cellular Phone Power Management Unit
Literature Number: SNOSAB4C
October 25, 2011
LP3941A
Cellular Phone Power Management Unit
General Description
LP3941A is a complete power management IC designed for
a cellular phone. It contains 11 low noise low dropout regulators, a linear charger for Li-Ion battery, a backup battery
charger, real time clock supply regulator, three open drain
drivers, two comparators and high speed I2C compatible serial interface to program individual regulator output voltages
as well as on/off control.
LP3941 is available in a LLP48 package.
Features
■
■
■
■
11 low dropout, low noise LDOs.
Dedicated low current LDO for real time clock supply.
Back-up battery charger
A constant current / constant voltage battery charger
controller with charge status indication via I2C compatible
interface.
■ Three open drain drivers to control a RGB LED
■ I2C compatible serial interface for maximum flexibility
Applications
■ GSM/EDGE cellular handsets
■ Wideband CDMA cellular handsets
Key Specifications
■
■
■
■
3.0V to 5.5V Input Voltage Range
27 µVRMS Output noise
2% (typical) Output Voltage Accuracy
1% Charger Voltage Accuracy
Typical Application
20094501
© 2011 Texas Instruments Incorporated
200945
200945 Version 4 Revision 2
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Print Date/Time: 2011/10/25 13:09:13
LP3941A Cellular Phone Power Management Unit
OBSOLETE
LP3941A
Connection Diagrams and Package Mark Information
48-Pin Leadless Leadframe Package
See NS Package Number LQA48B
20094503
20094502
Bottom View
Note: Circle marks pin 1 position. Pin 1 name is N/C.
Top View
20094517
Note: The actual physical placement of the package marking will vary from part to part. The package markings “UZYY” designate assembly and manufacturing
information. “TT” is a NSC internal code for die traceability. Both will vary considerably. “3941LQA” identifies the device.
Package Mark—Top View
Ordering Information
Order Number
Package Marking
Supplied As
LP3941LQ-A
LP3941LQA
250 units, Tape-and-Reel
LP3941LQX-A
LP3941LQA
2500 units, Tape-and-Reel
Note: *See LP3941A register table and LDO programming table for information on the default voltages for LP3941A.
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200945 Version 4 Revision 2
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LP3941A
Pin Descriptions
Pin #
Name
I/O
Type
1
N/C
-
-
Not used. Connect to ground.
Description
2
AGND3
G
G
Analog ground pin.
3
VO8
O
A
LDO 8 Output
4
IN5
I
P
Input power terminal to LDO's. Must be connected to IN1–4 and IN6.
5
VO9
O
A
LDO 9 output.
6
VO10
O
A
LDO 10 output.
7
IN6
I
P
Input power terminal to LDO's. Must be connected to IN1–5.
8
VO11
O
A
LDO 11 output.
9
DGND
G
G
Ground pin.
10
VO3
O
A
LDO 3 output.
11
IN2
I
P
Input power terminal to LDO's. Must be connected to IN1 and IN3–6.
12
VO2
O
A
LDO 2 output.
13
IN1
I
P
Input power terminal to LDO's. Must be connected to IN2–6.
14
VO1
O
A
LDO 1 output.
15
PS-HOLD
I
D
Active low off key initiated by the micro controller.
16
BU_BAT
I
A
Back-up battery connection.
17
VRTC
O
A
RTC_LDO output.
18
IN (COMP1)
I
A
Non-inverting inout of the comparator 1.
19
OUT (COMP1)
O
A
Output of the comparator 1.
20
AGND1
G
G
Analog ground pin.
21
IN (COMP2)
I
A
Non-inverting input of the comparator 2.
22
OUT (COMP2)
O
A
Output of the comparator 2.
23
REF-BYP
I
A
Reference bypass capacitor.
24
VO7
O
A
LDO 7 output.
25
VO6-EN
I
D
LDO 6 on/off pin. Internal pull-down resistor of 1 MΩ.
26
IN4
I
P
Input power terminal to LDO's. Must be connected to IN1–3 and IN5–6.
27
VO6
O
A
LDO 6 output.
28
VO5
O
A
LDO 5 output.
29
IN3
I
P
Input power terminal to LDO's. Must be connected to IN1–2 and IN4–6.
30
VO4
O
A
LDO 4 output.
31
BSNS
I
A
Main battery ID resistor connection.
32
ON
O
OD
Inverted open drain output signal of the ON input. Pulled low when ON is pulled high
and open drain when ON is pulled low. There is no significant delay between the ON
signal going high and ON pin going low. The delay between ON signal going low and
ON pin is determined by the pull up current and capacitance connected to this pin.
33
BATTSENSE
I
A
Battery voltage sense pin. Should be connected as close to the battery's + terminal
as possible.
34
Drive
O
A
Gate drive to the external MOSFET.
35
BATT
O
A
Battery supply input terminal. Must have 10 µF ceramic capacitor to GND.
36
VO5-EN
I
D
LDO 5 on/off pin. Internal pull down resistor of 1 MΩ.
37
RTC_ALARM
I
D
RTC_ALARM input.
38
ON
I
D
Active high power On/Off key. This pin is pulled to GND by an internal 200 kΩ resistor.
39
HF_PWR
I
D
Active high Hands Free connection signal. This pin has an internal 200 kΩ pull down
resistor.
40
CHG_IN
I
P
Charger input from a current limited power source. Must have a 1 µF ceramic
capacitor to GND.
41
ISENSE
O
A
Charge current sense resistor.
42
RESET
O
OD
Reset output. Active low. (See Power Up Timing Diagram.)
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200945 Version 4 Revision 2
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LP3941A
Pin #
Name
I/O
Type
Description
43
AGND2
G
G
Analog ground pin.
44
SCL
I
D
Serial interface clock input.
45
SDA
I/O
D
Serial interface data input/output.
46
LED1
O
OD
LED driver output pin.
47
LED2
O
OD
LED driver output pin.
48
LED3
O
OD
LED driver output pin.
A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin
I: Input Pin I/O: Input/Output Pin O: Output Pin OD: Open Drain Pin
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200945 Version 4 Revision 2
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2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
CHG-IN
IN1–6, BATT, SDA, SCL, ON,
HF-PWR, PS-HOLD, SYS,
COMP1_IN, COMP2_IN,
CHG_IN, BSNS, VO5-EN, VO6EN, LED1–3, RTC_ALARM,
BU_BAT, VRTC, RESET,
BATTSENSE.
REFBYP, ON, PS-HOLD,
COMP1_OUT, COMP2_OUT to
GND
VO1 to GND
VO2, VO3 to GND
VO4, VO5 to GND
VO6, VO7 to GND
VO8, VO9 to GND
VO10, VO11 to GND
−0.3V to +12V
Operating Ratings
(Note 1, Note 2)
VIN
VEN
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(Note 6)
−0.3V to +6V
−0.3V to +VBAT + 0.3V
−0.3V to +VIN1 + 0.3V
−0.3V to +VIN2 + 0.3V
−0.3V to +VIN3 + 0.3V
−0.3V to +VIN4 + 0.3V
−0.3V to +VIN5 + 0.3V
−0.3V to +VIN6 + 0.3V
Thermal Properties
3.0V to 6.0V
0V to (VIN + 0.3V)
−40°C to +125°C
−40°C to +85°C
(Note 7)
Junction-to-Ambient Thermal
Resistance (θJA)
26°C/W
Electrical Characteristics
Unless otherwise noted, VIN = 2.5V to 5.5V, CIN (IN1–6) = 4.7 µF, COUT (VO1 and VO9) = 4.7 µF, COUT (VO2, VO3, VO7, VO8, VO10
and VO11) = 2.2 µF, COUT (VO4 to VO6) = 1 µF, COUT (VRTC) = 1 µF ceramic, CBYP = 0.1 µF. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation,
−40 to +125°C. (Note 2, Note 8, Note 9, Note 10)
Symbol
IQ
Parameter
Condition
Shutdown Supply Current
Min
VBATT = 2.1V, UVLO on, internal logic
generator on, VRTC off, all other circuits
off.
No Load Supply Current, LDO 1 & VBATT = 3.6V, LDOs VO1, VO3 and VO5 on,
3 & 5 on
back-up battery charger and VRTC on,
charger disconnected, comparator 1 & 2
on.
No Load Supply Current
VBATT = 3.6V, All LDOs on, charger
disconnected.
Typ
Max
Units
14
µA
310
µA
500
µA
BATTERY UNDER VOLTAGE LOCKOUT
VUVLO-R
Under Voltage Lock-Out
VBATT Rising
2.91
3.1
3.32
V
VUVLO-F
Under Voltage Lock-Out
VBATT Falling
2.15
2.49
2.85
V
VTH-POR
Power-On Reset Threshold
VBATT Falling Edge
1
1.7
2.3
V
THERMAL SHUTDOWN
Threshold
Hysteresis
160
10
°C
OUTPUT CAPACITORS
COUT
Capacitance
ESR
1
5
20
500
µF
mΩ
0.4
V
LOGIC AND CONTROL INPUTS
VIL
Input Low Level
PS-HOLD, ON, BSNS, HF-PWR,
RTC_ALARM, SDA, SCL, VO5-EN, VO6EN.
2.5V ≤ VBATT ≤ 5.5V
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LP3941A
GND to GND SLUG
±0.3V
Maximum Continuous Power Dissipation
(PD_MAX) (Note 3)
3.07W
Junction Temperature (TJ-MAX)
150°C
Storage Temperature Range
−65°C to +150°C
Maximum Lead Temperature
(Soldering)
(Note 4)
ESD Ratings (Note 5)
All Pins
2 kV HBM
200V MM
Absolute Maximum Ratings (Note 1, Note
LP3941A
Symbol
VIH
Parameter
Condition
Input High Level
PS-HOLD, ON, BSNS, HF-PWR,
RTC_ALARM, SDA, SCL, VO5-EN, VO6EN.
Min
Typ
Max
Units
V
2.0
2.5V ≤ VBATT ≤ 5.5V
IIL
Logic Input Current
SDA, SCL
PS-HOLD Input Current
RIN
0V ≤ VIN ≤ 5.5V
−5
+5
µA
0V ≤ VIN ≤ VBATT
−5
+5
µA
ON, HF_PWR Pull-Down
Resistance to GND
200
kΩ
VO5-EN, VO6-EN, RTC_ALARM
Pull Down Resistance to GND
1700
kΩ
LOGIC AND CONTROL OUTPUTS
VOL
ON Output Low Level
ISINK = 1 mA
0.4
V
ILEAKAGE
ON Open Drain Leakage
VON = 4.2V
5
µA
IO-MAX
ON, RESET, OUT (COMP1), OUT
(COMP2) Output Maximum Sink/
Source Current
5
mA
VO1 LDO Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +85°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 200 mA, VOUT = 2.2V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 200 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
1.5
1.8
3.0
V
200
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
780
VIN–VOUT
Dropout Voltage
IOUT = 100 mA
70
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
254
mA
mV
VBATT = VIN ≤ 5.5V, IOUT = 100 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 200 mA
10
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 4.7 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 4.7 µF
60
dB
COUT
Output Capacitance
Output Capacitor ESR
1 mA ≤ IOUT ≤ 200 mA
tSTART-UP
Start-Up Time from Shutdown ON- COUT = 4.7 µF, IOUT = 200 mA (Note 10)
signal
mV
2
20
µF
5
500
mΩ
180
µs
80
120
Note: This LDO will be ON after start up by default.
Note: (VOUT + 0.25V, 3.0V)MAX means greater of the two. That is 3.0V if VOUT < 2.75V.
Note: The PMU can switch off if battery voltage is below 3.0V due to under voltage lockout designed to protect the battery from excessive discharge at low
voltages.
Note: The start-up time (tSTART-UP) is defined as the time between the rising edge of ON-, HF_PWR-, RTC ALARM- or CHG_IN- pins going high and activating
the power-up sequence of the LP3941A.
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200945 Version 4 Revision 2
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Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 200 mA, VOUT = 2.2V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 200 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
1.5
2.8
3.0
V
150
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
540
VIN–VOUT
Dropout Voltage
IOUT = 75 mA
30
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
174
mA
mV
VBATT = VIN ≤ 5.5V, IOUT = 75 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 150 mA
12
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 2.2 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 2.2 µF
57
dB
IGND
Ground Current
IOUT = 100 µA
COUT
Output Capacitance
Output Capacitor ESR
0 mA ≤ IOUT ≤ 150 mA
tSTART-UP
Start-Up Time from Shutdown
COUT = 2.2 µF, IOUT = 150 mA (Note 10)
mV
41
30
2
5
µA
20
µF
500
mΩ
60
µs
VO3 LDO Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 150 mA, VOUT = 2.7V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 150 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
2.5
3.0
3.2
V
150
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
520
VIN–VOUT
Dropout Voltage
IOUT = 75 mA
30
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
156
mA
mV
VBATT = VIN ≤ 5.5V, IOUT = 75 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 150 mA
12
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 2.2 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 2.2 µF
56
dB
IGND
Ground Current
IOUT = 500 µA
30
µA
COUT
Output Capacitance
Output Capacitor ESR
0 mA ≤ IOUT ≤ 150 mA
Start-Up Time from Shutdown
COUT = 2.2 µF, IOUT = 150 mA (Note 10)
tSTART-UP
mV
41
2
20
µF
5
500
mΩ
60
µs
Note: This LDO will be ON after start-up by default. It can be disabled via the register file.
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200945 Version 4 Revision 2
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LP3941A
VO2 LDO Electrical Characteristics
LP3941A
VO4 LDO Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 50 mA, VOUT = 2.2V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 50 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
1.5
3.0
3.0
V
50
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
VIN–VOUT
Dropout Voltage
IOUT = 25 mA
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
mA
140
7
90
mV
VBATT = VIN ≤ 5.5V, IOUT = 25 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 50 mA
4
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 1.0 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 1.0 µF
56
dB
IGND
Ground Current
IOUT = 100 µA
COUT
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 50 mA
tSTART-UP
Start-Up Time from Shutdown
COUT = 1.0 µF, IOUT = 50 mA (Note 10)
mV
31
30
1
5
µA
20
µF
500
mΩ
60
µs
VO5 LDO Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 50 mA, VOUT = 2.2V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 50 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
2.5
2.8
3.2
V
50
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
VIN–VOUT
Dropout Voltage
IOUT = 25 mA
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
mA
160
7
90
mV
VBATT = VIN ≤ 5.5V, IOUT = 25 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 50 mA
4
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 1.0 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 1.0 µF
56
dB
IGND
Ground Current
IOUT = 100 µA
30
µA
COUT
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 50 mA
Start-Up Time from Shutdown
COUT = 1.0 µF, IOUT = 50 mA (Note 10)
tSTART-UP
mV
31
1
20
µF
5
500
mΩ
60
µs
Note: This LDO will be ON after start-up by default.
Note: This LDO has an external active high enable pin, VO5-EN as well as the internal register enable bit. The LDO is on if either of these is “1” (OR-function).
The enable bit is “1” by default and can be disabled via the register file.
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200945 Version 4 Revision 2
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Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 50 mA, VOUT = 2.7V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 50 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
2.5
2.8
3.2
V
50
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
VIN–VOUT
Dropout Voltage
IOUT = 25 mA
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
mA
170
7
90
mV
VBATT = VIN ≤ 5.5V, IOUT = 25 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 50 mA
4
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 1.0 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 1.0 µF
56
dB
IGND
Ground Current
IOUT = 100 µA
COUT
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 50 mA
Start-Up Time from Shutdown
COUT = 1.0 µF, IOUT = 50 mA (Note 10)
tSTART-UP
mV
31
30
µA
1
20
µF
5
500
mΩ
60
µs
Note: This LDO has an external active high enable pin, VO6-EN as well as an internal register enable bit. The LDO is on if either of these is “1” (OR-function).
The enable bit is “0” by default and can be enabled via the register file.
VO7 LDO Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 150 mA, VOUT = 2.7V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 150 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
2.5
3.0
3.2
V
150
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
500
VIN–VOUT
Dropout Voltage
IOUT = 75 mA
30
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
173
mA
mV
VBATT = VIN ≤ 5.5V, IOUT = 75 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 150 mA
10
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 2.2 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 2.2 µF
57
dB
IGND
Ground Current
IOUT = 100 µA
COUT
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 150 mA
tSTART-UP
Start-Up Time from Shutdown
COUT = 2.2 µF, IOUT = 150 mA Note 10
30
2
5
9
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60
µA
20
µF
500
mΩ
µs
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LP3941A
VO6 LDO Electrical Characteristics
LP3941A
VO8 LDO Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 150 mA, VOUT = 2.7V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 150 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
2.5
3.0
3.2
V
150
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
510
VIN–VOUT
Dropout Voltage
IOUT = 75 mA
30
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
173
mA
mV
VBATT = VIN ≤ 5.5V, IOUT = 75 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 150 mA
12
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 2.2 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 2.2 µF
57
dB
IGND
Ground Current
IOUT = 100 µA
COUT
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 150 mA
Start-Up Time from Shutdown
COUT = 2.2 µF, IOUT = 150 mA (Note 10)
tSTART-UP
mV
41
30
µA
2
20
µF
5
500
mΩ
60
µs
VO9 LDO Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 200 mA, VOUT = 2.2V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 200 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
1.5
3.0
3.0
V
200
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
770
VIN–VOUT
Dropout Voltage
IOUT = 100 mA
50
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
288
mA
mV
VBATT = VIN ≤ 5.5V, IOUT = 100 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 200 mA
15
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 4.7 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 4.7 µF
60
dB
IGND
Ground Current
IOUT = 100 µA
30
µA
COUT
Output Capacitance
Output Capacitor ESR
1 µA ≤ IOUT ≤ 200 mA
Start-Up Time from Shutdown
COUT = 4.7 µF, IOUT = 200 mA (Note 10)
tSTART-UP
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2
20
µF
5
500
mΩ
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200945 Version 4 Revision 2
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60
µs
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 150 mA, VOUT = 2.2V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 150 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−3
±1.0
+3
%
1.5
2.5
3.0
V
150
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
610
VIN–VOUT
Dropout Voltage
IOUT = 75 mA
30
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
204
mA
mV
VBATT = VIN ≤ 5.5V, IOUT = 75 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 150 mA
12
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 2.2 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 2.2 µF
57
dB
IGND
Ground Current
IOUT = 100 µA
COUT
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 150 mA
tSTART-UP
Start-Up Time from Shutdown
COUT = 2.2 µF, IOUT = 150 mA (Note 10)
mV
41
30
2
5
µA
20
µF
500
mΩ
60
µs
VO11 LDO Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 10)
Symbol
Parameter
Condition
1 mA ≤ IOUT ≤ 200 mA, VOUT = 2.7V
VOUT
Accuracy
Output Voltage
VOUT
Range
Programmable Output Voltage
Range
0 µA ≤ IOUT ≤ 200 mA
Programming Resolution = 100 mV
IOUT
Output Current
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
3.0V ≤ VBATT = VIN ≤ 5.5V
Min
Typ
Max
Units
−2
±2.0
+5
%
1.8
1.8
3.3
V
200
VBATT = VIN ≤ 5.5V
Output Current Limit
VOUT = 0V
900
VIN–VOUT
Dropout Voltage
IOUT = 100 mA
50
ΔVOUT
Line Regulation
(VOUT + 0.25V, 3.0V)MAX ≤ VBATT
302
mA
mV
VBATT = VIN ≤ 5.5V, IOUT = 100 mA
3
Load Regulation
VIN = 3.6V, 1 mA ≤ IOUT ≤ 200 mA
15
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,
COUT = 4.7 µF
27
µVRMS
PSRR
Power Supply Ripple
Rejection Ratio
f = 217 Hz, COUT = 4.7 µF
60
dB
IGND
Ground Current
IOUT = 100 µA
30
µA
COUT
Output Capacitance
Output Capacitor ESR
1 mA ≤ IOUT ≤ 200 mA
Start-Up Time from Shutdown
COUT = 4.7 µF, IOUT = 200 mA (Note 10)
tSTART-UP
44
2
20
µF
5
500
mΩ
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60
µs
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LP3941A
VO10 LDO Electrical Characteristics
LP3941A
VRTC LDO Electrical Characteristics
Unless otherwise noted, 2.5V < VBU_BAT < 3.3V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note
9)
Symbol
Parameter
Condition
IOUT ≤ 50 µA, VOUT = 1.8V
VOUT
Accuracy
Output Voltage
IQ
Quiescent Current
IOUT = 6 µA
IOUT
Output Current
2.15V ≤ VBU-BAT ≤ 3.3V
Output Current Limit
VOUT = 0V
VIN–VRTC
Dropout Voltage
PSRR
Power Supply Ripple
Rejection Ratio
COUT
Output Capacitance
Output Capacitor ESR
1 mA ≤ IOUT ≤ 200 mA
2.15V ≤ VBU-BAT ≤ 3.3V
Min
Typ
Max
Units
1.6
1.8
2.0
V
2.6
6
µA
10
50
2000
10000
IOUT = 50 mA
150
190
f = 100 Hz, COUT = 1.0 µF
20
1000
0.75
1.0
5
µA
mV
dB
2.2
µF
500
mΩ
Note: The RTC_LDO can be disabled via the I2C compatible interface by setting the corresponding disable bit. See Table 1 for further details.
Back-Up Charger Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOUT +
0.4
5.5
V
3.15
3.3
V
VIN
Operational Voltage Range
VOUT
Accuracy
Output Voltage
IQ
Quiescent Current
IOUT < 50 µA
25
IOUT
Output Current
VOUT + 0.4 ≤ VBATT = VIN ≤ 5.5V,
VOUT = 3.0V
70
150
Output Current Limit
3.2V ≤ VBATT = VIN ≤ 5.5V
VOUT = 0V
1.5
2
Power Supply Ripple
Rejection Ratio
IOUT ≤ 50 µA, VOUT = 3.15V
VOUT + 0.4 ≤ VBATT = VIN ≤ 5.5V
f < 10 kHz
15
dB
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 100 µA
0.1
µF
PSRR
COUT
IOUT ≤ 50 µA, VOUT = 3.15V
VOUT + 0.4 ≤ VBATT ≤ 5.5V
3.0
0.7
5
µA
500
µA
mA
mΩ
Note: The back-up battery charger can be disabled by setting the corresponding enable bit ‘0’ via the I2C interface. See Table 1 for further details.
Comparators' Electrical Characteristics
Unless otherwise noted, VBATT = +2.5V to 5.5V, VO3 = 3.0V, VCM = 0.27V. Typical values and limits appearing in normal type apply
for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40 to +125°C.
(Note 2, Note 8, Note 9)
Symbol
Parameter
Condition
Min
Typ
Max
Units
270
300
mV
0.01
0.15
µA
VT
Comparator Trip Voltage
IB
Input Bias Current
IOS
Input Offset Current
PSRR
Power Supply Rejection Ratio
2.7V ≤ VBATT ≤ 5.5V
VOL
Output Voltage Low
ISINK = 1 mA
VOH
Output Voltage High
ISOURCE = 1 mA
tPLH
Propagation Delay Low to High
Overdrive = 100 mV (Note 10)
5
µs
tPHL
Propagation Delay High to Low
Overdrive = 100 mV (Note 10)
5
µs
230
VINV = 1.3V
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1
nA
50
dB
0.24
0.37
VO3–0.25
3
V
V
Parameter
Condition
Min
Typ
Max
Units
tLH
Rise Time Low to High
Overdrive = 100 mV
COUT = 10 pF (Note 10)
5
ns
tHL
Fall Time High to Low
Overdrive = 100 mV
COUT = 10 pF (Note 10)
5
ns
IQ
Quiescent Current per Comparator
5
µA
Note: Comparator output buffers are powered by LDO3 output voltage.
RESET Electrical Characteristics
Unless otherwise noted, VBATT = +2.5V to 5.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note
9)
Symbol
Parameter
Condition
Min
VOH
Output Voltage High
Internal Logic Supply
ISOURCE = 0 µA
VOL
Output Voltage Low
Internal Logic Supply
ISINK = 500 µA
VTSHLD
VO1 Threshold
VO1 Rising
90
VO1 Falling
82
Typ
Max
VO3–0.2
Units
V
0.4
V
93
96
%
85
88
%
tDELAY
RESET Active Time-Out Period
From VO1 ≥ 93% until RESET = High
34
40
47
ms
tPS-HOLD
PS-HOLD Timer
From RESET = Hi to PS-HOLD = Hi
From PS-HOLD = Low to RESET = Low
29
35
41
ms
tRESET
Shut-Down Timer
From RESET = Low until LDOs turned off
(no output regulation)
51
60
70
ms
RPU
Pull-up Resistance to VO1
IS-MAX
Maximum Sink Current
14
kΩ
5
mA
LED Driver Electrical Characteristics
Unless otherwise noted, VBATT = +2.5V to 5.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note
9)
Symbol
Parameter
Condition
VOL
LED1–3 Output Low Level
ISINK = 40 mA
ILEAKAGE
LED1–3 Off Leakage Current
VDR = 5.5V
Min
Typ
Max
0.17
0.55
4
Units
V
µA
Main Battery Charger Electrical Characteristics
Unless otherwise noted, VCHG-IN = 5V, VBATT = 4V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 9, Note
8, Note 12)
Symbol
VCHG-IN
VOK−TSHD
VUVLO−TSHD
Parameter
Condition
Input Voltage Range
Min
Max
12
4.5
6
Units
V
Operating Range
Battery Connected
Adapter OK Trip Point (CHG-IN)
VCHG-IN–VBATT Rising
80
mV
VCHG-IN–VBATT Falling
30
mV
Under Voltage Lock-Out Trip Point VCHG-IN Rising
3.85
VCHG-IN Falling
VOVLO−TSHD
Typ
4.5
4.25
4.65
3.90
Over Voltage Lock-Out Trip Point VCHG-IN Rising
5.46
VCHG-IN Falling
6.00
V
V
6.54
V
5.80
V
IBATTSENSE
Leakage Current
VBATT = 4.2V
8
µA
IBATT
Battery Input Current
VCHG-IN ≤ 4V
2
µA
Charging Complete, charger connected,
VBATT = 4.1V
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150
µA
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LP3941A
Symbol
LP3941A
Symbol
ICHG
Parameter
Condition
Fast Charge Current Accuracy
ICHG = 700 mA
Fast Charge Current Range
Min
Typ
Max
−10
±5
+10
%
937
mA
478
Programmable Charging Current
Step
IPRE−CHG
Pre-Charge Current
RSENSE
Internal Current Sense Resistance
43
VBATT = 2V
42
28
mA
59
120
Internal Current Sense Resistor
Load Current
Units
mA
mΩ
1.2
A
CHARGING PERFORMANCE
VBATT
Battery Regulation Voltage
(CV Mode, for 4.1V Cell)
TA −40°C to +85°C
4.015
4.1
4.19
Battery Regulation Voltage
CV mode, for 4.2V Cell)
TA −40°C to +85°C
4.115
4.2
4.289
VCHG-Q
Full Charge Qualification
Threshold
VBATT Rising, Transition from Pre-Charge
to Full Current
2.8
3.0
3.2
VBAT-RST
Restart Threshold Voltage
(For 4.1V Cell)
VBATT Falling, Transition from EOC, to
Pre-Qual State
3.9
Restart Threshold Voltage
(For 4.2 Cell)
VBATT Falling, Transition from EOC, to
Pre-Qual State
4.0
Time to EOC State
−40°C to +85°C (Note 10)
tEOC
V
V
4.80
5.625
6.55
Hrs
A/D CONVERTER PERFORMANCE
Resolution
8
INL
Relative Accuracy
DNL
Differential Nonlinearity
No Missing Code
Bits
−1
+1
LSB
−1
+1
LSB
Note: While charging a Li-Ion battery with this charger is possible in cold temperatures (generally below −5°C–0°C) is possible with the LP3941A, charging a
battery outside its manufacturer recommended temperature limits is strongly discouraged.
I2C Compatible Interface Electrical Characteristics
Unless otherwise noted, VBATT = +2.5V to 5.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, −40 to +125°C. (Note 2, Note 8, Note
9)
Symbol
Parameter
Condition
Min
Typ
Max
Units
400
kHz
FCLK
Clock Frequency
tBF
Bus-Free Time between START and STOP
(Note 10)
1.3
µs
tHOLD
Hold Time Repeated START Condition
(Note 10)
0.6
µs
tCLK-LP
CLK Low Period
(Note 10)
1.3
µs
tCLK-HP
CLK High Period
(Note 10)
0.6
µs
tSU
Set-Up Time Repeated START Condition
(Note 10)
0.6
µs
tDATA-HOLD
Data Hold Time
(Note 10)
0
µs
tDATA-SU
Data Set-Up Time
(Note 10)
100
ns
tSU
Set-Up Time for STOP Condition
(Note 10)
0.6
µs
tTRANS
Maximum Pulse Width of Spikes that must be (Note 10)
suppressed by the input filter of both DATA &
CLK signals.
50
ns
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula
P = (TJ – TA)/θJA,
where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance.
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(1)
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP)
(AN-1187).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200
pF capacitor discharged directly into each pin. (EAIJ)
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP − (θJA x PD-MAX).
Note 7: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the
JEDEC standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane
on the board is 50 mm x 50 mm. Thickness of copper layers are 36 μm/1.8 μm/18 μm/36 μm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22°
C, still air. Power dissipation is 1W.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special
care must be paid to thermal dissipation issues in board design.
The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum
power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to
Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
Note 8: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production
with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Note 9: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics.
Note 10: Guaranteed by design.
Note 11: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply
in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply
for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V.
Note 12: LP3941A is not intended as a Li-Ion battery protection device. Battery used in this application should have an adequate internal protection.
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LP3941A
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special
care must be paid to thermal dissipation issues in board design.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150ºC (typ.) and disengages at TJ = 140ºC
(typ.).
LP3941A
LP3941A Simplified Block Diagram
20094504
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Under nominal conditions. This means, unless otherwise noted,
TA = 25°C, VBATT = 3.6V, VBU_BATT = 3.15V.
200 mA LDO Output Voltage
200 mA LDO PSRR
20094506
20094509
150 mA LDO Output Voltage
150 mA LDO PSRR
20094505
20094508
50 mA LDO PSRR
50 mA LDO Output Voltage
20094507
20094510
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LP3941A
Typical Performance Characteristics
LP3941A
Pre-Charge Current
Fast Charging Current
20094516
20094515
Charging Termination Voltage
Back-Up Battery Full Voltage
20094514
20094513
Back-Up Battery Charging Current
RTC-LDO Output Voltage
20094512
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7h'7E
Numbers in parentheses indicate default setting: (0) bit is set to low state, and (1) bit is set to high state. R/O –Read Only, All other
bits are Read and Write.
TABLE 1. LP3941 Control and Data Codes
Addr
Register
7
6
5
4
3
2
1
0
LDO7–EN
(0)
LDO6–EN
(0)
LDO5–EN
(1)
LDO4–EN
(0)
LDO3–EN
(1)
LDO2–EN
(0)
LDO1–EN
(1)
LDO8–EN
(0)
8h′00
Enable
8h′01
LDO9/
LDO1 Data
Code
LDO9
Code 3
(1)
LDO9
Code 2
(1)
LDO9
Code 1
(1)
LDO9
Code 0
(1)
LDO1
Code 3
(0)
LDO1
Code 2
(0)
LDO1
Code 1
(1)
LDO1
Code 0
(1)
8h′02
LDO10/
LDO2 Data
Code
LDO10
Code 3
(1)
LDO10
Code 2
(0)
LDO10
Code 1
(1)
LDO10
Code 0
(0)
LDO2
Code 3
(1)
LDO2
Code 2
(1)
LDO2
Code 1
(0)
LDO2
Code 0
(1)
8h′03
LDO8/
LDO3 Data
Code
Not Used
(0)
LDO8
Code 2
(1)
LDO8
Code 1
(0)
LDO8
Code 0
(1)
Not Used
(0)
LDO3
Code 2
(1)
LDO3
Code 1
(0)
LDO3
Code 0
(1)
8h′04
LDO11/
LDO4 Data
Code
LDO11
Code 3
(0)
LDO11
Code 2
(0)
LDO11
Code 1
(0)
LDO11
Code 0
(0)
LDO4
Code 3
(1)
LDO4
Code 2
(1)
LDO4
Code 1
(1)
LDO4
Code 0
(1)
8h′05
LDO5
Data Code
Not Used
(0)
Not Used
(0)
Not Used
(0)
Not Used
(0)
Not Used
(0)
LDO5
Code 2
(0)
LDO5
Code 1
(1)
LDO5
Code 0
(1)
8h′06
LDO6
Data Code
Not Used
(0)
Not Used
(0)
Not Used
(0)
Not Used
(0)
Not Used
(0)
LDO6
Code 2
(0)
LDO6
Code 1
(1)
LDO6
Code 0
(1)
8h′07
LDO7
Data Code
Not Used
(0)
Not Used
(0)
Not Used
(0)
Not Used
(0)
Not Used
(0)
LDO7
Code 2
(1)
LDO7
Code 1
(0)
LDO7
Code 0
(1)
8h′08
Charger
Register –1
Not Used
(0)
Not Used
(0)
Not Used
(0)
4.1V/4.2V
(1)
Charger
Current
Code 3 (0)
Charger
Current
Code 2 (0)
Charger
Current
Code 1 (0)
Charger
Current
Code 0 (1)
8h′09
Charger
Register –2
Not Used
(0)
Not Used
(0)
Not Used
(0)
EOC
R/O
Charging
R/O
EOC Sel-1
(0)
EOC Sel-0
(1)
ChargerDIS
Off/On
(0)
8h′0a
Control/
Enable
LDO9-EN
(0)
LDO10-EN
(0)
LDO11-EN
(0)
Back-Up
Battery
Charger
Enable
(1)
RTC_LDO
Disable
(0)
LED1
Enable
(0)
LED2
Enable
(0)
LED3
Enable
(0)
8h′0b
ADC
Control
Register
Not Used
(0)
Not Used
(0)
Not Used
(0)
Not Used
(0)
ADC Start
(0)
ADC EN
(0)
ADC
Mux-1
(1)
ADC
Mux-0
(1)
8h′0c
ADC
Output
Register
ADC7
R/O
ADC6
R/O
ADC5
R/O
ADC4
R/O
ADC3
R/O
ADC2
R/O
ADC1
R/O
ADC0
R/O
8h′0d
Power-OnReason
Register
R/O
(0)
R/O
(0)
R/O
(0)
R/O
(0)
ON
R/O
RTC
ALARM
R/O
CHG_IN
R/O
HF_PWR
R/O
8h′2e
ADC/
Status
Register
COMP2
OUT
R/O
COMP1
OUT
R/O
ON
R/O
RTC
Alarm
R/O
Charger
Present
R/O
HF_PWR
R/O
ADC
Overflow
R/O
ADC
Data
Ready
R/O
19
200945 Version 4 Revision 2
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www.ti.com
LP3941A
LP3941A Serial Port Communication Address Code
LP3941A
Note 13: Registers h’0c, h’0d, h’2e and h’09 bits 3 and 4 are read only (R/O).
Note 14: Register h’0d stores the status of ON, RTC_ALARM, CHG_IN and HF_PWR inputs at the time of PMIC power on event. The bits indicate why the device
turned on, and are static after the power on incident.
ON = 1 means the ON-input was logic high at the moment of power-up-sequence start.
RTC_ALARM = 1 indicates that RTC_ALARM-input was logic high when the power-up-sequence started.
CHG_IN = 1 indicates that external battery charger initiated the power-up-sequence. This also implies that the battery is connected (BSNS = 0V) and that battery
voltage is over 3.0V, because otherwise the circuit will not power up.
HF_POWER = 1 indicates HF_PWR was logic high when the power-up-sequence started.
0 in any register bit position means that the corresponding signal did not initiate the power-up sequence.
Multiple bits can be ‘1’ at the same time if they simultaneously initiated the power-up-sequence.
Note 15: Register h’2e shows the current status of comparator outputs, ADC block, ON-, RTC_ALARM and HF_PWR-inputs. Bit 3 of the register indicates if a
valid external battery charger is connected to the LP3941 at the moment. Register h’2e is dynamic and shows the current status of these variables at all times.
COMP1/2 OUT = 1 means the corresponding comparator input is > threshold (see comparator specification).
ON, RTC_ALARM, HF_PWR = 1 indicates corresponding input pins are logic high.
CHARGER_PRESENT means CHG_IN pin has valid voltage for charging. (See charger specification.)
Note 16: For description on the operation of ADC Overflow and ADC Data Ready bits please see ADC specifications.
Regulator Output Voltage Programming
The following table summarizes the supported output voltages for LP3941A. Default voltages after start-up sequence have been
highlighted in bold.
Data Code
VO1
(V)
VO2
(V)
VO3
(V)
VO4
(V)
VO5
(V)
VO6
(V)
VO7
(V)
VO8
(V)
VO9
(V)
VO10
(V)
VO11
(V)
4h′00
1.5
1.5
2.5
1.5
2.5
2.5
2.5
2.5
1.5
1.5
1.8
4h′01
1.6
1.6
2.6
1.6
2.6
2.6
2.6
2.6
1.6
1.6
1.9
4h′02
1.7
1.7
2.7
1.7
2.7
2.7
2.7
2.7
1.7
1.7
2.0
4h′03
1.8
1.8
2.8
1.8
2.8
2.8
2.8
2.8
1.8
1.8
2.1
4h′04
1.9
1.9
2.9
1.9
2.9
2.9
2.9
2.9
1.9
1.9
2.2
4h′05
2.0
2.0
3.0
2.0
3.0
3.0
3.0
3.0
2.0
2.0
2.3
4h′06
2.1
2.1
3.1
2.1
3.1
3.1
3.1
3.1
2.1
2.1
2.4
4h′07
2.2
2.2
3.2
2.2
3.2
3.2
3.2
3.2
2.2
2.2
2.5
4h′08
2.3
2.3
2.3
2.3
2.3
2.6
4h′09
2.4
2.4
2.4
2.4
2.4
2.7
4h′0a
2.5
2.5
2.5
2.5
2.5
2.8
4h′0b
2.6
2.6
2.6
2.6
2.6
2.9
4h′0c
2.7
2.7
2.7
2.7
2.7
3.0
4h′0d
2.8
2.8
2.8
2.8
2.8
3.1
4h′0e
2.9
2.9
2.9
2.9
2.9
3.2
4h′0f
3.0
3.0
3.0
3.0
3.0
3.3
Register Programming Examples
ADC and Charger Programming
Example 1. Setting register h’00 value to 8h’ff’ will enable
LDOs 1–8.
Example 2. Setting register h’01 to 8h’8c’ will set LDO9 output
to 2.3V and LDO1 output to 2.7V. These voltages will appear
at the LDO outputs if the corresponding LDOs have been enabled. Programming a voltage value to a LDO, which is off,
will affect the LDO output voltage after the LDO is enabled.
Enabling and programming the output voltage are separate
operations.
Example 3. Setting register h’09 bit ‘0’ to ‘1’ will disable the
main battery charger. Note that all register bits have to be
programmed together. It is not possible to program individual
bits alone. Writing into read only or unused bit positions does
not affect those bits nor does it cause errors. Therefore to
disable the main charger and to retain other bits in their default
values on would write 8h‘03’
The following tables show how to select the main battery
charger End-Of-Charge current limit, how to set the charger
current limit and select a particular input for ADC measurement. Default values have been highlighted in bold.
www.ti.com
EOC Current Selection Code
SEL-1
SEL-0
0
1
0.1C
1
0
0.15C
1
1
0.2C
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200945 Version 4 Revision 2
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ISET (mA)
MUX-1
MUX-0
0
0
VBATT
Input
Output Code
0
1
ICHG
Device Temperature +85°C
1
0
BATT-ID (20 µA Scale)
ICHARGE (mA)
0
3.27
1
1
BATT-ID (200 µA Scale)
Output Code
h'00
h'01
ISET (mA)
4h'01
530
4h'02
574
4h'03
617
4h'04
660
4h'05
703
4h'06
746
4h'07
789
4h'08
832
4h'09
874
Battery Voltage (V)
Output Code
Output Code
h'00
h'01
…
ID Resistor (kΩ)
0
3.95
…
834
h'fe
h'ff
3.000
3.006 … 4.494
h'00
h'01
4.500
h'fe
h'ff
Scale 1 (200 µA)
Scale 1 (20 µA)
Data Code Range Data Code Range
0.22
h'00–h'12
0.75
h'13–h'32
1.8
h'33–h'65
3.3
h'66–h'a7
5.1
h'a8–h'ff
10
h'1e–h'31
15
h'32–h'49
1262
1267
22
h'4a–h'6d
h'fe
h'ff
33
h'6e–h'b0
55
h'b1–h'ff
Device Temperature +25°C
ICHARGE (mA)
831
Battery ID Detection Code
ADC Control Register Code 2h'0X
Device Temperature −40°C
4.97
h'ff
The battery ID resistor value can be determined using the following table in the two ADC Battery ID Modes.
A/D Converter's Charge Current Output Code
ADC Control Register Code 2h'0X
0
…
h'fe
A/D Converter's Battery Voltage Output Code
ADC Control Register Code 2h'0X
The following table is the conversion table for main battery
charger current measurement using the on-chip ADC. Temperature dependency is due to the temperature coefficient of
the aluminum sense resistor. The ADC itself is temperature
compensated as is the charging current in the main battery
charger.
ICHARGE (mA)
h'01
The next table shows the relationship between ADC output
code and main battery voltage in ADC Battery Voltage Measurement Mode.
Charger Current Selection Code
Data Code
h'00
1003
1007
ADC Block Functional Diagram
The ADC block provides four different functions on the LP3941A:
•
•
•
•
Main battery voltage measurement
Main battery charger charging current measurement
Battery ID resistor resistance measurement with 200 µA sense current
Battery ID resistor resistance measurement with 20 µA sense current
The following picture shows the implementation of these measurements with the ADC.
21
200945 Version 4 Revision 2
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www.ti.com
LP3941A
A/D Converter's Charge Current Output Code
ADC Control Register Code 2h'0X
A/D Input Selection Code
LP3941A
20094518
I2C Read and Write Sequences
20094528
Format to address LP3941A registers
20094519
Combined read and write format.
www.ti.com
22
200945 Version 4 Revision 2
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LP3941A
Li-Ion Battery Charger Operation
20094520
Charging Profile
Note 17: (*) Battery charging termination voltage level, charging current and End-of-Charging current level are programmable. Battery charging termination voltage
can be 4.1V or 4.2V (default). Maintenance charging start limit is 200 mV below the termination voltage level. End-of-Charging current level can be 20%, 15% or
10% (default) of maximum charging current. Picture shows typical situation with default programming. See LP3941A register map for programming details.
23
200945 Version 4 Revision 2
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www.ti.com
LP3941A
Li-Ion Battery Charger State Diagram
20094521
www.ti.com
24
200945 Version 4 Revision 2
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LP3941A
LP3941A Power-Up/Down Sequences
20094523
Power-up initiated by the ON-signal.
20094522
Power-up initiated by hands free signal, RTC Alarm or charger insertion.
Note 18: If LDO1 does not reach 93% of nominal output level in 60 ms, LP3941A powers down.
Note 19: If PS_HOLD does not go high in 35 ms from RESET high, LP3941A powers down.
Note 20: If UVLO occurs before the rising edge of the PS_HOLD, LP3941A powers down.
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www.ti.com
LP3941A
Note 21: If LDO1 output drops below 85% of nominal output level, LP3941A waits for 90 ms for it to recover to 93% (with RESET = ‘0’) before powering down.
If LDO1 output reaches 93%, power-up sequence resumes with 40 ms RESET delay.
Note 22: LP3941A powers down after PS_HOLD has been low for >35 ms continuously. ON-signal, HF_PWR, CHG_IN or RTC ALARM have no control over
shutdown operation, but it has to be initiated using PS_HOLD.
er is connected or the RTC_ALARM goes high the state
machine advances to the TURNON LDOs state.
Once in the TURNON LDOs state LDOs 1, 3 and 5 are enabled. The state machine remains in this state until LDO1
output reaches 93% of its nominal value or 60 ms have
passed. If LDO1 reaches 93%, the state machine advances
to the RESET OFF DELAY state. If 60 ms have passed before
the 93% level is achieved, the state machine returns to the
STANDBY state and waits for another wakeup source.
The RESET OFF DELAY state counts off 40 ms. If the battery
voltage drops below the UVLO threshold of 2.5V, the state
machine goes to the ENABLE RESET state and power down
sequence. If LDO1 output drops below 85% of the nominal
voltage the state machine returns to the TURNON LDOs state
in an attempt to restart the LDO. If neither of these conditions
occurs the state machine advances to the PS_HOLD DETECT state.
In the PS_HOLD DETECT, RESET is deasserted and the
state machine waits 35 ms for the PS_HOLD signal to go high.
If PS_HOLD goes high within 35 ms of RESET going low the
state machine advances to the IDLE state. If PS_HOLD in still
low after 35 ms the state machine goes to ENABLE RESET
state and the power down sequence. If battery voltage pins
drops below the UVLO threshold, the state machine advances to the ENABLE RESET state and the power down
sequence. If LDO1 output drops below its 85% point the state
machine returns to the TURNON LDOs state in an attempt to
try restart the LDOs.
The state machine remains in the IDLE state until PS_HOLD
goes low for 35 ms. If PS_HOLD is low for less than 35 ms
the state machine remains in the IDLE state. If PS_HOLD
stays low for more than 35 ms, the state machine advances
to the ENABLE RESET state and the power down sequence.
If LDO1 output falls below its 85% point the state machine
returns to the TURNON LDOs state in an attempt to restart
the LDOs. The UVLO is disabled in the IDLE state. The backup battery charger is on.
In the ENABLE RESET state RESET is asserted. After
60 ms all LDOs are turned off. UVLO as well as the back-up
battery charger are on. Once LDO1 falls to its 85% point the
state machine returns to the STANDBY state.
The RTC_LDO is powered by the back-up battery and is always on (unless specifically disabled via the I2C interface).
Power-Up/Down Reason and Status
Register Operation
Register h’0d stores the reason (the activating signal) for
powering up the PMU. The possible inputs that can activate
the LP3941 are the ON, HF_PWR, RTC ALARM and
CHG_IN signals. The signal that activated the LP3941A will
have its corresponding bit set to ‘1’. If multiple signals activate
the PMU simultaneously then they are all marked with ‘1’ in
register h’0d.
Register h’2e maintains the current status of ON, HF_PWR
and RTC_ALARM signals and indicates the presence of an
external charger connected to the PMU. This register shows
the current status of the inputs whereas h’0d indicates the
reason for power-up and remains thereafter static until another power-up sequence occurs.
Register h’2e also indicates the status of the two comparator
outputs and the status of the ADC as well.
Note that the bit indicating the presence of an external charger
voltage in register h’2e differs provides different information
than that in register h’0d. Register h’0d CHG_IN-bit is ‘1’ if
CHG_IN-pin was logic high at start-up. Register h’2e Charger
Present-bit indicates whether the CHG_IN pin voltage is within acceptable limits (4.5V ≤ VCHG_IN ≤ 6.0V) for charging. If
the VCHG_IN is valid for charging then this bit in register h’2e
is set to ‘1’.
Flowchart Operation
The power-up/power-down state machine is reset when
VBATT pin is less than 2.1V. The state machine is reset into
the POWEROFF state. In this state the UVLO in enabled. All
other functions except the RTC_LDO are off.
If an external charger or hands free power is connected, the
state machine advances to the EXTERNAL STANDBY state
and waits for the battery voltage to reach 3.0V. When the battery voltage reaches 3.0V the state machine advances to the
TURNON LDOs state. In the EXTERNAL STANDBY state
UVLO is enabled.
If the battery voltage reaches 3.0V before hands free power
or a charger is connected the state machine advances to the
STANDBY state. The back-up battery charger is enabled. If
the ON-key is pressed, a charger is inserted, hands free pow-
www.ti.com
26
200945 Version 4 Revision 2
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LP3941A
LP3941A Power-Up/Power-Down Flowchart
20094524
27
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www.ti.com
LP3941A
Detailed PU/PD Flowchart
20094525
www.ti.com
28
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LP3941A
20094526
29
200945 Version 4 Revision 2
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www.ti.com
LP3941A
20094527
www.ti.com
30
200945 Version 4 Revision 2
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LP3941A
Physical Dimensions inches (millimeters) unless otherwise noted
48–Pin Leadless Leadframe Package
NS Package Number LQA48B
31
200945 Version 4 Revision 2
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www.ti.com
LP3941A Cellular Phone Power Management Unit
Notes
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