L6563 L6563A Advanced transition-mode PFC controller General features ■ Transition-mode control of PFC pre-regulators ■ Very precise adjustable output overvoltage protection ■ Tracking boost function ■ Protection against feedback loop failure (Latched shutdown) ■ Interface for cascaded converter's PWM controller ■ Input voltage feedforward (1/V2) ■ Remote ON/OFF control ■ Low (≤90µA) start-up current ■ 5mA max. quiescent current ■ 1.5% (@ TJ = 25°C) internal reference voltage ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO ■ SO-14 Applications PFC pre-regulators for: ■ HI-END AC-DC adapter/charger ■ Desktop PC, server, WEB server ■ IEC61000-3-2 OR JEIDA-MITI compliant SMPS, in excess of 250W Order code Part number Package Packaging L6563 SO-14 Tube L6563TR SO-14 Tape & Reel L6563A SO-14 Tube L6563ATR SO-14 Tape & Reel SO14 package Block diagram IN V COM P 1 2 M U LT V FF 3 5 1 / V2 TRACKING BOOST T BO 6 Ideal diode LINE VOLTAGE FEEDFORW ARD 1:1 CURRENT MIRROR 1:1 BUFFER 3V MULTIPLIER + 4 2.5V from V FF V oltage references V O LTA G E R E G U LA TO R LEADING-EDGE BLANKING 1.7V - - + V bias + INDUCTOR SATURATION DETECTION ( not in L6563A ) SAT (INTERNAL SUPPLY BUS) 14 CS Q V CC V CC R R1 GND U VLO C O M P AR A TO R S 13 GD 12 + R2 - D river U V LO V RE F2 S tarter O FF 11 ZE R O C U R R E N T D E TE C TO R - S TA R TE R 0.2V 0.3V + 1.4V 0.7V ZCD 15 V Q + 10 7 SAT FE E D B A C K F A ILU R E D E TE C T IO N - Vbias 8 9 P W M _S TO P November 2006 LATCH + + D IS AB LE 0.52V 0.62V ON/OFF CONTROL (BROWNOUT DETECTION) P FC _O K - RUN 2.5V P W M _LA TC H Rev 3 1/37 www.st.com 37 Contents L6563 - L6563A Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Feedback Failure Protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 Tracking Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 Inductor saturation detection (L6563 only) . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 27 6.8 Summary of L6563/A idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/37 L6563 - L6563A 1 Description Description The device is a current-mode PFC controller operating in Transition Mode (TM). Based on the core of a standard TM PFC controller, it offers improved performance and additional functions. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @TJ = 25°C) internal voltage reference. The stability of the loop and the transient response to sudden mains voltage changes are improved by the voltage feedforward function (1/V2 correction). Additionally, the IC provides the option for tracking boost operation (where the output voltage is changed tracking the mains voltage). The device features extremely low consumption (≤90 µA before start-up and ≤5 mA running). An interface with the PWM controller of the DC-DC converter supplied by the PFC preregulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core saturation) and to disable the PFC stage in case of light load for the DC-DC converter, so as to make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote ON/OFF control both in systems where the PFC pre-regulator works as a master and in those where it works as a slave. In addition to an effective two-step OVP that handles normal operation overvoltages, the IC provides also a protection against feedback loop failures or erroneous output voltage setting. Figure 1. Typical system block diagram 3/37 Description 1.1 L6563 - L6563A Pin connection Figure 2. 1.2 Pin connection (top view) INV 1 14 Vcc COMP 2 13 GD MULT 3 12 GND CS 4 11 ZCD VFF 5 10 RUN TBO 6 9 PWM_STOP PFC_OK 7 8 PWM_LATCH Pin description Table 1. Pin description Pin N° Name Description 1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to change the output voltage so that it tracks the mains voltage. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. 3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. 4 5 4/37 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, shuts down the IC, reduces its consumption almost to the start-up level and asserts PWM_LATCH (pin 8) high. This function is not present in the L6563A. VFF Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak voltage at pin MULT (pin 3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND. L6563 - L6563A Description Table 1. Pin description (continued) Pin N° 1 6 7 Name Description INV Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. The pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to change the output voltage so that it tracks the mains voltage. TBO Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected between this pin and GND defines a current that is sunk from pin INV (pin 1). In this way, the output voltage is changed proportionally to the mains voltage (tracking boost). If this function is not used leave this pin open. PFC_OK PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high. Normal operation can be resumed only by cycling the Vcc. This function is used for protection in case the feedback loop fails. If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V. 8 Output pin for fault signaling. During normal operation this pin features high impedance. If either a voltage above 2.5V at PFC_OK (pin 7) or a voltage above 1.7V on CS (pin 4) of PWM_LATCH L6563A is detected the pin is asserted high. Normally, this pin is used to stop the operation of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of its PWM controller. If not used, the pin will be left floating. 9 Output pin for fault signaling. During normal operation this pin features high impedance. If the IC is disabled by a voltage below 0.5V on RUN (pin 10) the voltage at the pin is pulled PWM_STOP to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC converter supplied by the PFC pre-regulator by disabling its PWM controller. If not used, the pin will be left floating. 10 RUN Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC restarts as the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin 5) either directly or through a resistor divider to use this function as brownout (AC mains undervoltage) protection, tie to INV (pin 1) if the function is not used. 11 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negativegoing edge triggers MOSFET’s turn-on. 12 GND Ground. Current return for both the signal part of the IC and the gate driver. 13 GD 14 VCC Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages. Supply Voltage of both the signal part of the IC and the gate driver. 5/37 Absolute maximum ratings 2 L6563 - L6563A Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Pin VCC 14 --- Parameter Value Unit self-limited V -0.3 to 8 V Self-limited V 3 mA -10 (source) 10 (sink) mA 0.75 W Junction temperature operating range -25 to 150 °C Storage temperature -55 to 150 °C Value Unit 120 ° C/W IC supply voltage (Icc = 20mA) 2, 4 to 6, 8 Analog inputs & outputs to 10 Max. pin voltage (Ipin = 1 mA) --- 1, 3, 7 IPWM_STOP 10 Max. sink current IZCD 11 Zero current detector max. current Power dissipation @TA = 50°C Ptot TJ TSTG 3 Thermal data Table 3. Thermal data Symbol RthJA 6/37 Parameter Maximum thermal resistance junction-ambient L6563 - L6563A 4 Electrical characteristics Electrical characteristics Table 4. Electrical characteristics ( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF and GND; unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit 22 V Supply voltage Vcc Operating range After turn-on VccOn Turn-on threshold (1) 11 12 13 V VccOff Turn-off threshold (1) 8.7 9.5 10.3 V 2.7 V 25 28 V Hys Hysteresis VZ Zener Voltage 10.3 2.3 Icc = 20 mA 22 Supply current Istart-up Iq ICC Iqdis Iq Start-up current Before turn-on, Vcc=10V 50 90 µA Quiescent current After turn-on 3 5 mA 3.8 5.5 mA Latched by PFC_OK>Vthl or Vcs>VCSdis 180 250 µA Disabled by PFC_OK<Vth or RUN<VDIS 1.5 2.2 mA 2 3 mA -0.2 -1 µA Operating supply current @ 70kHz Idle state quiescent Current Quiescent current During static/dynamic OVP Multiplier input IMULT Input bias current VMULT Linear operation range VMULT = 0 to 3 V 0 to 3 VCLAMP Internal clamp level IMULT = 1 mA ∆V cs -------------------∆V MULT Output max. slope VMULT=0 to 0.5V, VFF=0.8V VCOMP = Upper clamp Gain (3) KM V 9 9.5 V 2.2 2.34 V/V VMULT = 1 V, VCOMP= 4 V, VVFF = VMULT 0.375 0.45 0.525 Voltage feedback input threshold Tj = 25 °C 2.465 2.5 2.535 10.3 V < Vcc < 22 V (2) 2.44 Line regulation Vcc = 10.3 V to 22V Input bias current TBO open, VINV = 0 to 4 V V Error amplifier VINV IINV V 2.56 2 5 mV -0.2 -1 µA 7/37 Electrical characteristics L6563 - L6563A Table 4. Electrical characteristics (continued) ( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF and GND; unless otherwise specified) Symbol Parameter VINVCLAMP Internal clamp level Gv Voltage gain GB Gain-bandwidth product ICOMP VCOMP Test condition Min Typ Max Unit IINV = 1 mA 9 9.5 V Open loop 60 80 dB 1 MHz Source current VCOMP = 4V, VINV = 2.4 V -2 -3.5 Sink current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 Upper clamp voltage ISOURCE = 0.5 mA 5.7 6.2 6.7 V Lower clamp voltage ISINK = 0.5 mA (2) 2.1 2.25 2.4 V -1 µA 300 ns -5 mA mA Current sense comparator ICS Input bias current tLEB Leading edge blanking td(H-L) 100 Delay to output VCSclamp Current sense reference clamp Vcsoffset Current sense offset VCSdis VCS = 0 Ic latch-off level (L6563 only) 200 120 VCOMP = Upper clamp, VVFF = VMULT =0.5V 1.0 1.08 VMULT = 0, VVFF = 3V 25 VMULT = 3V, VVFF = 3V 5 (2) ns 1.16 V mV 1.6 1.7 1.8 V 17 20 23 µA Output overvoltage IOVP Dynamic OVP triggering current Hys Hysteresis (4) Static OVP threshold (2) 15 2 2.15 µA 2.3 V 3 V 20 mV Voltage feedforward VVFF ∆V 8/37 Linear operation range Dropout VMULTpk-VVFF RFF=47 kΩ to GND 0.5 L6563 - L6563A Electrical characteristics Table 4. Electrical characteristics (continued) ( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF and GND; unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit Zero current detector VZCDH Upper clamp voltage IZCD = 2.5 mA 5.0 5.7 VZCDL Lower clamp voltage IZCD = - 2.5 mA -0.3 0 VZCDA Arming voltage (positive-going edge) (4) 1.4 V VZCDT Triggering voltage (negative-going edge) (4) 0.7 V IZCDb Input bias current VZCD = 1 to 4.5 V V 0.3 1 V µA IZCDsrc Source current capability -2.5 mA IZCDsnk Sink current capability 2.5 mA Tracking boost function ∆V Dropout voltage VVFF - VTBO ITBO Linear operation IINV - ITBO current mismatch VTBOclamp Clamp voltage ITBO = 0.25 mA 20 mV 0 0.25 mA ITBO = 25 µA to 0.25 mA -3.5 3.5 % (2) VVFF = 4V 2.9 3 3.1 V 2.4 2.5 2.6 V PFC_OK Vthl Latch-off threshold (2) voltage rising Vth Disable threshold (2) voltage falling 0.2 V VEN Enable threshold (2) voltage rising 0.26 V IPFC_OK Input bias current VPFC_OK = 0 to 2.5V -0.1 Clamp voltage IPFC_OK = 1 mA Vclamp 9 -1 9.5 µA V PWM_LATCH Ileak Low level leakage current VPWM_LATCH=0 VH High level IPWM_LATCH = -0.5 mA -1 3.7 µA V PWM_STOP Ileak High level leakage current VPWM_STOP = 6V 1 µA VL Low level IPWM_STOP = 0.5 mA 1 V Clamp voltage IPFC_OK = 2 mA Vclamp 9 9.5 V 9/37 Electrical characteristics L6563 - L6563A Table 4. Electrical characteristics (continued) ( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF and GND; unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit -1 µA Run function IRUN Input bias current VRUN = 0 to 3 V VDIS Disable threshold (2) voltage falling 0.5 0.52 0.54 V VEN Enable threshold (2) voltage rising 0.56 0.6 0.64 V 75 150 300 µs IGDsource = 20 mA 2 2.6 V IGDsource = 200 mA 2.5 3 V 1 2 V Start timer tSTART Start timer period Gate driver VOHdrop Dropout voltage VOLdrop IGDsink = 200 mA tf Current fall time 30 70 ns tr Current rise time 40 80 ns 12 15 V 1.1 V VOclamp Output clamp voltage IGDsource = 5mA; Vcc = 20V UVLO saturation Vcc=0 to VccOn, Isink=10mA 10 (1), (2) Parameters tracking each other (3) The multiplier output is given by: V MULT ⋅ ( V COMP – 2.5 ) V CS = K M ⋅ --------------------------------------------------------------2 V VFF (4) Parameters guaranteed by design, functionality tested in production. 10/37 L6563 - L6563A Typical electrical performance 5 Typical electrical performance Figure 3. Supply current vs supply voltage Figure 4. VCC Zener voltage vs TJ Ic c (m A ) V ccz (p in 14 ) (V ) 2 8 10 27 5 26 1 0 .5 25 0 .1 24 0 .0 5 Co = 1nF f = 70 kH z T j = 2 5 °C 0 .0 1 0 .0 0 5 23 0 0 Figure 5. Ic c 5 10 15 Vc c (V ) 20 22 -5 0 25 0 50 IC consumption vs TJ Figure 6. 150 Feedback reference vs TJ V R E F (p in 1 ) (V ) 2 .6 10 (m A ) O p e ra tin g 5 Vcc = 12 V Q u ie s c e n t 2 2 .5 5 1 D is a b le d o r d u rin g O V P Vcc = 12 V Co = 1 nF f = 70 kH z 0 .5 2 .5 L a tc h e d o ff 0 .2 0 .1 2 .4 5 B e fo re s ta rt-u p 0 .0 5 0 .0 2 -5 0 0 50 100 2 .4 -5 0 150 0 T j (°C ) Figure 7. 100 T j (°C ) 50 100 150 T j (°C ) Start-up & UVLO vs TJ Figure 8. E/A output clamp levels vs TJ V C O M P (p in 2) 12.5 VCC-ON (V) 12 (V ) 7 6 U p p e r cla m p 11.5 V cc = 1 2 V 5 11 4 10.5 10 3 V CC-OFF 9.5 (V) 2 9 -50 0 50 Tj (°C) 100 150 1 -5 0 Lo w e r cla m p 0 50 100 150 T j (°C ) 11/37 Typical electrical performance Figure 9. L6563 - L6563A Static OVP level vs TJ Figure 10. Vcs clamp vs TJ V C S x (p in 4 ) (V ) 1 .5 V C O M P (p in 2) (V ) 2 .5 2 .4 Vcc = 12 V 2 .3 1 .3 2 .2 1 .2 2 .1 1 .1 2 -5 0 0 50 100 Vcc = 12 V V C O M P = U p p e r c la m p 1 .4 1 -5 0 15 0 0 T j (°C ) Figure 11. Dynamic OVP current vs TJ (normalized value) IO V P 50 100 150 T j (°C ) Figure 12. Current-sense offset vs mains voltage phase angle V C S offs et (p in 4 ) 120% (m V ) Vcc = 12 V 30 V c c = 12 V T j = 25 ° 25 110% V M U LT = 0 to 3V V F F = 3V 20 100% 15 V M U LT = 0 to 0.7 V V F F = 0.7 V 10 90% 5 80% -5 0 0 50 100 0 150 0 0 .628 Figure 13. Delay-to-output vs TJ tD (H -L) (ns) 2 .512 3 .14 V p in 4 2 .0 (V ) Vcc = 12 V V cc = 12 V 250 1 .8 200 1 .6 150 1 .4 100 1 .2 0 50 Tj (°C ) 12/37 1 .884 Figure 14. Ic latch-off level on current sense vs TJ (L6563 only) 300 50 -50 1 .256 θ ( °) T j (°C ) 100 150 1 .0 -5 0 0 50 T j (°C ) 100 150 L6563 - L6563A Typical electrical performance Figure 15. Multiplier characteristics @ VFF = 1V Figure 16. ZCD clamp levels vs TJ VC S (pin 4 ) VC O M P (pin 2 ) (V ) (V ) u p pe r vo ltag e clam p V cc = 12 V T j = 25 °C 1 V Z C D (p in 1 1 ) 7 (V ) 5 .5 U p p e r c la m p 6 5 .0 5 4 .5 0.8 Vcc = 12 V IZ C D = ± 2 .5 m A 4 4 .0 3 0.6 2 3.5 0.4 1 3.0 0.2 L o w e r c la m p 0 2.6 0 0 0.2 0.4 0.6 0.8 1 -1 -5 0 1.2 0 VM U LT (pin 3) (V ) 50 100 150 T j (°C ) Figure 17. Multiplier characteristics @ VFF = 3V Figure 18. ZCD source capability vs TJ V C S (pin 4) VC O M P (pin 2) (V ) upper voltage clam p V cc = 12 V Tj = 25 °C 0.5 (V ) I Z C D src (m A ) 0 V cc = 12 V V Z C D = lo w er c la m p 5.5 0.4 5.0 0.3 4.5 -2 -4 4.0 0.2 3.5 0.1 0 -6 3.0 2.6 0 0.5 1 1.5 2 2.5 3 -8 -5 0 3.5 0 VM U LT (pin 3) (V ) Figure 19. Multiplier gain vs TJ KM 50 10 0 15 0 T j (°C ) Figure 20. VFF & TBO dropouts vs TJ (m V ) 6 1 V pin6 - V pin5 V cc = 12 V V COMP =4 V V M U LT = V FF = 1 V 0 .8 4 0 .6 V cc = 12 V V pin3 = 2.9 V 2 0 .4 V pin5 - V pin3 0 0 .2 0 -5 0 0 50 T j (°C ) 100 150 -2 -50 0 50 100 150 Tj (°C ) 13/37 Typical electrical performance L6563 - L6563A Figure 21. TBO current mismatch vs TJ 100· Figure 22. RUN thresholds vs TJ I(INV)-I(TBO ) I(INV) V p in 1 0 (V ) -0.8 1 .0 Vcc = 12 V -1.0 V cc = 12 V 0 .8 -1.2 0 .6 -1.4 ITBO = 250 µA ON O FF -1.6 0 .4 -1.8 -2.0 0 .2 ITBO = 25 µA -2.2 -2.4 -50 0 50 100 0 .0 -5 0 150 0 Figure 23. TBO-INV current mismatch vs TBO currents 100· 50 I(IN V )-I(TBO ) I(IN V ) 150 Figure 24. PWM_LATCH high saturation vs TJ V p in 8 5 .3 (V ) -1 .6 V cc = 12 V 5 .2 V cc = 12 V T j = 25 °C -1 .7 5 .1 Is o u rc e = 5 0 µ A -1 .8 5 .0 -1 .9 4 .9 -2 .0 4 .8 -2 .1 4 .7 4 .6 -2 .2 -2 .3 100 T j (°C ) Tj (°C) 0 10 0 20 0 300 400 500 4 .5 -5 0 600 Is o u rc e = 5 0 0 µ A 0 50 100 150 T j (°C ) I(TB O ) Figure 25. TBO clamp vs TJ Figure 26. PWM_STOP low saturation vs TJ V p in 9 05.5.00 V p in 6 3 .5 (V ) (V ) Vcc = 12 V Is in k = 0 .5 m A 04.4.00 3 .2 5 03.3.00 3 02.2.00 V cc = 12 V V p in 3 = 4 V 2 .7 5 2 .5 -5 0 0 50 T j (°C ) 14/37 100 01.1.00 150 0 .00 -5 0 0 50 T j (°C ) 100 150 L6563 - L6563A Typical electrical performance Figure 27. PFC_OK thresholds vs TJ Figure 28. UVLO saturation vs TJ V p in7 (V ) 3 .0 Vpin15 (V) 1.1 Vcc = 0 V L atch-off 2 .0 1 V c c = 12 V 1 .0 0.9 0 .5 0.8 0 .3 0.7 ON 0 .2 0.6 OFF 0 .1 -5 0 0 50 10 0 0.5 -50 15 0 0 50 100 150 Tj (°C) T j (°C ) Figure 29. Start-up timer vs TJ Figure 30. Gate-drive output low saturation V p in15 (V ) Tstart 150 (µs) 4 Vcc = 12 V T j = 25 °C Vcc = 11 V S IN K 140 3 130 2 120 1 110 100 -50 0 50 100 150 0 0 2 00 4 00 6 00 8 00 1,00 0 I G D (m A ) Tj (°C ) Figure 31. Gate-drive clamp vs TJ Figure 32. Gate-drive output high saturation Vpin15 clam p (V) 12 Vpin15 (V) -1.5 Vcc = 20 V Tj = 25 °C Vcc = 11 V SOURCE -2 Vcc - 2.0 11.5 Vcc --2.5 2.5 -3 Vcc - 3.0 11 Vcc --3.5 3.5 10.5 -4 Vcc - 4.0 -4.5 10 -50 0 50 Tj (°C) 100 150 0 100 200 300 400 500 600 700 IGD (mA) 15/37 Application information L6563 - L6563A 6 Application information 6.1 Overvoltage protection Normally, the voltage control loop keeps the output voltage VO of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. Neglecting the ripple components, under steady state conditions the current through R1 equals that through R2. Considering that the non-inverting input of the error amplifier is internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then: Equation 1 V O – 2.5 I R2 = I R1 = 2.5 -------- = --------------------R1 R2 If the output voltage experiences an abrupt change ∆Vo the voltage at pin INV is kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant. Then the current through R2 remains equal to 2.5/R2 but that through R1 becomes: Equation 2 V O – 2.5 + ∆V O I' R1 = --------------------------------------R1 The difference current ∆IR1 = I’R1 - I’R1 = ∆VO/R1 will flow through the compensation network and enter the error amplifier (pin COMP). This current is monitored inside the IC and when it reaches about 18 µA the output voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 20 µA, the OVP is triggered (Dynamic OVP), and the external power transistor is switched off until the current falls approximately below 5 µA. However, if the overvoltage persists (e.g. in case the load is completely disconnected), the error amplifier will eventually saturate low hence triggering an internal comparator (Static OVP) that will keep the external power switch turned off until the output voltage comes back close to the regulated value. The output overvoltage that is able to trigger the OVP function is then: Equation 3 ∆VO = R1 · 20 · 10-6 16/37 L6563 - L6563A Application information An important advantage of this technique is that the overvoltage level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 15%, which means 15% tolerance on the ∆VO. Since it is usually much smaller than Vo, the tolerance on the absolute value will be proportionally reduced. Example: VO = 400V, ∆VO = 40V. Then: R1 = 40V/20µA = 2MΩ ; R2 = 2.5·2MΩ·/(400-2.5) = 12.58kΩ. The tolerance on the OVP level due to the L6563/A will be 40·0.15 = 6 V, that is ± 1.36%. When either OVP is activated the quiescent consumption is reduced to minimize the discharge of the Vcc capacitor. Figure 33. Output voltage setting, OVP and FFP functions: internal block diagram Vout R3b { 0.26V R1b + FAULT (not latched) PFC_OK 7 + 9.5V FAULT (latched) 2.25V 9.5V ITBO Static OVP + Dynamic OVP - 2.5V INV 1 + E/A - + { R1 - R3 R1a + R3a TBO FUNCTION 20 µA 2 L6563 L6563A COMP Frequency Compensation R4 R2 17/37 Application information 6.2 L6563 - L6563A Feedback Failure Protection (FFP) The OVP function above described is able to handle "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. It cannot handle the overvoltage generated, for instance, when the upper resistor of the output divider (R1) fails open: the voltage loop can no longer read the information on the output voltage and will force the PFC pre-regulator to work at maximum ON-time, causing the output voltage to rise with no control. A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 33). This divider is selected so that the voltage at the pin reaches 2.5V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected, also including worst-case load/line transients. Example: VO = 400 V, Vox = 475V. Select: R3 = 3MΩ; then: R4 = 3MΩ ·2.5/(475-2.5) = 15.87kΩ. When this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 250 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver 3.7V min. with 0.5 mA load, intended for tripping a latched shutdown function of the PWM controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. To restart the system it is necessary to recycle the input power, so that the Vcc voltages of both the L6563/A and the PWM controller go below their respective UVLO thresholds. The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will shut down the IC, reducing its consumption below 1 mA. In this case both PWM_STOP and PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at the pin go above 0.26 V. Note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator. 6.3 Voltage Feedforward The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc ≅ 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage Feedforward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 34). 18/37 L6563 - L6563A Application information Figure 34. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic Rectified mains E/A output (VCOMP) current reference (Vcsx) MULTIPLIER R5 Vcsx 2 VCOMP=4V 1.5 "ideal" diode - 1/V 2 1 + 9.5V L6563 L6563A Actual Ideal 3 MULT R6 0.5 5 VFF CFF RFF 0 0 0.5 1 2 3 4 VFF=VMULT In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF); if it is too large there will be a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-off is required. The device realizes Voltage Feedforward with a technique that makes use of just two external parts and that limits the feedforward time constant trade-off issue to only one direction. A capacitor CFF and a resistor RFF , both connected from the VFF (pin 5) pin to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (pin 3). RFF provides a means to discharge CFF when the line voltage decreases (see Figure 34). In this way, in case of sudden line voltage rise, CFF will be rapidly charged through the low impedance of the internal diode and no appreciable overshoot will be visible at the pre-regulator's output; in case of line voltage drop CFF will be discharged with the time constant RFF·CFF, which can be in the hundred ms to achieve an acceptably low steady-state ripple and have low current distortion; consequently the output voltage can experience a considerable undershoot, like in systems with no feedforward compensation. 19/37 Application information L6563 - L6563A The twice-mains-frequency (2·fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by: Equation 4 2V MULTpk ∆V FF = --------------------------------------1 + 4f L R FF C FF where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2·fL component, will be: Equation 5 100 D 3 % = -------------------------------2πf L R FF C FF Figure 35 shows a diagram that helps choose the time constant RFF·CFF based on the amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the pin, the IC will not work properly if the pin is either left floating or connected directly to ground. Figure 35. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current 10 1 fL=50 Hz RFF· CFF [s] 0.1 fL=60 Hz 0.01 0.1 1 10 D3% The dynamics of the voltage feedforward input is limited downwards at 0.5V (see Figure 34), that is the output of the multiplier will not increase any more if the voltage on the VFF pin is below 0.5V. This helps to prevent excessive power flow when the line voltage is lower than the minimum specified value 20/37 L6563 - L6563A 6.4 Application information THD optimizer circuit The L6563/A is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 36. THD optimization: standard TM PFC controller (left side) and L6563/A (right side) Input current Input current Rectified mains voltage Imains Input current Rectified mains voltage Imains Input current MOSFET's drainVdrain voltage MOSFET's drainVdrain voltage 21/37 Application information L6563 - L6563A Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is modulated by the voltage on the VFF pin (see Section 6.3 on page 18 section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. The effect of the circuit is shown in Figure 36, where the key waveforms of a standard TM PFC controller are compared to those of this chip. To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness of the optimizer circuit. 6.5 Tracking Boost function In some applications it may be advantageous to regulate the output voltage of the PFC preregulator so that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators. This is commonly referred to as "tracking boost" or "follower boost" approach. With this IC the function can be realized by connecting a resistor (RT) between the TBO pin and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to V(TBO)/RT, that is internally 1:1 mirrored and sunk from pin INV (pin 1) input of the error amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connected between TBO and GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC preregulator will be forced to get higher. Obviously, the output voltage will move in the opposite direction if the input voltage decreases. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. If this function is not used, leave the pin open: the device will regulate a fixed output voltage. Starting from the following data: 22/37 ● Vin1 = minimum specified input RMS voltage; ● Vin2 = maximum specified input RMS voltage; ● Vo1 = regulated output voltage @ Vin = Vin1; ● Vo2 = regulated output voltage @ Vin = Vin2; ● Vox = absolute maximum limit for the regulated output voltage; ● ∆Vo = OVP threshold, L6563 - L6563A Application information to set the output voltage at the desired values use the following design procedure: 1. Determine the input RMS voltage Vinclamp that produces Vo = Vox: Equation 6 Vox – Vo 1 Vox – Vo 2 Vin clamp = --------------------------- ⋅ Vin 2 – --------------------------- ⋅ Vin 1 Vo 2 – Vo 1 Vo 2 – Vo 1 and choose a value Vinx such that Vin2 = Vinx < Vinclamp. This will result in a limitation of the output voltage range below Vox (it will equal Vox if one chooses Vinx = Vinclamp) 2. Determine the divider ratio of the MULT pin (pin 3) bias: Equation 7 3 k = -------------------------2 ⋅ Vin x and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than 0.65V. 3. Determine R1, the upper resistor of the output divider: Equation 8 ∆Vo 6 R1 = ----------- ⋅ 10 20 4. Calculate the lower resistor R2 of the output divider and the adjustment resistor RT: Equation 9 Vin 2 – Vin 1 R2 = 2.5 ⋅ R1 ⋅ -------------------------------------------------------------------------------------------------------( Vo 1 – 2.5 ) ⋅ Vin 2 – ( Vo 2 – 2.5 ) ⋅ Vin 1 RT = Vin 2 – Vin 1 2 ⋅ k ⋅ R1 ⋅ -----------------------------Vo 2 – Vo 1 23/37 Application information 5. L6563 - L6563A Check that the maximum current sourced by the TBO pin (pin 6) does not exceed the maximum specified (0.25mA): Equation 10 3 –3 I TBOmax = ------- ≤0.25 ⋅ 10 RT In the following Mathcad® sheet, as an example, the calculation is shown for the circuit illustrated in Figure 39 shows the internal block diagram of the tracking boost function. Design data Vin1 := 88V Vo1:= 200V Vin2 := 264V Vo2:= 385V Vox ;= 400V ∆Vo ;= 40V Step 1 Vox – Vo 1 Vox – Vo 2 Vin clamp : = --------------------------- ⋅ Vin 2 – --------------------------- ⋅ Vin 1 Vo 2 – Vo 1 Vo 2 – Vo 1 Vinclamp = 278.27V choose: Vinx: = 270V Step 2 3 k: = ------------------------2 ⋅ Vin x k = 7.857 x 10-3 Step 3 ∆Vo 6 R1: = ----------- ⋅ 10 20 24/37 R1 = 2 x 106 Ω L6563 - L6563A Application information Step 4 Vin 2 – Vin 1 R2: = 2.5 ⋅ R1 ⋅ -------------------------------------------------------------------------------------------------------( Vo 1 – 2.5 ) ⋅ Vin 2 – ( Vo 2 – 2.5 ) ⋅ Vin 1 RT : = k ⋅ R2 = 4.762 x 104 Ω RT = 2.114 x 104 Ω Vin 2 – Vin 1 2 ⋅ R1 ⋅ -----------------------------Vo 2 – Vo 1 Step 5 3 3 I TBOmax : = ------- ⋅ 10 RT Vo(Vi): = ITBOmax = 0.142 mA V MULTpk ←k ⋅ 2 ⋅ Vi Vo(Vin1) = 200V V TBO ←if ( V MULTpk < 3,V MULTpk ,3 ) Vo(Vin2) = 385V R1 2.5 ⋅ ⎛ 1 + R1 --------⎞ + V TBO ⋅ -------⎝ RT R2⎠ Vo(VinX) = 391.307V Figure 37. Processing result 25/37 Application information L6563 - L6563A Figure 38. 80W, wide-range-mains PFC pre-regulator with tracking boost function active Figure 39. Tracking boost and voltage feedforward blocks 6.6 Inductor saturation detection (L6563 only) Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current upslope becomes so large (50-100 times steeper, see Figure 40) that during the current sense propagation delay the current may reach abnormally high values. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the MOSFET may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. However, in some applications such as ac-dc adapters, where the PFC pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may occasionally slightly saturate when the PFC stage is restarted because of a larger load demand. This happens when the restart occurs at an unfavorable line voltage phase, so that the output voltage may drop significantly below the rectified peak voltage. As a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. 26/37 L6563 - L6563A Application information To cope with a saturated inductor, the L6563 is provided with a second comparator on the current sense pin (CS, pin 4) that stops and latches off the IC if the voltage, normally limited within 1.1V, exceeds 1.7V. Also the cascaded DC-DC converter can be stopped via the PWM_LATCH pin that is asserted high. In this way the entire system is stopped and enabled to restart only after recycling the input power, that is when the Vcc voltages of the L6563 and the PWM controller go below their respective UVLO thresholds. System safety will be considerably increased. To better suit the applications where a certain level of saturation of the boost inductor needs to be tolerated, the L6563A does not support this protection function. Figure 40. Effect of boost inductor saturation on the MOSFET current and detection method 6.7 Power management/housekeeping functions A special feature of this IC is that it facilitates the implementation of the "housekeeping" circuitry needed to coordinate the operation of the PFC stage to that of the cascaded DCDC converter. The functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power down sequencing or failures of either power stage be properly handled. This device provides some pins to do that. As already mentioned, one communication line between the IC and the PWM controller of the cascaded DC-DC converter is the PWM_LATCH pin, which is normally open when the PFC works properly and goes high if it loses control of the output voltage (because of a failure of the control loop) or if the boost inductor saturates, with the aim of latching off the PWM controller of the cascaded DC-DC converter as well (Section 6.2: Feedback Failure Protection (FFP) on page 18 for more details). A second communication line can be established via the disable function included in the PFC_OK pin (Section 6.2 on page 18 for more details ). Typically this line is used to allow the PWM controller of the cascaded DC-DC converter to shut down the L6563/A in case of light load, to minimize the no-load input consumption. Should the residual consumption of the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits like those shown in Figure 41, where the L6563/A works along with the L5991, PWM controller with standby function, can be used. Needless to say, this operation assumes that the cascaded DC-DC converter stage works as the master and the PFC stage as the slave or, in other words, that the DC-DC stage starts first, it powers both controllers and enables/disables the operation of the PFC stage. 27/37 Application information L6563 - L6563A Figure 41. Interface circuits that let DC-DC converter’s controller IC disable the L6563/A at light load The third communication line is the PWM_STOP pin (pin 9), which works in conjunction with the RUN pin (pin 10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded DC-DC converter. The pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0.52V on the RUN pin. It is important to point out that this function works correctly in systems where the PFC stage is the master and the cascaded DC-DC converter is the slave or, in other words, where the PFC stage starts first, powers both controllers and enables/disables the operation of the DC-DC stage. This function is quite flexible and can be used in different ways. In systems comprising an auxiliary converter and a main converter (e.g. desktop PC's silver box or hi-end LCD-TV), where the auxiliary converter also powers the controllers of the main converter, the pin RUN can be used to start and stop the main converter. In the simplest case, to enable/disable the PWM controller the PWM_STOP pin can be connected to either the output of the error amplifier (Figure 42 a) or, if the chip is provided with it, to its soft-start pin (Figure 42 b). The use of the soft-start pin allows the designer to delay the start-up of the DC-DC stage with respect to that of the PFC stage, which is often desired. An underlying assumption in order for that to work properly is that the UVLO thresholds of the PWM controller are certainly higher than those of the L6563/A. 28/37 L6563 - L6563A Application information Figure 42. Interface circuits that let the L6563/A switch on or off a PWM controller If this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the DC-DC stage from starting up correctly) or, simply, the PWM controller is devoid of soft start, the arrangement of Figure 43 lets the DC-DC converter start-up when the voltage generated by the PFC stage reaches a preset value. The technique relies on the UVLO thresholds of the PWM controller. Figure 43. Interface circuits for actual power-up sequencing (master PFC) Another possible use of the RUN and PWM_STOP pins (again, in systems where the PFC stage is the master) is brownout protection, thanks to the hysteresis provided. Brownout protection is basically a not-latched device shutdown function that must be activated when a condition of mains undervoltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shutdown the unit in case of brownout. 29/37 Application information L6563 - L6563A IC shutdown upon brownout can be easily realized as shown in Figure 44 The scheme on the left is of general use, the one on the right can be used if the bias levels of the multiplier and the RFF·CFF time constant are compatible with the specified brownout level and with the specified holdup time respectively. In it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. Figure 44. Brownout protection (master PFC) 6.8 Summary of L6563/A idle states . Table 5. Summary of L6563/A idle states 30/37 Condition Caused or revealed by PWM_LATCH (pin 8) PWM_STOP (pin 9) Typical IC consumption IC behavior UVLO Vcc < 8.7 V Open Open 50 µA Auto-restart Feedback disconnected PFC_OK > 2.5 V Active (high) Open 180 µA Latched Saturated Boost Inductor Vcs > 1.7 V (L6563 only) Active (high) (L6563 only) Open 180 µA (L6563 only) Latched (L6563 only) AC Brownout RUN < 0.52 V Open Active (low) 1.5 mA Auto-restart Standby PFC_OK < 0.2 V Open Open 1.5 mA Auto-restart L6563 - L6563A 7 Application examples and ideas Application examples and ideas Figure 45. Demo board (EVAL6563-80W) 80W, Wide-range, Tracking Boost: Electrical schematic Figure 46. EVAL6563-80W: PCB and component layout (Top view, real size: 64 x 94 mm) 31/37 Application examples and ideas L6563 - L6563A Figure 47. EVAL6563-80W: PCB layout, soldering side (Top view) Table 6. EVAL6563-80W: Evaluation results at full load Note: Vin (VAC) Pin (W) Vo (VDC) ∆Vo (Vpk-pk) Po (W) η(%) PF THD (%) 90 85.3 219.4 16.6 79.64 93.4 0.999 3.7 115 84.9 244.1 15.0 80.80 95.2 0.998 4.3 135 83.7 263.7 13.9 80.16 95.8 0.997 4.8 180 83.5 307.6 14.5 80.28 96.1 0.993 6.0 230 85.2 356.7 13.0 81.33 95.5 0.984 7.7 265 85.0 390.6 12.1 80.85 95.1 0.974 9.5 Measurements done with the line filter shown in Figure 49. Table 7. EVAL6563-80W: Evaluation results at half load Note: 32/37 Vin (VAC) Pin (W) Vo (VDC) ∆Vo (Vpk-pk) Po (W) η(%) PF THD (%) 90 43.4 219.9 8.6 40.90 94.2 0.997 4.8 115 42.6 244.5 7.7 40.10 94.1 0.994 5.7 135 43.1 264.0 7.3 40.39 93.7 0.989 6.5 180 43.8 307.7 7.7 40.31 92.0 0.978 8.4 230 45.6 356.8 6.8 41.03 90.0 0.951 9.6 265 46.0 390.7 6.7 40.63 88.3 0.920 14.2 Measurements done with the line filter shown in Figure 49. L6563 - L6563A Application examples and ideas Figure 48. EVAL6563-80W: Vout vs. Vin relationship (tracking boost) Figure 49. Line filter (not tested for EMI compliance) used for EVAL6563-80W evaluation Figure 50. 250W, wide-range-mains PFC pre-regulator with fixed output voltage D1 1N5406 L1 D2 STTH5L06 R1A 820 kΩ FUSE 8A/250V B1 KBU8M + R3 47 kΩ R1B 820 kΩ C1 1 µF 400V 2 R11B 1.87 MΩ 1 7 14 D3 1N4148 6 1 µF L6563 3 Vac 88V to 264V 5 10 8 9 C8 150 µF 450 V R6 33 Ω 13 R7 390 kΩ R11A 1.87 MΩ R9B 1 MΩ R5 C4 6.8 kΩ 1 µF 11 C2 Vout = 400V Pout = 250 W R9A 1 MΩ R4 1 MΩ Vcc 10.3 to 22 V NTC1 2.5 Ω 12 4 M1 STP12NM50 C6 470 nF 630 V C7 10 nF R2 10 kΩ C3 10nF C5 470nF R8A,B 0.22 Ω 1W R10 12.7 kΩ R12 20 kΩ Boost Inductor (L1) Spec ETD29x16x10 core, 3C85 ferrite or equivalent 1.5 mmgap for 150 µH primary inductance Primary: 74 turns 20xAWG30 (∅ 0.3 mm) Secondary: 8 turns 0.1 mm 33/37 Application examples and ideas L6563 - L6563A Figure 51. 350W, wide-range-mains PFC pre-regulator with fixed output voltage and FOT control D1 1N5406 L1 D2 STTH806DTI NTC1 2.5 Ω R13A 1 MΩ R4 1 MΩ R1A 620 kΩ B1 FUSE KBU8M + 8A/250V R1B 620 kΩ C1 1 µF 400V 14 8 9 1 7 6 L6563 - 5 C3 10nF C4 470nF D4 1N4148 12 4 11 R6 1.5 kΩ R8 1.5 kΩ D5 M1A STP12NM50 R7 12 kΩ C7 560 pF C8 330 pF M1B STP12NM50 C10 10 nF R11 330 Ω R12A,B,C 0.33 Ω 1W R14 12.7 kΩ L1: core E42*21*15, B2 material 1.9 mmair gap on centre leg, main winding inductance 0.55 mH 58 T of 20 x AWG32 (∅0.2 mm) Figure 52. Demagnetization sensing without auxiliary winding Figure 53. Enhanced turn-off for big MOSFET driving Vcc 14 13 GD Q DRIVER BC327 L6563 L6563A 12 GND 34/37 C11 220 µF 450 V C9 470 nF 630 V R10 6.8 Ω 1N4148 C6 330 pF TR1 BC557 R2 10 kΩ R9 6.8 Ω 13 10 R3 390 kΩ R15B 1.87 MΩ D3 1N4148 C2 1 µF 3 Vac 88V to 264V 2 R15A 1.87 MΩ R13B 1 MΩ R5 C5 6.8 kΩ 1 µF Vcc 10.3 to 22 V Vout = 400V Pout = 350W Rs R16 20 kΩ L6563 - L6563A 8 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Table 8. SO-14 Mechanical data mm. Dim. Min Typ inch Max Min Typ Max A 1.35 1.75 0.053 0.069 A1 0.10 0.30 0.004 0.012 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.01 D (1) 8.55 8.75 0.337 0.344 E 3.80 4.0 0.150 0.157 e 1.27 0.050 H 5.8 6.20 h 0.25 0.50 0.01 0.02 L 0.40 1.27 0.016 0.050 k ddd 0.228 0.244 0° (min.), 8° (max.) 0.10 0.004 Figure 54. Package dimensions 0016019D 35/37 Revision history 9 L6563 - L6563A Revision history Table 9. Revision history 36/37 Date Revision Changes 13-Nov-2004 1 First issue 24-Sep-2005 2 Changed the maturity from “Preliminary data” to “Datasheet” 11-Nov-2006 3 Added new part number L6563A (Table 1) Updated the Section 4 on page 7 & Section 7 on page 31 the document has been reformatted L6563 - L6563A Please Read Carefully: Information in this document is provided solely in connection with ST products. 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