NEC NP100P04PLG Mos field effect transistor Datasheet

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP100P04PLG
SWITCHING
P-CHANNEL POWER MOSFET
DESCRIPTION
The NP100P04PLG is P-channel MOS Field Effect Transistor designed for high current switching applications.
<R>
ORDERING INFORMATION
PART NUMBER
NP100P04PLG-E1-AY
Note
NP100P04PLG-E2-AY
Note
LEAD PLATING
PACKING
PACKAGE
Pure Sn (Tin)
Tape 800 p/reel
TO-263 (MP-25ZP)
Note Pb-free (This product does not contain Pb in external electrode.)
FEATURES
(TO-263)
• Super low on-state resistance
RDS(on)1 = 3.7 mΩ MAX. (VGS = −10 V, ID = −50 A)
RDS(on)2 = 5.1 mΩ MAX. (VGS = −4.5 V, ID = −50 A)
• High current rating: ID(DC) = m100 A
• Built-in gate protection diode
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
−40
V
Gate to Source Voltage (VDS = 0 V)
VGSS
m20
V
Drain Current (DC) (TC = 25°C)
ID(DC)
m100
A
ID(pulse)
m300
A
PT1
200
W
Drain Current (pulse)
Note1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
PT2
1.8
W
Channel Temperature
Tch
175
°C
Tstg
−55 to +175
°C
Storage Temperature
Single Avalanche Current
Note2
IAS
74
A
Single Avalanche Energy
Note2
EAS
550
mJ
Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, VDD = −30 V, RG = 25 Ω, VGS = −20 → 0 V
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Rth(ch-C)
0.75
°C/W
Channel to Ambient Thermal Resistance
Rth(ch-A)
83.3
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D18694EJ3V0DS00 (3rd edition)
Date Published May 2007 NS CP(K)
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2007
NP100P04PLG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = −40 V, VGS = 0 V
−10
μA
Gate Leakage Current
IGSS
VGS = m20 V, VDS = 0 V
m10
μA
VGS(th)
VDS = −10 V, ID = −1 mA
−1.0
−1.6
−2.5
V
| yfs |
VDS = −10 V, ID = −50 A
43
88
RDS(on)1
VGS = −10 V, ID = −50 A
2.8
3.7
mΩ
RDS(on)2
VGS = −4.5 V, ID = −50 A
3.4
5.1
mΩ
Input Capacitance
Ciss
VDS = −10 V,
15100
pF
Output Capacitance
Coss
VGS = 0 V,
2400
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
1130
pF
Turn-on Delay Time
td(on)
VDD = −20 V, ID = −50 A,
38
ns
Rise Time
tr
VGS = −10 V,
30
ns
Turn-off Delay Time
td(off)
RG = 0 Ω
300
ns
Fall Time
tf
100
ns
Total Gate Charge
QG
VDD = −32 V,
320
nC
Gate to Source Charge
QGS
VGS = −10 V,
37
nC
QGD
ID = −100 A
85
nC
VF(S-D)
IF = −100 A, VGS = 0 V
0.91
Reverse Recovery Time
trr
IF = −100 A, VGS = 0 V,
70
ns
Reverse Recovery Charge
Qrr
di/dt = −100 A/μs
123
nC
Gate to Source Threshold Voltage
Note
Forward Transfer Admittance
Drain to Source On-state Resistance
Note
Gate to Drain Charge
Body Diode Forward Voltage
Note
S
1.5
V
Note Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2%
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
50 Ω
PG.
VGS = −20 → 0 V
VDD
RG
PG.
VGS(−)
VGS
Wave Form
0
VGS
10%
90%
VDD
VDS(−)
−
IAS
BVDSS
VDS
ID
VGS(−)
0
VDS
Wave Form
τ
VDD
Starting Tch
τ = 1 μs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
2
IG = −2 mA
RL
50 Ω
VDD
Data Sheet D18694EJ3V0DS
VDS
90%
90%
10% 10%
0
td(on)
tr td(off)
ton
tf
toff
NP100P04PLG
TYPICAL CHARACTERISTICS (TA = 25°C)
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
120
240
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
200
160
120
80
40
0
0
0
25
50
75
100 125 150 175 200
0
25
Tch - Channel Temperature - °C
50
75
100 125 150 175 200
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
-1000
ID(pulse)
PW
=1
00
1i
μs
i
ms
DC
1i 0
i
ms
RDS(on) Limited
(VGS = −10 V)
D
er
-10
ID(DC)
w
Po
i ss
ip
io
at
-1
d
it e
im
nL
TC = 25°C
Single Pulse
-0.1
-0.1
-1
-10
-100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - °C/W
ID - Drain Current - A
i
-100
1000
100
Rth(ch-A) = 83.3°C/Wi
10
1
Rth(ch-C) = 0.75°C/Wi
0.1
0.01
Single Pulse
0.001
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet D18694EJ3V0DS
3
NP100P04PLG
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
-300
-1000
VGS = −10 V
-200
VDS = −10 V
Pulsed
-100
ID - Drain Current - A
ID - Drain Current - A
-250
−4.5 V
-150
-100
-50
-10
Tch = −55°C
−25°C
25°C
75°C
125°C
150°C
175°C
-1
-0.1
-0.01
Pulsed
0
-0.001
-0.5
-1
-1.5
-2
-0
-1
-4
-5
GATE TO SOURCE THRESHOLD VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
-3
-2.5
-2
-1.5
-1
-0.5
VDS = −10 V
ID = −1 mA
0
-75
-25
25
75
125
175
1000
Tch = −55°C
−25°C
25°C
75°C
100
225
10
1
VDS = −10 V
Pulsed
0.1
-0.1
-1
5
VGS = −4.5 V
3
−10 V
2
1
Pulsed
0
-1
-10
-100
-10
-100
-1000
-1000
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
RDS(on) - Drain to Source On-state Resistance - mΩ
6
4
125°C
150°C
175°C
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
RDS(on) - Drain to Source On-state Resistance - mΩ
-3
VGS - Gate to Source Voltage - V
Tch - Channel Temperature - °C
ID - Drain Current - A
4
-2
VDS - Drain to Source Voltage - V
| yfs | - Forward Transfer Admittance - S
VGS(th) - Gate to Source Threshold Voltage - V
0
10
8
ID = −100 A
−50 A
−20 A
6
4
2
Pulsed
0
0
-5
-10
-15
VGS - Gate to Source Voltage - V
Data Sheet D18694EJ3V0DS
-20
NP100P04PLG
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
8
100000
VGS = −4.5 V
4
−10 V
2
ID = −50 A
Pulsed
Ciss
10000
1000
-25
25
75
125
175
Crss
VGS = 0 V
f = 1 MHz
0
-75
Coss
100
-0.1
225
Tch - Channel Temperature - °C
-100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
-12
-40
1000
VDS - Drain to Source Voltage - V
10000
td(on), tr, td(off), tf - Switching Time - ns
-10
VDS - Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
td(off)
tf
100
td(on)
tr
10
VDD = −20 V
VGS = −10 V
RG = 0 Ω
1
-0.1
-1
VDD = −32 V
−20 V
−8 V
-30
-9
-6
-20
VGS
-3
-10
VDS
ID = −100 A
0
-10
-100
-1000
0
50
ID - Drain Current - A
100
150
200
250
300
0
350
QG - Gate Charge - nC
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
1000
-100
VGS = −10 V
-10
0V
-1
-0.1
Pulsed
trr - Reverse Recovery Time - ns
-1000
IF - Diode Forward Current - A
-1
100
10
-0.01
di/dt = −100 A/μs
VGS = 0 V
1
0
0.5
1
1.5
VF(S-D) - Source to Drain Voltage - V
Data Sheet D18694EJ3V0DS
-0.1
-1
-10
-100
IF - Diode Forward Current - A
5
VGS - Gate to Source Voltage - V
6
Ciss, Coss, Crss - Capacitance - pF
RDS(on) - Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
NP100P04PLG
PACKAGE DRAWING (Unit: mm)
1.35 ±0.3
TO-263 (MP-25ZP)
10.0 ±0.3
No plating
7.88 MIN.
4.45 ±0.2
1.3 ±0.2
9.15 ±0.3
0.5
15.25 ±0.5
8.0 TYP.
4
0.025
to 0.25
.2
0 to 8
˚
0.25
1 2
3
2.5
2.54
1. Gate
2. Drain
3. Source
4. Fin (Drain)
2.54 ±0.25
0.6 ±0
0.75 ±0.2
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
6
Data Sheet D18694EJ3V0DS
NP100P04PLG
• The information in this document is current as of May, 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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M8E 02. 11-1
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