IC42S16100 Document Title 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM Revision History Revision No History Draft Date Remark 0A 0B 0C 0D Initial Draft revise for typo on page 17 Add Pb-free package Add speed grade -5ns Obselte speed grade -8ns August 28,2001 January 10,2002 December 02,2003 June 25,2004 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 1 IC42S16100 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES DESCRIPTION • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto refresh, self refresh • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Package 400mil 50-pin TSOP-2 • Pb(lead)-free package is available ICSI's 16Mb Synchronous DRAM IC42S16100 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 50-Pin TSOP-2 VCC 1 50 GND I/O0 2 49 I/O15 I/O1 3 48 I/O14 GNDQ 4 47 GNDQ I/O2 5 46 I/O13 I/O3 6 45 I/O12 VCCQ 7 44 VCCQ I/O4 8 43 I/O11 I/O5 9 42 I/O10 GNDQ 10 41 GNDQ I/O6 11 40 I/O9 I/O7 12 39 I/O8 VCCQ 13 38 VCCQ LDQM 14 37 NC WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 NC A11 19 32 A9 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VCC 25 26 GND PIN DESCRIPTIONS A0-A11 Address Input CAS Column Address Strobe Command A0-A10 Row Address Input WE Write Enable A11 Bank Select Address LDQM Lower Bye, Input/Output Mask A0-A7 Column Address Input UDQM Upper Bye, Input/Output Mask I/O0 to I/O15 Data I/O Vcc Power CLK System Clock Input GND Ground CKE Clock Enable VccQ Power Supply for I/O Pin CS Chip Select GNDQ Ground for I/O Pin RAS Row Address Strobe Command NC No Connection ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 PIN FUNCTIONS Pin No. Symbol Type 20 to 24 27 to 32 A0-A10 Input Pin 19 A11 Input Pin 16 CAS Input Pin 34 CKE Input Pin 35 CLK Input Pin 18 CS Input Pin 2, 3, 5, 6, 8, 9, 11 I/O0 to 12, 39, 40, 42, 43, I/O15 45, 46, 48, 49 14, 36 LDQM, UDQM I/O Pin Input Pin 17 RAS Input Pin 15 WE Input Pin 7, 13, 38, 44 1, 25 4, 10, 41, 47 26, 50 VCCQ VCC GNDQ GND Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin Integrated Circuit Solution Inc. DR024-0D 06/25/2004 Function (In Detail) A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input and A0-A7 as column address inputs during read or write command input. A10 is also used to determine the precharge mode during other commands. If A10 is LOW during precharge command, the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged. When A10 is HIGH in read or write command cycle, the precharge starts automatically after the burst access. These signals become part of the OP CODE during mode register set command input. A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is selected. This signal becomes part of the OP CODE during mode register set command input. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. The CKE input determines whether the CLK input is enabled within the device. When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid. When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and UDQM pins. LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VCCQ is the output buffer power supply. VCC is the device internal power supply. GNDQ is the output buffer ground. GND is the device internal ground. 3 IC42S16100 CLK CKE CS RAS CAS WE A11 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER 11 ROW ADDRESS BUFFER 11 ROW DECODER FUNCTIONAL BLOCK DIAGRAM MEMORY CELL ARRAY 2048 BANK 0 DQM 11 CONTROLLER 11 ROW ADDRESS LATCH MULTIPLEXER REFRESH COUNTER 11 COLUMN ADDRESS BUFFER SELF REFRESH ROW ADDRESS BUFFER 11 ROW DECODER REFRESH CONTROLLER BURST COUNTER 8 COLUMN ADDRESS LATCH A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATA IN BUFFER SENSE AMP I/O GATE 256 16 16 I/O 0-15 COLUMN DECODER 8 256 DATA OUT BUFFER SENSE AMP I/O GATE 16 2048 MEMORY CELL ARRAY 16 Vcc/VccQ GND/GNDQ BANK 1 S16BLK.eps 4 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters VCC MAX VCCQ MAX VIN VOUT PD MAX ICS TOPR TSTG Maximum Supply Voltage Maximum Supply Voltage for Output Buffer Input Voltage Output Voltage Allowable Power Dissipation Output Shorted Current Operating Temperature Storage Temperature Rating Unit –1.0 to +4.6 –1.0 to +4.6 –1.0 to +4.6 –1.0 to +4.6 1 50 0 to +70 –55 to +150 V V V V W mA °C °C DC RECOMMENDED OPERATING CONDITIONS(2) (At TA = 0 to +70°C) Symbol VCC, VCCQ VIH VIL Parameter Min. Typ. Max. Unit Supply Voltage Input High Voltage(3) Input Low Voltage(4) 3.0 2.0 -0.3 3.3 — — 3.6 VDD + 0.3 +0.8 V V V CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25°C, Vcc = VccQ = 3.3 ± 0.3V, f = 1 MHz) Symbol Parameter CIN1 CIN2 CI/O Input Capacitance: A0-A11 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) Data Input/Output Capacitance: I/O0-I/O15 Typ. Max. Unit — — — 4 4 5 pF pF pF Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to GND. 3. VIH (max) = VCCQ + 2.0V with a pulse width ≤ 3 ns. 4. VIL (min) = GND – 2.0V with a pulse < 3 ns and -1.5V with a pulse < 5ns. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 5 IC42S16100 DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition IIL Input Leakage Current IOL Output Leakage Current VOH VOL Output High Voltage Level Output Low Voltage Level 0V ≤ VIN ≤ VCC, with pins other than the tested pin at 0V Output is disabled 0V ≤ VOUT ≤ VCC IOUT = –2 mA IOUT = +2 mA ICC1 Operating Current(1,2) ICC2 Precharge Standby Current (In Power-Down Mode) Active Standby Current (In Non Power-Down Mode) ICC3 Speed Min. Max. Unit –5 5 µA –10 10 µA 2.4 — — 0.4 V V One Bank Operation, Burst Length=1 tRC ≥ tRC (min.) IOUT = 0mA CKE ≤ VIL (MAX) CAS latency = 3 -5 -6 -7 — — — 150 145 140 mA mA mA tCK = tCK (MIN) — — 2 mA CKE ≥ VIH (MIN) tCK = tCK (MIN) — — — -5 -6 -7 -5 -6 -7 — —5 —6 —7 — — — — — — — 50 45 40 150 140 130 100 90 80 1 mA mA mA mA mA mA mA mA mA mA ICC4 Operating Current (In Burst Mode)(1) tCK = tCK (MIN) IOUT = 0mA ICC5 Auto-Refresh Current tRC = tRC (MIN) ICC6 Self-Refresh Current CKE ≤ 0.2V Notes: 1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vcc and GND for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Icc1 and Icc4 depend on the output load. 6 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 AC CHARACTERISTICS(1,2,3) -5 Symbol Parameter tCK3 tCK2 tAC3 tAC2 tCHI tCL tOH tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKA tCS tCH tRC tRAS tRP tRCD tRRD tDPL Clock Cycle Time tDAL tT tREF Access Time From CLK(4) CLK HIGH Level Width CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time Output HIGH Impedance Time(5) Min. CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 Input Data Setup Time Input Data Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time CKE to CLK Recovery Delay Time Command Setup Time (CS, RAS, CAS, WE, DQM) Command Hold Time (CS, RAS, CAS, WE, DQM) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Active Command To Read / Write Command Delay Time Command Period (ACT [0] to ACT[1]) Input Data To Precharge Command Delay time Input Data To Active / Refresh Command Delay time (During Auto-Precharge) Transition Time Refresh Cycle Time (4096) -6 Max. Min. -7 Max. Min. Max Units 5 — 7 — — 4.5 — 5 2 — 2 — 2 — 0 — — 4.5 — 5 2 — 1 — 2 — 1 — 2 — 1 — 1CLK+3 — 2 — 1 — 50 — 30 100,000 15 — 15 — 10 — 2CLK — 6 — 8 — — 5.5 — 6 2 — 2 — 2 — 0 — — 5.5 — 6 2 — 1 — 2 — 1 — 2 — 1 — 1CLK+3 — 2 — 1 — 60 — 36 100,000 18 — 18 — 12 — 2CLK — 7 — 8.6 — — 6 — 6 2.5 — 2.5 — 2 — 0 — — 6 — 6 2 — 1 — 2 — 1 — 2 — 1 — 1CLK+3 — 2 — 1 — 70 — 42 100,000 21 — 21 — 14 — 2CLK — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2CLK+tRP — 2CLK+tRP — 2CLK+tRP — ns 1 — 10 64 1 — 10 64 1 — 10 64 ns ms Notes: 1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated voltages. Also note that the power-on sequence must be executed before starting memory operation. 2. Measured with tT = 1 ns. 3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.). 4. Access time is measured at 1.4V with the load shown in the figure below. 5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.) when the output is in the high impedance state. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 7 IC42S16100 OPERATING FREQUENCY / LATENCY RELATIONSHIPS Symbol Parameter — — tCAC t RCD tRAC t RC tRAS tRP t RRD t CCD tDPL tDAL tRBD tWBD tRQL tWDL tPQL tQMD tDMD tMCD Clock Cycle Time Operating Frequency CAS Latency Active Command To Read/Write Command Delay Time RAS Latency (tRCD + tCAC) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Command Period (ACT[0] to ACT [1]) Column Command Delay Time (READ, READA, WRIT, WRITA) Input Data To Precharge Command Delay Time Input Data To Active/Refresh Command Delay Time (During Auto-Precharge) Burst Stop Command To Output in HIGH-Z Delay Time (Read) Burst Stop Command To Input in Invalid Delay Time (Write) Precharge Command To Output in HIGH-Z Delay Time (Read) Precharge Command To Input in Invalid Delay Time (Write) Last Output To Auto-Precharge Start Time (Read) DQM To Output Delay Time (Read) DQM To Input Delay Time (Write) Mode Register Set To Command Delay Time -5 -6 -7 Units 5 200 3 3 6 10 6 3 2 1 6 166 3 3 6 10 6 3 2 1 7 143 3 3 6 10 6 3 2 1 ns MHz cycle cycle cycle cycle cycle cycle cycle cycle 2 5 2 5 2 5 cycle cycle 3 3 3 cycle 0 0 0 cycle 3 3 3 cycle 0 0 0 cycle –2 2 0 2 –2 2 0 2 –2 2 0 2 cycle cycle cycle cycle AC TEST CONDITIONS (Input/Output Reference Level: 1.4V) Input tCK tCL tCHI 2.4V CLK 1.4V 0.4V tCS tCH 2.4V INPUT 1.4V 0.4V tAC tOH OUTPUT Output Load 1.4V ZO = 50Ω 1.4V 50 Ω +1.4V I/O 30 pF 8 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 COMMANDS Active Command Read Command CLK CLK CKE HIGH CKE HIGH CS CS RAS RAS CAS CAS WE WE A0-A9 ROW COLUMN (1) A0-A9 AUTO PRECHARGE ROW A10 A10 NO PRECHARGE BANK 1 A11 BANK 1 A11 BANK 0 Write Command BANK 0 Precharge Command CLK CLK CKE HIGH CKE HIGH CS CS RAS RAS CAS CAS WE WE COLUMN(1) A0-A9 A0-A9 BANK 0 AND BANK 1 AUTO PRECHARGE A10 A10 NO PRECHARGE BANK 0 OR BANK 1 BANK 1 A11 BANK 1 A11 BANK 0 No-Operation Command CLK CKE Device Deselect Command CLK HIGH CKE CS CS RAS RAS CAS CAS WE WE A0-A9 A0-A9 A10 A10 A11 A11 Notes: 1. A8-A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 BANK 0 HIGH Don’t Care 9 IC42S16100 COMMANDS (cont.) Mode Register Set Command CLK CKE Auto-Refresh Command CLK HIGH HIGH CKE CS CS RAS RAS CAS CAS WE WE A0-A9 OP-CODE A0-A9 A10 OP-CODE A10 A11 OP-CODE A11 Self-Refresh Command Power Down Command CLK CLK CKE CKE CS CS NOP RAS RAS NOP CAS CAS NOP WE WE A0-A9 A0-A9 A10 A10 A11 A11 Clock Suspend Command CLK CKE NOP Burst Stop Command CLK BANK(S) ACTIVE CKE HIGH CS NOP CS RAS NOP RAS CAS NOP CAS WE ALL BANKS IDLE NOP WE A0-A9 A0-A9 A10 A10 A11 A11 Don’t Care 10 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Mode Register Set Command (CS, RAS, CAS, WE = LOW) The IC42S16100 product incorporates a register that defines the device operating mode. This command functions as a data input pin that loads this register from the pins A0 to A11. When power is first applied, the stipulated power-on sequence should be executed and then the IC42S16100 should be initialized by executing a mode register set command. Note that the mode register set command can be executed only when both banks are in the idle state (i.e. deactivated). When the A10 pin is HIGH, this command functions as a read with auto-precharge command. After the burst read completes, the bank selected by pin A11 is precharged. When the A10 pin is LOW, the bank selected by the A11 pin remains in the activated state after the burst read completes. Write Command (CS, CAS, WE = LOW, RAS = HIGH) Another command cannot be executed after a mode register set command until after the passage of the period tMCD, which is the period required for mode register set command execution. When burst write mode has been selected with the mode register set command, this command selects the bank specified by the A11 pin and starts a burst write operation at the start address specified by pins A0 to A9. This first data must be input to the I/O pins in the cycle in which this command. Active Command The selected bank must be activated before executing this command. (CS, RAS = LOW, CAS, WE= HIGH) The IC42S16100 includes two banks of 4096 rows each. This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs. When A10 pin is HIGH, this command functions as a write with auto-precharge command. After the burst write completes, the bank selected by pin A11 is precharged. When the A10 pin is low, the bank selected by the A11 pin remains in the activated state after the burst write completes. After the input of the last burst write data, the application must wait for the write recovery period (tDPL, tDAL) to elapse according to CAS latency. Precharge Command (CS, RAS, WE = LOW, CAS = HIGH) This command starts precharging the bank selected by pins A10 and A11. When A10 is HIGH, both banks are precharged at the same time. When A10 is LOW, the bank selected by A11 is precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period tRP, which is the period required for bank precharging. Auto-Refresh Command (CS, RAS, CAS = LOW, WE, CKE = HIGH) This command executes the auto-refresh operation. The row address and bank to be refreshed are automatically generated during this operation. Both banks must be placed in the idle state before executing this command. This command corresponds to the RAS signal from LOW to HIGH in conventional DRAMs The stipulated period (tRC) is required for a single refresh operation, and no other commands can be executed during this period. Read Command The device goes to the idle state after the internal refresh operation completes. (CS, CAS = LOW, RAS, WE = HIGH) This command selects the bank specified by the A11 pin and starts a burst read operation at the start address specified by pins A0 to A9. Data is output following CAS latency. This command must be executed at least 4096 times every 64 ms. This command corresponds to CBR auto-refresh in conventional DRAMs. The selected bank must be activated before executing this command. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 11 IC42S16100 Self-Refresh Command Power-Down Command (CS, RAS, CAS, CKE = LOW, WE = HIGH) (CKE = LOW) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh operation is started by dropping the CKE pin from HIGH to LOW. The self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins. The selfrefresh operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the device internal recovery period (tRC) has elapsed. After the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an auto-refresh should immediately be performed for all addresses (4096 cycles). When both banks are in the idle (inactive) state, or when at least one of the banks is not in the idle (inactive) state, this command can be used to suppress device power dissipation by reducing device internal operations to the absolute minimum. Power-down mode is started by dropping the CKE pin from HIGH to LOW. Power-down mode continues as long as the CKE pin is held low. All pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. The power-down operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the recovery period (tCKA) has elapsed. Both banks must be placed in the idle state before executing this command. Burst Stop Command (CS, WE, = LOW, RAS, CAS = HIGH) The command forcibly terminates burst read and write operations. When this command is executed during a burst read operation, data output stops after the CAS latency period has elapsed. No Operation (CS, = LOW, RAS, CAS, WE = HIGH) This command has no effect on the device. Device Deselect Command (CS = HIGH) This command does not select the device for an object of operation. In other words, it performs no operation with respect to the device. 12 Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tREF). Thus the maximum time that power-down mode can be held is just under the refresh cycle time. Clock Suspend (CKE = LOW) This command can be used to stop the device internal clock temporarily during a read or write cycle. Clock suspend mode is started by dropping the CKE pin from HIGH to LOW. Clock suspend mode continues as long as the CKE pin is held LOW. All input pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. Also note that the device internal state is maintained. Clock suspend mode is terminated by raising the CKE pin from LOW to HIGH, at which point device operation restarts. The next command cannot be executed until the recovery period (tCKA) has elapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tREF). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 COMMAND TRUTH TABLE(1,2) Symbol CKE n-1 n Command MRS REF SREF PRE PALL ACT WRIT WRITA READ READA BST NOP DESL SBY ENB MASK Mode Register Set Auto-Refresh(5) Self-Refresh(5,6) Precharge Selected Bank Precharge Both Banks Bank Activate(7) Write Write With Auto-Precharge(8) Read(8) Read With Auto-Precharge(8) Burst Stop(9) No Operation Device Deselect Clock Suspend / Standby Mode Data Write / Output Enable Data Mask / Output Disable H H H H H H H H H H H H H L H H (3,4) X H L X X X X X X X X X X X X X CS RAS CAS WE DQM A11 A10 L L L L L L L L L L L L H X X X L L L L L L H H H H H H X X X X L L L H H H L L L L H H X X X X L H H L L H L L H H L H X X X X X X X X X X X X X X X X X X L H X X BS X BS BS BS BS BS X X X X X X A9-A0 OP CODE X X X X L X H X Row Row L Column(18) H Column(18) L Column(18) H Column(18) X X X X X X X X X X X X I/On X HIGH-Z HIGH-Z X X X X X X X X X X X Active HIGH-Z DQM TRUTH TABLE(1,2) Symbol Command ENB MASK ENBU ENBL MASKU MASKL Data Write / Output Enable Data Mask / Output Disable Upper Byte Data Write / Output Enable Lower Byte Data Write / Output Enable Upper Byte Data Mask / Output Disable Lower Byte Data Mask / Output Disable CKE n-1 n H H H H H H DQM UPPER LOWER X X X X X X L H L X H X L H X L X H CKE TRUTH TABLE(1,2) Symbol Command Current State SPND — — REF SELF SELFX Start Clock Suspend Mode Clock Suspend Terminate Clock Suspend Mode Auto-Refresh Start Self-Refresh Mode Terminate Self-Refresh Mode Active Other States Clock Suspend Idle Idle Self-Refresh PDWN Start Power-Down Mode Idle — Terminate Power-Down Mode Power-Down Integrated Circuit Solution Inc. DR024-0D 06/25/2004 CKE n-1 n H L L H H L L H H L L L H H L H H L L H CS RAS CAS WE A11 A10 A9-A0 X X X L L L H L H X X X X L L H X H X X X X X L L H X H X X X X X H H H X H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 13 IC42S16100 OPERATION COMMAND TABLE(1,2) Current State Command Operation CS RAS CAS WE A11 A10 A9-A0 Idle No Operation or Power-Down(12) No Operation or Power-Down(12) No Operation or Power-Down Illegal Illegal Row Active No Operation Auto-Refresh or Self-Refresh(13) Mode Register Set No Operation No Operation No Operation Read Start(17) Write Start(17) Illegal(10) Precharge(15) Illegal Illegal Burst Read Continues, Row Active When Done Burst Read Continues, Row Active When Done Burst Interrupted, Row Active After Interrupt Burst Interrupted, Read Restart After Interrupt(16) Burst Interrupted Write Start After Interrupt(11,16) Illegal(10) Burst Read Interrupted, Precharge After Interrupt Illegal Illegal Burst Write Continues, Write Recovery When Done Burst Write Continues, Write Recovery When Done Burst Write Interrupted, Row Active After Interrupt Burst Write Interrupted, Read Start After Interrupt(11,16) Burst Write Interrupted, Write Restart After Interrupt(16) Illegal(10) Burst Write Interrupted, Precharge After Interrupt Illegal Illegal Burst Read Continues, Precharge When Done Burst Read Continues, Precharge When Done Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L Row Active Read Write Read With AutoPrecharge 14 DESL NOP BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X X V V V V X X X X V V V V X X X X V V V V X X X X V V V V X X X X V V V V X X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 OPERATION COMMAND TABLE(1,2) Current State Command Operation CS RAS CAS WE A11 A10 A9-A0 Write With DESL Auto-Precharge NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Precharge DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Immediately DESL Following NOP Row Active BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Write DESL Recovery NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Burst Write Continues, Write Recovery And Precharge When Done Burst Write Continues, Write Recovery And Precharge Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal No Operation, Idle State After tRP Has Elapsed No Operation, Idle State After tRP Has Elapsed No Operation, Idle State After tRP Has Elapsed Illegal(10) Illegal(10) Illegal(10) No Operation, Idle State After tRP Has Elapsed(10) Illegal Illegal No Operation, Row Active After tRCD Has Elapsed No Operation, Row Active After tRCD Has Elapsed No Operation, Row Active After tRCD Has Elapsed Illegal(10) Illegal(10) Illegal(10,14) Illegal(10) Illegal Illegal No Operation, Row Active After tDPL Has Elapsed No Operation, Row Active After tDPL Has Elapsed No Operation, Row Active After tDPL Has Elapsed Read Start Write Restart Illegal(10) Illegal(10) Illegal Illegal H X X X X L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X V V V V X Integrated Circuit Solution Inc. DR024-0D 06/25/2004 X X X V V V V X X X X V V V V X X X X V V V V X X X X X X X V V(18) V V(18) V V(18) V X X X OPCODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE 15 IC42S16100 OPERATION COMMAND TABLE(1,2) Current State Command Operation CS RAS CAS WE A11 A10 A9-A0 Write Recovery DESL With AutoNOP Precharge BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Refresh DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Mode Register DESL Set NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS No Operation, Idle State After tDAL Has Elapsed No Operation, Idle State After tDAL Has Elapsed No Operation, Idle State After tDAL Has Elapsed Illegal(10) Illegal(10) Illegal(10) Illegal(10) Illegal Illegal No Operation, Idle State After tRP Has Elapsed No Operation, Idle State After tRP Has Elapsed No Operation, Idle State After tRP Has Elapsed Illegal Illegal Illegal Illegal Illegal Illegal No Operation, Idle State After tMCD Has Elapsed No Operation, Idle State After tMCD Has Elapsed No Operation, Idle State After tMCD Has Elapsed Illegal Illegal Illegal Illegal Illegal Illegal H L L L L L L L L H L L L L L L L L H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X X V V V V X X X X V V V V X X X X V V V V X X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE X X X X X X V V(18) V V(18) V V(18) V X X X OP CODE Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input 2. All input signals are latched on the rising edge of the CLK signal. 3. Both banks must be placed in the inactive (idle) state in advance. 4. The state of the A0 to A11 pins is loaded into the mode register as an OP code. 5. The row address is generated automatically internally at this time. The I/O pin and the address pin data is ignored. 6. During a self-refresh operation, all pin data (states) other than CKE is ignored. 7. The selected bank must be placed in the inactive (idle) state in advance. 8. The selected bank must be placed in the active state in advance. 9. This command is valid only when the burst length set to full page. 10. This is possible depending on the state of the bank selected by the A11 pin. 11. Time to switch internal busses is required. 12. The IC42S16100 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 13. The IC42S16100 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state. Input pins other than CKE are ignored at this time. 14. Possible if tRRD is satisfied. 15. Illegal if tRAS is not satisfied. 16. The conditions for burst interruption must be observed. Also note that the IC42S16100 will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 17. Command input becomes possible after the period tRCD has elapsed. Also note that the IC42S16100 will enter the precharged state immediately after the burst operation completes if auto-precharge is selected. 18. A8,A9 = don't care. 16 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 CKE RELATED COMMAND TRUTH TABLE(1) Current State Operation Self-Refresh Undefined Self-Refresh Recovery(2) Self-Refresh Recovery(2) Illegal(2) Illegal(2) Self-Refresh Idle State After tRC Has Elapsed Idle State After tRC Has Elapsed Illegal Illegal Power-Down on the Next Cycle Power-Down on the Next Cycle Illegal Illegal Clock Suspend Termination on the Next Cycle (2) Clock Suspend Undefined Power-Down Mode Termination, Idle After That Termination(2) Power-Down Mode No Operation See the Operation Command Table Bank Active Or Precharge Auto-Refresh Mode Register Set See the Operation Command Table See the Operation Command Table See the Operation Command Table Self-Refresh(3) See the Operation Command Table Power-Down Mode(3) See the Operation Command Table Clock Suspend on the Next Cycle(4) Clock Suspend Termination on the Next Cycle Clock Suspend Termination on the Next Cycle Self-Refresh Recovery Power-Down Both Banks Idle Other States CKE n-1 n CS RAS CAS WE A11 A10 A9-A0 H L L L L L H H H H H H H H L L H L X H H H H L H H H H L L L L H L X H X H L L L X H L L L H L L L X X X X X X H H L X X H H L X H H L X X X X X X H L X X X H L X X H L X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X L H H H H H H H H H H L H H L L L H H H H H L L L L L X H L H L X H L L L L H L L L L X X X X X X X H L L L X H L L L X X X X X X X X H L L X X H L L X X X X X X X X X H L X X X H L X X X X X X X X X X X X X X X OP CODE X X X X OP CODE X X X X X X X X X X X X X X X X X X X X X X X X X X X X Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input 2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The minimum setup time (tCKA) required before all commands other than mode termination must be satisfied. 3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode. 4. The input must be command defined in the operation command table. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 17 IC42S16100 TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2) Previous State BANK 0 BANK 1 Next State BANK 0 BANK 1 Operation CS RAS CAS WE A11 A10 A9-A0 DESL NOP BST H L L X H H X H H X H L X X X X X X X X X Any Any R/W/A I I/A I/A Any Any I/A I/A R/W/A I Any Any A I I/A I/A Any Any I/A I/A A I READ/READA L H L H H H H H L L L L H H L L H H L L CA(3) CA(3) CA(3) CA(3) CA(3) CA(3) CA(3) CA(3) I/A R/W I/A R/W R/W/A A R/W/A A R/W/A A R/W/A A I/A R/W I/A R/W I/A A I/A A RP RP R R RP RP R R I/A A I/A A WRIT/WRITA L H L L ACT L L H H PRE/PALL L L H L REF MRS L L L L L L H L H H H H L L L L H L X X H H L L X H CA(3) H CA(3) L CA(3) L CA(3) H CA(3) H CA(3) L CA(3) L CA(3) RA RA RA RA H X H X L X L X L X L X X X OPCODE I/A R/W/A R/W A I/A R/W/A R/W A R/W/A I/A A R/W R/W/A I/A A R/W Any I I Any R/W/A/I I/A I/A R/W/A/I I/A R/W/A/I R/W/A/I I/A R/W/A/I I/A I/A R/W/A/I I I I I I/A WP A WP I/A W A W WP I/A WP A W I/A W A Any A A Any I I I I I/A I R/W/A/I I I I/A I R/W/A/I I I I I Notes: 1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address 2. The device state symbols are interpreted as follows: I Idle (inactive state) A Row Active State R Read W Write RP Read With Auto-Precharge WP Write With Auto-Precharge Any Any State 3. CA: A8,A9 = don't care. 18 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation) SELF REFRESH SREF entry SREF exit MRS MODE AUTO REFRESH REF IDLE REGISTER SET CKE_ CKE IDLE POWER DOWN ACT ACTIVE POWER DOWN CKE_ CKE BANK ACTIVE BST BST READ WRIT WRIT READ WRITA READA READ WRITE READ CKE_ CKE_ WRIT CKE CLOCK SUSPEND READA WRITA WRITA CKE_ CKE READA WRITE WITH AUTO PRECHARGE POWER ON POWER APPLIED PRE CLOCK SUSPEND CKE_ READ WITH AUTO PRECHARGE PRE PRE CKE CKE PRE PRECHARGE Automatic transition following the completion of command execution. Transition due to command input. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 19 IC42S16100 Device Initialization At Power-On Burst Length (Power-On Sequence) When writing or reading, data can be input or output data continuously. In these operations, an address is input only once and that address is taken as the starting address internally by the device. The device then automatically generates the following address. The burst length field in the mode register stipulates the number of data items input or output in sequence. In the IC42S16100 product, a burst length of 1, 2, 4, 8, or full page can be specified. See the table on the next page for details on setting the mode register. As is the case with conventional DRAMs, the IC42S16100 product must be initialized by executing a stipulated poweron sequence after power is applied. After power is applied and VCC and VCCQ reach their stipulated voltages, set and hold the CKE and DQM pins HIGH for 100 µs. Then, execute the precharge command to precharge both bank. Next, execute the auto-refresh command twice or more and define the device operation mode by executing a mode register set command. The mode register set command can be also set before auto-refresh command. Mode Register Settings The mode register set command sets the mode register. When this command is executed, pins A0 to A9, A10, and A11 function as data input pins for setting the register, and this data becomes the device internal OP code. This OP code has four fields as listed in the table below. Input Pin Field A11, A10, A9, A8 A6, A5, A4 A3 A2, A1, A0 Mode Options CAS Latency Burst Type Burst Length Note that the mode register set command can be executed only when both banks are in the idle (inactive) state. Wait at least two cycles after executing a mode register set command before executing the next command. CAS Latency During a read operation, the between the execution of the read command and data output is stipulated as the CAS latency. This period can be set using the mode register set command. The optimal CAS latency is determined by the clock frequency and device speed grade (-10/12). See the "Operating Frequency / Latency Relationships" item for details on the relationship between the clock frequency and the CAS latency. See the table on the next page for details on setting the mode register. 20 Burst Type The burst data order during a read or write operation is stipulated by the burst type, which can be set by the mode register set command. The IC42S16100 product supports sequential mode and interleaved mode burst type settings. See the table on the next page for details on setting the mode register. See the "Burst Length and Column Address Sequence" item for details on I/O data orders in these modes. Write Mode Burst write or single write mode is selected by the OP code (A11, A10, A9) of the mode register. A burst write operation is enabled by setting the OP code (A11, A10, A9) to (0,0,0). A burst write starts on the same cycle as a write command set. The write start address is specified by the column address and bank select address at the write command set cycle. A single write operation is enabled by setting OP code (A11, A10, A9) to (0,0,1). In a single write operation, data is only written to the column address and bank select address specified by the write command set cycle without regard to the bust length setting. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 MODE REGISTER 11 10 9 8 7 WRITE MODE 6 5 4 LT MODE 3 BT 2 1 Address Bus Mode Register (Mx) 0 BL Burst Length Burst Type Latency Mode M11 M10 M9 M8 M7 0 0 0 0 0 1 0 0 0 0 others Integrated Circuit Solution Inc. DR024-0D 06/25/2004 M2 M1 M0 Sequential Interleaved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 Reserved Reserved Reserved Full Page 1 2 4 8 Reserved Reserved Reserved Reserved M3 Type 0 1 Sequential Interleaved M6 M5 M4 CAS Latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Write Mode Burst Read & Burst Write Burst Read & Single Write Reserved 21 IC42S16100 BURST LENGTH AND COLUMN ADDRESS SEQUENCE Burst Length 2 4 8 Full Page (256) Column Address A2 A1 A0 X X X X X X 0 0 0 0 1 1 1 1 n X X 0 0 1 1 0 0 1 1 0 0 1 1 n 0 1 0 1 0 1 0 1 0 1 0 1 0 1 n Address Sequence Sequential Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4..... ...Cn-1(Cn+255), Cn(Cn+256)..... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 None Notes: 1. The burst length in full page mode is 256. 22 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 BANK SELECT AND PRECHARGE ADDRESS ALLOCATION Row X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 Column Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 — — — — — — — — — — 0 1 0 1 Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Row Address Precharge of the Selected Bank (Precharge Command) Row Address Precharge of Both Banks (Precharge Command) (Active Command) Bank 0 Selected (Precharge and Active Command) Bank 1 Selected (Precharge and Active Command) — — — — — — — — — — 0 1 0 1 Column Address Column Address Column Address Column Address Column Address Column Address Column Address Column Address Don't Care Don't Care Auto-Precharge - Disabled Auto-Precharge - Enables Bank 0 Selected (Read and Write Commands) Bank 1 Selected (Read and Write Commands) 23 IC42S16100 Burst Read The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the clock signal after the CAS latency period. Next, data corresponding to an address generated automatically by the device is output in synchronization with the clock signal. is a full page is an exception. In this case the output buffers must be set to the high impedance state by executing a burst stop command. Note that upper byte and lower byte output data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tQMD) is fixed at two, regardless of the CAS latency setting, when this function is used. The output buffers go to the LOW impedance state CAS latency minus one cycle after the read command, and go to the HIGH impedance state automatically after the last data is output. However, the case where the burst length The selected bank must be set to the active state before executing this command. CLK COMMAND READ A0 tQMD=2 UDQM LDQM I/O8-I/O15 DOUT A0 I/O0-I/O 7 CAS latency = 2, burst length = 4 DOUT A0 READ (CA=A, BANK 0) HI-Z DOUT A2 DOUT A1 DOUT A3 HI-Z HI-Z DATA MASK (LOWER BYTE) DATA MASK (UPPER BYTE) Burst Write The write cycle is started by executing the command. The address provided during write command execution is used as the starting address, and at the same time, data for this address is input in synchronization with the clock signal. Next, data is input in other in synchronization with the clock signal. During this operation, data is written to address generated automatically by the device. This cycle terminates automatically after a number of clock cycles determined by the stipulated burst length. However, the case where the burst length is a full page is an exception. In this case the write cycle must be terminated by executing a burst stop command. The latency for I/O pin data input is zero, regardless of the CAS latency setting. However, a wait period (write recovery: tDPL) after the last data input is required for the device to complete the write operation. Note that the upper byte and lower byte input data can be masked independently under control of the signals applied to the U/LDQM pins. The delay period (tDMD) is fixed at zero, regardless of the CAS latency setting, when this function is used. The selected bank must be set to the active state before executing this command. CLK COMMAND I/O WRITE DIN 0 DIN 1 DIN 2 DIN 3 BURST LENGTH CAS latency = 2,3, burst length = 4 24 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read With Auto-Precharge The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation. During this operation, the delay period (tPQL) between the last burst data output and the start of the precharge operation differs depending on the CAS latency setting. three, the precharge operation starts on two clock cycles before the last burst data is output (tPQL = –2). Therefore, the selected bank can be made active after a delay of tRP from the start position of this precharge operation. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. When the CAS latency setting is two, the precharge operation starts on one clock cycle before the last burst data is output (tPQL = –1). When the CAS latency setting is CAS Latency tPQL 3 –2 2 –1 CLK COMMAND READA 0 ACT 0 tPQL I/O DOUT 0 READ WITH AUTO-PRECHARGE (BANK 0) DOUT 1 DOUT 2 PRECHARGE START DOUT 3 tRP CAS latency = 2, burst length = 4 CLK COMMAND ACT 0 READA 0 tPQL I/O READ WITH AUTO-PRECHARGE (BANK 0) DOUT 0 PRECHARGE START DOUT 1 DOUT 2 DOUT 3 tRP CAS latency = 3, burst length = 4 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 25 IC42S16100 Write With Auto-Precharge The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation. During this operation, the delay period (tDAL) between the last burst data input and the completion of the precharge operation differs depending on the CAS latency setting. The delay (tDAL) is tRP plus one CLK period. That is, the precharge operation starts one clock period after the last burst data input. Therefore, the selected bank can be made active after a delay of tDAL. The selected bank must be set to the active state before executing this command. The auto-precharge function is invalid if the burst length is set to full page. CAS Latency tDAL 3 1CLK +tRP 2 1CLK +tRP CLK COMMAND ACT 0 WRITE A0 PRECHARGE START I/O DIN 0 DIN 1 DIN 2 DIN 3 tRP tDAL WRITE WITH AUTO-PRECHARGE (BANK 0) CAS latency = 2, burst length = 4 CLK COMMAND ACT 0 WRITE A0 PRECHARGE START I/O DIN 0 DIN 1 WRITE WITH AUTO-PRECHARGE (BANK 0) DIN 2 DIN 3 tRP tDAL CAS latency = 3, burst length = 4 26 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Interval Between Read Command The interval between two read command (tCCD) must be at least one clock cycle. A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command. The selected bank must be set to the active state before executing this command. CLK COMMAND READ A0 READ B0 I/O DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 tCCD READ (CA=A, BANK 0) READ (CA=B, BANK 0) CAS latency = 2, burst length = 4 Interval Between Write Command A new command can be executed while a write cycle is in progress, i.e., before that cycle completes. At the point the second write command is executed, data corresponding to the new write command can be input in place of the data for the previous write command. The interval between two write commands (tCCD) must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND I/O WRITE A0 WRITE B0 DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0) CAS latency = 2, burst length = 4 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 27 IC42S16100 Interval Between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read command was executed. The I/On pins must be placed in the HIGH impedance state at least one cycle before data is output during this operation. The interval (tCCD) between command must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND I/O WRITE A0 READ B0 DIN A0 HI-Z WRITE (CA=A, BANK 0) DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 READ (CA=B, BANK 0) CAS latency = 2, burst length = 4 CLK tCCD COMMAND I/O WRITE A0 READ B0 DIN A0 WRITE (CA=A, BANK 0) CAS latency = 3, burst length = 4 28 HI-Z DOUT B3 READ (CA=B, BANK 0) Don’t Care Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Interval Between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i. e., before that cycle completes. Data corresponding to the new write command can be input at the point new write command is executed. To prevent collision between input and output data at the I/On pins during this operation, the output data must be masked using the U/LDQM pins. The interval (tCCD) between these commands must be at least one clock cycle. The selected bank must be set to the active state before executing this command. CLK tCCD COMMAND READ A0 WRITE B0 U/LDQM HI-Z I/O DIN B0 READ (CA=A, BANK 0) DIN B1 DIN B2 DIN B3 WRITE (CA=B, BANK 0) CAS latency = 2, 3, burst length = 4 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 29 IC42S16100 Precharge Read Cycle Interruption The precharge command sets the bank selected by pin A11 to the precharged state. This command can be executed at a time tRAS following the execution of an active command to the same bank. The selected bank goes to the idle state at a time tRP following the execution of the precharge command, and an active command can be executed again for that bank. Using the Precharge Command A read cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (t RQL) from the execution of the precharge command to the completion of the burst output is the clock cycle of CAS latency. If pin A10 is low when this command is executed, the bank selected by pin A11 will be precharged, and if pin A10 is HIGH, both banks will be precharged at the same time. This input to pin A11 is ignored in the latter case. CAS Latency tRQL 3 2 3 2 CLK tRQL COMMAND PRE 0 READ A0 I/O DOUT A0 READ (CA=A, BANK 0) DOUT A1 DOUT A2 HI-Z PRECHARGE (BANK 0) CAS latency = 2, burst length = 4 CLK tRQL COMMAND READ A0 I/O PRE 0 DOUT A0 READ (CA=A, BANK 0) DOUT A1 DOUT A2 HI-Z PRECHARGE (BANK 0) CAS latency = 3, burst length = 4 30 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (tWDL) from the precharge command to the point where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS. Inversely, to write all the burst data to the device, the precharge command must be executed after the write data recovery period (t DPL ) has elapsed. Therefore, the precharge command must be executed on one clock cycle that follows the input of the last burst data item. To inhibit invalid write, the DQM signal must be asserted HIGH with the precharge command. This precharge command and burst write command must be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual bank operation. CAS Latency tWDL 3 2 0 0 tDPL 1 1 CLK tWDL=0 COMMAND PRE 0 WRITE A0 DQM I/O DIN A0 DIN A1 DIN A2 DIN A3 MASKED BY DQM WRITE (CA=A, BANK 0) PRECHARGE (BANK 0) CAS latency = 2, 3, burst length = 4 CLK tDPL COMMAND WRITE A0 I/O DIN A0 PRE 0 DIN A1 WRITE (CA=A, BANK 0) DIN A2 DIN A3 PRECHARGE (BANK 0) CAS latency = 2, 3, burst length = 4 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 31 IC42S16100 Read Cycle (Full Page) Interruption Using the Burst Stop Command The IC42S16100 can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IC42S16100 repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed within the ACT to PRE command period (tRAS max.) following the burst stop command. After the period (tRBD) required for burst data output to stop following the execution of the burst stop command has elapsed, the outputs go to the HIGH impedance state. This period (tRBD) is two clock cycle when the CAS latency is two and three clock cycle when the CAS latency is three. CAS Latency 3 2 tRBD 3 2 CLK tRBD COMMAND READ A0 I/O BST DOUT A0 DOUT A0 DOUT A1 DOUT A2 DOUT A3 HI-Z BURST STOP READ (CA=A, BANK 0) CAS latency = 2, burst length = full page CLK tRBD COMMAND BST READ A0 I/O DOUT A0 READ (CA=A, BANK 0) DOUT A0 DOUT A1 DOUT A2 DOUT A3 HI-Z BURST STOP CAS latency = 3, burst length = full page 32 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle (Full Page) Interruption Using the Burst Stop Command The IC42S16100 can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full page. The IC42S16100 repeats the operation starting at the 256th cycle with data input returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed within the ACT to PRE command period (tRAS max.) following the burst stop command. After the period (tWBD) required for burst data input to stop following the execution of the burst stop command has elapsed, the write cycle terminates. This period (tWBD) is zero clock cycles, regardless of the CAS latency. CLK tWBD=0 COMMAND WRITE A0 BST tRP PRE 0 INVALID DATA I/O DIN A0 DIN A1 DIN A DIN A1 DIN A2 READ (CA=A, BANK 0) BURST STOP PRECHARGE (BANK 0) CAS latency = 2, 3, burst length = full page Don’t Care Burst Data Interruption Using the U/LDQM Pins (Read Cycle) Burst data output can be temporarily interrupted (masked) during a read cycle using the U/LDQM pins. Regardless of the CAS latency, two clock cycles (tQMD) after one of the U/ LDQM pins goes HIGH, the corresponding outputs go to the HIGH impedance state. Subsequently, the outputs are maintained in the high impedance state as long as that U/ LDQM pin remains HIGH. When the U/LDQM pin goes LOW, output is resumed at a time tQMD later. This output control operates independently on a byte basis with the UDQM pin controlling upper byte output (pins I/O8-I/O15) and the LDQM pin controlling lower byte output (pins I/O0 to I/O7). Since the U/LDQM pins control the device output buffers only, the read cycle continues internally and, in particular, incrementing of the internal burst counter continues. CLK COMMAND READ A0 tQMD=2 UDQM LDQM I/O8-I/O15 DOUT A0 I/O0-I/O 7 DOUT A0 READ (CA=A, BANK 0) CAS latency = 2, burst length = 4 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 HI-Z DOUT A2 DOUT A1 DOUT A3 HI-Z HI-Z DATA MASK (LOWER BYTE) DATA MASK (UPPER BYTE) 33 IC42S16100 Burst Data Interruption U/LDQM Pins (Write Cycle) that pin is dropped to LOW and data will be written to the device. This input control operates independently on a byte basis with the UDQM pin controlling upper byte input (pin I/O8 to I/O15) and the LDQM pin controlling the lower byte input (pins I/O0 to I/O7). Burst data input can be temporarily interrupted (muted ) during a write cycle using the U/LDQM pins. Regardless of the CAS latency, as soon as one of the U/LDQM pins goes HIGH, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be muted as long as that U/LDQM pin remains HIGH. Since the U/LDQM pins control the device input buffers only, the cycle continues internally and, inparticular, incrementing of the internal burst counter continues. The IC42S16100 will revert to accepting input as soon as CLK COMMAND WRITE A0 UDQM tDMD=0 LDQM I/O8-I/O15 DIN A1 I/O0-I/O7 DIN A0 WRITE (CA=A, BANK 0) CAS latency = 2, burst length = 4 DIN A2 DIN A3 DIN A3 DATA MASK (LOWER BYTE) DATA MASK (UPPER BYTE) Don’t Care Burst Read and Single Write The burst read and single write mode is set up using the mode register set command. During this operation, the burst read cycle operates normally, but the write cycle only writes a single data item for each write cycle. The CAS latency and DQM latency are the same as in normal mode. CLK COMMAND I/O WRITE A0 DIN A0 WRITE (CA=A, BANK 0) CAS latency = 2, 3 34 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Bank Active Command Interval When the selected bank is precharged, the period trp has elapsed and the bank has entered the idle state, the bank can be activated by executing the active command. If the other bank is in the idle state at that time, the active command can be executed for that bank after the period tRRD has elapsed. At that point both banks will be in the active state. When a bank active command has been executed, a precharge command must be executed for that bank within the ACT to PRE command period (tRAS max). Also note that a precharge command cannot be executed for an active bank before tRAS (min) has elapsed. After a bank active command has been executed and the trcd period has elapsed, read write (including autoprecharge) commands can be executed for that bank. CLK tRRD COMMAND ACT 0 ACT 1 BANK ACTIVE (BANK 0) BANK ACTIVE (BANK 1) CLK tRCD COMMAND CAS latency = 3 ACT 0 READ 0 BANK ACTIVE (BANK 0) BANK ACTIVE (BANK 0) Clock Suspend When the CKE pin is dropped from HIGH to LOW during a read or write cycle, the IC42S16100 enters clock suspend mode on the next CLK rising edge. This command reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as long as the CKE pin remains low. In this state, all inputs other than CKE pin are invalid and no other commands can be executed. Also, the device internal states are maintained. When the CKE pin goes from LOW to HIGH clock suspend mode is terminated on the next CLK rising edge and device operation resumes. The next command cannot be executed until the recovery period (tCKA) has elapsed. Since this command differs from the self-refresh command described previously in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (tref). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time. CLK CKE COMMAND READ 0 I/O DOUT 0 READ (BANK 0) CAS latency = 2, burst length = 4 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 DOUT 1 DOUT 2 DOUT 3 CLOCK SUSPEND 35 IC42S16100 OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle T0 T1 T2 T3 T10 T17 T18 T19 T20 CLK tCHI tCK CKE HIGH tCS tCL tCH CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS A0-A9 tAH ROW CODE tAS A10 tAS tAH tAH ROW CODE BANK 0 & 1 tAS A11 tAH BANK 1 CODE BANK 0 DQM HIGH I/O WAIT TIME T=100 s <PALL> tRC tRP <REF> <REF> tRAS tRC tMCD tRC <MRS> <ACT> Undefined CAS latency = 2, 3 36 Don’t Care Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Power-Down Mode Cycle T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL tCKH tCKS tCKA CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH ROW A0-A9 tAS A10 tAH BANK 0 & 1 ROW BANK 0 OR 1 BANK 1 A11 BANK 1 BANK 0 BANK 0 DQM I/O POWER DOWN MODE tRP <PRE> <PALL> CAS latency = 2, 3 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 <SBY> EXIT POWER DOWN MODE tRAS tRC <ACT> Undefined Don’t Care 37 IC42S16100 Auto-Refresh Cycle T0 T1 T2 T3 Tl Tm Tn Tn+1 CLK tCKS tCK tCS tCH tCHI tCL CKE CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE ROW A0-A9 A10 ROW BANK 0 & 1 BANK 1 A11 BANK 0 DQM I/O tRC tRP <PALL> CAS latency = 2, 3 38 <REF> <REF> tRAS tRC tRC tRC <REF> <ACT> Undefined Don’t Care Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Self-Refresh Cycle T0 T1 T2 T3 Tm Tm+1 Tm+2 Tn CLK tCKS CKE tCK tCHI tCL tCKS tCKS tCKA tCS tCKA tCH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE A0-A9 A10 BANK 0 & 1 A11 DQM I/O tRP <PALL> SELF REFRESH MODE <SELF> EXIT SELF REFRESH tRC tRC <REF> Undefined CAS latency = 2, 3 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 39 IC42S16100 Read Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS ROW BANK 0 AND 1 tAH NO PRE ROW A10 tAH tAS A11 (1) COLUMN m ROW A0-A9 ROW BANK 0 OR 1 BANK 1 BANK 1 BANK 1 BANK 1 BANK 0 tCS BANK 0 tCH tQMD BANK 0 BANK 0 DQM tAC tAC tOH I/O DOUT m tAC tAC tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tLZ tCAC tRCD tHZ tRAS tRQL tRCD tRP tRAS tRC tRC <ACT> <READ> <PRE> <PALL> <ACT> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 40 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle / Auto-Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE ROW A0-A9 tAS COLUMN m ROW AUTO PRE ROW BANK 1 BANK 1 tAH ROW A10 tAH tAS A11 (1) BANK 1 BANK 0 tCS BANK 0 BANK 0 tCH tQMD DQM tAC tAC tOH I/O DOUT m tAC tAC tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tLZ tRCD tCAC tRAS tHZ tPQL tRCD tRP tRAS tRC tRC <ACT> <READA> <ACT> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 41 IC42S16100 Read Cycle / Full Page T0 T1 T2 T3 T4 T5 T6 T260 T261 T262 T263 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS tAH ROW A10 tAH tAS A11 (1) COLUMN ROW A0-A9 BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCS tCH tQMD DQM tAC tAC tOH I/O DOUT 0m tAC tOH DOUT 0m+1 tAC tOH DOUT 0m-1 tAC tOH tOH DOUT 0m DOUT 0m+1 tLZ tRCD tCAC tHZ tRBD (BANK 0) tRP (BANK 0) tRAS tRC (BANK 0) <ACT 0> <READ0> <BST> <PRE 0> Undefined CAS latency = 2, burst length = full page Don’t Care Note 1: A8,A9 = Don't Care. 42 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle / Ping-Pong Operation (Bank Switching) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE (1) ROW COLUMN tAS ROW COLUMN AUTO PRE tAH AUTO PRE ROW ROW A10 ROW NO PRE tAH tAS A11 (1) ROW A0-A9 BANK 0 BANK 0 BANK 1 tCS NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 0 OR 1 BANK 0 BANK 1 tCH tQMD DQM tAC tAC tAC tOH I/O DOUT 0m+1 tLZ tCAC (BANK 1) tOH DOUT 1m+1 tLZ tCAC (BANK 1) tRCD (BANK 1) tRP (BANK 0) tRAS (BANK 0) tRC (BANK 0) <ACT 0> DOUT 1m tHZ tRRD (BANK 0 TO 1) tRCD (BANK 0) tOH tOH DOUT 0m tAC tHZ tRCD (BANK 0) tRAS (BANK 0) tRC (BANK 0) tRAS (BANK 1) tRC (BANK 1) <READ 0> <READA 0> <ACT1> <READ 1> <READA 1> tRP (BANK1) <PRE 0> <ACT 0> <PRE 1> Undefined CAS latency = 2, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 43 IC42S16100 Write Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH A0-A9 tAS COLUMN m ROW BANK 0 AND 1 tAH NO PRE ROW A10 tAH tAS A11 (1) ROW ROW BANK 1 BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 BANK 1 BANK 0 tCS tCH DQM tDS tDH tDS DIN m I/O tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDPL tRCD tRAS tRCD tRP tRAS tRC <ACT> tRC <WRIT> <PRE> <PALL> <ACT> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 44 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle / Auto-Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE ROW A0-A9 tAS COLUMN m ROW AUTO PRE ROW BANK 1 BANK 1 tAH ROW A10 tAH tAS A11 (1) BANK 1 BANK 0 BANK 0 tCS BANK 0 tCH DQM tDS tDH tDS DIN m I/O tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDAL tRCD tRAS tRCD tRP tRAS tRC <ACT> tRC <WRITA> <ACT> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 45 IC42S16100 Write Cycle / Full Page T0 T1 T2 T3 T4 T5 T258 T259 T260 T261 T262 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS tAH ROW A10 tAH tAS A11 (1) COLUMN m ROW A0-A9 BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCH tCS DQM tDS I/O tDH tDS DIN 0m tDH tDS DIN 0m+1 tDH tDS DIN 0m+2 tDH DIN 0m-1 DIN 0m tDPL tRCD tRAS tRP tRC <ACT 0> <WRIT0> <BST> <PRE 0> Undefined CAS latency = 2, burst length = full page Don’t Care Note 1: A8,A9 = Don't Care. 46 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle / Ping-Pong Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH A0-A9 (1) ROW COLUMN tAS tAH AUTO PRE tAH NO PRE ROW COLUMN AUTO PRE ROW A10 ROW tAS A11 (1) ROW BANK 0 BANK 0 ROW BANK 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 0 tCH tCS DQM tDS tDH tDS DIN 0m I/O tRRD (BANK 0 TO 1) tRCD (BANK 0) DIN 0m+1 tDH tDS DIN 0m+2 tDH tDS DIN 0m+3 tDH tDS DIN 1m tDH tDS DIN 1m+1 tDH tDS DIN 1m+2 tDH DIN 1m+3 tDPL tDPL tRCD (BANK 1) tRP tRAS (BANK 0) tRC (BANK 0) <ACT 0> tDH tDS (BANK 0) tRCD (BANK 0) tRAS (BANK 0) tRC (BANK 0) tRAS (BANK 1) tRC (BANK 1) <WRIT 0> <WRITA 0> <ACT 1> <WRIT 1> <WRITA 1> <PRE 0> <ACT 0> Undefined CAS latency = 2, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 47 IC42S16100 Read Cycle / Page Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS tAH tAS A11 COLUMN m COLUMN n NO PRE NO PRE BANK 1 BANK 1 (1) COLUMN o tAH ROW A10 (1) (1) ROW A0-A9 BANK 1 BANK 0 tCS BANK 0 BANK 0 tQMD AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 tCH DQM tAC tAC tOH I/O tAC tOH DOUT m DOUT m+1 tAC tOH DOUT n tAC tOH DOUT n+1 tAC tOH tOH DOUT o DOUT o+1 tLZ tRCD tRAS tRC <ACT> tHZ tCAC <READ> tCAC <READ> tCAC <READ> <READA> tRQL tRP <PRE> <PALL> Undefined CAS latency = 2, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. 48 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle / Page Mode; Data Masking T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS COLUMN o COLUMN n tAH ROW A10 (1) (1) COLUMN m ROW A0-A9 tAH tAS A11 (1) BANK 1 BANK 0 tCS NO PRE NO PRE BANK 1 BANK 1 BANK 0 BANK 0 tQMD NO PRE AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 tCH tQMD DQM tAC tAC tAC tOH I/O tOH DOUT m DOUT m+1 tLZ tRCD tRAS tRC <ACT> tCAC <READ> tAC tOH DOUT n DOUT o tLZ tHZ tCAC <MASK> tAC tOH tHZ tCAC <READ, ENB> <READA, ENB> tOH DOUT o+1 tRQL tRP <PRE> <PALL> Undefined CAS latency = 2, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 49 IC42S16100 Write Cycle / Page Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH A0-A9 tAS (1) (1) COLUMN o COLUMN n tAH ROW A10 tAH tAS A11 (1) COLUMN m ROW BANK 1 BANK 0 tCS NO PRE NO PRE BANK 1 BANK 1 BANK 0 BANK 0 AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 tCH DQM tDS tDH tDS DIN m I/O tDH tDS DIN m+1 tDH tDS DIN n tDH tDS DIN n+1 tDH tDS tDH DIN o DIN o+1 tRCD tRAS tRC <ACT> tDPL tRP <WRIT> <WRIT> <WRIT> <WRITA> <PRE> <PALL> Undefined CAS latency = 2, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. 50 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle / Page Mode; Data Masking T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS tAH tAS A11 COLUMN o COLUMN n tAH ROW A10 (1) (1) (1) COLUMN m ROW A0-A9 BANK 1 BANK 0 tCS AUTO PRE BANK 0 AND 1 NO PRE NO PRE BANK 1 BANK 1 NO PRE BANK 1OR 0 BANK 0 BANK 0 BANK 1 BANK 0 BANK 1 BANK 0 tCH DQM tDS tDH tDS DIN m I/O tDH tDS DIN m+1 tDH tDS DIN n tDH tDS tDH DIN o DIN o+1 tRCD tRAS tRC <ACT> tDPL tRP <WRIT> <WRIT> <MASK> <WRIT> <WRITA> <PRE> <PALL> Undefined CAS latency = 2, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 51 IC42S16100 Read Cycle / Clock Suspend T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCKS tCL tCKH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS ROW tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 ROW ROW A10 tAS A11 (1) COLUMN m ROW A0-A9 BANK 1 BANK 0 tCS tCH tQMD DQM tAC tAC tOH I/O tOH DOUT m DOUT m+1 tLZ tRCD tHZ tCAC tRAS tRAS tRP tRC <ACT 0> tRC <READ> <READ A> <SPND> <SPND> <PRE> <PALL> <ACT > Undefined CAS latency = 2, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. 52 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle / Clock Suspend T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL tCKS tCKH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE COLUMN m ROW A0-A9 tAS ROW tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 ROW ROW A10 tAS A11 (1) BANK 1 BANK 0 tCS tCH DQM tDS tDS tDH DIN m I/O tDH DIN m+1 tRCD tDPL tRAS tRAS tRP tRC <ACT> tRC <WRIT, SPND> <WRITA, SPND> <SPND> <PRE> <PALL> <ACT > Undefined CAS latency = 2, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 53 IC42S16100 Read Cycle / Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS COLUMN n ROW AUTO PRE tAH ROW ROW A10 tAH tAS A11 COLUMN m ROW A0-A9 (1) (1) BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCS BANK 1 BANK 0 tCH tQMD NO PRE BANK 1 BANK 0 DQM tAC tAC tOH I/O DOUT m tAC tOH tHZ tOH DOUT m+1 DOUT m+2 tLZ tRCD tCAC tRAS tRQL tRCD tRP tRAS tRC <ACT 0> tCAC tRC <READ 0> <PRE 0> <ACT > <READ> <READA> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 54 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle / Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH A0-A9 tAS COLUMN n ROW AUTO PRE tAH ROW ROW A10 BANK 0 OR 1 NO PRE tAH tAS A11 (1) (1) COLUMN m ROW BANK 0 BANK 0 NO PRE BANK 1 BANK 0 tCS tCH tCS tDH tDS tDH BANK 1 BANK 0 tCH BANK 0 tCS DQM tDH tDS tDS I/O DIN 0m DIN 0m+1 tDH tDS DIN 0m+2 DIN 0n tRCD tRCD tRAS tRAS tRP tRC <ACT 0> tRC <WRIT 0> <PRE 0> <ACT > <WRIT> <WRITA> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 55 IC42S16100 Read Cycle / Byte Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH A0-A9 tAS ROW tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 ROW ROW A10 tAS A11 (1) COLUMN m ROW BANK 1 BANK 0 tCS tQMD BANK 1 BANK 0 tCH BANK 0 UDQM tQMD tCS tCH LDQM tAC tLZ I/O8-15 tAC tHZ tOH tLZ tLZ tAC tOH DOUT m I/O0-7 tRCD tCAC tOH DOUT m+3 DOUT m+2 DOUT m tAC tAC tOH tOH DOUT m+1 tQMD tRQL tRAS tRCD tRP tRAS tRC tRC <ACT> <READ> <READA> <MASKU> <ENBU, MASKL> <MASKL> <PRE> <PALL> <ACT> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 56 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle / Byte Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS ROW AUTO PRE tAH BANK 0 AND 1 ROW ROW A10 tAH tAS A11 (1) COLUMN m ROW A0-A9 BANK 1 BANK 0 tCS NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 tCH BANK 1 BANK 0 UDQM tCS tCH tDS tDS tDH LDQM I/O8-15 DIN m tDH DIN m+1 DIN m+3 tDH tDS tDH tDS DIN m I/O0-7 tDH tDS DIN m+3 tRCD tDPL tRCD tRAS tRP tRAS tRC tRC <ACT> <WRIT> <WRITA> <MASKL> <MASK> <ENB> <PRE> <PALL> <ACT> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 57 IC42S16100 Read Cycle, Write Cycle / Burst Read, Single Write T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS COLUMN n tAH tAH tAS AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 0 NO PRE ROW A10 (1) COLUMN m ROW A0-A9 A11 (1) BANK 1 BANK 1 BANK 0 tCS BANK 0 tCH tQMD DQM tAC tAC tOH I/O DOUT m tLZ tRCD tAC tAC tDS tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tDH DIN n tHZ tCAC tDPL tRAS tRP tRC <ACT> <READ> <WRIT> <WRITA> <PRE> <PALL> Undefined CAS latency = 2, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 58 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS BANK 0 AND 1 NO PRE tAH tAS A11 ROW tAH ROW A10 (1) COLUMN m ROW A0-A9 ROW BANK 0 OR 1 BANK 1 BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 tCS tCH BANK 0 tQMD BANK 0 DQM tAC tAC tOH I/O DOUT m tAC tAC tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tLZ tRCD tHZ tCAC tRAS tRQL tRCD tRP tRAS tRC tRC <ACT> <READ> <PRE> <PALL> <ACT> Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 59 IC42S16100 Read Cycle / Auto-Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS tAH ROW AUTO PRE ROW ROW A10 tAH tAS A11 (1) COLUMN ROW A0-A9 BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 tCS BANK 0 tCH tQMD DQM tAC tAC tOH I/O DOUT m tAC tAC tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tLZ tRCD tCAC tRAS tHZ tPQL tRCD tRP tRAS tRC tRC <ACT> <READA> <ACT> Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 60 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle / Full Page T0 T1 T2 T3 T4 T5 T6 T7 T8 T262 T263 T264 T265 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS tAH NO PRE ROW A10 BANK 0 OR 1 tAH tAS A11 (1) COLUMN ROW A0-A9 BANK 0 BANK 0 BANK 0 tCH tCS DQM tAC tAC tOH I/O DOUT 0m tAC tOH DOUT 0m+1 tAC tOH DOUT 0m-1 tAC tOH tOH DOUT 0m DOUT 0m+1 tLZ tRCD tCAC (BANK 0) tRAS (BANK 0) tRC (BANK 0) (BANK 0) <ACT 0> tHZ tRBD tRP (BANK 0) <READ0> <BST> <PRE 0> Undefined CAS latency = 3, burst length = full page Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 61 IC42S16100 Read Cycle / Ping Pong Operation (Bank Switching) T0 T1 T2 T3 T4 T5 T6 T7 T8 ROW COLUMN COLUMN AUTO PRE AUTO PRE T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH ROW A0-A9 tAS tAH ROW tAH tAS A11 ROW ROW ROW A10 (1) (1) BANK 0 NO PRE NO PRE BANK 0 OR 1 BANK 0 OR 1 BANK 0 BANK 1 BANK 0 BANK1 BANK 1 tCS BANK 0 tCH tQMD DQM tAC tLZ tAC tOH I/O DOUT 0m tRRD (BANK 0 TO 1) tRCD (BANK 0) DOUT 0m+1 tAC tOH tOH DOUT 1m DOUT 1m+1 tCAC (BANK 1) tRCD (BANK 1) tCAC (BANK 0) tRAS (BANK 0) tRC (BANK 0) <ACT 0> tAC tOH tHZ tRQL (BANK 0) tRP (BANK 0) tRCD (BANK 0) tRAS (BANK 0) tRC (BANK 0) tRAS (BANK 1) tRC (BANK 1) <ACT1> <READ 0> <READA 0> <READ 1> <READA 1> tRP (BANK1) <PRE 0> <PRE 1> <ACT 0> Undefined CAS latency = 3, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. 62 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE (1) ROW A0-A9 tAS COLUMN BANK 0 AND 1 tAH NO PRE ROW A10 tAH tAS A11 ROW ROW BANK 1 BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 BANK 1 BANK 0 tCS tCH DQM tDS tDH tDS DIN m I/O tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDPL tRCD tRAS tRCD tRP tRAS tRC <ACT> tRC <WRIT> <PRE> <PALL> <ACT> Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 63 IC42S16100 Write Cycle / Auto-Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS COLUMN ROW AUTO PRE tAH ROW A10 ROW tAH tAS A11 (1) ROW A0-A9 BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 tCS BANK 0 tCH DQM tDS tDH tDS DIN m I/O tDH tDS DIN m+1 tDH tDS DIN m+2 tDH DIN m+3 tDAL tRCD tRAS tRCD tRP tRAS tRC <ACT> tRC <WRITA> <ACT> Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 64 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle / Full Page T0 T1 T2 T3 T4 T5 T6 T259 T260 T261 T262 T263 T264 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE (1) COLUMN ROW A0-A9 tAS tAH NO PRE ROW A10 A11 BANK 0 OR 1 tAH tAS BANK 0 BANK 0 BANK 0 tCH tCS DQM tDS I/O tDH tDS DIN 0m tDH tDS DIN 0m+1 tDH tDS DIN 0m+2 tDH DIN 0m-1 DIN 0m tDPL tRCD tRAS tRP tRC <ACT 0> <WRIT0> <BST> <PRE 0> Undefined CAS latency = 3, burst length = full page Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 65 IC42S16100 Write Cycle / Ping-Pong Operation (Bank Switching) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T11 T10 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH ROW COLUMN tAS tAH AUTO PRE tAH NO PRE ROW COLUMN AUTO PRE ROW A10 ROW tAS A11 (1) (1) ROW A0-A9 BANK 0 BANK 0 ROW BANK 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 tCH tCS DQM tDS tDH tDS DIN 0m I/O tDH tDS DIN 0m+1 tRRD (BANK 0 TO 1) tRCD (BANK 0) tDH tDS DIN 0m+2 tDH tDS DIN 0m+3 tDH tDS DIN 1m tDH tDS DIN 1m+1 tDH tDS DIN 1m+2 tDH DIN 1m+3 tDPL (BANK 0) tDPL tRCD tRCD (BANK 1) tRP tRAS (BANK 0) tRC (BANK 0) tRAS (BANK 0) tRC tRAS (BANK 1) tRC (BANK 1) <ACT 0> <WRIT 0> <WRITA 0> <ACT 1> <WRIT 1> <WRITA 1> <PRE 0> <ACT 0> Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 66 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle / Page Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE COLUMN m ROW A0-A9 tAS (1) COLUMN n COLUMN o NO PRE tAH tAS A11 (1) tAH ROW A10 (1) BANK 1 BANK 0 BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 BANK 0 NO PRE BANK 1 BANK 1 BANK 0 AUTO PRE tCS tQMD BANK 0 tCH DQM tAC tLZ tAC tOH I/O DOUT m tAC tAC tAC tOH tOH tOH DOUT m+1 DOUT n DOUT n+1 tCAC <ACT> tCAC <READ> DOUT o tOH DOUT o+1 tHZ tCAC tRCD tRAS tRC tAC tOH tRQL tRP <READ> <READ> <READA> <PRE> <PALL> Undefined CAS latency = 3, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 67 IC42S16100 Read Cycle / Page Mode; Data Masking T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T11 T10 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH ROW A0-A9 tAS (1) COLUMN o NO PRE AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 NO PRE tAH tAS A11 (1) COLUMN n tAH ROW A10 (1) COLUMN m BANK 1 BANK 0 BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 BANK 0 tCS tQMD tCH tQMD DQM tAC tAC tOH tLZ I/O DOUT m tCAC tRCD tRAS tRC <ACT> tAC tOH tAC tAC tOH DOUT m+1 tOH DOUT n DOUT o tHZ tCAC tCAC <READ> tOH DOUT o+1 tRQL tRP <READ> <READ, MASK> <READA, MASK> <ENB> <PRE> <PALL> Undefined CAS latency = 3, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. 68 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Write Cycle / Page Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE ROW A0-A9 tAS (1) (1) (1) COLUMN m COLUMN n COLUMN o tAH ROW A10 tAH tAS A11 AUTO PRE BANK 0 AND 1 NO PRE NO PRE BANK 1 BANK 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 0 BANK 0 BANK 1 BANK 0 BANK 0 tCS tCH DQM tDS tDH tDS DIN m I/O tDH tDS DIN m+1 tDH tDS tDH tDS DIN o DIN n tRCD tRAS tRC <ACT> tDH DIN o+1 tDPL tRP <WRIT> <WRIT> <MASK> <WRIT> <WRITA> <PRE> <PALL> Undefined CAS latency = 3, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 69 IC42S16100 Write Cycle / Page Mode; Data Masking T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH ROW A0-A9 tAS (1) (1) COLUMN n COLUMN o tAH NO PRE ROW A10 tAH tAS A11 (1) COLUMN m BANK 1 BANK 0 tCS AUTO PRE BANK 0 AND 1 NO PRE BANK 1OR 0 NO PRE BANK 1 BANK 1 BANK 0 BANK 0 BANK 1 BANK 0 tCH BANK 1 BANK 0 DQM tDS tDH tDS DIN m I/O tDH tDS DIN m+1 tDH tDS DIN n tDH tDS tDH DIN o DIN o+1 tRCD tRAS tRC <ACT> tDPL tRP <WRIT> <WRIT> <MASK> <WRIT> <WRITA> <PRE> <PALL> Undefined CAS latency = 3, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. 70 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle / Clock Suspend T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCKS tCL tCKH CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH (1) COLUMN m ROW A0-A9 tAS tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 0 ROW A10 tAS A11 BANK 1 BANK 0 tCS BANK 1 tCH tQMD DQM tAC tAC tOH I/O tOH DOUT m DOUT m+1 tLZ tRCD tHZ tCAC tRAS tRP tRC <ACT> <READ> <READ A> <SPND> <SPND> <PRE> <PALL> Undefined CAS latency = 3, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 71 IC42S16100 Write Cycle / Clock Suspend T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL tCKS tCKH CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS ROW tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 0 BANK 1 BANK 0 BANK 0 ROW ROW A10 tAS A11 (1) COLUMN m ROW A0-A9 BANK 1 BANK 0 tCS tCH DQM tDS tDH DIN m I/O tRCD tDS tDH DIN m+1 tDPL tRAS tRAS tRP tRC <ACT> tRC <WRIT, SPND> <SPND> <WRITA, SPND> <PRE> <PALL> <ACT > Undefined CAS latency = 3, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. 72 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle / Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE (1) COLUMN m ROW A0-A9 tAS ROW tAH ROW ROW A10 tAH tAS A11 BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCS BANK 1 BANK 0 tCH tQMD DQM tAC tAC tOH I/O DOUT m tAC tOH tHZ tOH DOUT m+1 DOUT m+2 tLZ tRCD tCAC tRAS tRQL tRCD tRP tRAS tRC <ACT 0> tRP <READ 0> <PRE 0> <ACT> Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 73 IC42S16100 Write Cycle / Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS ROW tAH ROW ROW A10 tAH tAS A11 (1) COLUMN m ROW A0-A9 BANK 0 NO PRE BANK 0 OR 1 BANK 0 BANK 0 tCS tCS tCH BANK 1 BANK 0 tCH DQM tDH tDS tDS I/O DIN 0m tDH tDS DIN 0m+1 tDH DIN 0m+2 tRCD tRCD tRAS tRAS tRP tRC <ACT 0> tRP <WRIT 0> <PRE 0> <ACT > Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 74 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle / Byte Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH tAS tAH RAS CAS WE tAS (1) COLUMN m ROW A0-A9 ROW tAH AUTO PRE BANK 0 AND 1 tAH NO PRE BANK 0 OR 1 BANK 1 BANK 1 BANK 1 BANK 0 BANK 0 ROW ROW A10 tAS A11 tCS tQMD tCS tQMD BANK 1 BANK 0 tCH BANK 0 UDQM tCH LDQM tAC tLZ I/O8-15 tAC tHZ tOH DOUT m+2 DOUT m tAC tLZ I/O0-7 tRCD tCAC tAC tLZ tAC tHZ tOH DOUT m+3 tHZ tOH tOH DOUT m DOUT m+1 tQMD tRAS tRQL tRCD tRP tRAS tRP tRC <ACT> <READ> <READA> <MASKU> <ENBU, MASKL> <MASKL> <PRE> <PALL> <ACT> Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 75 IC42S16100 Write Cycle / Byte Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS tAH ROW AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 0 BANK 1 ROW ROW A10 tAH tAS A11 (1) COLUMN m ROW A0-A9 BANK 1 BANK 0 tCS BANK 0 tCH BANK 1 BANK 0 UDQM tCS tCH tDS tDS tDH LDQM I/O8-15 DIN m tDH DIN m+1 DIN m+3 tDH tDS tDH tDS DIN m I/O0-7 tDH tDS DIN m+3 tRCD tDPL tRCD tRAS tRP tRAS tRP tRC <ACT> <WRIT> <WRITA> <MASKL> <MASK> <ENB> <PRE> <PALL> <ACT> Undefined CAS latency = 3, burst length = 4 Don’t Care Note 1: A8,A9 = Don't Care. 76 Integrated Circuit Solution Inc. DR024-0D 06/25/2004 IC42S16100 Read Cycle, Write Cycle / Burst Read, Single Write T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T11 T10 T12 CLK tCKS tCK tCS tCKA tCH CKE tCHI tCL CS tCS tCH tCS tCH tCS tCH RAS CAS WE tAS tAH tAS AUTO PRE BANK 0 AND 1 NO PRE BANK 0 OR 1 BANK 1 BANK 1 NO PRE tAH tAS A11 COLUMN n tAH ROW A10 (1) (1) COLUMN m ROW A0-A9 BANK 1 BANK 1 BANK 0 BANK 0 tCS BANK 0 tQMD tCH BANK 0 DQM tAC I/O tLZ tRC tAC tDS tOH tOH DOUT m DOUT m+1 tDH DIN n tHZ tCAC tDPL tRAS tRP tRC <ACT> <READ> <WRIT> <WRITA> <PRE> <PALL> Undefined CAS latency = 3, burst length = 2 Don’t Care Note 1: A8,A9 = Don't Care. Integrated Circuit Solution Inc. DR024-0D 06/25/2004 77 IC42S16100 ORDERING INFORMATION Commercial Range: 0οC to 70οC Frequency Speed (ns) Order Part No. Package 200MHz 5 166MHz 6 143MHz 7 IC42S16100-5T IC42S16100-5TG IC42S16100-6T IC42S16100-6TG IC42S16100-7T IC42S16100-7TG 400mil TSOP-2 400mil TSOP-2(Pb-free) 400mil TSOP-2 400mil TSOP-2(Pb-free) 400mil TSOP-2 400mil TSOP-2(Pb-free) ORDERING INFORMATION Industrial Temperature Range: -40οC to 85οC Frequency Speed (ns) 200MHz 5 166MHz 6 143MHz 7 Order Part No. Package IC42S16100-5TI IC42S16100-5TIG IC42S16100-6TI IC42S16100-6TIG IC42S16100-7TI IC42S16100-7TIG 400mil TSOP-2 400mil TSOP-2(Pb-free) 400mil TSOP-2 400mil TSOP-2(Pb-free) 400mil TSOP-2 400mil TSOP-2(Pb-free) Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 78 Integrated Circuit Solution Inc. DR024-0D 06/25/2004