19-3704; Rev 2; 1/12 KIT ATION EVALU E L B A AVAIL 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver Features The MAX7042 fully integrated, low-power, CMOS superheterodyne RF receiver is designed to receive frequency-shift-keyed (FSK) data at rates up to 66kbps nonreturn-to-zero (NRZ) (33kbps Manchester). The MAX7042 requires only a few external components to realize a complete wireless RF receiver at 308, 315, 418, and 433.92MHz. o +2.4V to +3.6V or +4.5V to +5.5V Single-Supply Operation The MAX7042 includes all the active components required in a superheterodyne receiver including a lownoise amplifier (LNA), an image-rejection (IR) mixer, a fully integrated phase-locked loop (PLL), local oscillator (LO), 10.7MHz IF limiting amplifier with received-signalstrength indicator (RSSI), low-noise FM demodulator, and a 3V regulator. Differential peak-detecting data demodulators are included for baseband data recovery. o Fast Startup (< 250µs) o Small 32-Pin TQFN Package o Low Operating Supply Current 6.2mA Continuous 20nA Power-Down o Integrated PLL, VCO, and Loop Filter o 45dB Integrated Image Rejection o Selectable IF BW with External Filter The MAX7042 is available in a 32-pin TQFN and is specified over the automotive -40°C to +125°C temperature range. o Four User-Selectable Carrier Frequencies 308, 315, 418, and 433.92MHz o -110dBm RF Input Sensitivity at 315MHz o -109dBm RF Input Sensitivity at 433.92MHz o Positive and Negative Peak Detectors o RSSI Output Ordering Information Applications Remote Keyless Entry Tire-Pressure Monitoring PART MAX7042ATJ+ TEMP RANGE PIN-PACKAGE -40°C TO +125°C 32 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Home and Office Lighting Control Pin Configuration Remote Sensing Security Systems OP+ DS+ DS- PDMAX PDMIN Local Telemetry Systems DF TOP VIEW DGND Home Automation DVDD Smoke Alarms 24 23 22 21 20 19 18 17 N.C. 25 16 IFIN+ EN 26 15 IFIN- FSEL1 27 14 AGND FSEL2 28 13 MIXOUT HVIN 29 12 MIXIN- MAX7042 DATA 30 11 MIXIN+ LNASEL 31 10 LNAOUT N.C. 32 9 LNASRC EP 4 5 6 N.C. RSSI XTAL2 XTAL1 7 8 AVDD 3 LNAIN 2 N.C. Typical Application Circuit appears at end of data sheet. 1 N.C. + TQFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX7042 General Description MAX7042 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver ABSOLUTE MAXIMUM RATINGS HVIN to AGND or DGND .......................................-0.3V to +6.0V AVDD, DVDD to AGND or DGND..........................-0.3V to +4.0V FSEL1, FSEL2, LNASEL, EN, DATA...............................(DGND - 0.3V) to (HVIN + 0.3V) All Other Pins............................(AGND - 0.3V) to (AVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFN (derate 34.5mW/°C above +70°C)..........2759mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Maximum RF Input Power ................................................+0dBm Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VHVIN = +2.4V to +3.6V, fRF = 308, 315, 418, and 433.92MHz; T A = -40°C to +125°C, unless otherwise noted. Typical values are at V AVDD = V DVDD = V HVIN = +3.0V, fRF = 433.92MHz, PRFIN ≤ -80dBm, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage (3V) VDD HVIN, AVDD, and DVDD connected to power supply 2.4 3.0 3.6 V Supply Voltage (5V) HVIN HVIN connected to power supply, AVDD and DVDD unconnected from HVIN, but connected together 4.5 5.0 5.5 V 315MHz (3V) 315MHz (5V) Supply Current IDD 434MHz (3V) 434MHz (5V) Shutdown Current (3V) Shutdown Current (5V) Startup Time ISHDN ISHDN tON All digital inputs low All digital inputs low Operating, 1x ILNA 6.2 Operating, 2x ILNA 6.8 Operating, 1x ILNA 6.4 Operating, 2x ILNA 7.0 Operating, 1x ILNA 6.4 8.7 Operating, 2x ILNA 7.0 8.6 Operating, 1x ILNA 6.6 8.4 Operating, 2x ILNA 7.2 9.2 TA = +25°C 0.02 TA = +85°C 0.1 TA = +125°C 0.85 TA = +25°C 0.6 TA = +85°C 1.4 TA = +125°C 4 Time from EN = high to final signal detection; does not include baseband filter or dataslicer reference settling mA µA 6 µA 7 250 µs DIGITAL I/O Input High Threshold VIH Input Low Threshold VIL 2 0.9 x VHVIN V 0.1 x VHVIN _______________________________________________________________________________________ V 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VHVIN = +2.4V to +3.6V, fRF = 308, 315, 418, and 433.92MHz; T A = -40°C to +125°C, unless otherwise noted. Typical values are at V AVDD = V DVDD = V HVIN = +3.0V, fRF = 433.92MHz, PRFIN ≤ -80dBm, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Input High Pulldown Current IIH Input Low-Leakage Current IIL TYP MAX VHVIN = +3.6V CONDITIONS 8 15 VHVIN = +5.5V 20 40 VHVIN = +3.6V <1 1 VHVIN = +5.5V <1 1 Output High Voltage VOH ISOURCE = 500µA Output Low Voltage VOL ISINK = 500µA MIN UNITS µA µA VHVIN - 0.4 V 0.4 V VOLTAGE REGULATOR Output Voltage VREG 2.5 3.0 3.5 V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VHVIN = +2.4V to +3.6V, fRF = 308, 315, 418, and 433.92MHz; T A = -40°C to +125°C, unless otherwise noted. Typical values are at V AVDD = V DVDD = V HVIN = +3.0V, fRF = 433.92MHz, PRFIN ≤ -80dBm, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Maximum Input Level MIN TYP 0 315MHz setting Operating, 1x ILNA -107 Operating, 2x ILNA -110 434MHz setting Operating, 1x ILNA -106 Operating, 2x ILNA -109 Sensitivity (Note 1) Receiver Image Rejection 45 MAX UNITS dBm dBm dB LNA/MIXER Input Impedance (Note 2) ZIN_LNA 1dB Input Compression Point P1dB Input-Referred 3rd-Order Intercept Point IIP3 Normalized to 2x ILNA 315MHz 50Ω 2x ILNA 433.92MHz -47 2x ILNA 315MHz -52 1x ILNA 315MHz -37 2x ILNA 315MHz -42 ZoutMIX 330Ω IF filter load (Note 3) Voltage Conversion Gain 0.94 - j2.1 1x ILNA 315MHz LO Signal Feedthrough to Antenna Mixer Output Impedance 0.94 - j3.2 dBm dBm -80 dBm 330 Ω 1x ILNA 315MHz 52 2x ILNA 315MHz 57 1x ILNA 433.92MHz 47 2x ILNA 433.92MHz 52 dB IF LIMITING AMPLIFIER Input Impedance -3dB Bandwidth ZIN_IF 330 Ω 10 MHz _______________________________________________________________________________________ 3 MAX7042 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, 50Ω system impedance, VAVDD = VDVDD = VHVIN = +2.4V to +3.6V, fRF = 308, 315, 418, and 433.92MHz; T A = -40°C to +125°C, unless otherwise noted. Typical values are at V AVDD = V DVDD = V HVIN = +3.0V, fRF = 433.92MHz, PRFIN ≤ -80dBm, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Operating Frequency CONDITIONS MIN TYP fIF MAX UNITS 10.7 RSSI Slope MHz 10 16 21 mV/dB 1.1 2.1 3.0 mV/kHz FSK DEMODULATOR Conversion Gain ANALOG BASEBAND Maximum Peak-Detector Bandwidth 50 kHz Maximum Data-Filter Bandwidth BWDF 50 kHz Maximum Data-Slicer Bandwidth BWDS 100 kHz Maximum Data Rate Manchester coded 33 NRZ 66 kHz CRYSTAL OSCILLATOR Crystal Frequency fXTAL Crystal Load Capacitance (fRF - 10.7) / 32 MHz 4.5 pF Note 1: 0.2% BER, 4kbps, Manchester coded, 280kHz IF BW, ±50kHz frequency deviation. Note 2: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 3.9nH inductive degeneration from the LNA source to ground. The impedance at 433.92MHz includes a 0nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 47Ω in series with 3.2pF at 315MHz and 47Ω in series with 3.5pF at 433.92MHz. Note 3: The voltage conversion gain is measured with the LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not include the IF filter insertion loss. Typical Operating Characteristics (Typical Application Circuit, VDD = 3.0V, fRF = 433.92MHz, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2%, TA = +25°C, unless otherwise noted.) 6.4 6.2 +25°C 6.0 5.8 7.6 +85°C 7.4 7.2 7.0 +25°C 6.8 6.8 6.6 6.6 +125°C 6.4 +85°C +25°C 6.2 6.0 6.4 5.6 5.8 6.2 -40°C 5.4 2.7 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 -40°C -40°C 6.0 2.4 4 +125°C SUPPLY CURRENT (mA) 6.6 7.0 MAX7042 toc02 +85°C 6.8 7.8 SUPPLY CURRENT (mA) +125°C 7.0 8.0 MAX7042 toc01 7.2 SUPPLY CURRENT vs. RF FREQUENCY (1x ILNA) SUPPLY CURRENT vs. SUPPLY VOLTAGE (2x ILNA) MAX7042 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE (1x ILNA) SUPPLY CURRENT (mA) MAX7042 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver 5.6 2.4 2.7 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 300 325 350 375 400 RF FREQUENCY (MHz) _______________________________________________________________________________________ 425 450 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver 6.9 +25°C 6.7 6.5 6.1 MAX7042 toc05 VDD = +3.6V 400 VDD = +3.0V 325 350 375 400 425 450 10 1 0.2% BER 0.1 VDD = +2.4V fRF = 315MHz 0.01 0 300 -40 -15 10 35 60 85 -114 110 -112 -110 -106 -108 -104 RF FREQUENCY (MHz) TEMPERATURE (°C) AVERAGE INPUT POWER (dBm) BIT-ERROR RATE vs. AVERAGE INPUT POWER (2x ILNA) SENSITIVITY vs. TEMPERATURE (1x ILNA) SENSITIVITY vs. TEMPERATURE (2x ILNA) -103 -106 -104 MAX7042 toc09 fRF = 433.92MHz MAX7042 toc07 100 -107 1 0.2% BER SENSITIVITY (dBm) 10 SENSITIVITY (dBm) BIT-ERROR RATE (%) fRF = 433.92MHz 600 200 -40°C 6.3 800 BIT-ERROR RATE (%) +85°C 100 MAX7042 toc08 SUPPLY CURRENT (mA) 7.1 DEEP-SLEEP CURRENT (nA) +125°C 7.3 1000 MAX7042 toc04 7.5 BIT-ERROR RATE vs. AVERAGE INPUT POWER (1x ILNA) DEEP-SLEEP CURRENT vs. TEMPERATURE MAX7042 toc06 SUPPLY CURRENT vs. RF FREQUENCY (2x ILNA) -105 -106 fRF = 433.92MHz -107 -108 -109 fRF = 433.92MHz -110 0.1 -108 fRF = 315MHz 0.01 -111 -109 -112 -109 -107 -40 -15 10 35 60 85 -40 110 -15 10 35 60 85 110 TEMPERATURE (°C) TEMPERATURE (°C) SENSITIVITY vs. FREQUENCY DEVIATION RSSI AND DELTA vs. IF INPUT POWER FSK DEMODULATOR OUTPUT vs. IF FREQUENCY RSSI RSSI (V) 1 0.9 0 -108 0.6 -1 -110 0.3 DELTA -112 -2 -3 0 10 FREQUENCY DEVIATION (kHz) 100 -90 -70 -50 -30 IF INPUT POWER (dBm) -10 10 MAX7042 toc12 2.0 2 1.5 1.2 -106 3 FSK DEMODULATION OUTPUT (V) MAX7042 toc11 1.8 -104 1 fRF = 315MHz AVERAGE INPUT POWER (dBm) FREQUENCY DEVIATION IS MEASURED FROM 0 TO PEAK -102 SENSITIVITY (dBm) -113 DELTA (%) -100 -115 MAX7042 toc10 -117 -111 fRF = 315MHz 1.6 1.2 0.8 0.4 0 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0 IF FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX7042 Typical Operating Characteristics (continued) (Typical Application Circuit, VDD = 3.0V, fRF = 433.92MHz, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2%, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VDD = 3.0V, fRF = 433.92MHz, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2%, TA = +25°C, unless otherwise noted.) SYSTEM GAIN vs. IF FREQUENCY (2x ILNA) 50 45dB IMAGE REJECTION 10 SYSTEM GAIN (dB) FROM RFIN TO MIXOUT fRF = 433.92MHz 30 20 UPPER SIDEBAND LOWER SIDEBAND 40 FROM RFIN TO MIXOUT fRF = 433.92MHz 45dB IMAGE REJECTION 30 20 LOWER SIDEBAND 10 0 -10 0 5 10 15 20 25 0 30 5 10 15 20 25 30 30 20 0 -40 -15 35 -3 fRF = 315MHz 30 20 -6 -9 -12 -15 10 -18 0 -40 -15 10 35 60 85 10 1 110 IF FREQUENCY (MHz) TEMPERATURE (°C) S11 vs. RF FREQUENCY MAX7042 toc18 0 S11 (dB) -4 -8 433.92MHz -12 -16 100 250 400 550 700 850 1000 RF FREQUENCY (MHz) 6 60 MAX7042 toc17 0 NORMALIZED IF GAIN (dB) fRF = 433.92MHz 10 NORMALIZED IF GAIN vs. IF FREQUENCY MAX7042 toc16 60 IMAGE REJECTION (dB) fRF = 315MHz TEMPERATURE (°C) IMAGE REJECTION vs. TEMPERATURE (2x ILNA) 40 40 IF FREQUENCY (MHz) IF FREQUENCY (MHz) 50 fRF = 433.92MHz 10 0 -10 50 MAX7042 toc15 UPPER SIDEBAND 60 MAX7042 toc14 40 60 MAX7042 toc13 50 IMAGE REJECTION vs. TEMPERATURE (1x ILNA) IMAGE REJECTION (dB) SYSTEM GAIN vs. IF FREQUENCY (1x ILNA) SYSTEM GAIN (dB) MAX7042 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver _______________________________________________________________________________________ 100 85 110 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION S11 SMITH PLOT OF RFIN MAX7042 toc20 MAX7042 toc19 70 -150 433.92MHz 60 -160 50 -170 40 -180 REAL IMPEDANCE 30 IMAGINARY IMPEDANCE (Ω) REAL IMPEDANCE (Ω) fRF = 315MHz -190 IMAGINARY IMPEDANCE 20 -200 10 1 100 INDUCTIVE DEGENERATION (nH) PHASE NOISE vs. OFFSET FREQUENCY INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION 90 fRF = 433.92MHz -70 -100 fRF = 315MHz 80 -110 70 IMAGINARY IMPEDANCE 60 -120 50 REAL IMPEDANCE 40 -130 PHASE NOISE (dBc/Hz) -80 IMAGINARY IMPEDANCE (Ω) REAL IMPEDANCE (Ω) MAX7042 toc22 MAX7042 toc21 fRF = 433.92MHz -90 -100 -110 -120 30 -140 20 1 10 INDUCTIVE DEGENERATION (nH) 100 -130 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) _______________________________________________________________________________________ 7 MAX7042 Typical Operating Characteristics (continued) (Typical Application Circuit, VDD = 3.0V, fRF = 433.92MHz, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = ±50kHz, BER = 0.2%, TA = +25°C, unless otherwise noted.) 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042 Pin Description 8 PIN NAME 1, 2 N.C. No Connection. Internally pulled down. FUNCTION 3, 25, 32 N.C. No Connection. Not internally connected. 4 RSSI Buffered Received-Signal-Strength-Indicator Output 5 XTAL2 6 XTAL1 Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference. 7 AVDD Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in +5V operation. Bypass AVDD to GND with 0.1µF and 220pF capacitors placed as close to the pin as possible. 8 LNAIN Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference. Low-Noise Amplifier Input. Must be AC-coupled. 9 LNASRC Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set the LNA input impedance. 10 LNAOUT Low-Noise Amplifier Output. Connect to VAVDD through a parallel LC tank filter. AC-couple to MIXIN+. 11 MIXIN+ Noninverting Mixer Input. Must be AC-coupled to the LNA output. 12 MIXIN- Inverting Mixer Input. Bypass to VAVDD or AGND with a capacitor. 13 MIXOUT 14 AGND 15 IFIN- Inverting 330Ω IF Limiter Amplifier Input. Bypass to AGND with a capacitor. 16 IFIN+ Noninverting 330Ω IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter. 17 PDMIN Minimum-Level Peak Detector for Demodulator Output 18 PDMAX Maximum-Level Peak Detector for Demodulator Output 330Ω Mixer Output. Connect to the input of the 10.7MHz IF filter. Analog Ground 19 DS- Inverting Data-Slicer Input 20 DS+ Noninverting Data-Slicer Input 21 OP+ 22 DF 23 DGND Digital Ground 24 DVDD Digital Power-Supply Voltage. Bypass to DGND with 0.01µF and 220pF capacitors placed as close to the pin as possible. 26 EN Enable. Internally pulled down. Drive high for normal operation. Drive low or leave unconnected to put the device into shutdown mode. 27 FSEL1 Frequency-Select Pin 1 (see Table 1). Internally pulled down. Connect to EN for logic-high operation. 28 FSEL2 Frequency-Select Pin 2 (see Table 1). Internally pulled down. Connect to EN for logic-high operation. 29 HVIN High-Voltage Supply Input. For +3V operation, connect HVIN to AVDD and DVDD. For +5V operation, connect only HVIN to +5V. Bypass HVIN to AGND with 0.01µF and 220pF capacitors placed as close to the pin as possible. 30 DATA 31 LNASEL EP GND Noninverting Op-Amp Input for the Sallen-Key Data Filter Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. Receiver Data Output LNA Bias Current Select Pin. Internally pulled down. Set LNASEL to logic-low for low LNA current and set LNASEL to logic-high for high LNA current. Connect to EN for logic-high operation. Exposed Pad. Connect to ground. _______________________________________________________________________________________ 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver LNAOUT MIXIN+ MIXIN- 10 11 12 MIXOUT IFIN- 13 IFIN+ 15 16 IMAGE REJECTION LNAIN 8 LNASRC 9 LNA 0˚ Σ 90˚ XTAL2 6 CRYSTAL OSCILLATOR AGND 14 XTAL1 IF LIMITING AMPS DIVIDEBY-32 RSSI 4 RSSI VCO FSK FSK DEMODULATOR 5 PHASE DETECTOR 27 FSEL1 RDF1 100kΩ LOOP FILTER EN 26 RDF2 100kΩ DVDD 24 EXPOSED PAD* MAX7042 FSK DATA FILTER DGND 23 HVIN 29 AVDD 7 28 FSEL2 31 LNASEL 3.0V REG 3.0V 30 19 18 17 DATA DS- PDMAX PDMIN 20 21 22 DS+ OP+ DF *MUST BE CONNECTED TO AGND. _______________________________________________________________________________________ 9 MAX7042 Functional Diagram MAX7042 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver Detailed Description The MAX7042 CMOS superheterodyne receiver and a few external components provide a complete FSK receive chain from the antenna to the digital output data. FSK uses the difference in frequency of the carrier to represent a logic 0 and logic 1. Depending on signal power and component selection, data rates as high as 66kbps NRZ can be achieved. Frequency Selection The MAX7042 can be tuned to one of four frequencies using the 2 frequency-select bits FSEL1 and FSEL2: 308, 315, 418, and 433.92MHz, as shown in Table 1. The LO frequencies are 32 times the crystal reference frequencies of 9.29063, 9.50939, 12.72813, and 13.22563MHz. The selected crystal frequency is used to calibrate the FSK detector PLL so that it operates at the middle of the 10.7MHz IF. Table 1. Frequency Selection Table FSEL2 FSEL1 FREQUENCY (MHz) 0 0 308 0 1 315 1 0 418 1 1 433.92 Low-Noise Amplifier (LNA) The LNA is a cascode amplifier with off-chip inductive degeneration. The gain and the noise figure are dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer input. The MAX7042 allows for user programmability of the LNA bias current. Input LNASEL programs 1x to 2x bias currents in increments of 0.6mA from 0.6mA to 1.2mA. Setting LNASEL to logic-low programs the LNA to consume 1x bias current and setting LNASEL to logic-high programs the LNA to consume 2x bias current. Larger bias currents yield better sensitivity and gain at the expense of current drain. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible match to a low-input 10 impedance such as printed circuit board (PCB) trace antenna. A nominal value of this inductor for a 50Ω input impedance is 3.9nH at 315MHz and 0nH (short) at 433.92MHz, but is affected by the PCB trace. See the Typical Operating Characteristics for the relationship between the inductance and input impedance. The LC tank filter connected to LNAOUT consists of L2 and C9 (see the Typical Application Circuit). Select L2 and C9 to resonate at the desired RF input frequency. The resonant frequency is given by: f = 1 2π LTOTAL x CTOTAL where LTOTAL = L2 + LPARASITICS and CTOTAL = C9 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PCB traces, package pins, mixer input impedance, LNA output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation is required to optimize the center frequency of the tank. The parasitic capacitance is generally 5pF to 7pF. There are two ways to verify experimentally that the resonant frequency of the tank is centered at the desired RF frequency: 1) Drive the crystal oscillator externally and sweep both the RF frequency and the LO frequency (FXTAL x 32) to keep the IF at 10.7MHz while monitoring the RSSI voltage (pin 4). There is a peak in the RSSI voltage at resonance. The external source must be AC-coupled into XTAL1 and the XTAL2 pin must have an AC bypass to ground. The recommended drive power is -10dBm. 2) Use a network analyzer to measure the resonance. The port 1 power from the network analyzer is input to the receiver, and this power must be -30dBm or less. A coaxial stub with the center conductor exposed (commonly called an RF “sniffer” is used to monitor the tank power and serves as the port 2 input to the network analyzer. The sniffer should be placed in close proximity to, but not actually touching, the tank inductor. ______________________________________________________________________________________ 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver MAX7042 TO FSK BASEBAND FILTER AND DATA SLICER IF LIMITING AMPS PHASE DETECTOR CHARGE PUMP LOOP FILTER 10.7MHz VCO 2.1mV/kHz Figure 1. FSK Demodulator PLL Block Diagram Mixer Intermediate Frequency (IF) A unique feature of the MAX7042 is the integrated image rejection of the mixer. This device is designed to eliminate the need for a costly front-end SAW filter in many applications. The advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double-balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz intermediate frequency (IF) with low-side injection (i.e., fLO = fRF - fIF). The image-rejection circuit then combines these signals to achieve a typical image rejection of approximately 45dB. Low-side injection is required as high-side injection is not possible due to the on-chip image rejection. The IF output is driven by a source follower, biased to create a driving impedance of 330Ω to interface with an off-chip 330Ω ceramic IF filter. Note that MIXIN+ and MIXIN- are functionally identical. The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The internal six AC-coupled limiting amplifiers produce an overall gain of approximately 65dB. The limiting amplifiers have a bandpass-filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. The limiter output is fed into a PLL to demodulate the IF, producing a baseband voltage with a demodulation slope of 2.1mV/kHz. The RSSI circuit produces a DC output proportional to the log of the IF signal level with a slope of approximately 16mV/dB. Phase-Locked Loop (PLL) The PLL block contains a phase detector, charge pump/integrated loop filter, voltage-controlled oscillator (VCO), asynchronous 32x frequency divider, and crystal oscillator. This PLL does not require any external components. The relationship between the RF, IF, and crystal reference frequencies is given by: fXTAL = (fRF − fIF) 32 For additional information on proper crystal selection, see the Crystal Oscillator and Frequency Tolerance sections. FSK Demodulator The FSK demodulator uses an integrated 10.7MHz PLL that tracks the input RF modulation and determines the difference between frequencies as logic ones and zeros. The PLL is illustrated in Figure 1. The input to the PLL comes from the output of the IF limiting amplifiers. The PLL control voltage responds to changes in the frequency of the input signal with a nominal gain of 2.1mV/kHz. For example, an FSK peak-to-peak deviation of 50kHz generates a 105mVP-P signal on the control line. This control line is then filtered and sliced by the FSK baseband circuitry. The FSK demodulator PLL requires calibration to overcome variations in process, voltage, and temperature. The maximum calibration time is 120µs, which is included in the startup time. Recalibration is necessary after a significant change in temperature or supply voltage. Calibration occurs automatically each time the MAX7042 is powered up. Drive EN low and then high to force a recalibration. EN must be driven from low to high after the MAX7042 supply voltage is stable for proper initial FSK calibration. ______________________________________________________________________________________ 11 MAX7042 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver Crystal Oscillator Frequency Tolerance The XTAL oscillator in the MAX7042 is used to generate the LO for mixing with the received signal. The XTAL oscillator frequency sets the received signal frequency as: fRECEIVE = (fXTAL x 32) + 10.7MHz The received image frequency at: fIMAGE = (fXTAL x 32) - 10.7MHz The frequency tolerance of the crystal, the frequency and bandwidth tolerance of the IF filter, and the desired modulation bandwidth of the signal are all interrelated. The combination of these characteristics should be such to ensure that the modulated signal bandwidth stays within the passband of the IF filter after downconversion. As is shown below, a 50ppm tolerance crystal in combination with a 280kHz bandwidth IF filter is sufficient for most FSK-modulated signals. Smaller IF filter bandwidths can be used if high-tolerance crystals are used for generating both transmitter and MAX7042 receiver PLL references. The modulated spectrum of the transmitted signal must be downconverted by the MAX7042 to fall within the passband of the IF filter. The crystal tolerances must take into account the initial +25°C tolerance, aging, load capacitance tolerances, and temperature drift for both the transmitter and MAX7042 receiver. To achieve acceptable signal reception, the following equation must hold: 2 x (∆FTX + ∆FRX + ∆FIF + FDEV + 5 x FMOD) < IFBWmin where: ∆FTX = (transmitter crystal tolerance in ppm) x (carrier frequency in MHz). This includes aging, load capacitance, and temperature effects for the crystal tolerance. ∆FRX = (MAX7042 crystal tolerance in ppm) x (carrier frequency in MHz). This includes aging, load capacitance, and temperature effects for the crystal tolerance. ∆FIF = The center frequency tolerance of the selected IF filter. This includes temperature drift of the IF filter center frequency. FDEV = ±FSK frequency deviation from carrier frequency. FMOD = One half of NRZ data rate, or the data rate if Manchester coding is used. IFBWmin = The minimum bandwidth of the selected IF filter. As an example, assume 315MHz carrier frequency, ±50ppm crystal tolerances for both transmitter and MAX7042, ±30kHz IF filter center frequency tolerance, ±50kHz frequency deviation, and 4.8kHz Manchester data rate: 2 x [(315 x 50) + (315 x 50) + 30000 +50000 + 5 x 4800] = 271kHz < IFBWmin This operating condition necessitates a 280kHz IF filter. is suppressed by the integrated quadrature imagerejection circuitry. The XTAL oscillator in the MAX7042 is designed to present a capacitance of approximately 3pF between XTAL1 and XTAL2. In most cases, this corresponds to a 4.5pF load capacitance applied to the external crystal when typical PCB parasitics are added. It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7042 crystal oscillator plus PCB parasitics. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its intended operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. In reality, the oscillator pulls every crystal. A crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: fp = ⎞ 1 1 Cm ⎛ − x 106 2 ⎜⎝ Ccase + Cload Ccase + Cspec ⎟⎠ where: fp is the amount the crystal frequency is pulled in ppm. Cm is the motional capacitance of the crystal. Ccase is the case capacitance. Cspec is the specified load capacitance. Cload is the actual load capacitance. When the crystal is loaded as specified, i.e., Cload = Cspec, the frequency pulling equals zero. 12 ______________________________________________________________________________________ 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver b a(100kΩ)(π)(fC) a CF2 = 4(100kΩ)(π)(fC) CF1 = Table 2. Coefficients to Calculate CF1 and CF2 FILTER TYPE a b Butterworth (Q = 0.707) 1.414 1.000 Bessel (Q = 0.577) 1.3617 0.618 MAX7042 FSK DEMOD 100kΩ DS+ DF OP+ CF2 100kΩ CF1 Figure 2. Sallen-Key Lowpass Data Filter where fC is the desired 3dB corner frequency. For example, choose a Butterworth filter response with a 5kHz corner frequency: 1.000 ≈ 450pF (1.414)(100kΩ)(3.14)(5kHz) 1.414 CF2 = ≈ 225pF (4)(100kΩ)(3.14)(5kHz) CF1 = Choosing standard capacitor values changes CF1 to 470pF and CF2 to 220pF. In the Typical Application Circuit, CF1 and CF2 are named C4 and C3, respectively. Data Slicer The purpose of a data slicer is to take the analog output of a data filter and convert it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. The threshold voltage is set by the voltage on the DS- pin, which is connected to the negative input of the data-slicer comparator. The positive input of the data-slicer comparator is connected to the output of the data filter internally. ______________________________________________________________________________________ 13 MAX7042 Data Filters The data filter is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency in kHz should be to approximately the fastest expected data rate in kbps for NRZ and twice the fastest expected data rate in kbps for Manchester coding from the transmitter. Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 2 creates a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of the capacitors, use the following equations along with the coefficients in Table 2: MAX7042 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver Numerous configurations can be used to generate the data-slicer threshold. For example, the circuit in Figure 3 shows a simple method using only one resistor and one capacitor. This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R and C affect how fast the threshold tracks the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate. With this configuration, a long string of zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. Figure 4 shows a configuration that uses the positive and negative peak detectors to generate the threshold. This configuration sets the threshold to the midpoint between a high output and a low output of the data filter. MAX7042 DATA SLICER DATA The positive and negative peak detectors can be used together to form a data-slicer threshold voltage at a midvalue between the most positive and most negative voltage levels of the data stream (see the Data Slicers section and Figure 4). Set the RC time constant of the peak-detector combining network to at least 5 times the data period. The MAX7042 peak detectors track the baseband filter output voltage until all internal circuits are stable following an enable pin low-to-high transition. This feature allows for an extremely fast startup because the peak detectors never “catch” a false level created by a startup transient. The peak detectors exhibit a fast-attack/slowdecay response. Power-Supply Connections The MAX7042 can be powered from a 2.4V to 3.6V supply or a 4.5V to 5.5V supply. The device has an onchip linear regulator that reduces the 5V supply to 3V needed to operate the chip. 14 DS+ R C Figure 3. Generating Data-Slicer Threshold MAX7042 Peak Detectors The maximum peak detector (PDMAX) and minimum peak detector (PDMIN) outputs, in conjunction with a resistor and capacitor connected to GND, create DC output voltages proportional to the high- and low-peak values of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output voltage. DS- PEAK DET DATA SLICER DATA PDMAX PEAK DET R C R PDMIN C Figure 4. Generating Data-Slicer Threshold Using the Peak Detectors To operate the MAX7042 from a 3V supply, connect DVDD, AVDD, and HVIN to the 3V supply. When using a 5V supply, connect the supply to HVIN only, and connect AVDD to DVDD. In both cases, bypass DVDD and HVIN with a 0.01µF capacitor and AVDD with a 0.1µF capacitor. Place all bypass capacitors as close to the respective supply pin as possible. Control Interface Considerations When operating the MAX7042 with a +4.5V to +5.5V supply voltage, the LNASEL, FSEL1, FSEL2, and EN pins can be driven by a microcontroller with either 3V or 5V interface logic levels. When operating the MAX7042 with a +2.4V to +3.6V supply, the microcontroller must produce logic levels tha conform to the VIH and V IL specifications in the DC Electrical Characteristics Table. ______________________________________________________________________________________ 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capacitors close to all power-supply connections. A properly designed PCB is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of λ/10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PCB trace adds about 20nH Typical Application Circuit RSSI LNASEL VDD DATA 3.0V FSEL2 FSEL1 VDD C16 EN EN FSEL1 FSEL2 VDD DVDD XTAL2 DF XTAL1 MAX7042 C15 OP+ 7 DS+ DS- C1 PDMAX 9 10 11 12 C11 PDMIN IFIN- MIXOUT AGND MIXIN- MIXIN+ EXPOSED PAD C2 22 21 20 19 C4 R1 C5 18 17 IFIN+ LNAIN LNAOUT 8 23 C3 C13 L1 24 AVDD LNASRC RF INPUT 26 DGND 6 VDD C7 27 C14 X1 C6 28 HVIN RSSI 29 DATA 4 5 30 LNASEL 31 15 16 13 14 C12 C8 L3 C9 VDD IN L2 GND Y1 OUT C10 ______________________________________________________________________________________ 15 MAX7042 Layout Considerations MAX7042 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver Table 3. Component Values for Typical Application Circuit COMPONENT VALUE FOR 315MHz RF VALUE FOR 433.92MHz RF DESCRIPTION C1 0.01µF 0.01µF 5% C2 220pF 220pF 5% C3 220pF 220pF 5% C4 470pF 470pF 5% C5 0.047µF 0.047µF 10% C6 0.1µF 0.1µF 10% C7 100pF 100pF 10% C8 100pF 100pF 10% C9 1.2pF Open ±0.1pF C10 220pF 220pF 10% C11 100pF 100pF 10% C12 1500pF 1500pF 10% C13 220pF 220pF 10% C14 100pF 100pF 10% C15 100pF 100pF 10% C16 0.01µF 0.01µF 10% L1 82nH 39nH 5% or better* L2 30nH 16nH 5% or better* L3 3.9nH Short 5% or better* R1 100kΩ 100kΩ 5% X1 9.50939MHz 13.22563MHz Crystal, 4.5pF CLOAD, Crystek or Hong Kong X’tals Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata *Wirewound recommended. Chip Information Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 32 TQFN-EP T3255+3 21-0140 90-0001 16 PROCESS: CMOS ______________________________________________________________________________________ 308MHz/315MHz/418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver REVISION NUMBER 2 REVISION DATE 1/12 DESCRIPTION Updated Ordering Information, Absolute Maximum Ratings, DC and AC Electrical Characteristics, TOCs 5, 6, 7, 11; updated Pin Configuration, Pin Description, Functional Diagram, Phase-Locked Loop section, Power-Supply Connections section, Typical Application Circuit, and Table 3. PAGES CHANGED 1–5, 8, 9, 11, 14, 15, 16 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX7042 Revision History