LTC1419 14-Bit, 800ksps Sampling A/D Converter with Shutdown U FEATURES DESCRIPTIO ■ The LTC ®1419 is a 1µs, 800ksps, 14-bit sampling A/D converter that draws only 150mW from ±5V supplies. This easy-to-use device includes a high dynamic range sample-and-hold and a precision reference. Two digitally selectable power shutdown modes provide flexibility for low power systems. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 800ksps Power Dissipation: 150mW 81.5dB S/(N + D) and 93dB THD No Missing Codes No Pipeline Delay Nap and Sleep Shutdown Modes Operates with 2.5V Internal 15ppm/°C Reference or External Reference True Differential Inputs Reject Common Mode Noise 20MHz Full-Power Bandwidth Sampling Bipolar Input Range: ±2.5V 28-Pin SSOP and SO Packages U APPLICATIO S ■ ■ ■ ■ ■ Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 20MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has a µP compatible, 14-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5581252. U ■ The LTC1419 has a full-scale input range of ±2.5V. Outstanding AC performance includes 81.5dB S/(N + D) and 93dB THD with a 100kHz input; 80dB S/(N + D) and 86dB THD at the Nyquist input frequency of 400kHz. TYPICAL APPLICATIO Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency 800kHz, 14-Bit Sampling A/D Converter 27 –5V 26 25 10µF 10µF 24 23 22 µP CONTROL LINES 21 20 EFFECTIVE BITS 1µF 5V 28 14 86 13 80 12 74 11 68 10 62 9 8 7 6 19 5 18 4 17 3 16 2 fSAMPLE = 800kHz 1k 15 SIGNAL/(NOISE + DISTORTION) (dB) VREF OUTPUT 2.50V LTC1419 DIFFERENTIAL 1 AVDD +AIN ANALOG INPUT (–2.5V TO 2.5V) 2 –AIN DVDD 3 VREF VSS 4 REFCOMP BUSY 5 10µF AGND CS 6 D13(MSB) CONVST 7 D12 RD 8 D11 SHDN 9 D10 D0 10 D9 D1 11 14-BIT D8 D2 PARALLEL 12 D7 D3 BUS 13 D6 D4 14 DGND D5 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1419 TA02 1419 TA01 1419fb 1 LTC1419 W W W AXI U U U W PACKAGE/ORDER I FOR ATIO U ABSOLUTE RATI GS AVDD = VDD = DVDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3).............................(VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ......... (VSS – 0.3V) to 10V Digital Output Voltage ........ (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range LTC1419C .............................................. 0°C to 70°C LTC1419I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C +AIN 1 28 AVDD –AIN 2 27 DVDD VREF 3 26 VSS REFCOMP 4 LTC1419ACG LTC1419ACSW LTC1419AIG LTC1419AISW LTC1419CG LTC1419CSW LTC1419IG LTC1419ISW 25 BUSY AGND 5 24 CS D13(MSB) 6 23 CONVST D12 7 22 RD D11 8 21 SHDN D10 9 20 D0 D9 10 19 D1 D8 11 18 D2 D7 12 17 D3 D6 13 16 D4 DGND 14 15 D5 G PACKAGE 28-LEAD PLASTIC SSOP SW PACKAGE 28-LEAD PLASTIC SO TJMAX = 125°C, θJA = 95°C/W (G) TJMAX = 125°C, θJA = 130°C/W (SW) Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult factory for Military grade parts. U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6) PARAMETER CONDITIONS MIN ● Resolution (No Missing Codes) Integral Linearity Error (Note 7) Differential Linearity Error LTC1419 TYP MAX MIN 13 LTC1419A TYP MAX 14 UNITS Bits ● ±0.8 ±2 ±0.6 ● ±0.7 ±1.5 ±0.5 ±1 LSB ● ±5 ±20 ±5 ±20 LSB ±60 ±10 ±5 ±60 LSB LSB Offset Error (Note 8) Full-Scale Error Internal Reference External Reference = 2.5V ±10 ±5 Full-Scale Tempco IOUT(REF) = 0 ±15 ±1.25 ±15 LSB ppm/°C U U A ALOG I PUT The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (Note 9) 4.75V ≤ VDD ≤ 5.25V, –5.25 ≤ VSS ≤ – 4.75V ● MIN IIN Analog Input Leakage Current CS = High ● CIN Analog Input Capacitance Between Conversions During Conversions tACQ Sample-and-Hold Acquisition Time t AP Sample-and-Hold Aperture Delay Time t jitter Sample-and-Hold Aperture Delay Time Jitter CMRR Analog Input Common Mode Rejection Ratio TYP ±1 90 –1.5 UNITS V 15 5 ● – 2.5V < (– AIN = AIN) < 2.5V MAX ±2.5 µA pF pF 300 ns ns 2 psRMS 60 dB 1419fb 2 LTC1419 W U DY A IC ACCURACY The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP 78 81.5 80.0 S/(N + D) Signal-to-(Noise + Distortion) Ratio 100kHz Input Signal 390kHz Input Signal ● THD Total Harmonic Distortion 100kHz Input Signal, First 5 Harmonics 390kHz Input Signal, First 5 Harmonics ● – 93 – 86 – 86 dB dB SFDR Spurious Free Dynamic Range 100kHz Input Signal ● – 95 – 86 dB IMD Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.446kHz S/(N + D) ≥ 77dB U U U I TER AL REFERE CE CHARACTERISTICS PARAMETER UNITS dB dB – 86 Full-Power Bandwidth Full-Linear Bandwidth MAX dB 20 MHz 1 MHz (Note 5) CONDITIONS MIN TYP MAX UNITS VREF Output Voltage IOUT = 0 2.480 2.500 2.520 VREF Output Tempco IOUT = 0 ±15 ppm/°C VREF Line Regulation 4.75V ≤ VDD ≤ 5.25V, – 5.25 ≤ VSS ≤ – 4.75V 0.05 LSB/V VREF Output Resistance – 0.1mA ≤ ⏐IOUT⏐ ≤ 0.1mA REFCOMP Output Voltage IOUT = 0 V 2 kΩ 4.06 V U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.75V ● IIN Digital Input Current VIN = 0V to VDD ● CIN Digital Input Capacitance VOH High Level Output Voltage VOL Low Level Output Voltage MIN VDD = 4.75V IO = – 10µA IO = – 200µA ● VDD = 4.75V IO = 160µA IO = 1.6mA ● TYP MAX UNITS 2.4 V 0.8 V ±10 µA 5 pF 4.5 V V 4.0 0.05 0.10 0.4 V V IOZ Hi-Z Output Leakage D13 to D0 VOUT = 0V to VDD, CS High ● ±10 µA COZ Hi-Z Output Capacitance D13 to D0 CS High (Note 9 ) ● 15 pF ISOURCE Output Source Current VOUT = 0V – 10 mA ISINK Output Sink Current VOUT = VDD 10 mA U W POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS VDD Positive Supply Voltage (Note 10) VSS Negative Supply Voltage (Note 10) IDD Positive Supply Current Nap Mode Sleep Mode SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V Negative Supply Current Nap Mode Sleep Mode SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V ISS MIN TYP MAX UNITS 4.75 5.25 V – 4.75 – 5.25 V ● 11 1.5 250 20 mA mA µA ● 19 100 1 30 mA µA µA 1419fb 3 LTC1419 U W POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER PDIS Power Dissipation Nap Mode Sleep Mode CONDITIONS MIN ● SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V TYP MAX UNITS 150 7.5 1.2 240 12 mW mW mW WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency CONDITIONS ● MIN tCONV Conversion Time ● tACQ Acquisition Time ● 90 300 ns tACQ + CONV Acquisition + Conversion Time ● 1040 1250 ns t1 CS to RD Setup Time t2 t3 t4 SHDN↑ to CONVST↓ Wake-Up Time (Note 10) t5 CONVST Low Time (Notes 10, 11) t6 CONVST to BUSY Delay CL = 25pF (Notes 9, 10) ● CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● CS↓ to SHDN↓ Setup Time (Notes 9, 10) ● TYP Data Ready Before BUSY↑ 950 ns ns 40 ns 40 ns 400 ns 20 ns ns 40 ns 50 ● 20 15 Delay Between Conversions (Note 10) ● 40 t9 Wait Time RD↓ After BUSY↑ (Note 9) ● –5 t10 Data Access Time After RD↓ CL = 25pF 50 CL = 100pF ns 15 25 35 ns ns 20 35 50 ns ns 10 20 25 30 ns ns ns ● Bus Relinquish Time ● ● ns ns ns ● 0°C ≤ TA ≤ 70°C – 40°C ≤ TA ≤ 85°C 1150 0 t8 t11 UNITS kHz ● t7 MAX 800 t12 RD Low Time ● t 10 ns t13 CONVST High Time ● 40 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliabilty and lifetime. Note 2: All voltage values are with respect to ground with DGND and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended +AIN input with – AIN grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling edge of CONVST starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 650ns after the start of the conversion or after BUSY rises. 1419fb 4 LTC1419 U W TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude Signal-to-Noise Ratio vs Input Frequency VIN = 0dB 70 VIN = –20dB 80 60 50 40 30 AMPLITUDE (dB BELOW THE FUNDAMENTAL) 80 SIGNAL-TO -NOISE RATIO (dB) SIGNAL/(NOISE + DISTORTION) (dB) Distortion vs Input Frequency 90 90 VIN = –60dB 20 10 70 60 50 40 30 20 10 0 0 1k 100k 10k INPUT FREQUENCY (Hz) 1k 1M 2M 10k 100k INPUT FREQUENCY (Hz) –10 –20 –30 –40 –50 –60 –70 –80 THD –90 2ND –100 3RD – 110 1k 1M 2M 10k 100k INPUT FREQUENCY (Hz) 1419 G02 1419 G01 Spurious-Free Dynamic Range vs Input Frequency 0 Differential Nonlinearity vs Output Code – 20 –20 1.0 fSAMPLE = 800kHz fIN1 = 95.8984375kHz fIN2 = 104.1015625kHz –10 1M 2M 1419 G03 Intermodulation Distortion Plot 0 0.5 –40 –50 –60 –70 DNL ERROR (LSBs) –30 AMPLITUDE (dB) SPURIOUS-FREE DYNAMIC RANGE (dB) 0 – 40 – 60 – 80 –80 0 – 0.5 – 90 –100 –100 –110 10k –1.0 –120 100k INPUT FREQUENCY (Hz) 1M 0 2M 50 100 150 200 250 300 350 400 FREQUENCY (kHz) 1419 G04 INL ERROR (LSBs) 0.5 0 – 0.5 –1.0 0 4096 12288 8192 OUTPUT CODE 16384 1419 G07 12288 8192 OUTPUT CODE Power Supply Feedthrough vs Ripple Frequency Input Common Mode Rejection vs Input Frequency 0 80 –10 70 –20 –30 –40 –50 –60 –70 –80 VDD VSS –90 DGND –100 1k 100k 10k RIPPLE FREQUENCY (Hz) 16384 1419 G06 COMMON MODE REJECTION (dB) 1.0 4096 1419 G05 AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) Integral Nonlinearity vs Output Code 0 60 50 40 30 20 10 0 1M 2M 1419 G08 1 1000 10 100 INPUT FREQUENCY (Hz) 10000 1419 G09 1419fb 5 LTC1419 U U U PI FU CTIO S + AIN (Pin 1): ±2.5V Positive Analog Input. – AIN (Pin 2): ±2.5V Negative Analog Input. VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 1µF. REFCOMP (Pin 4): 4.06V Reference Output. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The output format is 2’s complement. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND. D5 to D0 (Pins 15 to 20): Three-State Data Outputs. The output format is 2’s complement. SHDN (Pin 21): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by CS. CS = 0 for nap mode and CS = 1 for sleep mode. RD (Pin 22): Read Input. This enables the output drivers when CS is low. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): Chip Select. The input must be low for the ADC to recognize CONVST and RD inputs. CS also sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high and SHDN low select sleep mode. BUSY (Pin 25): The BUSY output shows the converter status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY. VSS (Pin 26): – 5V Negative Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. DVDD (Pin 27): 5V Positive Supply. Short to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. U U W FU CTIO AL BLOCK DIAGRA CSAMPLE +AIN AVDD CSAMPLE – AIN 2k VREF DVDD ZEROING SWITCHES 2.5V REF VSS + REF AMP COMP 14-BIT CAPACITIVE DAC – REFCOMP (4.096V) AGND SUCCESSIVE APPROXIMATION REGISTER 14 • • • OUTPUT LATCHES D13 D0 DGND INTERNAL CLOCK CONTROL LOGIC 1419 BD SHDN CONVST RD CS BUSY 1419fb 6 LTC1419 TEST CIRCUITS Load Circuits for Output Float Delay Load Circuits for Access Timing 5V 5V 1k 1k DBN DBN DBN 1k CL 1k CL 100pF (A) VOH TO Hi-Z (B) Hi-Z TO VO (A) Hi-Z TO VOH DBN 100pF (B) VOL TO Hi-Z 1419 TC02 1419 TC01 U U W U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1419 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. +CSAMPLE +AIN SAMPLE HOLD –AIN ZEROING SWITCHES –CSAMPLE SAMPLE HOLD HOLD HOLD +CDAC + +VDAC –CDAC COMP DYNAMIC PERFORMANCE – –VDAC 14 SAR • D13 • • D0 OUTPUT LATCHES 1419 F01 Figure 1. Simplified Block Diagram During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the + AIN and – AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 200ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches open, putting the comparator into compare mode. The input switches the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the + AIN and – AIN input charges. The SAR contents (a 14-bit data word) which represents the difference of + AIN and – AIN are loaded into the 14-bit output latches. The LTC1419 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for 1419fb 7 LTC1419 U W U U APPLICATIONS INFORMATION frequencies outside the fundamental. Figure 2 shows a typical LTC1419 FFT plot. 0 fSAMPLE = 800kHz fIN = 99.804687kHz SFDR = 98dB THD = –93.3dB – 20 AMPLITUDE (dB) – 40 Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 800kHz, the LTC1419 maintains near ideal ENOBs up to the Nyquist input frequency of 400kHz (refer to Figure 3). – 60 – 80 –100 –120 –140 0 50 Figure 2a. LTC1419 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz 0 fSAMPLE = 800kHz fIN = 375kHz SFDR = 88.3dB SINAD = 80.1 AMPLITUDE (dB) – 20 EFFECTIVE BITS 1419 F02a 14 86 13 80 12 74 11 68 10 62 9 8 7 6 5 4 3 – 40 2 fSAMPLE = 800kHz 1k – 60 SIGNAL/(NOISE + DISTORTION) (dB) 100 150 200 250 300 350 400 FREQUENCY (kHz) 10k 100k INPUT FREQUENCY (Hz) – 80 1M 2M 1419 TA02 –100 Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency –120 –140 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) 1419 F02b Figure 2b. LTC1419 Nonaveraged, 4096 Point FFT, Input Frequency = 375kHz Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical spectral content with a 800kHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 400kHz. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: V22 + V32 + V 42 + … Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure 4. The LTC1419 has good distortion performance up to the Nyquist frequency and beyond. THD = 20Log 1419fb 8 LTC1419 U W U U AMPLITUDE (dB BELOW THE FUNDAMENTAL) APPLICATIONS INFORMATION 0 (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: –10 –20 –30 –40 ( ) IMD fa + fb = 20 Log –50 –60 Amplitude at (fa + fb) Amplitude at fa –70 –80 THD –90 Peak Harmonic or Spurious Noise 2ND –100 3RD – 110 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M 1419 G03 Figure 4. Distortion vs Input Frequency Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include 0 fSAMPLE = 800kHz fIN1 = 95.8984375kHz fIN2 = 104.1015625kHz AMPLITUDE (dB) – 20 – 40 – 60 – 80 –100 –120 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) 1419 G05 Figure 5. Intermodulation Distortion Plot The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 77dB (12.5 effective bits). The LTC1419 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1419 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the – AIN input is grounded). The + AIN and – AIN inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1419 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is 1419fb 9 LTC1419 U W U U APPLICATIONS INFORMATION that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 200ns for full throughput rate). ACQUISITION TIME (µs) 10 LT1223: 100MHz video current feedback amplifier. ±5V to ±15V supplies, 6mA supply current. Low distortion at frequencies above 400kHz. Low noise. Good for AC applications. LT1227: 140MHz video current feedback amplifier. ±5V to ±15V supplies, 10mA supply current. Lowest distortion at frequencies above 400kHz. Low noise. Best for AC applications. 1 0.1 0.01 0.01 LT ® 1220: 30MHz unity-gain bandwidth voltage feedback amplifier. ±5V to ±15V supplies. Excellent DC specifications. 1 10 0.1 SOURCE RESISTANCE (kΩ) 100 1419 F06 Figure 6. tACQ vs Source Resistance Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz should be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 20MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1419 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1419. More detailed information is available in the Linear Technology databooks, the LinearViewTM CD-ROM and on our web site at www.lineartech. com. LinearView is a trademark of Linear Technology Corporation. LT1229/LT1230: Dual/quad 100MHz current feedback amplifiers. ±2V to ±15V supplies, 6mA supply current each amplifier. Low noise. Good AC specs. LT1360: 50MHz voltage feedback amplifier. ±5V to ±15V supplies, 3.8mA supply current. Good AC and DC specs. LT1363: 70MHz, 1000V/µs op amps, 6.3mA supply current. Good AC and DC specs. LT1364/LT1365: Dual and quad 70MHz, 1000V/µs op amps. 6.3mA supply current per amplifier. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1419 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 20MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for ANALOG INPUT 50Ω 1 +AIN 1000pF 2 –AIN LTC1419 3 4 VREF REFCOMP 10µF 5 AGND 1419 F07 Figure 7. RC Input Filter 1419fb 10 LTC1419 U W U U APPLICATIONS INFORMATION many applications. For example, Figure 7 shows a 1000pF capacitor from + AIN to ground and a 100Ω source resistor to limit the input bandwidth to 1.6MHz. The 1000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Input Range The ±2.5V input range of the LTC1419 is optimized for low noise and low distortion. Most op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1419 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1419 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3) see Figure 8a. A 2.500V 4.0625V R1 2k 3 VREF 4 REFCOMP 1 ANALOG INPUT VIN 2 LT1019A-2.5 VOUT 3 +AIN –AIN VREF LTC1419 4 + 10µF 0.1µF 5 REFCOMP AGND 1419 F08b Figure 8b. Using the LT1019-2.5 as an External Reference 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry, see Figure 8b. The reference amplifier gains the voltage at the VREF pin by 1.625 to create the required internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin (REFCOMP, Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater. For the best noise performance, a 10µF ceramic or 10µF tantalum in parallel with a 0.1µF ceramic is recommended. The VREF pin can be driven with a DAC or other means shown in Figure 9. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1419 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed for after a reference adjustment. 1 ANALOG INPUT 1.25V TO 3V DIFFERENTIAL BANDGAP REFERENCE 2 +AIN –AIN LTC1419 REFERENCE AMP LTC1450 1.25V TO 3V 3 R2 40k 10µF 5 AGND 5V 4 VREF REFCOMP 10µF R3 64k 5 AGND LTC1419 1419 F09 1419 F08a Figure 8a. LTC1419 Reference Circuit Figure 9. Driving VREF with a DAC 1419fb 11 LTC1419 U U W U APPLICATIONS INFORMATION Differential Inputs The LTC1419 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of + AIN – (– AIN) independent of the common mode voltage (see Figure 11a). The common mode rejection holds up to extremely high frequencies, see Figure 10a. The only requirement is that both inputs can not exceed the AVDD or AVSS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Dynamic performance is also affected by the common mode voltage. THD will degrade as the inputs approach either power supply rail, from 86dB with a common mode of 0V to 76dB with a common mode of 2.5V or – 2.5V. Differential inputs allow greater flexibility for accepting different input ranges. Figure 10b shows a circuit that converts a 0V to 5V analog input signal with only an additional buffer that is not in the signal path. Full-Scale and Offset Adjustment Figure 11a shows the ideal input/output characteristics for the LTC1419. The code transitions occur midway between successive integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output is two’s complement binary with 1LSB = FS – (– FS)/16384 = 5V/16384 = 305.2µV. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 11b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset 011...111 70 011...110 60 50 OUTPUT CODE COMMON MODE REJECTION (dB) 80 40 30 000...001 000...000 111...111 111...110 20 100...001 10 100...000 0 1 1000 10 100 INPUT FREQUENCY (Hz) 10000 INPUT VOLTAGE [+AIN – (–AIN)] 1419 F11a Figure 10a. CMRR vs Input Frequency ANALOG INPUT 1 2 ±2.5V 0V TO 5V + 3 – Figure 11a. LTC1419 Transfer Characteristics 5V R8 50k –AIN R4 100Ω VREF R6 24k REFCOMP 1 2 3 R5 R7 47k 50k 4 5 + 10µF 5 ANALOG INPUT R3 24k +AIN LTC1419 4 FS – 1LSB – (FS – 1LSB) 1419 G09 10µF 0.1µF +AIN –AIN LTC1419 VREF REFCOMP AGND 1419 F11b AGND 1419 F10 Figure 10b. Selectable 0V to 5V or ±2.5V Input Range Figure 11b. Offset and Full-Scale Adjust Circuit 1419fb 12 LTC1419 U U W U APPLICATIONS INFORMATION microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. applied to the – AIN input. For zero offset error, apply – 152µV (i.e., – 0.5LSB) at + AIN and adjust the offset at the – AIN input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.499544V (FS/2 – 1.5LSBs) is applied to + A IN and R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. The LTC1419 has differential inputs to minimize noise coupling. Common mode noise on the + AIN and – AIN leads will be rejected by the input CMRR. The – AIN input can be used as a ground sense for the + AIN input; the LTC1419 will hold and convert the difference voltage between + AIN and – AIN. The leads to + AIN (Pin 1) and – AIN (Pin 2) should be kept as short as possible. In applications where this is not possible, the + AIN and – AIN traces should be run side by side to equalize coupling. BOARD LAYOUT AND GROUNDING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1419, a printed circuit board with ground plane is required. Layout should ensure that digital and analog signal lines are separated as much as possible. Particular care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.The analog input should be screened by AGND. SUPPLY BYPASSING High quality, low series resistance ceramic, 10µF bypass capacitors should be used at the VDD and REFCOMP pins as shown in the Typical Application on the fist page of this data sheet. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively, 10µF tantalum capacitors in parallel with 0.1µF ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the 1 + – 2 Figures 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a 2-layer printed circuit board. DIGITAL SYSTEM LTC1419 +AIN –AIN REFCOMP ANALOG INPUT CIRCUITRY Example Layout AGND 4 5 10µF AVDD DVDD VSS 26 10µF 28 DGND 27 14 10µF ANALOG GROUND PLANE 1419 F12 Figure 12. Power Supply Grounding Practice 1419fb 13 J7 J5 VLOGIC R19 51Ω CS RD SHDN JP5B JP5A HC14 2 JP5C 1 3 R20 1M HC14 U7B C13 10µF 16V C11 1000pF R15 51Ω D15 SS12 R16 51Ω C8 1µF 16V JP2 U7A JP4 DGND C7 1000pF R18 10k R17 10k VOUT GND TABGND 2 4 VIN 3 4 C2 22µF 10V JP3 C4 0.1µF C12 0.1µF C9 10µF 16V VCC C3 VSS 0.1µF U3 V+ LT1363 2 7 – 6 3 + 8 1 V– 4 VCC R14 20Ω VOUT VCC C6 1000pF + VCC NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5% 2. ALL CAPACITOR VALUES IN µF, 25V, 20% AND IN pF, 50V, 10% CLK A– A+ AGND J2 J4 GND +VIN 1 LT1121-5 14 5 26 27 28 21 22 23 24 25 4 3 2 1 C10 10µF 10V C15 0.1µF 7 VCC U7G HC14 GND 14 VLOGIC DGND AGND VSS DVDD AVDD SHDN RD CONVST CS BUSY D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 B11 B10 8 9 13 HC14 U7F 20 B00 19 B01 18 B02 17 B03 16 B04 15 B05 13 B06 12 B07 11 B08 10 B09 B12 B13 7 6 U1 79L05 1 IN OUT GND 5 D14 SS12 U4 LTC1419 REFCOMP VREF –AIN +AIN DATA READY + –VIN J1 –7V TO –15V 2 VSS 12 B[00:13] C1 22µF 10V 1 5 9 8 7 B07 B06 6 5 4 3 2 11 1 9 8 7 6 5 B08 B09 B10 B11 B12 B13 B05 B04 B03 4 3 B01 B02 2 B00 11 Figure 13a. Suggested Evaluation Circuit Schematic C5 10µF 16V VSS C14 0.1µF VLOGIC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 HC14 U7C D7 D6 D5 D4 D3 D2 D1 D0 0E 6 12 13 14 15 16 17 18 19 12 13 14 15 16 17 18 19 C16 15pF R21 1k Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 U6 74HC574 D7 D6 D5 D4 D3 D2 D1 D0 0E U5 74HC574 D06 D07 D08 D09 D10 D11 D12 D13 D05 D04 D03 D02 D01 D00 9 HC14 U7D 11 8 HC14 U7E D[00:13] 10 D13 RDY D13 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D13 D12 D11 J6-12 J6-11 J6-14 JP1 LED D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 DC124 SCHEM DGND DGND RDY D13 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 HEADER 18-PIN J6-18 J6-17 J6-16 J6-15 J6-2 J6-1 J6-4 J6-3 J6-6 J6-5 J6-8 J6-7 J6-10 J6-9 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D10 J6-13 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 1.2k U U W U2 APPLICATIONS INFORMATION U 14 + J3 7V TO 15V LTC1419 1419fb LTC1419 U W U U APPLICATIONS INFORMATION Figure 13b. Suggested Evaluation Circuit Board—Component Side Silkscreen Figure 13c. Suggested Evaluation Circuit Board—Component Side Layout 1419fb 15 LTC1419 U W U U APPLICATIONS INFORMATION Figure 13d. Suggested Evaluation Circuit Board—Solder Side Layout DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 0.95µs and a maximum conversion time over the full operating temperature range of 1.15µs. No external adjustments are required. The guaranteed maximum acquisition time is 300ns. In addition, a throughput time of 1.25µs and a minimum sampling rate of 800ksps are guaranteed. mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from nap to active is 400ns. In sleep mode, the reference is shut down and only a small current remains, about 250µA. Wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 10ms with the recommended 10µF capacitor. Shutdown is controlled by Pin 21 (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 20 (CS); low selects nap. CS t3 SHDN 1419 F14a Power Shutdown Figure 14a. CS to SHDN Timing The LTC1419 provides two power shutdown modes, nap and sleep, to save power during inactive periods. The nap 1419fb 16 LTC1419 U U W U APPLICATIONS INFORMATION In slow memory and ROM modes (Figures 19 and 20), CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). SHDN t3 CONVST 1419 F14b Figure 14b. SHDN to CONVST Wake-Up Timing In slow memory mode, the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a WAIT state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A logic “0” applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. Figures 16 through 20 show several different modes of operation. In modes 1a and 1b (Figures 16 and 17), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. CS t1 RD In mode 2 (Figure 18), CS is tied low. The falling edge of the CONVST signal again starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus. 1419 F15 Figure 15. CS to CONVST Set-Up Timing t CONV CS = RD = 0 (SAMPLE N) t5 CONVST t6 t8 BUSY t7 DATA DATA (N – 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1419 F16 Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) 1419fb 17 LTC1419 U U W U APPLICATIONS INFORMATION tCONV CS = RD = 0 t8 t5 t13 CONVST t6 t6 t6 BUSY t7 DATA (N – 1) DB13 TO DB0 DATA DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1419 F17 Figure 17. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) t13 (SAMPLE N) tCONV t5 CS = 0 t8 CONVST t6 BUSY t9 t 11 t 12 RD t 10 DATA N DB13 TO DB0 DATA 1419 F18 Figure 18. Mode 2. CONVST Starts a Conversion. Data is Read by RD t8 t CONV CS = 0 (SAMPLE N) RD = CONVST t6 t 11 BUSY t 10 DATA t7 DATA (N – 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1419 F19 Figure 19. Slow Memory Mode Timing 1419fb 18 LTC1419 W U U UO APPLICATI S I FOR ATIO t CONV CS = 0 t8 (SAMPLE N) RD = CONVST t6 t 11 BUSY t 10 DATA N DB13 TO DB0 DATA (N – 1) DB13 TO DB0 DATA 1419 F20 Figure 20. ROM Mode Timing U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 10.07 – 10.33* (0.397 – 0.407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 5.20 – 5.38** (0.205 – 0.212) 1.73 – 1.99 (0.068 – 0.078) 0° – 8° 0.13 – 0.22 (0.005 – 0.009) 0.55 – 0.95 (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 0.65 (0.0256) BSC 0.25 – 0.38 (0.010 – 0.015) 0.05 – 0.21 (0.002 – 0.008) G28 SSOP 1098 1419fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1419 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.037 – 0.045 (0.940 – 1.143) 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.050 (1.270) BSC 0.016 – 0.050 (0.406 – 1.270) 0.004 – 0.012 (0.102 – 0.305) 0.014 – 0.019 (0.356 – 0.482) TYP S28 (WIDE) 1098 NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1278/79 Single Supply, 500ksps/600ksps ADCs Low Power, 5V or ±5V Supply LTC1400 High Speed, Serial 12-Bit ADC 400ksps, Complete with Internal Reference, SO-8 Package LTC1409 Low Power, 12-Bit, 800ksps Sampling ADC Best Dynamic Performance, fSAMPLE ≤ 800ksps, 80mW Dissipation LTC1410 12-Bit, 1.25Msps Sampling ADC with Shutdown Best Dynamic Performance, THD = 84dB and SINAD = 71dB at Nyquist LTC1415 Single 5V, 12-Bit 1.25Msps ADC Single Supply, 55mW Dissipation LTC1604 16-Bit 333ksps ADC ±2.5V Inputs, Pin Compatible with the LTC1608 LTC1605 Single 5V, 16-Bit 100ksps ADC Low Power, ±10V Inputs LTC1606 16-Bit 250ksps ADC ±10V Inputs, Pin Compatible with the LTC1605 LTC1608 16-Bit 500ksps ADC ±2.5V Inputs, Pin Compatible with the LTC1604 1419fb 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com LT 0506 REV B • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1997