AD AD5530 Serial input, voltage output 12-/14-bit dac Datasheet

a
Serial Input, Voltage Output
12-/14-Bit DACs
AD5530/AD5531
FEATURES
Pin-Compatible 12- and 14-Bit DACs
Serial Input, Voltage Output
Maximum Output Voltage Range of ⴞ10 V
Data Readback
3-Wire Serial Interface
Clear Function to a User-Defined Voltage
Power-Down Function
Serial Data Output for Daisy-Chaining
16-Lead TSSOP Packages
GENERAL DESCRIPTION
The AD5530 and AD5531 are single 12-/14-bit serial input,
voltage output DACs, respectively.
They utilize a versatile 3-wire interface that is compatible with
SPI™, QSPI™, MICROWIRE™, and DSP interface standards.
Data is presented to the part in the format of a 16-bit serial word.
Serial data is available on the SDO pin for daisy-chaining purposes. Data readback allows the user to read the contents of the
DAC register via the SDO pin.
The DAC output is buffered by a gain of 2 amplifier and referenced to the potential at DUTGND. LDAC may be used to update
the output of the DAC asynchronously. A power-down (PD) pin
allows the DAC to be put into a low power state, and a CLR pin
allows the output to be cleared to a user-defined voltage, the
potential at DUTGND.
APPLICATIONS
Industrial Automation
Automatic Test Equipment
Process Control
General-Purpose Instrumentation
The AD5530 and AD5531 are available in 16-lead TSSOP
packages.
FUNCTIONAL BLOCK DIAGRAM
VSS
VDD
AD5530/AD5531
REFIN
R
–
R
12-/14-BIT DAC
+
LDAC
R
R
DAC REGISTER
RBEN
VOUT
–
+
REFAGND
DUTGND
CLR
SHIFT REGISTER
SDIN
POWER-DOWN
CONTROL LOGIC
GND
SCLK
SYNC
PD
SDO
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
(VDD = +15 V ±10%; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and
L
MIN to TMAX, unless otherwise noted.)
AD5530/AD5531–SPECIFICATIONS1 C = 220 pF to GND. All specifications T
Parameter
AD5530
AD5531
Unit
12
±1
±1
±2
±2
±1
0.5
10
14
±2
±1
±8
±8
±4
0.5
10
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
ppm FSR/°C typ
ppm FSR/°C max
0/5
100
±1
0/5
100
±1
V min/V max
MΩ typ
µA max
60
± 0.3
–4/+4
60
± 0.3
–4/+4
kΩ typ
mA typ
V min/V max
O/P CHARACTERISTICS
Output Voltage Swing
Short Circuit Current
Resistive Load
Capacitive Load
DC Output Impedance
± 10
15
5
1200
0.5
± 10
15
5
1200
0.5
V max
mA max
kΩ min
pF max
Ω max
DIGITAL I/O
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance2
SDO VOL Output Low Voltage
2.4
0.8
± 10
10
0.4
2.4
0.8
± 10
10
0.4
V min
V max
µA max
pF max
V max
Total for All Pins
3 pF Typ
ISINK = 1 mA
+15/–15
+15/–15
V nom
± 10% For Specified Performance
110
100
2
2
150
110
100
2
2
150
dB typ
dB typ
mA max
mA max
µA max
Outputs Unloaded
Outputs Unloaded
Typically 50 µA
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Gain Temperature Coefficient2
REFERENCE INPUTS2
Reference Input Range
DC Input Resistance
Input Current
Test Conditions/Comments
Guaranteed Monotonic Over Temperature
Typically within ± 1 LSB
Typically within ± 1 LSB
Max Output Range ± 10 V
Per Input. Typically ± 20 nA.
2
DUTGND INPUT
DC Input Impedance
Max Input Current
Input Range
Max Output Range ± 10 V
2
POWER REQUIREMENTS
VDD/VSS
Power Supply Sensitivity
∆Full Scale/∆VDD
∆Full Scale/∆VSS
IDD
ISS
IDD in Power-Down
To 0 V
To 0 V
NOTES
1
Temperature range for B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
SPECIFICATIONS1 (V
AD5530/AD5531
DD = +12 V ±10%; VSS = –12 V ±10%; GND = 0 V;
RL = 5 kΩ and CL = 220 pF to GND; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
AD5530
AD5531
Unit
12
±1
±1
±2
±2
±1
0.5
10
14
±2
±1
±8
±8
±4
0.5
10
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
ppm FSR/°C typ
ppm FSR/°C max
REFERENCE INPUTS2
Reference Input Range
DC Input Resistance
Input Current
0/4.096
100
±1
0/4.096
100
±1
V min/V max
MΩ typ
µA max
DUTGND INPUT2
DC Input Impedance
Max Input Current
Input Range
60
± 0.3
–3/+3
60
± 0.3
–3/+3
kΩ typ
mA typ
V min/V max
O/P CHARACTERISTICS
Output Voltage Swing
Short Circuit Current
Resistive Load
Capacitive Load
DC Output Impedance
± 8.192
15
5
1200
0.5
± 8.192
15
5
1200
0.5
V max
mA max
kΩ min
pF max
Ω max
DIGITAL I/O
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance2
SDO VOL Output Low Voltage
2.4
0.8
± 10
10
0.4
2.4
0.8
± 10
10
0.4
V min
V max
µA max
pF max
V max
Total for All Pins
3 pF Typ
ISINK = 1 mA
+12/–12
+12/–12
V nom
± 10% For Specified Performance
110
100
2
2
150
110
100
2
2
150
dB typ
dB typ
mA max
mA max
µA max
Outputs Unloaded
Outputs Unloaded
Typically 50 µA
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Gain Temperature Coefficient2
Test Conditions/Comments
Guaranteed Monotonic Over Temperature
Typically within ± 1 LSB
Typically within ± 1 LSB
Max Output Range ± 8.192 V
Per Input. Typically ± 20 nA.
Max Output Range ± 8.192 V
2
POWER REQUIREMENTS
VDD /VSS
Power Supply Sensitivity
∆Full Scale/∆VDD
∆Full Scale/∆VSS
IDD
ISS
IDD in Power-Down
To 0 V
To 0 V
NOTES
1
Temperature range for B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V; RL = 5 kΩ and
L
MIN to TMAX, unless otherwise noted.)
AC PERFORMANCE CHARACTERISTICS C = 220 pF to GND. All specifications T
Parameter
A
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
20
µs typ
Full-Scale Change to ± 1/2 LSB. DAC Latch Contents
alternately loaded with all 0s and all 1s.
Slew Rate
Digital-to-Analog Glitch Impulse
1.3
120
V/µs typ
nV-s typ
Digital Feedthrough
Output Noise Spectral Density
@ 1 kHz
0.5
nV-s typ
DAC Latch alternately loaded with 0FFF Hex and
1000 Hex. Not dependent on load conditions.
Effect of Input Bus Activity on DAC Output Under Test
100
nV/(Hz)1/2typ
All 1s Loaded to DAC
Specifications subject to change without notice. Guaranteed by design, not subject to production test.
REV. 0
–3–
AD5530/AD5531
STANDALONE TIMING CHARACTERISTICS1, 2 (V
DD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V;
RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
7
140
60
60
50
40
50
40
15
5
50
5
50
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Frequency
SCLK Cycle Time
SCLK Low Time
SCLK High Time
SYNC to SCLK Falling Edge Setup Time
SCLK Falling Edge to SYNC Rising Edge
Min SYNC High Time
Data Setup Time
Data Hold Time
SYNC High to LDAC Low
LDAC Pulsewidth
LDAC High to SYNC Low
CLR Pulsewidth
1
Guaranteed by design. Not production tested.
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns
(10% to 90% of V DD) and timed from a voltage level of (V IL +VIH)/2.
Specifications subject to change without notice.
2
t1
t3
SCLK
t2
t4
SYNC
t5
t6
t7
MSB
SDIN
DB15
DB14
t8
DB11
LSB
DB0
t9
LDAC*
t11
t10
t12
CLR
*LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED
Figure 1. Timing Diagram for Standalone Mode
–4–
REV. 0
AD5530/AD5531
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS1, 2, 3 (V
DD = 10.8 V to 16.5 V, VSS = –10.8 V
to –16.5 V; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
t1
t2
t3
t4
t5
t6
t7
t8
t12
t13
t14
t15
t16
t17
2
500
200
200
50
40
50
40
15
50
130
50
50
50
100
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
SCLK Frequency
SCLK Cycle Time
SCLK Low Time
SCLK High Time
SYNC to SCLK Falling Edge Setup Time
SCLK Falling Edge to SYNC Rising Edge
Min SYNC High Time
Data Setup Time
Data Hold Time
CLR Pulsewidth
SCLK Falling Edge to SDO Valid
SCLK Falling Edge to SDO Invalid
RBEN to SCLK Falling Edge Setup Time
RBEN Hold Time
RBEN Falling Edge to SDO Valid
1
Guaranteed by design. Not production tested.
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns
(10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2.
3
SDO; RPULLUP = 5 kΩ, CL = 15 pF.
Specifications subject to change without notice.
2
t1
t3
SCLK
SYNC
t6
t7
MSB
SDIN
t2
t5
t4
DB15
DB14
t8
DB11
LSB
DB0
t13
SDO
(DAISY
CHAINING)
t14
MSB
DB15
LSB
DB11
DB0
t15
t16
RBEN
t13
t17
SDO
(READBACK)
0
MSB
Figure 2. Timing Diagram for Daisy-Chaining and READBACK Mode
REV. 0
–5–
0
t14
RB13
RB0
LSB
AD5530/AD5531
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Impedance θJA
TSSOP (RU-16) . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (< 20 sec) . . . . . . . . . . . . 235°C
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V
Digital Inputs to GND . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
SDO to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.5 V
REFIN to REFAGND . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
REFIN to GND . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD +0.3 V
REFAGND to GND . . . . . . . . . . . . . VSS – 0.3 V, VDD +0.3 V
DUTGND to GND . . . . . . . . . . . . . . VSS – 0.3 V, VDD +0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
*
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
AD5530BRU –40°C to +85 °C
AD5531BRU –40°C to +85 °C
Resolution
INL (LSBs)
DNL(LSBs)
Package Option*
12
14
±1
±2
±1
±1
RU-16
RU-16
*RU = Thin Shrink Small Outline Package.
PIN CONFIGURATION
REFAGND 1
16 VDD
REFIN 2
LDAC 3
SDIN 4
15 VOUT
AD5530/
AD5531
14 DUTGND
13 VSS
TOP VIEW
SYNC 5 (Not to Scale) 12 NC
RBEN 6
11 GND
SCLK 7
10 PD
SDO 8
9
CLR
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5530/AD5531 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–6–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD5530/AD5531
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
REFAGND
For bipolar ± 10 V output range, this pin should be tied to 0 V.
2
REFIN
This is the voltage reference input for the DAC. Connect to external +5 V reference for specified bipolar
± 10 V output.
3
LDAC
Load DAC logic input (active low). When taken low, the contents of the shift register are transferred to
the DAC register. LDAC may be tied permanently low enabling the outputs to be updated on the rising
edge of SYNC.
4
SDIN
Serial data input. This device accepts 16-bit words. Data is clocked into the input register on the falling
edge of SCLK.
5
SYNC
Active low control input. Data is clocked into the shift requester on the falling edges of SCLK.
6
RBEN
Active low readback enable function. This function allows the contents of the DAC register to be read.
Data from the DAC register will be shifted out on SDO pin on each rising edge of SCLK.
7
SCLK
Clock input. Data is clocked into the input register on the falling edge of SCLK.
8
SDO
Serial data out. This pin is used to clock out the serial data previously written to the input shift register or
may be used in conjunction with RBEN to read back the data from the DAC register. This is an open
drain output; it should be pulled high with an external pull-up resistor. In standalone mode, SDO should
be tied to GND or left high impedance.
9
CLR
Level sensitive, active low input. A falling edge of CLR resets VOUT to DUTGND. The contents of the
registers are untouched.
10
PD
This allows the DAC to be put into a power-down state.
11
GND
Ground reference
12
NC
Do not connect anything to this pin.
13
VSS
Negative analog supply voltage, –12 V ± 10% or –15 V ± 10% for specified performance.
14
DUTGND
VOUT is referenced to the voltage applied to this pin.
15
VOUT
DAC output
16
VDD
Positive analog supply voltage, +12 V ± 10% or +15 V ± 10% for specified performance.
TERMINOLOGY
Gain Error
Relative Accuracy
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is the
deviation in slope of the DAC transfer characteristic from ideal.
Relative accuracy or endpoint linearity is a measure of the maximum
deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maximum
ensures monotonicity.
Digital-to-Analog Glitch Impulse
Zero-scale error is a measure of the output error when all 0s are
loaded to the DAC latch.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the
major carry transition.
Full-Scale Error
Digital Feedthrough
Zero-Scale Error
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. It is specified
in nV-s and is measured with a full-scale code change on the data
bus, i.e., from all 0s to all 1s and vice versa.
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 VREF – 1 LSB.
REV. 0
–7–
AD5530/AD5531–Typical Performance Characteristics
1
1
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
TA = +25ⴗC
0.8
0.6
0.4
0.5
0.25
LSB
0.2
LSB
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
TA = +25ⴗC
0.75
0
–0.2
0
–0.25
–0.4
–0.5
–0.6
–0.75
–0.8
–1
0
500
1000
1500
2000
2500
3000
3500
–1
4000
2000
0
4000
6000
code
10000 12000 14000 16000
code
TPC 1. AD5530 Typical INL Plot
TPC 4. AD5531 Typical DNL Plot
0.5
2.0
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
TA = +25ⴗC
0.4
0.3
1.5
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
1.0
ERROR – LSBs
0.2
0.1
LSB
8000
0
–0.1
0.5
0
–0.5
–0.2
–1.0
–0.3
–1.5
–0.4
–0.5
0
500
1000
1500
2000
2500
3000
3500
–2.0
–40
4000
–20
0
TPC 2. AD5530 Typical DNL Plot
1.0
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
TA = +25ⴗC
1
40
60
80
TPC 5. AD5531 Typical INL Error vs. Temperature
2
1.5
20
TEMPERATURE – ⴗC
code
0.8
0.6
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
ERROR – LSBs
0.4
LSB
0.5
0
–1
0.2
0
–0.2
–0.4
–0.3
–0.6
–1.5
–2
–0.8
0
2000
4000
6000
8000
–1.0
–40
10000 12000 14000 16000
–20
0
20
40
60
80
TEMPERATURE – ⴗC
code
TPC 3. AD5531 Typical INL Plot
TPC 6. AD5531 Typical DNL Error vs. Temperature
–8–
REV. 0
AD5530/AD5531
3
0.03
VDD = +15V
VSS = –15V
REFAGND = 0V
TA = +25ⴗC
2
–40ⴗC
0.02
1
IDD – mA
ERROR – LSBs
POSITIVE INL
0
NEGATIVE INL
–1
+85ⴗC
+25ⴗC
0.01
–2
–3
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
6.0
10
REFIN VOLTAGE – V
12
13
14
15
16
17
SUPPLY VOLTAGE – V
TPC 7. AD5531 Typical INL Error vs. Reference Voltage
TPC 10. IDD in Power-Down vs. Supply
0
12
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
–0.5
8
4
–1.0
VOUT – V
ERROR – LSBs
11
–1.5
0
–4
5 ␮s/div
–2.0
–8
–2.5
–40
–20
0
20
40
60
–12
80
TEMPERATURE – ⴗC
TPC 8. Typical Full-Scale and Offset Error
vs. Temperature
0
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
TA = +25ⴗC
TIME – ␮s
TPC 11. Settling Time
1.50
0
1.45
–0.02
–0.04
1.40
–0.06
+25ⴗC
1.35
VOUT – V
CURRENT – mA
+85ⴗC
–40ⴗC
1.30
–0.08
–0.10
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
TA = +25ⴗC
–0.12
1.25
–0.14
1.20
10
11
12
13
14
15
16
17
–0.16
VDD/V SS – V
TIME – 750ns/DIV
TPC 9. IDD vs. VDD / VSS
REV. 0
TPC 12. Typical Digital-to-Analog Glitch Impulse
–9–
AD5530/AD5531
VDD = +15V
VSS = –15V
REFIN = +5V
REFAGND = 0V
TA = +25ⴗC
VOUT
REFIN
12-/14-BIT DAC
OUTPUT
14
LDAC
DAC REGISTER
14
PD
SYNC
2V/DIV
SYNC REGISTER
14
2V/DIV
SDIN
TPC 13. Typical Power-Down Time
16-BIT SHIFT
REGISTER
SDO
Figure 4. Simplified Serial Interface
Data written to the part via SDIN is available on the SDO pin
16 clocks later if the readback function is not used. SDO data is
clocked out on the falling edge of the serial clock with some delay.
GENERAL DESCRIPTION
DAC Architecture
PD Function
The PD pin allows the user to place the device into power-down
mode. While in this mode, power consumption is at a minimum;
the device draws only 50µA of current. The PD function does
not affect the contents of the DAC register.
The AD5530/AD5531 are pin-compatible 12-/14-bit DACs.
The AD5530 consists of a straight 12-bit R-2R voltage mode DAC,
while the AD5531 consists of a 14-bit R-2R section. Using a +5 V
reference connected to the REFIN pin and REFAGND tied to
0 V, a bipolar ± 10 V voltage output results. The DAC coding is
straight binary.
READBACK Function
The AD5530/AD5531 allows the data contained in the DAC
register to be read back if required. The pins involved are the
RBEN and SDO (serial data out). When RBEN is taken low, on
the next falling edge of SCLK, the contents of the DAC register
are transferred to the shift register. RBEN may be used to frame
the readback data by leaving it low for 16 clock cycles, or it may
be asserted high after the required hold time. The shift register
contains the DAC register data and this is shifted out on the
SDO line on each falling edge of SCLK with some delay. This
ensures the data on the serial data output pin is valid for the
falling edge of the receiving part. The two MSBs of the 16-bit
word will be ‘0’s.
Serial Interface
Serial data on the SDIN input is loaded to the input register under
the control of SCLK, SYNC, and LDAC. A write operation
transfers a 16-bit word to the AD5530/AD5531. Figures 1 and 2
show the timing diagrams. Figure 3 shows the contents of the
input shift register. Twelve or 14 bits of the serial word are data
bits; the rest are don’t cares.
DB15 (MSB)
DB0 (LSB)
X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
DATA BITS
CLR Function
Figure 3a. AD5530 Input Shift Register Contents
DB15 (MSB)
DB0 (LSB)
X X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
Figure 3b. AD5531 Input Shift Register Contents
The serial word is framed by the signal, SYNC. After a high to low
transition on SYNC, data is latched into the input shift register
on the falling edges of SCLK. There are two ways in which the
DAC register and output may be updated. The LDAC signal is
examined on the falling edge of SYNC; depending on its status,
either a synchronous or asynchronous update is selected. If
LDAC is low, then the DAC register and output are updated on
the low to high transition of SYNC. Alternatively, if LDAC is
high upon sampling, the DAC register is not loaded with the
new data on a rising edge of SYNC. The contents of the DAC
register and the output voltage will be updated by bringing
LDAC low any time after the 16-bit data transfer is complete.
LDAC may be tied permanently low if required. A simplified
diagram of the input loading circuitry is illustrated in Figure 4.
The falling edge of CLR causes VOUT to be reset to the same
potential as DUTGND. The contents of the registers remain
unchanged, so the user can reload the previous data with LDAC
after CLR is asserted high. Alternatively, if LDAC is tied low,
the output will be loaded with the contents of the DAC register
automatically after CLR is brought high.
Output Voltage
The DAC transfer function is as follows:

D

2
VOUT = 2 [2 ×  REFIN – REFAGND ×
N



+ 2 × REFAGND − REFIN ] – DUTGND
where:
D is the decimal data word loaded to the DAC register,
N is the resolution of the DAC.
Bipolar Configuration
Figure 5 shows the AD5530/AD5531 in a bipolar circuit configuration. REFIN is driven by the AD586, 5 V reference, while the
REFAGND and DUTGND pins are tied to GND. This results
in a bipolar output voltage ranging from –10 V to +10 V. Resistor
R1 is provided (if required) for gain adjust. Figure 6 shows the
transfer function of the DAC when REFAGND is tied to 0 V.
–10–
REV. 0
AD5530/AD5531
+15V
VOUT
6
REFIN
8
AD586
C1
1␮F
5
R1
10k⍀
VOUT
(–10V TO +10V)
VOUT
AD5530/
AD5531*
4
SIGNAL
GND
FO
LDAC
TFS
SYNC
DT
SDIN
SCLK
DUTGND
REFAGND
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
SIGNAL
GND
Figure 7. AD5530/AD5531 to ADSP-21xx Interface
AD5530/AD5531 to 8051 Interface
–15V
A serial interface between the AD5530/AD5531 and the 8051 is
shown in Figure 8. TXD of the 8051 drives SCLK of the AD5530/
AD5531, while RXD drives the serial data line, SDIN. P3.3 and
P3.4 are bit-programmable pins on the serial port and are used
to drive SYNC and LDAC respectively.
Figure 5. Bipolar ± 10 V Operation
2 REFIN
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user will have to ensure that the data in the
SBUF register is arranged correctly as the DAC expects MSB first.
0V
80C51/80L51*
–2 REFIN
DAC INPUT CODE 000 001
(3)FFF
AD5530/
AD5531*
P3.4
LDAC
P3.3
SYNC
RXD
SDIN
TXD
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. Output Voltage vs. DAC Input Codes (Hex)
Figure 8. AD5530/AD5531 to 8051 Interface
MICROPROCESSOR INTERFACING
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RXD is clocked out of the microcontroller on the rising
edge of TXD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.
Microprocessor interfacing to the AD5530/AD5531 is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5530/AD5531 requires a
16-bit data word with data valid on the falling edge of SCLK.
The 8051 transmits data in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. As the DAC expects a
16-bit word, P3.3 must be left low after the first 8 bits are transferred.
After the second byte has been transferred, the P3.3 line is taken
high. The DAC may be updated using LDAC via P3.4 of the 8051.
For all the interfaces, the DAC output update may be done
automatically when all the data is clocked in or asynchronously
under the control of LDAC.
The contents of the DAC register may be read using the readback
function. RBEN is used to frame the readback data, which is
clocked out on SDO. The following figures illustrate these DACs
interfacing with a simple 4-wire interface. The serial interface of
the AD5530/AD5531 may be operated from a minimum of
three wires.
AD5530/AD5531 to MC68HC11 Interface
Figure 9 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the DAC, while the MOSI
output drives the serial data lines, SDIN. SYNC is driven from
one of the port lines, in this case PC7.
AD5530/AD5531 to ADSP-21xx
An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in Figure 7. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control register should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the LDAC pin via the DSP. Alternatively,
the LDAC input could be tied permanently low and then the
update takes place automatically when TFS is taken high.
REV. 0
SCLK
VSS
*ADDITIONAL PINS OMITTED FOR CLARITY
DAC OUTPUT VOLTAGE
AD5530/
AD5531*
ADSP-2101/
ADSP-2103*
2
–11–
MC68HC11*
AD5530/
AD5531*
PC6
LDAC
PC7
SYNC
MOSI
SDIN
SCK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5530/AD5531 to MC68HC11 Interface
AD5530/AD5531
The 68HC11 is configured for master mode, MSTR= 1,
CPOL = 0, and CPHA = 1. When data is transferred to the part,
PC7 is taken low and data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight
falling clock edges occur in the transmit cycle, so in order to load
the required 16-bit word, PC7 is not brought high until the second
8-bit word has been transferred to the DAC’s input shift register.
Serial Interface to Multiple AD5530s or AD5531s
Figure 11 shows how the SYNC pin is used to address multiple
AD5530/AD5531s. All devices receive the same serial clock and
serial data, but only one device will receive the SYNC signal at any
one time. The DAC addressed will be determined by the decoder.
There will be some feedthrough from the digital input lines, the
effects of which can be minimized by using a burst clock.
LDAC is controlled by the PC6 port output. The DAC can be
updated after each 2-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. If CLR
were used, it could be controlled by port output PC5. In order to
read data back from the DAC register, the SDO line could be
connected to MISO of the MC68HC11, with RBEN tied to another
port output controlling and framing the readback data transfer.
AD5530/AD5531*
SCLK
SYNC
SDIN
SDIN
VOUT
SCLK
VCC
AD5530/AD5531*
APPLICATIONS
Optocoupler Interface
ENABLE
EN
SYNC
DECODER*
CODED
ADDRESS
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in excess
of 3 kV. The serial loading structure of the AD5530/AD5531
makes it ideal for opto-isolated interfaces as the number of
interface lines is kept to a minimum. Figure 10 shows a 4- channel
isolated interface to the AD5530/AD5531. To reduce the
number of opto-isolators, if simultaneous updating is not required, then the LDAC pin may be tied permanently low.
SDIN
DGND
VOUT
SCLK
*ADDITIONAL PINS
OMITTED FOR CLARITY
AD5530/AD5531*
SYNC
SDIN
VOUT
SCLK
VCC
AD5530/AD5531*
SYNC
␮CONTROLLER
SDIN
CONTROL OUT
TO LDAC
SYNC OUT
TO SYNC
VOUT
SCLK
Figure 11. Addressing Multiple AD5530/AD5531s
SERIAL CLOCK OUT
Daisy-Chaining Interface with Multiple AD5530s or AD5531s
A number of these DAC parts may be daisy-chained together
using the SDO pin. Figure 12 illustrates such a configuration.
TO SCLK
TO SDIN
SERIAL DATA OUT
OPTOCOUPLER
Figure 10. Opto-Isolated Interface
VDD
AD5530/AD5531*
SCLK
SCLK
SDIN
SDIN
SYNC
SYNC
R
AD5530/AD5531*
SCLK
SDO
R
AD5530/AD5531*
R
SCLK
SDIN
SDO
SYNC
SDIN
SYNC
SDO
TO OTHER
SERIAL DEVICES
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. Daisy-Chaining Multiple AD5530/AD5531s
–12–
REV. 0
AD5530/AD5531
OUTLINE DIMENSIONS
Dimensions shown in millimeters
16-Lead Thin Shrink SO Package (TSSOP)
(RU-16)
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
COPLANARITY
0.15
0.05
1.20
MAX
0.65
BSC
0.30
0.19
SEATING
PLANE
0.20
0.09
8ⴗ
0ⴗ
COMPLIANT TO JEDEC STANDARDS MO-153AB
REV. 0
–13–
0.75
0.60
0.45
–14–
–15–
–16–
PRINTED IN U.S.A.
C00938–0–5/02(0)