Freescale MCF5213 Microcontroller family hardware specification Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
MCF5213EC
Rev. 1.2, 01/2006
MCF5213 Microcontroller Family
Hardware Specification
The MCF5213 is a member of the ColdFire® family of
reduced
instruction
set
computing
(RISC)
microprocessors. This document provides an overview
of the 32-bit MCF5213 microcontroller, focusing on its
highly integrated and diverse feature set. Freescale
reserves the right to change or discontinue this product
without notice. Specifications and information herein are
subject to change without notice.
This 32-bit device is based on the Version 2 ColdFire
core operating at a frequency up to 80 MHz, offering
high performance and low power consumption. On-chip
memories connected tightly to the processor core include
256 Kbytes of Flash and 32 Kbytes of static random
access memory (SRAM). On-chip modules include the
following:
• V2 ColdFire core delivering 76 MIPS
(Dhrystone 2.1) at 80 MHz running from
internal Flash with Multiply Accumulate (MAC)
Unit and hardware divider
• FlexCAN controller area network (CAN)
module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
Table of Contents
1
MCF5213 Family Configurations .........................2
1.1 Block Diagram ...................................................3
1.2 Features.............................................................4
1.3 Part Numbers and Packaging..........................14
1.4 Package Pinouts..............................................15
1.5 Reset Signals ..................................................22
1.6 PLL and Clock Signals ....................................22
1.7 Mode Selection................................................22
1.8 External Interrupt Signals ................................23
1.9 Queued Serial Peripheral Interface (QSPI) .....23
1.10 I2C I/O Signals.................................................24
1.11 UART Module Signals .....................................24
1.12 DMA Timer Signals..........................................24
1.15 Pulse Width Modulator Signals........................25
1.16 Debug Support Signals....................................25
1.17 EzPort Signal Descriptions ..............................27
1.18 Power and Ground Pins...................................27
2
Preliminary Electrical Characteristics ................27
3
Mechanical Outline Drawings ............................44
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
• Preliminary
MCF5213 Family Configurations
•
•
•
•
•
•
•
•
•
•
Inter-integrated circuit (I2C™) bus controller
Queued serial peripheral interface (QSPI) module
Eight-channel 12-bit fast analog-to-digital converter (ADC)
Four-channel direct memory access (DMA) controller
Four 32-bit input capture/output compare timers with DMA support (DTIM)
Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width
modulation (PWM), and pulse accumulation
Eight-channel/Four-channel, 8-bit/16-bit pulse width modulation timer
Two 16-bit periodic interrupt timers (PITs)
Programmable software watchdog timer
Interrupt controller capable of handling 57 sources
•
•
Clock module with 8 MHz on-chip relaxation oscillator and integrated phase locked loop (PLL)
Test access/debug port (JTAG, BDM)
1
MCF5213 Family Configurations
Table 1. MCF5213 Family Configurations
Module
5211
5212
5213
ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit)
x
x
x
System Clock
66 MHz
66, 80 MHz
63
up to 76
Flash / Static RAM (SRAM)
128/16 Kbytes
256/32 Kbytes
Interrupt Controller (INTC)
x
x
x
Fast Analog-to-Digital Converter (ADC)
x
x
x
FlexCAN 2.0B Module
—
—
x
Four-channel Direct-Memory Access (DMA)
x
x
x
Software Watchdog Timer (WDT)
x
x
x
Programmable Interrupt Timer
2
2
2
Four-Channel General Purpose Timer
x
x
x
32-bit DMA Timers
4
4
4
QSPI
x
x
x
UART(s)
3
3
3
I
x
x
x
Eight/Four-channel 8/16-bit PWM Timer
x
x
x
General Purpose I/O Module (GPIO)
x
x
x
Performance (Dhrystone 2.1 MIPS)
2C
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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MCF5213 Family Configurations
Table 1. MCF5213 Family Configurations (continued)
Module
5211
5212
5213
Chip Configuration and Reset Controller Module
x
x
x
Background Debug Mode (BDM)
x
x
x
x
x
x
64 LQFP
64 QFN
81 MAPBGA
64 LQFP
81 MAPBGA
81 MAPBGA
100 LQFP
1
JTAG - IEEE 1149.1 Test Access Port
Package
NOTES:
1 The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on
smaller packages.
1.1
Block Diagram
Figure 1 shows a top-level block diagram of the MCF5213. Package options for this family are described
later in this document.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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3
MCF5213 Family Configurations
EzPQ
EzPCK
EzPort
EzPCS
Interrupt
Controller
Arbiter
UART
0
4 CH DMA
To/From PADI
GPTn
QSPI_DIN,
QSPI_DOUT
QSPI_SCK,
QSPI_PCSn
UART
1
DTIM
0
SWT
UART
2
DTIM
1
I2C
DTIM
2
QSPI
PADI – Pin Muxing
EzPD
UnTXD
UnRXD
UnRTS
UnCTS
DTINn/DTOUTn
CANRX
DTIM
3
CANTX
PWMn
MUX
JTAG_EN
V2 ColdFire CPU
IFP
JTAG
TAP
AN[7:0]
32 Kbytes
SRAM
(4Kx16)x4
ADC
VRH
FlexCAN
OEP
VRL
MAC
256 Kbytes
Flash
(32Kx16)x4
PMM
PORTS
(GPIO)
CIM
RSTI
RSTO
VSTBY
Edge
Port
PLL OCO
CLKGEN
EXTAL
XTAL
PIT0
PIT1
GPT
PWM
CLKOUT
CLKMOD0 CLKMOD1
To/From Interrupt Controller
Figure 1. MCF5213 Block Diagram
1.2
Features
The MCF5213 family includes the following features:
• Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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•
•
•
•
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and
four new instructions for improved bit processing (ISA_A+)
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16 × 16 → 32 or
32 × 32 → 32 operations
— Illegal instruction decode that allows for 68K emulation support
System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can
be configured into a 1- or 2-level trigger
On-chip memories
— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with
standby power supply support
— 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard Data and Remote Frames (up to 109 bits long)
– Extended Data and Remote Frames (up to 127 bits long)
– 0–8 bytes data length
– Programmable bit rate up to 1 Mbit/sec
— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length
each, configurable as Rx or Tx, all supporting standard and extended messages
— Unused MB space can be used as general purpose RAM space
— Listen only mode capability
— Content-related addressing
— No read/write semaphores
— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for
MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— “Time stamp” based on 16-bit free-running timer
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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Preliminary
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MCF5213 Family Configurations
•
•
•
•
•
— Global network time, synchronized by a specific message
— Maskable interrupts
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
I2C module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125 µs conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over
low/high limit
— Unused analog channels can be used as digital I/O
Four 32-bit DMA timers
— 12.5-ns resolution at 80 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
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MCF5213 Family Configurations
•
•
•
•
•
— Input capture capability with programmable trigger edge on input pin
— Output compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or output compare
— DMA trigger capability on input capture or output compare
Four-channel general purpose timer
— 16-bit architecture
— Programmable prescaler
— Output pulse widths variable from microseconds to seconds
— Single 16-bit input pulse accumulator
— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
— One dual-mode pulse accumulation channel
Pulse-width modulation timer
— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
— Programmable period and duty cycle
— Programmable enable/disable for each channel
— Software selectable polarity for each channel
— Period and duty cycle are double buffered. Change takes effect when the end of the current
period is reached (PWM counter reaches zero) or when the channel is disabled.
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown
Two periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down
Software watchdog timer
— 32-bit counter
— Low power mode support
Clock generation features
— 1 to 16 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference
options
— Trimmed relaxation oscillator
— 2 to 10 MHz reference frequency for normal PLL mode
— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator
— Low power modes supported
— 2n (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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Preliminary
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MCF5213 Family Configurations
•
•
•
•
Interrupt controller
— Uniquely programmable vectors for all interrupt sources
— Fully programmable level and priority for all peripheral interrupt sources
— Seven external interrupt signals with fixed level and priority
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for
16-byte (4 x 32-bit) burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)
Reset
— Separate reset in and reset out signals
— Seven sources of reset:
– Power-on reset (POR)
– External
– Software
– Watchdog
– Loss of clock
– Loss of lock
– Low-voltage detection (LVD)
— Status flag indication of source of last reset
Chip integration module (CIM)
— System configuration during reset
— Selects one of six clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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MCF5213 Family Configurations
•
•
1.2.1
General purpose I/O interface
— Up to 56 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address
generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds
prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes
two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
MCF5213 core includes the multiply-accumulate (MAC) unit for improved signal processing capabilities.
The MAC implements a three-stage arithmetic pipeline, optimized for 16 x 16 bit operations, with support
for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers,
signed fractional operands, and a complete set of instructions to process these data types. The MAC
provides support for execution of DSP operations within the context of a single processor at a minimal
hardware cost.
1.2.2
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
debug information and real-time tracing capability is provided on 100-lead packages. This allows the
processor and system to be debugged at full speed without the need for costly in-circuit emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an
address mask register, a data and a data mask register, four PC registers, and one PC mask register. These
registers can be accessed through the dedicated debug serial communication channel or from the
processor’s supervisor mode programming model. The breakpoint registers can be configured to generate
triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions.
The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
The MCF5213 implements revision B+ of the coldfire Debug Architecture.
The MCF5213’s interrupt servicing options during emulator mode allow real-time critical interrupt service
routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data
(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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Preliminary
9
MCF5213 Family Configurations
data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF5213
includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor status (PST[3:0])
signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 100-pin packages. However, every product features
the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.3
JTAG
The MCF5213 supports circuit board test strategies based on the Test Technology Committee of IEEE and
the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state
controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan
register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.
Test logic, implemented using static logic design, is independent of the device system logic.
The MCF5213 implementation can do the following:
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample MCF5213 system pins during operation and transparently shift out the result in the
boundary scan register
• Bypass the MCF5213 for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
1.2.4
1.2.4.1
On-Chip Memories
SRAM
The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access
in a single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the
4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the
system stack. Because the SRAM module is physically connected to the processor's high-speed local bus,
it can quickly service core-initiated accesses or memory-referencing commands from the debug module.
The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal
for implementing applications with double-buffer schemes, where the processor and a DMA device
operate in alternate regions of the SRAM to maximize system performance.
1.2.4.2
Flash
The ColdFire Flash module (CFM) is a non-volatile memory (NVM) module that connects to the
processor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays to
generate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable and
programmable, non-volatile program and data memory. The Flash memory is ideal for program and data
storage for single-chip applications, allowing for field reprogramming without requiring an external high
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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MCF5213 Family Configurations
voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory
controller which supports interleaved accesses from the 2-cycle Flash arrays. A backdoor mapping of the
Flash memory is used for all program, erase, and verify operations, as well as providing a read datapath
for the DMA. Flash memory may also be programmed via the EzPort, which is a serial Flash programming
interface that allows the Flash to be read, erased and programmed by an external controller in a format
compatible with most SPI bus Flash memory chips.
1.2.5
Power Management
The MCF5213 incorporates several low power modes of operation which are entered under program
control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors
the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)
monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the
LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip
falls below the standby battery voltage.
1.2.6
FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts
A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific
requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of
FlexCAN has 16 message buffers.
1.2.7
UARTs
The MCF5213 has three full-duplex UARTs that function independently. The three UARTs can be clocked
by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third
UART is multiplexed with other digital I/O functions.
1.2.8
I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange
and minimizes the interconnection between devices. This bus is suitable for applications requiring
occasional communications over a short distance between many devices.
1.2.9
QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with
queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU
intervention between transfers.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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MCF5213 Family Configurations
1.2.10 Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold
(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible
buffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or
perform a programmed scan sequence repeatedly until manually stopped.
The ADC can be configured for either sequential or simultaneous conversion. When configured for
sequential conversions, up to eight channels can be sampled and stored in any order specified by the
channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same
time. This configuration requires that a single channel may not be sampled by both S/H circuits
simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures
below the low threshold limit or above the high threshold limit set in the limit registers) or at several
different zero crossing conditions.
1.2.11 DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)
on the MCF5213. Each module incorporates a 32-bit timer with a separate register set for configuration
and control. The timers can be configured to operate from the system clock or from an external clock
source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The
input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter
register (TCRn). Each of these timers can be configured for input capture or reference (output) compare
mode. Timer events may optionally cause interrupt requests or DMA transfers.
1.2.12 General Purpose Timer (GPT)
The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter
driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input capture
or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit
range of the counter. The input capture and output compare functions allow simultaneous input waveform
measurements and output waveform generation. The input capture function can capture the time of a
selected transition edge. The output compare function can generate output waveforms and timer software
delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.
1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular
intervals with minimal processor intervention. Each timer can either count down from the value written in
its PIT modulus register, or it can be a free-running down-counter.
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1.2.14 Pulse Width Modulation Timers
The MCF5213 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty
cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms
with software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, and
can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle
resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a
single 16-bit channel. The module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit
channels.
1.2.15 Software Watchdog Timer
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter
is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown.
1.2.16 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked
loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control
logic. In order to improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their
own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply
pins, VDD and VSS.
1.2.17 Interrupt Controller (INTC)
The MCF5213 has a single interrupt controller that supports up to 63 interrupt sources. There are 56
programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining 7
sources are unassigned and may be used for software interrupt requests.
1.2.18 DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with
minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line
transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the
occurrence of certain UART or DMA timer events.
1.2.19 Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and
keeps track of what caused the last reset. There are seven sources of reset:
• External reset input
• Power-on reset (POR)
• Watchdog timer
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
13
MCF5213 Family Configurations
•
•
•
•
Phase locked-loop (PLL) loss of lock
PLL loss of clock
Software
Low-voltage detector (LVD)
Control of the LVD and its associated reset and interrupt are handled by the reset controller. Other registers
provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO
pin.
1.2.20 GPIO
Nearly all pins on the MCF5213 have general purpose I/O capability and are grouped into 8-bit ports.
Some ports do not use all 8 bits. Each port has registers that configure, monitor, and control the port pins.
1.3
Part Numbers and Packaging
This product is RoHS-compliant. Refer to the product page at freescale.com or contact your sales office
for up-to-date RoHS information.
Table 2. Part Number Summary
Part Number
Flash / SRAM
Key Features
Package
Speed
MCF5211
128 Kbytes / 16 Kbytes
3 UARTs, I2C, QSPI, A/D
16-/32-bit/PWM Timers
64 LQFP
81 MAPBGA
64 QFN
66 MHz
66, 80 MHz
66 MHz
MCF5212
256 Kbytes / 32 Kbytes
3 UARTs, I2C, QSPI, A/D
16-/32-bit/PWM Timers
64 LQFP
81 MAPBGA
66 MHz
66, 80 MHz
MCF5213
256 Kbytes / 32 Kbytes
3 UARTs, I2C, QSPI, A/D
16-/32-bit/PWM Timers, CAN
81 MAPBGA
100 LQFP
66, 80 MHz
66, 80 MHz
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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1.4
Package Pinouts
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
VDDPLL
EXTAL
XTAL
VSSPLL
PST3
PST2
VDD
VSS
PST1
PST0
PSTCLK
PWM7
GPT3
GPT2
PWM5
GPT1
GPT0
VDD
VSS
VSTBY
AN4
AN5
AN6
AN7
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
JTAG_EN
UCTS2
URXD2
UTXD2
URTS2
DTIN2
DTIN3
PWM3
VDD
VSS
DTIN0
DTIN1
PWM1
CLKMOD1
CLKMOD0
VDD
VSS
AN0
AN1
AN2
AN3
VSSA
VRL
VRH
VDDA
VDD
VDD
VSS
URTS1
TEST
UCTS0
URXD0
UTXD0
URTS0
SCL
SDA
QSPI_CS3
QSPI_CS2
VDD
VSS
QSPI-DIN
QSPI_DOUT
QSPI_CLK
QSPI_CS1
QSPI_CS0
RCON
VDD
VDD
VSS
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
URXD1
UTXD1
UCTS1
RSTO
RSTI
IRQ7
IRQ6
VDD
VSS
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
ALLPST
DSCLK
DDATA3
DDATA2
VSS
VDD
DSO
DSI
DDATA1
DDATA0
BKPT
Figure 2 shows the pinout configuration for the 100 LQFP.
Figure 2. 100 LQFP Pin Assignments
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
15
MCF5213 Family Configurations
Figure 3 shows the pinout configuration for the 81 MAPBGA.
1
2
3
4
5
6
7
8
9
A
VSS
UTXD1
RSTI
IRQ5
IRQ3
ALLPST
TDO
TMS
VSS
B
URTS1
URXD1
RSTO
IRQ6
IRQ2
TRST
TDI
VDDPLL
EXTAL
C
UCTS0
TEST
UCTS1
IRQ7
IRQ4
IRQ1
TCLK
VSSPLL
XTAL
D
URXD0
UTXD0
URTS0
VSS
VDD
VSS
PWM7
GPT3
GPT2
E
SCL
SDA
VDD
VDD
VDD
VDD
VDD
PWM5
GPT1
F
QSPI_CS3
QSPI_CS2
QSPI_DIN
VSS
VDD
VSS
GPT0
VSTBY
AN4
G
QSPI_DOUT
QSPI_CLK
RCON
DTIN1
CLKMOD0
AN2
AN3
AN5
AN6
H
QSPI_CS0
QSPI_CS1
DTIN3
DTIN0
CLKMOD1
AN1
VSSA
VDDA
AN7
J
VSS
JTAG_EN
DTIN2
PWM3
PWM1
AN0
VRL
VRH
VSSA
Figure 3. 81 MAPBGA Pin Assignments
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
16
Preliminary
Freescale Semiconductor
MCF5213 Family Configurations
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VSS
URXD1
UTXD1
UCTS1
RSTO
RSTI
IRQ7
IRQ4
IRQ1
ALLPST
DSCLK
VSS
VDD
DSO
DSI
BKPT
Figure 4 shows the pinout configuration for the 64 LQFP and 64 QFN.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-Pin Packages
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDPLL
EXTAL
XTAL
VSSPLL
PSTCLK
GPT3
GPT2
GPT1
GPT0
VDD
VSS
VSTBY
AN4
AN5
AN6
AN7
JTAG_EN
DTIN2
DTIN3
VDD
VSS
DTIN0
DTIN1
CLKMOD0
AN0
AN1
AN2
AN3
VSSA
VRL
VRH
VDDA
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
URTS1
TEST
UCTS0
URXD0
UTXD0
URTS0
SCL
SDA
VDD
VSS
QSPI_DIN
QSPI_DOUT
QSPI_CLK
QSPI_CS0
RCON
Figure 4. 64 LQFP and 64 QFN Pin Assignments
Table 3 shows the pin functions by primary and alternate purpose, and illustrates which packages contain
each pin.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
17
Drive
Secondary Tertiary Quaternary
Slew Rate /
Pull-up /
Strength /
Function Function Function
Control1 Pull-down2
1
Control
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Preliminary
Freescale Semiconductor
Pin
Group
Primary
Function
ADC
AN7
—
—
GPIO
Low
FAST
—
51
H9
33
AN6
—
—
GPIO
Low
FAST
—
52
G9
34
AN5
—
—
GPIO
Low
FAST
—
53
G8
35
AN4
—
—
GPIO
Low
FAST
—
54
F9
36
AN3
—
—
GPIO
Low
FAST
—
46
G7
28
AN2
—
—
GPIO
Low
FAST
—
45
G6
27
AN1
—
—
GPIO
Low
FAST
—
44
H6
26
AN0
—
—
GPIO
Low
FAST
—
43
J6
25
SYNCA
—
—
—
N/A
N/A
—
—
—
—
No Primary
SYNCB
—
—
—
N/A
N/A
—
—
—
—
No Primary
VDDA
—
—
—
N/A
N/A
—
50
H8
32
VSSA
—
—
—
N/A
N/A
—
47
H7
29
VRH
—
—
—
N/A
N/A
—
49
J8
31
VRL
—
—
—
N/A
N/A
—
48
J7
30
EXTAL
—
—
—
N/A
N/A
—
73
B9
47
XTAL
—
—
—
N/A
N/A
—
72
C9
46
VDDPLL
—
—
—
N/A
N/A
—
74
B8
48
VSSPLL
—
—
—
N/A
N/A
—
71
C8
45
ALLPST
—
—
—
High
FAST
—
86
A6
55
DDATA[3:0]
—
—
GPIO
High
FAST
—
84,83,78,77
—
—
PST[3:0]
—
—
GPIO
High
FAST
—
70,69,66,65
—
—
SCL
CANTX3
UTXD2
GPIO
PDSR[0]
PSRR[0]
pull-up4
10
E1
8
SDA
3
PSRR[0]
4
11
E2
9
Clock
Generation
Debug
Data
I2C
CANRX
URXD2
GPIO
PDSR[0]
pull-up
Pin on
100 LQFP
Pin on 81 Pin on 64
MAPBGA LQFP/QFN
Notes
MCF5213 Family Configurations
18
Table 3. Pin Functions by Primary and Alternate Purpose
Freescale Semiconductor
Table 3. Pin Functions by Primary and Alternate Purpose
Drive
Secondary Tertiary Quaternary
Slew Rate /
Pull-up /
Strength /
Function Function Function
Control1 Pull-down2
1
Control
Primary
Function
Interrupts
IRQ7
—
—
GPIO
Low
FAST
—
95
C4
58
IRQ6
—
—
GPIO
Low
FAST
—
94
B4
—
IRQ5
—
—
GPIO
Low
FAST
—
91
A4
—
IRQ4
—
—
GPIO
Low
FAST
—
90
C5
57
IRQ3
—
—
GPIO
Low
FAST
—
89
A5
—
IRQ2
—
—
GPIO
Low
FAST
—
88
B5
—
IRQ1
SYNCA
PWM1
GPIO
High
FAST
pull-up4
87
C6
56
JTAG_EN
—
—
—
N/A
N/A
pull-down
26
J2
17
TCLK/
PSTCLK
CLKOUT
—
—
High
FAST
pull-up5
64
C7
44
TDI/DSI
—
—
—
N/A
N/A
pull-up5
79
B7
50
TDO/DSO
—
—
—
High
FAST
—
80
A7
51
76
A8
49
JTAG/BDM
Mode
Selection6
PWM
Pin on
100 LQFP
Pin on 81 Pin on 64
MAPBGA LQFP/QFN
TMS
/BKPT
—
—
—
N/A
N/A
pull-up5
TRST
/DSCLK
—
—
—
N/A
N/A
pull-up5
85
B6
54
CLKMOD0
—
—
—
N/A
N/A
pull-down6
40
G5
24
CLKMOD1
—
—
—
N/A
N/A
pull-down6
39
H5
—
RCON/
EZPCS
—
—
—
N/A
N/A
pull-up
21
G3
16
PWM7
—
—
GPIO
PDSR[31]
PSRR[31]
—
63
D7
—
PWM5
—
—
GPIO
PDSR[30]
PSRR[30]
—
60
E8
—
PWM3
—
—
GPIO
PDSR[29]
PSRR[29]
—
33
J4
—
PWM1
—
—
GPIO
PDSR[28]
PSRR[28]
—
38
J5
—
Notes
19
MCF5213 Family Configurations
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Preliminary
Pin
Group
Drive
Secondary Tertiary Quaternary
Slew Rate /
Pull-up /
Strength /
Function Function Function
Control1 Pull-down2
1
Control
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Preliminary
Freescale Semiconductor
Pin
Group
Primary
Function
QSPI
QSPI_DIN/
EZPD
CANRX3
RXD1
GPIO
PDSR[2]
PSRR[2]
—
16
F3
12
QSPI_DOUT
/EZPQ
CANTX3
TXD1
GPIO
PDSR[1]
PSRR[1]
—
17
G1
13
QSPI_CLK/
EZPCK
SCL
RTS1
GPIO
PDSR[3]
PSRR[3]
pull-up7
18
G2
14
QSPI_CS3
SYNCA
SYNCB
GPIO
PDSR[7]
PSRR[7]
—
12
F1
—
QSPI_CS2
—
—
GPIO
PDSR[6]
PSRR[6]
—
13
F2
—
QSPI_CS1
—
—
GPIO
PDSR[5]
PSRR[5]
—
19
H2
—
QSPI_CS0
SDA
CTS1
GPIO
PDSR[4]
PSRR[4]
pull-up7
20
H1
15
RSTI
—
—
—
N/A
N/A
pull-up8
96
A3
59
RSTO
—
—
—
high
FAST
—
97
B3
60
Test
TEST
—
—
—
N/A
N/A
pull-down
5
C2
3
Timers,
16-bit
GPT3
—
PWM7
GPIO
PDSR[23]
PSRR[23]
pull-up9
62
D8
43
GPT2
—
PWM5
GPIO
PDSR[22]
PSRR[22]
pull-up9
61
D9
42
GPT1
—
PWM3
GPIO
PDSR[21]
PSRR[21]
pull-up9
59
E9
41
GPT0
—
PWM1
GPIO
PDSR[20]
PSRR[20]
pull-up9
58
F7
40
DTIN3
DTOUT3
PWM6
GPIO
PDSR[19]
PSRR[19]
—
32
H3
19
DTIN2
DTOUT2
PWM4
GPIO
PDSR[18]
PSRR[18]
—
31
J3
18
DTIN1
DTOUT1
PWM2
GPIO
PDSR[17]
PSRR[17]
—
37
G4
23
DTIN0
DTOUT0
PWM0
GPIO
PDSR[16]
PSRR[16]
—
36
H4
22
UCTS0
CANRX
—
GPIO
PDSR[11]
PSRR[11]
—
6
C1
4
URTS0
CANTX
—
GPIO
PDSR[10]
PSRR[10]
—
9
D3
7
URXD0
—
—
GPIO
PDSR[9]
PSRR[9]
—
7
D1
5
UTXD0
—
—
GPIO
PDSR[8]
PSRR[8]
—
8
D2
6
Reset8
Timers,
32-bit
UART 0
Pin on
100 LQFP
Pin on 81 Pin on 64
MAPBGA LQFP/QFN
Notes
MCF5213 Family Configurations
20
Table 3. Pin Functions by Primary and Alternate Purpose
Freescale Semiconductor
Table 3. Pin Functions by Primary and Alternate Purpose
Drive
Secondary Tertiary Quaternary
Slew Rate /
Pull-up /
Strength /
Function Function Function
Control1 Pull-down2
1
Control
Primary
Function
UART 1
UCTS1
SYNCA
URXD2
GPIO
PDSR[15]
PSRR[15]
—
98
C3
61
URTS1
SYNCB
UTXD2
GPIO
PDSR[14]
PSRR[14]
—
4
B1
2
URXD1
—
—
GPIO
PDSR[13]
PSRR[13]
—
100
B2
63
UTXD1
—
—
GPIO
PDSR[12]
PSRR[12]
—
99
A2
62
UCTS2
—
—
GPIO
PDSR[27]
PSRR[27]
—
27
—
—
URTS2
—
—
GPIO
PDSR[26]
PSRR[26]
—
30
—
—
URXD2
—
—
GPIO
PDSR[25]
PSRR[25]
—
28
—
—
UTXD2
—
—
GPIO
PDSR[24]
PSRR[24]
—
29
—
—
CANRX
N/A
N/A
—
—
—
—
See Note3,10
CANTX
N/A
N/A
—
—
—
—
See Note3,10
55
F8
37
UART 2
FlexCAN
Pin on
100 LQFP
Pin on 81 Pin on 64
MAPBGA LQFP/QFN
VSTBY
VSTBY
—
—
—
N/A
N/A
—
VDD
VDD
—
—
—
N/A
N/A
—
1,2,14,22, D5,E3–E7, 1,10,20,39,
23,34,41,
F5
52
57,68,81,93
VSS
VSS
—
—
—
N/A
N/A
—
3,15,24,25, A1,A9,D4,
35,42,56,
D6,F4,F6,
67,75,82,92
J1
Notes
11,21,38,
53,64
NOTES:
The PDSR and PSSR registers are described in the Ports/GPIO chapter of the MCF5213 Reference Manual. All programmable signals default to 2mA drive
and FAST slew rate in normal (single-chip) mode.
2 All signals have a pull-up in GPIO mode.
3 The multiplexed CANTX and CANRX signals are not available on the MCF5211 or MCF5212
4 For primary and GPIO functions only.
5 Only when JTAG mode is enabled.
6 CLKMOD0 and CLKMOD1 have internal pull-down resistors, however the use of external resistors is very strongly recommended
7 For secondary and GPIO functions only.
8 RSTI has an internal pull-up resistor, however the use of an external resistor is very strongly recommended
9 For GPIO function. Primary Function has pull-up control within the GPT module
10
CANTX and CANRX are secondary functions only.
1
21
MCF5213 Family Configurations
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Preliminary
Pin
Group
MCF5213 Family Configurations
1.5
Reset Signals
Table 4 describes signals that are used to either reset the chip or as a reset indication.
Table 4. Reset Signals
1.6
Signal Name
Abbreviation
Function
I/O
Reset In
RSTI
Primary reset input to the device. Asserting RSTI immediately resets
the CPU and peripherals.
I
Reset Out
RSTO
Driven low for 512 CPU clocks after the reset source has deasserted.
O
PLL and Clock Signals
Table 5 describes signals that are used to support the on-chip clock generation circuitry.
Table 5. PLL and Clock Signals
1.7
Signal Name
Abbreviation
External Clock In
EXTAL
Crystal
XTAL
Clock Out
CLKOUT
Function
I/O
Crystal oscillator or external clock input except when the on-chip
relaxation oscillator is used.
I
Crystal oscillator output except when CLKMOD1=1, then sampled as
part of the clockmode selection mechanism.
O
This output signal reflects the internal system clock.
O
Mode Selection
Table 6 describes signals used in mode selection, Table 7 describes particular clocking modes.
Table 6. Mode Selection Signals
Signal Name
Clock Mode Selection
Abbreviation
Function
I/O
CLKMOD[1:0] Selects the clock boot mode.
I
Reset Configuration
RCON
The Serial Flash Programming mode is entered by asserting the
RCON pin (with the TEST pin negated) as the chip comes out of
reset. During this mode, the EzPort has access to the Flash memory
which can be programmed from an external device.
Test
TEST
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of
test functions.
I
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
22
Preliminary
Freescale Semiconductor
MCF5213 Family Configurations
Table 7. Clocking Modes
1.8
CLKMOD[1:0]
XTAL
Configure the clock mode.
00
0
PLL disabled, clock driven by external oscillator
00
1
PLL disabled, clock driven by on-chip oscillator
01
N/A
10
0
PLL in normal mode, clock driven by external oscillator
10
1
PLL in normal mode, clock driven by on-chip oscillator
11
N/A
PLL disabled, clock driven by crystal
PLL in normal mode, clock driven by crystal
External Interrupt Signals
Table 8 describes the external interrupt signals.
Table 8. External Interrupt Signals
1.9
Signal Name
Abbreviation
External Interrupts
IRQ[7:1]
Function
External interrupt sources.
I/O
I
Queued Serial Peripheral Interface (QSPI)
Table 9 describes QSPI signals.
Table 9. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name
QSPI Synchronous
Serial Output
Abbreviation
Function
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK.
I/O
O
QSPI Synchronous
Serial Data Input
QSPI_DIN
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK.
I
QSPI Serial Clock
QSPI_CLK
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable.
O
Synchronous Peripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active
Chip Selects
high or low.
O
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
23
MCF5213 Family Configurations
1.10 I2C I/O Signals
Table 10 describes the I2C serial interface module signals.
Table 10. I2C I/O Signals
Signal Name
Abbreviation
Function
I/O
Serial Clock
SCL
Open-drain clock signal for the for the I2C interface. Either it is driven
by the I2C module when the bus is in master mode or it becomes the
clock input when the I2C is in slave mode.
I/O
Serial Data
SDA
Open-drain signal that serves as the data input/output for the I2C
interface.
I/O
1.11 UART Module Signals
Table 11 describes the UART module signals.
Table 11. UART Module Signals
Signal Name
Abbreviation
Function
I/O
Transmit Serial Data
Output
UTXDn
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, LSB first, on this pin at
the falling edge of the serial clock source.
O
Receive Serial Data
Input
URXDn
Receiver serial data inputs for the UART modules. Data is received on
this pin LSB first. When the UART clock is stopped for power-down
mode, any transition on this pin restarts it.
I
Clear-to-Send
UCTSn
Indicate to the UART modules that they can begin data transmission.
I
Request-to-Send
URTSn
Automatic request-to-send outputs from the UART modules. This
signal can also be configured to be asserted and negated as a
function of the RxFIFO level.
O
1.12 DMA Timer Signals
Table 12 describes the signals of the four DMA timer modules.
Table 12. DMA Timer Signals
Signal Name
Abbreviation
DMA Timer Input
DTIN
DMA Timer Output
DTOUT
Function
I/O
Event input to the DMA timer modules.
I
Programmable output from the DMA timer modules.
O
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
24
Preliminary
Freescale Semiconductor
MCF5213 Family Configurations
1.13 ADC Signals
Table 13 describes the signals of the Analog-to-Digital Converter.
Table 13. ADC Signals
Signal Name
Abbreviation
Analog Inputs
AN[7:0]
Analog Reference
VRH
Function
Inputs to the A-to-D converter.
I
Reference voltage high and low inputs.
I
VRL
Analog Supply
I/O
I
Isolate the ADC circuitry from power supply noise
VDDA
—
—
VSSA
1.14 General Purpose Timer Signals
Table 14 describes the General Purpose Timer Signals.
Table 14. GPT Signals
Signal Name
Abbreviation
General Purpose Timer
Input/Output
GPT[3:0]
Function
I/O
Inputs to or outputs from the general purpose timer module
I/O
1.15 Pulse Width Modulator Signals
Table 15 describes the PWM signals.
Table 15. PWM Signals
Signal Name
Abbreviation
Function
I/O
PWM Output Channels
PWM[7:0]
Pulse width modulated output for PWM channels
O
1.16 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM
logic.
Table 16. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
JTAG Enable
JTAG_EN
Select between debug module and JTAG signals at reset
I
Test Reset
TRST
This active-low signal is used to initialize the JTAG logic
asynchronously.
I
Test Clock
TCLK
Used to synchronize the JTAG logic.
I
Test Mode Select
TMS
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
I
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
25
MCF5213 Family Configurations
Table 16. Debug Support Signals (continued)
Signal Name
Abbreviation
Function
I/O
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Development Serial Clock-Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
I
Breakpoint
BKPT
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0]PSTDDATA[7:0]) as the value 0xF.
If CSR[BKD] is set (disabling normal BKPT functionality), asserting
BKPT generates a debug interrupt exception in the processor.
I
Development Serial
Input
DSI
Development Serial Input -Internally synchronized input that provides
data input for the serial communication port to the debug module,
once the DSCLK has been seen as high (logic 1).
I
Development Serial
Output
DSO
Development Serial Output -Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
O
Debug Data
DDATA[3:0]
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
O
Processor Status Clock
PSTCLK
Processor Status Clock - Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and
PST and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
O
Processor Status
Outputs
PST[3:0]
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
O
All Processor Status
Outputs
ALLPST
Logical “AND” of PST[3.0]
O
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
26
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
1.17 EzPort Signal Descriptions
Table 17 contains a list of EzPort external signals
Table 17. EzPort Signal Descriptions
Signal Name
Abbreviation
Function
I/O
EzPort Clock
EZPCK
Shift clock for EzPort transfers
I
EzPort Chip Select
EZPCS
Chip select for signalling the start and end
of serial transfers
I
EzPort Serial Data In
EZPD
EZPD is sampled on the rising edge of
EZPCK
I
EzPort Serial Data Out
EZPQ
EZPQ transitions on the falling edge of
EZPCK
O
1.18 Power and Ground Pins
The pins described in Table 18 provide system power and ground to the chip. Multiple pins are provided
for adequate current capability. All power supply pins must have adequate bypass capacitance for
high-frequency noise suppression.
Table 18. Power and Ground Pins
2
Signal Name
Abbreviation
Function
I/O
PLL Analog Supply
VDDPLL,
VSSPLL
Dedicated power supply signals to isolate the sensitive PLL analog
circuitry from the normal levels of noise present on the digital power
supply.
I
Positive Supply
VDD
These pins supply positive power to the core logic.
I
Ground
VSS
This pin is the negative supply (ground) to the chip.
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MCF5213
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5213.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this appendix supersede any values found in the
module specifications.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
27
Preliminary Electrical Characteristics
2.1
Maximum Ratings
Table 19. Absolute Maximum Ratings1, 2
Rating
Symbol
Value
Unit
VDD
– 0.3 to +4.0
V
Clock Synthesizer Supply Voltage
VDDPLL
– 0.3 to +4.0
V
RAM Memory Standby Supply Voltage
VSTBY
– 0.3 to + 4.0
V
VIN
– 0.3 to + 4.0
V
EXTAL pin voltage
VEXTAL
0 to 3.3
V
XTAL pin voltage
VXTAL
0 to 3.3
V
IDD
25
mA
TA
(TL - TH)
– 40 to 85
°C
Tstg
– 65 to 150
°C
Supply Voltage
Digital Input Voltage
3
Instantaneous Maximum Current
Single pin limit (applies to all pins) 4, 5
Operating Temperature Range (Packaged)
Storage Temperature Range
NOTES:
1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum
Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress
beyond those listed may affect device reliability or cause permanent damage to the device.
2 This device contains circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).
3 Input must be current limited to the I
DD value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then
use the larger of the two values.
4 All functional non-supply pins are internally clamped to V
SS and VDD.
5 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD,
the injection current may flow out of VDD and could result in external power supply going out of
regulation. Insure external VDD load will shunt current greater than maximum injection current. This
will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must
maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions.
2.2
Current Consumption
Table 20. Current Consumption in Low-Power Mode1,2
8MHz (Typ)3 16MHz (Typ)2 64MHz (Typ)2 80MHz (Typ)2 80MHz (Peak)4
Mode
Stop Mode 3 (Stop 11)5
0.13
TBD
5
2.29
TBD
Stop Mode 2 (Stop 10)
5,6
Stop Mode 1 (Stop 01)
2.80
3.08
4.76
5.38
TBD
Stop Mode 0 (Stop 00)5
2.80
3.08
4.76
5.39
TBD
Wait / Doze
11.12
20.23
30.17
33.36
TBD
Run
12.40
22.74
39.92
45.47
TBD
Units
mA
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
28
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
NOTES:
1
All values are measured with a 3.30V power supply
2
Refer to the Power Management chapter in the MCF5213 Reference Manual for more information on low-power modes.
3
CLKOUT and all peripheral clocks except UART0 and CFM off before entering low power mode. CLKOUT is disabled. All
code executed from FLASH. Code run from SRAM reduces power consumption further. Tests performed at room
temperature.
4 CLKOUT and all peripheral clocks on before entering low power mode. All code is executed from FLASH. All code is
executed at 80MHz clock.
5
See the description of the Low-Power Control Register (LCPR) in the MCF5213 Reference Manual for more information
on Stop modes 0–3.
6
Results are identical to STOP 00 for typical values since they only differ by CLKOUT power consumption. CLKOUT is
already disabled in this instance prior to entering low power mode.
50.00
45.00
40.00
mA @ 3.3V
35.00
Stop 0 - Flash
Stop 1 - Flash
Stop 2 - Flash
Stop 3 - Flash
Wait/Doze - Flash
Run - Flash
30.00
25.00
20.00
15.00
10.00
5.00
0.00
0
8
16
24
32
40
48
56
64
72
80
System Clock (MHz)
Typical Current Consumption in Low-Power Modes
Table 21. Typical Active Current Consumption Specifications
Symbol
Typical1
Active
(SRAM)
Typical1
Active
(Flash)
Peak2
Unit
IDD
TBD
3.48
TBD
mA
• 8 MHz core & I/O
7.28
13.37
19.02
• 16 MHz core & I/O
12.08
25.08
35.66
• 64 MHz core & I/O
40.14
54.62
85.01
• 80 MHz core & I/O
49.2
64.09
100.03
Characteristic
• 1 MHz core & I/O
RAM Memory Standby Supply Current
Normal Operation: VDD > VSTBY - 0.3 V
Transient Condition: VSTBY - 0.3 V > VDD > VSS + 0.5 V
Standby Operation: VDD < VSS + 0.5 V
ISTBY
Analog Supply Current
Normal Operation
Low-Power Stop
IDDA
0
TBD
TBD
—
—
—
—
TBD
TBD
TBD
µA
mA
µA
TBD
TBD
mA
µA
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
29
Preliminary Electrical Characteristics
NOTES:
1
Tested at room temperature with CPU polling a status register. All clocks were off except the UART and CFM (when
running from Flash).
2
Peak current measured with all modules active, and default drive strength with matching load.
2.3
Thermal Characteristics
Table 22 lists thermal resistance values.
Table 22. Thermal Characteristics
Characteristic
100 LQFP
Unit
Single Layer board (1s)
θJA
531,2
°C/W
Junction to ambient, natural convection
Four layer board (2s2p)
θJA
391,3
°C/W
Single Layer board (1s)
θJMA
421,3
°C/W
Four layer board (2s2p)
θJMA
1,3
°C/W
Junction to ambient, (@200 ft/min)
33
Junction to board
θJB
254
°C/W
Junction to case
θJC
95
°C/W
Junction to top of package
Ψjt
26
°C/W
Tj
105
oC
Natural convection
Maximum operating junction temperature
Junction to ambient, natural convection
Single Layer board (1s)
θJA
611,2
°C/W
Junction to ambient, natural convection
Four layer board (2s2p)
θJA
352,3
°C/W
Single Layer board (1s)
θJMA
502,3
°C/W
Four layer board (2s2p)
θJMA
312,3
°C/W
Junction to board
θJB
204
°C/W
Junction to case
θJC
125
°C/W
Junction to top of package
Ψjt
26
°C/W
Tj
105
oC
Junction to ambient, (@200 ft/min)
Junction to ambient, (@200 ft/min)
Natural convection
Maximum operating junction temperature
64 LQFP
Value
Junction to ambient, natural convection
Junction to ambient, (@200 ft/min)
81 MAPBGA
Symbol
Junction to ambient, natural convection
Single layer board (1s)
θJA
621,2
°C/W
Junction to ambient, natural convection
Four layer board (2s2p)
θJA
431,3
°C/W
Single layer board (1s)
θJMA
1,3
50
°C/W
Four layer board (2s2p)
θJMA
361,3
°C/W
Junction to board
θJB
264
°C/W
Junction to case
θJC
95
°C/W
Junction to top of package
Ψjt
26
°C/W
Tj
105
oC
Junction to ambient (@200 ft/min)
Junction to ambient (@200 ft/min)
Natural convection
Maximum operating junction temperature
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
30
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 22. Thermal Characteristics (continued)
Characteristic
64 QFN
Symbol
Value
Unit
Single layer board (1s)
θJA
681,2
°C/W
Four layer board (2s2p)
θJA
241,3
°C/W
Junction to ambient (@200 ft/min)
Single layer board (1s)
θJMA
1,3
55
°C/W
Junction to ambient (@200 ft/min)
Four layer board (2s2p)
θJMA
191,3
°C/W
Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to board
θJB
Junction to case (bottom)
θJC
0.6
°C/W
Junction to top of package
Ψjt
6
3
°C/W
Tj
105
Natural convection
Maximum operating junction temperature
4
8
5
°C/W
o
C
NOTES:
θJA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction
temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device
junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt
parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
2 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
3 Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
4 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written in conformance with Psi-JT.
1
The average chip-junction temperature (TJ) in °C can be obtained from:
T J = T A + ( P D × Θ JMA ) (1)
Where:
TA
= Ambient Temperature, °C
ΘJA
= Package Thermal Resistance, Junction-to-Ambient, °C/W
PD
= PINT + PI/O
PINT
= IDD × VDD, Watts - Chip Internal Power
PI/O
= Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
P D = K ÷ ( T J + 273°C )
(2)
Solving equations 1 and 2 for K gives:
K = PD × (TA + 273 °C) + ΘJMA × PD 2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for
any value of TA.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
31
Preliminary Electrical Characteristics
2.4
Flash Memory Characteristics
The Flash memory characteristics are shown in Table 23 and Table 24.
Table 23. SGFM Flash Program and Erase Characteristics
(VDDF = 2.7 to 3.6 V)
Parameter
System clock (read only)
System clock
(program/erase)1
Symbol
Min
Typ
Max
Unit
fsys(R)
0
—
80
MHz
fsys(P/E)
0.15
—
80
MHz
NOTES:
1 Refer to the Flash section for more information
Table 24. SGFM Flash Module Life Characteristics
(VDDF = 2.7 to 3.6 V)
Parameter
Symbol
Value
Unit
P/E
10,0002
Cycles
Retention
10
Years
Maximum number of guaranteed program/erase cycles1 before failure
Data retention at average operating temperature of 85°C
NOTES:
1 A program/erase cycle is defined as switching the bits from 1 → 0 → 1.
2 Reprogramming of a Flash array block prior to erase is not required.
2.5
ESD Protection
Table 25. ESD Protection Characteristics1, 2
Characteristics
ESD Target for Human Body Model
ESD Target for Machine Model
Symbol
Value
Units
HBM
2000
V
MM
200
V
HBM Circuit Description
Rseries
1500
ohms
C
100
pF
MM Circuit Description
Rseries
0
ohms
pF
C
200
Number of pulses per pin (HBM)
positive pulses
negative pulses
—
—
1
1
Number of pulses per pin (MM)
positive pulses
negative pulses
—
—
3
3
Interval of Pulses
—
1
—
—
sec
NOTES:
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
32
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
2.6
DC Electrical Specifications
Table 26. DC Electrical Specifications 1
Characteristic
Symbol
Min
Max
Unit
Supply Voltage
VDD
3.0
3.6
V
Input High Voltage
VIH
0.7 x VDD
4.0
V
Input Low Voltage
VIL
VSS – 0.3
0.35 x VDD
V
VHYS
0.06 x VDD
—
mV
Iin
–1.0
1.0
µA
Output High Voltage (All input/output and all output pins)
IOH = –2.0 mA
VOH
OVDD - 0.5
__
V
Output Low Voltage (All input/output and all output pins)
IOL = 2.0mA
VOL
__
0.5
V
Output High Voltage (High Drive)
IOH = TBD
VOH
OVDD - 0.5
__
V
Output Low Voltage (High Drive)
IOL = TBD
VOL
__
0.5
V
Output High Voltage (Low Drive)
IOH = TBD
VOH
OVDD - 0.5
__
V
Output Low Voltage (Low Drive)
IOL = TBD
VOL
__
0.5
V
Weak Internal Pull Up Device Current, tested at VIL Max.2
IAPU
-10
- 130
µA
—
—
7
7
Input Hysteresis
Input Leakage Current
Vin = VDD or VSS, digital pins
3
Input Capacitance
All input-only pins
All input/output (three-state) pins
pF
Cin
NOTES:
1 Refer to Table 27 for additional PLL specifications.
2
Refer to the MCF5213 signals chapter for pins having weak internal pull-up devices.
3 This parameter is characterized before qualification rather than 100% tested.
2.7 Clock Source Electrical Specifications
Table 27. PLL Electrical Specifications
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
PLL Reference Frequency Range
Crystal reference
External reference
Symbol
Min
Max
fref_crystal
fref_ext
2
2
10.0
10.0
0
fref / 32
80
80
fLOR
100
1000
kHz
fSCM
1
5
MHz
tcst
—
10
ms
MHz
System Frequency 1
External Clock Mode
On-Chip PLL Frequency
fsys
Loss of Reference Frequency 2, 4
Self Clocked Mode Frequency
Crystal Start-up Time
Unit
3, 4
4, 5
MHz
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
33
Preliminary Electrical Characteristics
Table 27. PLL Electrical Specifications (continued)
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
Symbol
Min
Max
2.0
VDD
VSS
0.8
tlpll
—
500
µs
tdc
40
60
% fref
Frequency un-LOCK Range
fUL
- 1.5
1.5
% fref
Frequency LOCK Range
fLCK
- 0.75
0.75
% fref
—
—
10
.01
% fsys
7.84
8.16
MHz
EXTAL Input High Voltage
External reference
VIHEXT
EXTAL Input Low Voltage
External reference
VILEXT
PLL Lock Time4,6
Duty Cycle of reference
4
4, 5, 7, 7,8
CLKOUT Period Jitter
, Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter (Averaged over 2 ms interval)
On-chip oscillator frequency
Unit
V
V
Cjitter
foco
NOTES:
All internal registers retain data at 0 Hz.
2 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self
clocked mode.
3 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
fLOR with default MFD/RFD settings.
4 This parameter is characterized before qualification rather than 100% tested.
5 Proper PC board layout procedures must be followed to achieve specifications.
6 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
7 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the Cjitter percentage for a given interval
8 Based on slow system clock of 40 MHz measured at f
sys max.
1
2.8
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1,
Interrupts and USB interfaces. When in GPIO mode, the timing specification for these pins is given in
Table 28 and Figure 5.
Table 28. GPIO Timing
NUM
Characteristic
Symbol
Min
Max
Unit
G1
CLKOUT High to GPIO Output Valid
tCHPOV
-
10
ns
G2
CLKOUT High to GPIO Output Invalid
tCHPOI
1.5
-
ns
G3
GPIO Input Valid to CLKOUT High
tPVCH
9
-
ns
G4
CLKOUT High to GPIO Input Invalid
tCHPI
1.5
-
ns
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
34
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
CLKOUT
G2
G1
GPIO Outputs
G4
G3
GPIO Inputs
Figure 5. GPIO Timing
2.9
Reset Timing
Table 29. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM
Characteristic
Symbol
Min
Max
Unit
R1
RSTI Input valid to CLKOUT High
tRVCH
9
-
ns
R2
CLKOUT High to RSTI Input invalid
tCHRI
1.5
-
ns
tRIVT
5
-
tCYC
tCHROV
-
10
ns
2
R3
RSTI Input valid Time
R4
CLKOUT High to RSTO Valid
NOTES:
1 All AC timing is shown with respect to 50% O V
DD levels unless otherwise noted.
2 During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to
the system. Thus, RSTI must be held a minimum of 100 ns.
CLKOUT
1R1
RSTI
R2
R3
R4
R4
RSTO
Figure 6. RSTI and Configuration Override Timing
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
35
Preliminary Electrical Characteristics
2.10 I2C Input/Output Timing Specifications
Table 30 lists specifications for the I2C input timing parameters shown in Figure 7.
Table 30. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
11
Start condition hold time
2 x tCYC
—
ns
I2
Clock low period
8 x tCYC
—
ns
I3
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
mS
I4
Data hold time
0
—
ns
I5
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
mS
I6
Clock high time
4 x tCYC
—
ns
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2 x tCYC
—
ns
I9
Stop condition setup time
2 x tCYC
—
ns
Table 31 lists specifications for the I2C output timing parameters shown in Figure 7.
Table 31. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
111
I2
1
Characteristic
Min
Max
Units
Start condition hold time
6 x tCYC
—
ns
Clock low period
10 x tCYC
—
ns
—
—
µS
7 x tCYC
—
ns
—
3
ns
I32
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
I41
Data hold time
I53
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
I61
Clock high time
10 x tCYC
—
ns
I71
Data setup time
2 x tCYC
—
ns
Start condition setup time (for repeated start
condition only)
20 x tCYC
—
ns
Stop condition setup time
10 x tCYC
—
ns
I8
1
I91
NOTES:
1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with
the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 31. The
I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL
low period. The actual position is affected by the prescale and division values programmed into the
IFDR; however, the numbers given in Table 31 are minimum values.
2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
3 Specified at a nominal 50-pF load.
Figure 7 shows timing for the values in Table 30 and Table 31.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
36
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
I2
SCL
I6
I1
I5
I4
I3
I8
I7
I9
SDA
Figure 7. I2C Input/Output Timings
2.11 Analog-to-Digital Converter (ADC) Parameters
Table 32 lists specifications for the analog-to-digital converter.
Table 32. ADC Parameters1
Name
Characteristic
Min
Typical
Max
Unit
VREFL
Low reference voltage
VSS
—
VREFH
V
VREFH
High reference voltage
VREFL
—
VDDA
V
VDDA
ADC analog supply voltage
3.0
3.3
3.6
V
VADIN
Input voltages
VREFL
—
VREFH
V
12
—
12
Bits
RES
Resolution
2
INL
Integral Non-Linearity (Full input signal range)
—
±2.5
±3
LSB3
INL
Integral Non-Linearity (10% to 90% input signal range)4
—
±2.5
±3
LSB
DNL
Differential Non-Linearity
—
-1 < DNL < +1
<+1
LSB
Monotonicity
GUARANTEED
fADIC
ADC internal clock
0.1
—
5.0
MHz
RAD
Conversion Range
VREFL
—
VREFH
V
—
6
13
tAIC cycles6
time5
tADPU
ADC power-up
tREC
Recovery from auto standby
—
0
1
tAIC cycles
tADC
Conversion time
—
6
—
tAIC cycles
tADS
Sample time
—
1
—
tAIC cycles
CADI
Input capacitance
—
See Figure 8
—
pF
XIN
Input impedance
IADI
Input injection
IVREFH
VOFFSET
EGAIN
VOFFSET
SNR
current7,
Ω
See Figure 8
per pin
—
—
3
mA
VREFH current
—
0
—
µ
Offset voltage internal reference
—
±8
±15
mV
Gain Error (transfer path)
.99
1
1.01
—
Offset voltage external reference
—
±3
TBD
mV
TBD
62 to 66
Signal-to-Noise ratio
dB
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
37
Preliminary Electrical Characteristics
Table 32. ADC Parameters1 (continued)
Name
Min
Typical
Total Harmonic Distortion
TBD
-75
dB
SFDR
Spurious Free Dynamic Range
TBD
67 to 70.3
dB
SINAD
Signal-to-Noise plus Distortion
TBD
61 to 63.9
dB
ENOB
Effective Number OF Bits
9.1
10.6
Bits
THD
Characteristic
Max
Unit
NOTES:
1
All measurements are preliminary pending full characterization, and were made at VDD = 3.3V, VREFH = 3.3V, and VREFL =
ground
2 INL measured from V = V
IN
REFL to VIN = VREFH
3 LSB = Least Significant Bit
4
INL measured from VIN = 0.1VREFH to VIN = 0.9VREFH
5 Includes power-up of ADC and V
REF
6 ADC clock cycles
7 The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
ADC
2.11.1 Equivalent Circuit for ADC Inputs
Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at
the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (VREFH-VREFL)/2, while the other charges to the analog input voltage. When the
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches switch on
every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are
additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the
S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is
that there is an on-going input current, which is a function of the analog input voltage, VREF and the ADC
clock frequency.
125Ω ESD Resistor
8pF noise damping capacitor
3
Analog Input
4
S1
C1
S/H
S3
1
1.
2.
3.
4.
2
(VREFH- VREFL )/ 2
S2
C2
C1 = C2 = 1pF
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
Equivalent resistance for the channel select mux; 100 ohms
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
38
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
5.
1
Equivalent input impedance, when the input is selected =
(ADC Clock Rate) x 1.4 x 10-12
Figure 8. Equivalent Circuit for A/D Loading
2.12 DMA Timers Timing Specifications
Table 33 lists timer module AC timings.
Table 33. Timer Module AC Timing Specifications
Characteristic1
Name
Min
Max
Unit
T1
DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time
3 x tCYC
—
ns
T2
DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width
1 x tCYC
—
ns
NOTES:
1 All timing references to CLKOUT are given to its rising edge.
2.13 QSPI Electrical Specifications
Table 34 lists QSPI timings.
Table 34. QSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
QS1
QSPI_CS[3:0] to QSPI_CLK
1
510
tCYC
QS2
QSPI_CLK high to QSPI_DOUT valid.
—
10
ns
QS3
QSPI_CLK high to QSPI_DOUT invalid (Output hold)
2
—
ns
QS4
QSPI_DIN to QSPI_CLK (Input setup)
9
—
ns
QS5
QSPI_DIN to QSPI_CLK (Input hold)
9
—
ns
The values in Table 34 correspond to Figure 9.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
39
Preliminary Electrical Characteristics
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 9. QSPI Timing
2.14 JTAG and Boundary Scan Timing
Table 35. JTAG and Boundary Scan Timing
Characteristics1
Num
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
1/4
fsys/2
J2
TCLK Cycle Period
tJCYC
4 x tCYC
-
ns
J3
TCLK Clock Pulse Width
tJCW
26
-
ns
J4
TCLK Rise and Fall Times
tJCRF
0
3
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
4
-
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
26
-
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
0
33
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
0
33
ns
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
4
-
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10
-
ns
J11
TCLK Low to TDO Data Valid
tTDODV
0
26
ns
J12
TCLK Low to TDO High Z
tTDODZ
0
8
ns
J13
TRST Assert Time
tTRSTAT
100
-
ns
J14
TRST Setup Time (Negation) to TCLK High
tTRSTST
10
-
ns
NOTES:
1
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
40
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 10. Test Clock Input Timing
TCLK
VIL
VIH
J5
Data Inputs
J6
Input Data Valid
J7
Data Outputs
Output Data Valid
J8
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 11. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
TDI
TMS
J10
Input Data Valid
J11
TDO
Output Data Valid
J12
TDO
J11
TDO
Output Data Valid
Figure 12. Test Access Port Timing
TCLK
14
TRST
13
Figure 13. TRST Timing
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
41
Preliminary Electrical Characteristics
2.15 Debug AC Timing Specifications
Table 36 lists specifications for the debug AC timing parameters shown in Figure 15.
Table 36. Debug AC Timing Specification
166 MHz
Num
Characteristic
Units
Min
Max
D0
PSTCLK cycle time
0.5
D1
PST, DDATA to CLKOUT setup
4
ns
D2
CLKOUT to PST, DDATA hold
1.5
ns
D3
DSI-to-DSCLK setup
1 x tCYC
ns
D41
DSCLK-to-DSO hold
4 x tCYC
ns
D5
DSCLK cycle time
5 x tCYC
ns
D6
BKPT input data setup time to CLKOUT Rise
4
ns
D7
BKPT input data hold time to CLKOUT Rise
1.5
ns
D8
CLKOUT high to BKPT high Z
0.0
10.0
tCYC
ns
NOTES:
1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative
to the rising edge of CLKOUT.
Figure 14 shows real-time trace timing for the values in Table 36.
CLKOUT
D1
D2
PST[3:0]
DDATA[3:0]
Figure 14. Real-Time Trace AC Timing
Figure 15 shows BDM serial port AC timing for the values in Table 36.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
42
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
CLKOUT
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Current
Figure 15. BDM Serial Port AC Timing
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
Freescale Semiconductor
Preliminary
43
Mechanical Outline Drawings
3
Mechanical Outline Drawings
This section describes the physical properties of the MCF5213 and its derivatives.
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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Preliminary
Freescale Semiconductor
Mechanical Outline Drawings
MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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Mechanical Outline Drawings
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Mechanical Outline Drawings
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Mechanical Outline Drawings
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Mechanical Outline Drawings
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Mechanical Outline Drawings
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MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2
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Preliminary
55
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MCF5213EC
Rev. 1.2, 01/2006
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