MGA-30116 150MHz – 1GHz ½ Watt High Linearity Amplifier Data Sheet Description Features Avago Technologies’ MGA-30116 is a high linearity ½ Watt PA with good OIP3 performance and exceptionally good PAE at p1dB gain compression point, achieved through the use of Avago Technologies’ proprietary 0.25um GaAs Enhancement-mode pHEMT process. High linearity and P1dB The adjustable temperature compensated internal bias circuit allowed the device to be operated at either class A or class AB operation Built in adjustable temperature compensated internal bias circuitry GaAs E-pHEMT Technology [1] Standard QFN 3X3 package 5V supply Excellent uniformity in product specifications The MGA-30116 is housed inside a standard 16 pin QFN 3X3 package. Tape-and-Reel packaging option available Applications High MTTF for base station application Class A driver amplifier for GSM/CDMA Base Stations. Specifications General purpose gain block. 900MHz; 5V, 202.8mA (typical) 17.0 dB Gain Component Image 44.1 dBm Output IP3 16 pins QFN 3x3 Vg 15 RFgnd 16 27.7 dBm Output Power at 1dB gain compression 47.0% PAE at P1dB 2.0 dB Noise Figure NC 12 1 Vm VDD/RFout 11 2 Vbias GND VDD/RFout 10 3 RF in NC 9 4 NC 5 NC 6 NC 7 GND 8 NC TOP VIEW GND 14 NC 13 30116 YYWW XXXX MSL-1 and Lead-free Notes: 1. Enhancement mode technology employs positive gate voltage, thereby eliminating the need of negative gate voltage associated with conventional depletion mode devices. nc = not connected BOTTOM VIEW Notes: Package marking provides orientation and identification “30116” = Device Part Number “YYWW” = Work Week and Year of manufacture “XXXX” = Last 4 digit of Lot number Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 60 V ESD Human Body Model = 300 V Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. Absolute Maximum Rating [1] TA=25C Symbol Parameter Units Absolute Max. Vdd,max Device Voltage, RF output to ground V 5.5 Ids,max Device Drain Current mA 400 Vctrl,max Control Voltage V 5.5 Pin,max CW RF Input Power dBm 22 Pdiss Total Power Dissipation [3] W 2.2 Tj, max Junction Temperature C 150 TSTG Storage Temperature C -65 to 150 Thermal Resistance [2] jc = 33 C/W (Vdd=5, Ids=200mA, Tc=85C) Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using Infra-Red measurement technique. 3. This is limited by maximum Vdd and Ids. Derate 30.3mW/ C for Tc> 77.5 C. Electrical Specifications [4] TA = 25C, Vdd =5V, Vctrl =5V, RF performance at 900 MHz, measured on demo board (see Fig. 7) unless otherwise specified. Symbol Parameter and Test Condition Units Min. Typ. Max. Ids Quiescent current mA 165 202.8 240 Ictrl Vctrl current mA - 7 - Gain Gain dB 15.5 17.0 18.5 OIP3 [5] Output Third Order Intercept Point dBm 41 44.1 - OP1dB Output Power at 1dB Gain Compression dBm 26.2 27.7 - PAE Power Added Efficiency % - 47.0 - NF Noise Figure dB - 2.0 - S11 Input Return Loss, 50Ω source dB - -14 - S22 Output Return Loss, 50Ω load dB - -14 - S12 Reverse Isolation dB - -23.5 - Notes: 4. Measurements at 900MHz obtained using demo board described in Figure 6 and 7. 5. 900 MHz OIP3 test condition: FRF1 - FRF2 = 10MHz with input power of -5dBm per tone measured at worse side band 6. Use proper biasing, heat sink and de-rating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application note (if applicable) for more details. 2 Product Consistency Distribution Charts [1,2] CPK = 2.209 Stdev = 5.612 Figure 1. Ids at 900MHz; LSL=165mA, nominal =202.8mA, USL=240mA CPK = 1.645 stdev = 0.628 Figure 2. OIP3 at 900MHz; LSL=41dB, nominal=44.1dBm CPK = 27.78 Stdev = 0.018 Figure 3. P1dB at 900MHz; LSL, 26.2dBm, nominal=27.7dBm stdev =0.187 Figure 4. PAE at P1dB 900MHz; nominal=47.0% CPK = 6.858 Stdev = 0.0729 Figure 5. Gain at 900MHz; LSL=15.5dB, Nominal =17.0dB, USL=18.5dB, Notes: 1. Distribution data sample size is 500 samples taken from 2 different wafer lots and 3 different wafers. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 2. Measurements were made on a characterization test board, which represents a trade-off between optimal OIP3, gain, P1dB and PAE. Circuit trace losses have not been de-embedded from measurements above. 3 Demo Board (750MHz to 1GHz) Vctrl Vdd L4 C10 Rbias NC 1 12 Vdd RFout 2 11 C4 3 10 NC NC 4 9 RFout L2 8 NC 7 GND 6 NC NC C2 5 C3 L1 C11 Vdd RFout RFin RFin C9 L3 Vm Vbias C1 C8 13 NC 14 GND 15 Vg C7 16 RFgnd C6 Top View Figure 6. Demo board and application schematic (750MHz to 1GHz) Demo Board Part List Circuit Symbol Size Value Part Number Description L1 0402 10nH LLP1005-FH10NC (TOKO) MLC Inductor L2 0402 6.8nH LLP1005-FH6N8C (TOKO) MLC Inductor L3 0402 8.2nH LL1005-FHL8N2J (TOKO) MLC Inductor L4 0402 15nH MLK1005S15NJ (TDK) MLC Inductor C1 0402 6pF C1005C0G1H060D (TDK) Ceramic Chip Capacitor C2 0402 1.8pF GRM1555C1H1R8CZ01B (Murata) Ceramic Chip Capacitor C3 0402 4.3pF GRM1555C1H4R3CZ01B (Murata) Ceramic Chip Capacitor C4 0402 5.6pF GRM1555C1H5R6CZ01B (Murata) Ceramic Chip Capacitor C6 0402 100pF GRM1555C1H101JZ01B (Murata) Ceramic Chip Capacitor C7 0402 0.1uF GRM155R71E103KA01B (Murata) Ceramic Chip Capacitor C8 0402 100pF GRM1555C1H101JZ01B (Murata) Ceramic Chip Capacitor C9 0805 2.2uF GRM21BR61E225KA12L (Murata) Ceramic Chip Capacitor C10 0402 100pF GRM1555C1H101JZ01B (Murata) Ceramic Chip Capacitor C11 0402 100pF GRM1555C1H101JZ01B (Murata) Ceramic Chip Capacitor Note: Rbias is used to lower the quiescent current. Default is 0 ohm 4 Figure 7. Demo board Layout Recommended PCB material is 10 mils Rogers RO4350, with FR4 backing for mechanical strength. Suggested component values may vary according to layout and PCB material. MGA-30116 Typical Performance (750MHz to 1GHz) 250 240 230 220 210 200 190 180 170 160 150 0.75 OIP3 (dB) Ids (mA) TA = +25C, Vdd = 5V, Vctrl =5V, Input Signal=CW unless stated otherwise. 85ºC 25ºC -40ºC 0.8 0.85 0.9 Frequency (GHz) Figure 8. Over Temperature Ids vs Frequency 5 0.95 1 48 47 46 45 44 43 42 41 40 39 38 0.75 85ºC 25ºC -40ºC 0.8 0.85 0.9 Frequency (GHz) Figure 9. Over Temperature OIP3 vs Frequency 0.95 1 MGA-30116 Typical Performance (750MHz to 1GHz) TA = +25C, Vdd = 5V, Vctrl =5V, Input Signal=CW unless stated otherwise. 31 30 Gain (dB) P1dB (dBm) 29 28 27 26 85ºC 25ºC -40ºC 25 24 0.75 0.8 0.85 0.9 Frequency (GHz) 0.95 1 S22 (dB) S11 (dB) 85ºC 25ºC -40ºC 0.8 0.85 0.9 Frequency (GHz) 0.95 1 0.85 0.9 Frequency (GHz) 0.95 1 85ºC 25ºC -40ºC 0.8 0.85 0.9 Frequency (GHz) Figure 13. Over Temperature S22 vs Frequency 0.95 1 -25 -30 -35 0.8 0.85 0.9 Frequency (GHz) 0.95 -40 -45 -50 3GPP WCDMA Test Test Model Model 1+64DPCH 1+64DPCH +/- 5MHz Offset -55 85ºC 25ºC -40ºC Figure 14. Over Temperature S12 vs Frequency 6 0.8 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 0.75 ACPR (dBC) S12 (dB) Figure 12. Over Temperature S11 vs Frequency -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 0.75 85ºC 25ºC -40ºC Figure 11. Over Temperature Gain vs Frequency Figure 10. Over Temperature P1dB vs Frequency 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 0.75 20 19 18 17 16 15 14 13 12 11 10 0.75 -60 1 -65 15 16 17 18 19 20 21 22 Output Channel Power (dBm) Figure 15. Over Temperature ACPR (900MHz) Vs Pout 85ºC 25ºC -40ºC 23 24 S-Parameter (Vdd = 5V, Vctrl = 5V, T=25°C, unmatched 50 ohm) freq (GHz) S11 (dB) S11 (ang) S21 (dB) S21 (ang) S12 (dB) S12 (ang) S22 (dB) S22 (ang) 0.1 0.819 -66.87 36.25 135.3 0.01439 56.48 0.351 -106.5 0.2 0.6424 -106.1 23.96 113.3 0.02695 48.02 0.4369 -140.2 0.3 0.5681 -130.9 17.2 101.3 0.03032 42.92 0.4617 -155.3 0.4 0.5316 -147 13.32 92.88 0.03406 41.9 0.4729 -164.7 0.5 0.5116 -159.1 10.8 86.62 0.03866 42.74 0.4766 -171.1 0.6 0.5009 -168.6 9.069 81.19 0.0432 42.68 0.4793 -176.5 0.7 0.4943 -176.6 7.799 76.55 0.04839 41.84 0.4773 179.4 0.8 0.4905 176.6 6.861 72.06 0.0529 41.61 0.4778 175.7 0.9 0.4873 170.4 6.112 68.09 0.0576 40.96 0.476 172 1 0.4857 164.9 5.514 64.13 0.06263 39.99 0.4748 169 1.5 0.4835 142.2 3.737 46.16 0.08796 31.73 0.4576 155.1 2 0.4751 123.8 2.85 28.84 0.116 20.17 0.4279 141.7 2.5 0.4638 108.1 2.356 11.91 0.1442 7.589 0.3851 128.2 3 0.4474 93.43 2.038 -5.352 0.1734 -6.182 0.3323 112.6 3.5 0.433 78.93 1.808 -23.21 0.2033 -21.36 0.2701 93.95 4 0.429 64.65 1.624 -41.21 0.2311 -37.08 0.2136 69.63 4.5 0.4433 48.8 1.456 -60.71 0.2561 -54.46 0.1842 35.57 5 0.4797 33.04 1.299 -79.6 0.2706 -71.5 0.1845 -0.1869 5.5 0.5308 17.84 1.145 -98.31 0.2812 -88.72 0.1949 -28.5 6 0.5849 4.304 0.9923 -117 0.28 -105.5 0.1758 -50.71 6.5 0.6311 -6.453 0.8475 -134.2 0.2682 -121.8 0.09589 -63.29 7 0.6711 -15.37 0.6847 -151.2 0.25 -136.4 0.1006 46.42 7.02 0.6718 -15.54 0.6791 -151.4 0.2488 -136.8 0.1055 47.03 7.5 0.702 -22.92 0.5296 -161.9 0.2195 -145.6 0.3269 34.85 8 0.7192 -30.47 0.4375 -163.6 0.2083 -148.2 0.5113 11.84 8.5 0.7036 -38.8 0.4401 -164 0.2316 -150.2 0.5983 -9.504 9 0.6344 -44.46 0.4975 -172.7 0.2788 -159.9 0.5515 -29.89 9.5 0.623 -48.02 0.4827 163.9 0.2918 176.7 0.4055 -20.64 10 0.6313 -59.65 0.3887 164.1 0.2573 176.4 0.5668 -27.29 10.5 0.5825 -75.16 0.445 162.5 0.3127 172.2 0.5751 -46.67 11 0.5164 -91.87 0.5292 151.8 0.3834 161.5 0.5242 -66.71 11.5 0.4614 -109.1 0.6084 136.6 0.4587 145.2 0.4551 -90.35 12 0.4244 -125.4 0.668 119 0.5192 126.1 0.3841 -118.8 12.5 0.4056 -142.1 0.6845 101.1 0.5644 107.3 0.2985 -144.4 13.5 0.385 -156.5 0.7347 84.24 0.6157 90.41 0.3366 -168.2 14 0.3726 -176 0.7055 49.21 0.6262 53.26 0.4046 138 14.5 0.3731 166.5 0.736 33.92 0.6716 36.92 0.3906 113.9 15 0.3205 148.6 0.7673 16.35 0.7162 18.91 0.3296 95.44 15.5 0.2225 132.8 0.8008 -3.142 0.7613 -1.432 0.2269 86.25 16 0.08651 165.7 0.8194 -25.57 0.7898 -24.97 0.1099 119.9 16.5 0.2734 -144.7 0.776 -51.48 0.7658 -52.01 0.2566 174.7 17 0.5265 -164 0.6454 -76.43 0.6397 -78.62 0.5016 168 17.5 0.6917 176.9 0.4937 -95.96 0.5045 -99.26 0.6825 155.3 18 0.778 164.8 0.3822 -108.9 0.3851 -112.5 0.7874 146.4 18.5 0.8257 157.3 0.3054 -118.3 0.316 -122.4 0.8485 140.4 19 0.8475 153.3 0.2549 -124.5 0.261 -128.5 0.8782 137 19.5 0.8593 151.2 0.2233 -128.9 0.2331 -134.3 0.8881 134.9 20 0.8592 150.1 0.2099 -132.6 0.2211 -137.5 0.8915 133.4 Note: Circuit layout refer to Figure 16. 7 S-Parameter Test circuit Vdd NC 13 GND 14 Vg 15 Vdd RFout 11 RFin 3 Vdd RFout 10 NC 4 NC 9 Reference Plane NC 8 Vbias 2 GND 7 NC 12 NC 5 J1 RFin Vm 1 NC 6 11612A Bias Network 45 MHZ-26.5 GHz RFgnd 16 Vg Reference Plane Top View Figure 16. S-Parameter Test circuit. 8 11612A Bias Network 45 MHZ-26.5 GHz J2 RFout S-Parameter (Vdd = 5V, Vctrl = 5V, T=25°C, unmatched 50 ohm), with L4 = 15nH, C6 = 100pF freq (GHz) S11 (dB) S11 (ang) S21 (dB) S21 (ang) S12 (dB) S12 (ang) S22 (dB) S22 (ang) 0.1 0.2568 161.2 13.78 175.8 0.009444 101.7 0.2746 -34.24 0.2 0.1672 164.7 15.64 160.5 0.01771 93.57 0.4101 -66.49 0.3 0.1339 -153.1 16.74 141.1 0.02985 83.91 0.5896 -96.1 0.4 0.2804 -144.2 14.9 117.7 0.03976 67.74 0.6465 -126.2 0.5 0.3701 -158.3 12.01 102.7 0.04382 57.22 0.6219 -144.3 0.6 0.4127 -169.5 9.849 92.68 0.04783 54.35 0.5948 -155.9 0.7 0.434 -178.1 8.307 85.46 0.05033 50.56 0.5741 -164.1 0.8 0.4476 174.6 7.201 79.36 0.05531 48.96 0.5571 -170.5 0.9 0.456 168.5 6.349 74.28 0.05979 46.76 0.5467 -176 1 0.4621 162.9 5.684 69.52 0.06393 44.7 0.537 179.6 1.5 0.474 140.1 3.742 49.18 0.0896 34.64 0.5022 161.6 2 0.4713 122.3 2.861 31.48 0.1158 22.85 0.4649 146.8 2.5 0.4595 106.4 2.36 14.01 0.1449 9.838 0.4205 132.1 3 0.4391 93.36 2.029 -3.058 0.1725 -3.918 0.3676 116.7 3.5 0.43 78.17 1.806 -21.48 0.2036 -19.57 0.301 96.73 4 0.416 64.62 1.611 -40.19 0.2316 -35.9 0.2393 71.35 4.5 0.4298 53.2 1.464 -57 0.2534 -51.13 0.2033 41.6 5 0.4771 36.4 1.298 -78.1 0.2707 -70.57 0.1884 1.547 5.5 0.529 21.01 1.14 -97.23 0.2796 -87.99 0.185 -29.27 6 0.5852 7.048 0.9772 -116.3 0.2741 -105 0.1468 -54.03 6.5 0.6344 -4.632 0.8161 -134.1 0.2564 -121.2 0.04241 -50.92 7 0.6793 -14.22 0.6446 -149.4 0.2351 -133.6 0.1712 53.21 7.5 0.7121 -22.65 0.4994 -157.8 0.2102 -140.4 0.3948 31.35 8 0.7198 -30.56 0.4489 -158.4 0.2158 -142.5 0.5287 6.43 8.5 0.7155 -37.25 0.3997 -161.6 0.2157 -147.8 0.6248 -6.672 9 0.6895 -44.03 0.4167 -163.8 0.242 -151.7 0.6518 -21.27 9.5 0.6597 -51.88 0.4662 -169.9 0.287 -159.2 0.6371 -34.6 10 0.6101 -61.74 0.5308 179.8 0.3463 -169.5 0.596 -47.68 10.5 0.5423 -73.63 0.6054 167.2 0.4186 176.2 0.5318 -63.41 11 0.4595 -87.08 0.6852 149.4 0.4918 159.2 0.4226 -81.47 11.5 0.404 -98.92 0.7138 132 0.5402 140.2 0.359 -100.4 12 0.3637 -116.4 0.744 115.6 0.5821 121.9 0.3031 -125.5 12.5 0.3447 -131.9 0.767 97.51 0.623 103.1 0.2751 -154.6 13 0.3432 -151 0.784 79.81 0.6501 85.67 0.2787 176.6 13.5 0.3322 -171 0.7906 61.96 0.6802 67.27 0.3048 151.7 14 0.2999 170.4 0.776 43.77 0.6889 48.08 0.3259 133.6 14.5 0.2504 155.7 0.7477 27.31 0.6811 30.17 0.3555 116 15 0.211 147.3 0.7599 13.03 0.7052 15.74 0.3124 93.28 15.5 0.1448 140 0.8115 -5.748 0.7699 -3.878 0.1677 81.45 16 0.1042 -155.1 0.8283 -28.92 0.8003 -28.21 0.09555 169 16.5 0.3274 -145.4 0.769 -55.06 0.7618 -55.63 0.3365 -176.2 17 0.5576 -166.2 0.6286 -79.44 0.6235 -81.61 0.5759 169.1 17.5 0.7072 175.6 0.4753 -97.98 0.4856 -101.6 0.7331 155.1 18 0.7852 164.1 0.3653 -109.8 0.3679 -113.4 0.8093 146.1 18.5 0.8251 157 0.2913 -117.8 0.3018 -122.1 0.8536 140.4 19 0.844 153.6 0.2531 -123 0.2596 -127.1 0.877 137.2 19.5 0.8577 151.5 0.2235 -128.5 0.2327 -133.7 0.8891 135.3 20 0.8584 150.2 0.2104 -132 0.2192 -137.1 0.8957 133.5 Note: Circuit layout refer to Figure 17, with L4 = 15 nH, C6 = 100pF 9 S-Parameter (Vdd = 5V, Vctrl = 5V, T=25°C,unmatched 50 ohm), with L4 = 100nH, C6 = 1nF freq (GHz) S11 (dB) S11 (ang) S21 (dB) 0.1 0.5555 10.29 35.34 174.2 0.01595 110.7 0.4953 -65.36 0.2 0.5652 -85.53 27.11 125.1 0.02909 57.57 0.5617 -125.6 0.3 0.5267 -124 18.44 106.2 0.03285 48.87 0.5286 -148 0.4 0.508 -144.3 13.83 95.53 0.03656 46.17 0.5126 -160.7 0.5 0.4988 -157.9 11.03 88.31 0.04119 45.19 0.5023 -168.4 0.6 0.4939 -168.1 9.165 82.26 0.04457 44.09 0.4972 -174.9 0.7 0.491 -176.3 7.837 77.29 0.04883 43.54 0.49 -179.7 0.8 0.4886 176.9 6.869 72.51 0.05316 42.65 0.4852 176.2 0.9 0.4882 170.7 6.104 68.36 0.05725 41.06 0.4794 172.2 1 0.4864 164.6 5.426 63.68 0.06378 39.49 0.474 168.2 1.5 0.4837 142.8 3.708 45.42 0.08746 30.28 0.4467 153.3 2 0.4758 124.9 2.815 27.12 0.1145 18.41 0.3984 138.4 2.5 0.4643 110.1 2.305 8.764 0.1405 3.984 0.3289 123.2 3 0.4577 97.19 1.953 -9.91 0.161 -10.33 0.2475 106.1 3.5 0.4543 83.77 1.654 -30 0.1863 -26.26 0.1208 86.57 4 0.4629 71.65 1.32 -49.22 0.1997 -44.31 0.03653 -178 4.5 0.5275 55.55 1.034 -60.21 0.1803 -56.57 0.1689 165.4 5 0.5184 35.23 1.154 -72.72 0.2383 -64.62 0.1434 60.22 5.5 0.5989 22.32 0.8585 -95.63 0.2059 -84.56 0.1319 130.6 6 0.657 5.12 0.7102 -103.2 0.2058 -88.56 0.303 76.52 6.5 0.6875 -8.43 0.6763 -112.5 0.228 -98.33 0.4378 37.31 7 0.7137 -18.74 0.6198 -123.6 0.2438 -109.7 0.5354 14.7 7.5 0.7241 -27.56 0.5931 -133.6 0.2581 -120.6 0.602 -4.645 8 0.718 -34.72 0.5767 -143.5 0.2772 -131.7 0.619 -19.73 8.5 0.691 -40.68 0.574 -156 0.2962 -145 0.5626 -31.17 9 0.681 -46.15 0.5259 -162 0.294 -151.2 0.597 -34.04 9.5 0.6393 -53.84 0.585 -170.5 0.347 -160.2 0.5657 -48.44 10 0.5788 -62.6 0.6443 176.5 0.4063 -172.9 0.4858 -60.16 10.5 0.5028 -72.36 0.6962 161.6 0.4677 171.4 0.3994 -71.89 11 0.4265 -84.11 0.7372 145.1 0.5198 155.6 0.3199 -85.13 11.5 0.3683 -97.04 0.7685 128.3 0.574 137.7 0.2552 -104.2 12 0.335 -117 0.7789 112.7 0.6045 120.7 0.2232 -123.8 12.5 0.291 -137.5 0.8156 95.6 0.6712 102.2 0.2332 -159.9 13 0.2902 -156.5 0.8394 77.54 0.7033 83.72 0.2479 164.5 13.5 0.2995 -175.6 0.8415 59.73 0.728 65.05 0.2676 137.2 14 0.2998 166.6 0.8388 42.03 0.7442 46.45 0.2708 117.2 14.5 0.2813 150.2 0.8378 24.27 0.7641 27.53 0.2565 102 15 0.2247 137 0.8449 5.782 0.7925 8.6 0.1958 85.32 15.5 0.1216 146.5 0.8498 -15 0.8132 -13.14 0.06727 93.91 16 0.1879 -152.9 0.8167 -38.64 0.7948 -37.8 0.1754 -166.3 16.5 0.4125 -159.5 0.7132 -62.79 0.711 -63.33 0.4122 -179 17 0.6075 -175.1 0.5777 -84.42 0.5747 -86.65 0.618 166.5 17.5 0.7305 170.5 0.4383 -100.8 0.4495 -104.4 0.7513 153.2 18 0.795 161.6 0.3427 -111.1 0.3447 -114.9 0.8168 144.9 18.5 0.8315 156 0.2809 -119.2 0.2901 -123.2 0.8596 139.9 19 0.8501 152.7 0.2379 -124.7 0.2442 -128.7 0.8821 136.6 19.5 0.8572 150.8 0.2114 -129.4 0.2222 -134.3 0.8914 134.5 20 0.8568 149.6 0.2022 -132.8 0.2114 -137.5 0.8967 133.1 Note: Circuit layout refer to Figure 17, with L4 = 100 nH, C6 = 1nF 10 S21 (ang) S12 (dB) S12 (ang) S22 (dB) S22 (ang) S-Parameter Test circuit (400MHz – 700 MHz) Vctrl Vdd L4 = 15nH C10 = 100pF NC 12 Vbias 2 Vdd RFout 11 RFin 3 Vdd RFout 10 NC 8 9 GND 7 NC 4 NC 6 NC Reference Plane Reference Plane TOP VIEW Figure 17. S-Parameter Test Circuit. 11 11612A Bias Network 45 MHZ-26.5 GHz NC 13 GND 14 Vg 15 Vm 1 NC 5 J1 RFin RFgnd 16 Rbias =0 ohm C6 = 100pF J2 RFout Demo Board (400MHz to 700MHz) Vctrl Vdd L4 C7 R2 C5 R1 L3 Vm NC 1 12 Vdd RFout Vbias 2 C1 J1 RFin C4 13 NC 14 GND 15 Vg C3 16 RFgnd C6 11 C2 J2 RFout Vdd RFout RFin 3 10 NC NC 4 9 8 NC 7 GND 6 NC NC L1 5 L2 Top View Figure 18. Demo board and application schematic (400MHz to 700 MHz) Demo Board Part List (400MHz to 700MHz) Circuit Symbol Value Part Number C1 10 pF Murata GRM155 series C2 10p Murata GRM155 series C3 1 nF Murata GRM155 series C4 100 nF Murata GRM155 series C5 1 nF Murata GRM155 series C6 1 nF Murata GRM155 series C7 1 nF Murata GRM155 series J1 142-0701-841 Johnson edge launch SMA female J2 142-0701-841 Johnson edge launch SMA female L1 22 nH Toko LL1005 series L2 15 nH Toko LL1005 series L3 100 nH Toko LL1005 series L4 100 nH Toko LL1005 series Q1 Mga30116 R1 0R Figure 19. Demo board Layout for 400MHz to 700MHz R2 390 R Notes: 1. Recommended PCB material is 10 mils Rogers RO4350, with FR4 backing for mechanical strength. 2. Suggested component values may vary according to layout and PCB material. 12 MGA-30116 Typical Performance (400MHz to 700MHz) 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -40°C 25°C 85°C S12(dB) S11(dB) TA = +25°C, Vdd = 5V, Vctrl =5V, Input Signal=CW unless stated otherwise. 0.40 0.45 0.50 0.55 0.60 Frequency (GHz) 0.65 0.70 0.50 0.55 0.60 Frequency (GHz) 0.65 0.70 20 18 16 0.45 0.50 0.55 0.60 Frequency (GHz) 0.65 14 12 -40°C 25°C 85°C 10 -40°C 25°C 85°C 8 6 0.70 Figure 22. Over Temperature S22 vs Frequency 0.4 0.45 0.5 0.55 0.6 Frequency (GHz) 0.65 0.7 Figure 23. Over Temperature Gain vs Frequency 31 46 30 44 42 29 28 OiP3 (dB) P1dB (dB) 0.45 Figure 21. Over Temperature S12 vs Frequency 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 0.40 27 26 -40°C 25°C 85°C 25 0.4 0.45 0.5 0.55 Frequency (GHz) Figure 24. Over Temperature P1dB vs Frequency 0.6 0.65 40 38 36 34 -40°C 25°C 85°C 32 24 13 -40°C 25°C 85°C 0.40 Gain (dB) S22(dB) Figure 20. Over Temperature S11 vs Frequency -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 0.7 30 0.4 0.45 0.5 0.55 Frequency (GHz) Figure 25. Over Temperature OIP3 vs Frequency 0.6 0.65 0.7 PCB Layout and Stencil Design 0.490 Chamfer 0.24 0.325 0.500 Chamfer 0.192 Chamfer 0.06 0.500 ∅0.260 0.560 1.240 1.550 0.210 0.325 0.230 0.500 0.490 0.350 1.240 1.550 PCB Land Pattern (Top View) Stencil Outline 0.500 0.230 1.240 1.550 0.210 0.360 1.240 1.550 Combined PCB & Stencil Layouts Notes: 1. All dimensions are in milimeters. Part Number Ordering Information Product Family Part Number No. of Devices Container MGA-30116-TR1G 1000 MGA-30116-TR2G 3000 MGA-30116-BLKG 100 Frequency Band 7” Reel Output Power 700MHz-1GHz 1.7- 2.7GHz 3.3-3.9GHz 13” Reel 0.5W MGA-30116 MGA-30216 MGA-30316 1W ALM-31122 ALM-31222 ALM-31322 2W ALM-32120 ALM-32220 ALM-32320 antistatic bag Note: MGA-30116 operates from 400MHz to 1GHz. 14 Package Dimensions 0.20 Ref Pin 1 Dot by marking PIN #1 IDENTIFICATION CHAMFER 0.30 X 45° 1.55±0.05 Exp.DAP 3.00 ± 0.10 0.40±0.05 0.50 Bsc 30116 Y Y WW XXXX 3.00 ± 0.10 1.55±0.05 Exp.DAP 0.23±0.05 0.00 ± 0.05 1.50 Ref. 0.85 ± 0.05 TOP VIEW BOTTOM VIEW SIDE VIEW Notes: 1. All dimensions are in milimeters 2. Dimensions are inclusive of plating 3. Dimensions are exclusive of mold flash and metal burr Device Orientation REEL USER FEED DIRECTION CARRIER TAPE 30116 YYXX XXXX 30116 YYXX XXXX 30116 YYXX XXXX TOP VIEW USER FEED DIRECTION END VIEW COVER TAPE Tape Dimensions 2.0 ±0.1[1] 0.3 ±0.05 4.0 ±0.1[2] 1.75 ±0.1 1.55 ±0.05 5.5 ±0.1[1] CL 3.3 ±0.1 1.6 ±0.1 12.0 ±0.3 R 0.3 Typical 1.55 ±0.1 8.0 ±0.1 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ± 0.20 3. All dimensions in millimeter unless otherwise stated 15 3.3±0.1 Reel Dimensions - 7 inch 6.25mm EMBOSSED LETTERS LETTERING THICKNESS: 1.6mm SLOT HOLE "a" SEE DETAIL "X" Ø178.0±0.5 SLOT HOLE "b" FRONT BACK 6 PS SLOT HOLE(2x) 180° APART. 6 PS RECYCLE LOGO SLOT HOLE "a": 3.0±0.5mm(1x) SLOT HOLE "b": 2.5±0.5mm(1x) FRONT VIEW 45° +0.5 Ø13.0 -0.2 Ø20.2 MIN. ° R10.65 120 65° 1.5 MIN. +1.5* 12.4 -0.0 R5.2 BACK VIEW Ø178.0±0.5 Ø51.2±0.3 18.0* MAX. SEE DETAIL "Y" DETAIL "X" 3.5 DETAIL "Y" (Slot Hole) 1.0 Ø55.0±0.5 45° EMBOSSED RIBS RAISED: 0.25mm, WIDTH: 1.25mm 16 BACK Ø178.0±0.5 FRONT Reel Dimensions - 13 inch 11 12 1 2 3 4 0 2 10 9 7 6 5 DATE CODE 12MM 8 EMBOSSED LETTERING 16.0mm HEIGHT x MIN. 0.4mm THICK. Ø329.0±1.0 HUB Ø100.0±0.5 6 PS 02 12 12 10 911 876534 MP N CPN EMBOSSED LETTERING 7.5mm HEIGHT EMBOSSED LETTERING 7.5mm HEIGHT 1.5 (MI N.) FRONT VIEW EMBOSSED LINE (2x) 89.0mm LENGTH LINES 147.0mm AWAY FROM CENTER POINT +0.5 -0.2 20.2(MIN.) Ø13.0 11.9-15.4** +2.0* 12.4 -0.0 Ø16.0 ESD LOGO 6 PS RECYCLE LOGO Detail "X" SEE DETAIL "X" Ø100.0±0.5 Ø329.0±1.0 6 PS R19.0±0.5 BACK VIEW SLOT 5.0±0.5(3x) Ø12.3±0.5(3x) For product information and a complete list of distributors, please go to our web site: 18.4 MAX.* www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-1063EN - March 13, 2012