Freescale MCF52252CAF66 Coldfire microcontroller Datasheet

Document Number: MCF52259
Rev. 2, 8/2009
MCF52259
LQFP–144
20 mm x 20 mm
MCF52259 ColdFire
Microcontroller
The MCF52259 microcontroller family (MCF52252,
MCF52254, MCF52255, MCF52256, MCF52258, and
MCF52259 devices) is a member of the ColdFire® family of
reduced instruction set computing (RISC) microprocessors.
This document provides an overview of the 32-bit MCF52259
microcontroller, focusing on its highly integrated and diverse
feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 80 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to
512 Kbytes of flash memory and 64 Kbytes of static random
access memory (SRAM). On-chip modules include:
• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at
80 MHz running from internal flash memory with
Enhanced Multiply Accumulate (MAC) Unit and hardware
divider
• Cryptography Acceleration Unit (CAU)
• Fast Ethernet controller (FEC)
• Mini-FlexBus external bus interface available on 144 pin
packages
• Universal Serial Bus On-The-Go (USBOTG)
• USB Transceiver
• FlexCAN controller area network (CAN) module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Two inter-integrated circuit (I2C™) bus interface modules
• Queued serial peripheral interface (QSPI) module
• Eight-channel 12-bit fast analog-to-digital converter
(ADC) with simultaneous sampling
• Four-channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
MAPBGA–144
13 mm x 13 mm
•
•
•
•
•
•
•
•
(PWM), pulse-code modulation (PCM), and pulse
accumulation
Eight-channel/Four-channel, 8-bit/16-bit pulse width
modulation timer
Two 16-bit periodic interrupt timers (PITs)
Real-time clock (RTC) module with 32 kHz crystal
Programmable software watchdog timer
Secondary watchdog timer with independent clock
Interrupt controller capable of handling 57 sources
Clock module with 8 MHz on-chip relaxation oscillator
and integrated phase-locked loop (PLL)
Test access/debug port (JTAG, BDM)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
LQFP–100
14 mm x 14 mm
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Freescale Semiconductor
Data Sheet: Technical Data
1
2
Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .26
2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .28
2.5 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .29
2.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30
2.8 Clock Source Electrical Specifications . . . . . . . . . . . . .31
2.9 USB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.10 Mini-FlexBus External Interface Specifications . . . . . . .32
3
4
2.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . .
2.12 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . .
2.13 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 I2C Input/Output Timing Specifications . . . . . . . . . . . .
2.15 Analog-to-Digital Converter (ADC) Parameters. . . . . .
2.16 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . .
2.17 DMA Timers Timing Specifications . . . . . . . . . . . . . . .
2.18 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . .
2.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . .
2.20 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
35
36
37
38
39
40
40
40
43
44
45
MCF52259 ColdFire Microcontroller, Rev. 2
2
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Table of Contents
1
Family Configurations
Table 1. MCF52259 Family Configurations
Module
52252
52254
52255
52256
52258
52259
Version 2 ColdFire Core with eMAC
(Enhanced multiply-accumulate unit) and CAU
(Cryptographic acceleration unit)
•
•
•
•
•
•
System Clock
up to 66 or 80 MHz1
Performance (Dhrystone 2.1 MIPS)
up to
80 MHz1
up to 66 or 80 MHz1
up to
80 MHz1
up to 63 or 76
Flash
256 KB
512 KB
512 KB
256 KB
512 KB
512 KB
Static RAM (SRAM)
32 KB
64 KB
64 KB
32 / 64 KB
64 KB
64 KB
Two Interrupt Controllers (INTC)
•
•
•
•
•
•
Fast Analog-to-Digital Converter (ADC)
•
•
•
•
•
•
USB On-The-Go (USB OTG)
•
•
•
•
•
•
Mini-FlexBus external bus interface
—
—
—
•
•
•
Fast Ethernet Controller (FEC)
•
•
•
•
•
•
Random Number Generator and
Cryptographic Acceleration Unit (CAU)
—
—
•
—
—
•
Varies
Varies
•
Varies
Varies
•
Four-channel Direct-Memory Access (DMA)
•
•
•
•
•
•
Software Watchdog Timer (WDT)
•
•
•
•
•
•
Secondary Watchdog Timer
•
•
•
•
•
•
Two-channel Periodic Interrupt Timer (PIT)
2
2
2
2
2
2
Four-Channel General Purpose Timer (GPT)
•
•
•
•
•
•
32-bit DMA Timers
4
4
4
4
4
4
QSPI
•
•
•
•
•
•
UART(s)
3
3
3
3
3
3
2
2
2
2
2
2
Eight/Four-channel 8/16-bit PWM Timer
•
•
•
•
•
•
General Purpose I/O Module (GPIO)
•
•
•
•
•
•
Chip Configuration and Reset Controller Module
•
•
•
•
•
•
Background Debug Mode (BDM)
•
•
•
•
•
•
JTAG - IEEE 1149.1 Test Access Port
•
•
•
•
•
•
FlexCAN 2.0B Module
I
2C
Package
1
100 LQFP
144 LQFP or 144 MAPBGA
66 MHz = 63 MIPS; 80 MHz = 76 MIPS
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
1.1
Block Diagram
Figure 1 shows a top-level block diagram of the device. Package options for this family are described later in this document.
EzPD
EzPCK
EzPort
EzPCS
EzPQ
USB
Mini-FlexBus
Mini-FlexBus
To/From
PADI
Arbiter
Interrupt
Controllers
USB
FEC
UARTs
0–2
I2C
0–1
PITs
0–1
QSPI
4 ch DMA
DTIMs
0–3
To/From PADI
FlexCAN
Edge
Port
AN[7:0]
I2Cs
QSPI
PADI – Pin Muxing
To/From PADI
UARTs
GPTn
IRQn
FEC
DTINn/DTOUTn
CANRX
RTC
CANTX
PWMn
EzPort
JTAG/BDM
MUX
JTAG_EN
V2 ColdFire CPU
IFP
JTAG
TAP
To/From
PADI
up to 64 Kbytes
SRAM
(4K×16)×4
ADC
VRH
OEP
CAU
EMAC
up to 512Kbytes
Flash
(64K×16)×4
PMM
CCM,
Reset
PORTS
(GPIO)
RSTIN
RSTOUT
VRL
PLL
CLKGEN
EXTAL
Watchdog
Timer
RNGA
GPT
PWM
XTAL CLKOUT
Figure 1. Block Diagram
1.2
1.2.1
Features
Feature Overview
The MCF52259 family includes the following features:
•
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
MCF52259 ColdFire Microcontroller, Rev. 2
4
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
—
—
—
—
•
•
•
•
•
Up to 80 MHz processor core frequency
40 MHz or 33 MHz peripheral bus frequency
Sixteen general-purpose, 32-bit data and address registers
Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
for improved bit processing (ISA_A+)
— Enhanced Multiply-Accumulate (EMAC) unit with four 32-bit accumulators to support 16×16 → 32 or
32×32 → 48 operations
— Cryptographic Acceleration Unit (CAU)
– Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions
– Support for DES, 3DES, AES, MD5, and SHA-1 algorithms
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or
2-level trigger
On-chip memories
— Up to 64-Kbyte dual-ported SRAM on CPU internal bus, supporting core, DMA, and USB access with standby
power supply support for the first 16 Kbytes
— Up to 512 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used (except backup watchdog timer)
— Software controlled disable of external clock output for low-power consumption
FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard data and remote frames (up to 109 bits long)
– Extended data and remote frames (up to 127 bits long)
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mbit/sec
— Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as
Rx or Tx, all supporting standard and extended messages
— Unused MB space can be used as general purpose RAM space
— Listen-only mode capability
— Content-related addressing
— No read/write semaphores
— Three programmable mask registers: global for MBs 0–13, special for MB14, and special for MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— Time stamp based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller
— Full-speed / low-speed host controller
— USB 1.1 and 2.0 compliant full-speed / low speed device controller
— 16 bidirectional end points
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
•
— DMA or FIFO data stream interfaces
— Low power consumption
— OTG protocol logic
Fast Ethernet controller (FEC)
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
•
•
•
•
•
Mini-FlexBus
— External bus interface available on 144 pin packages
— Supports glueless interface with 8-bit ROM/flash/SRAM/simple slave peripherals. Can address up to 2 Mbytes of
addresses
— 2 chip selects (FB_CS[1:0])
— Non-multiplexed mode: 8-bit dedicated data bus, 20-bit address bus
— Multiplexed mode: 16-bit data and 20-bit address bus
— FB_CLK output to support synchronous memories
— Programmable base address, size, and wait states to support slow peripherals
— Operates at up to 40 MHz (bus clock) in 1:2 mode or up to 80 MHz (core clock) in 1:1 mode
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
Two I2C modules
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to three chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC)
— Eight analog input channels
— 12-bit resolution
— Minimum 1.125 μs conversion time
— Simultaneous sampling of two channels for motor control applications
— Single-scan or continuous operation
— Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit
MCF52259 ColdFire Microcontroller, Rev. 2
6
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
•
•
•
•
•
•
•
•
— Unused analog channels can be used as digital I/O
Four 32-bit timers with DMA support
— 12.5 ns resolution at 80 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input capture capability with programmable trigger edge on input pin
— Output compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or output compare
— DMA trigger capability on input capture or output compare
Four-channel general purpose timer
— 16-bit architecture
— Programmable prescaler
— Output pulse-widths variable from microseconds to seconds
— Single 16-bit input pulse accumulator
— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
— One dual-mode pulse accumulation channel
Pulse-width modulation timer
— Support for PCM mode (resulting in superior signal quality compared to conventional PWM)
— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
— Programmable period and duty cycle
— Programmable enable/disable for each channel
— Software selectable polarity for each channel
— Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached
(PWM counter reaches zero) or when the channel is disabled.
— Programmable center or left aligned outputs on individual channels
— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
— Emergency shutdown
Two periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down
Real-Time Clock (RTC)
— Maintains system time-of-day clock
— Provides stopwatch and alarm interrupt functions
— Standby power supply (Vstby) keeps the RTC running when the system is shut down
Software watchdog timer
— 32-bit counter
— Low-power mode support
Backup watchdog timer (BWT)
— Independent timer that can be used to help software recover from runaway code
— 16-bit counter
— Low-power mode support
Clock generation features
— Twelve to 48 MHz crystal, 8 MHz on-chip trimmed relaxation oscillator, or external oscillator reference options
— Two to 10 MHz reference frequency for normal PLL mode with a pre-divider programmable from 1 to 8
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
•
•
•
•
•
•
— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator
— Low power modes supported
— 2n (n ≤ 0 ≤ 15) low-power divider for extremely low frequency operation
Interrupt controller
— Uniquely programmable vectors for all interrupt sources
— Fully programmable level and priority for all peripheral interrupt sources
— Seven external interrupt signals with fixed level and priority
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low-power modes
DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4×32-bit)
burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle-steal support
— Software-programmable DMA requests for the UARTs (3) and 32-bit timers (4)
— Channel linking support
Reset
— Separate reset in and reset out signals
— Seven sources of reset:
– Power-on reset (POR)
– External
– Software
– Watchdog
– Loss of clock / loss of lock
– Low-voltage detection (LVD)
– JTAG
— Status flag indication of source of last reset
Chip configuration module (CCM)
— System configuration during reset
— Selects one of six clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
General purpose I/O interface
— Up to 56 bits of general purpose I/O on 100-pin package
— Up to 96 bits of general purpose I/O on 144-pin package
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
MCF52259 ColdFire Microcontroller, Rev. 2
8
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
1.2.2
V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage
instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is
a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP).
The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage
(AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire instruction set architecture revision A+ with support for a separate user stack pointer
register and four new instructions to assist in bit processing. Additionally, the core includes the enhanced multiply-accumulate
(EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic pipeline, optimized
for 32x32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and
unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC
provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
1.2.3
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator
development tools. Through a standard debug interface, access to debug information and real-time tracing capability is provided
on 144-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit
emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register,
a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the
dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint
registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or
dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
This device implements revision B+ of the ColdFire Debug Architecture.
The processor’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be
serviced while processing a debug interrupt event. This ensures the system continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports.
These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining
processor activity at the CPU’s clock rate. The device includes a new debug signal, ALLPST. This signal is the logical AND of
the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 144-pin packages. However, every product features the dedicated debug
serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.4
JTAG
The processor supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action
Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and
three test registers (a 1-bit bypass register, a boundary-scan register, and a 32-bit ID register). The boundary scan register links
the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system
logic.
The device implementation can:
•
•
•
•
•
Perform boundary-scan operations to test circuit board electrical continuity
Sample system pins during operation and transparently shift out the result in the boundary scan register
Bypass the device for a given circuit board test by effectively reducing the boundary-scan register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
9
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
1.2.5
1.2.5.1
On-Chip Memories
SRAM
The dual-ported SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a
single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. This
memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is
physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or
memory-referencing commands from the debug module.
The SRAM module is also accessible by the DMA, FEC, and USB. The dual-ported nature of the SRAM makes it ideal for
implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of
the SRAM to maximize system performance.
1.2.5.2
Flash Memory
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local
bus. The CFM is constructed with four banks of 64-Kbyte×16-bit flash memory arrays to generate 512 Kbytes of 32-bit flash
memory. These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash
memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring
an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller
that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for
all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be
programmed via the EzPort, which is a serial flash memory programming interface that allows the flash memory to be read,
erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips.
1.2.6
Cryptographic Acceleration Unit
The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the CAU is a coprocessor
tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of
software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms.
Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules
supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost.
1.2.7
Power Management
The device incorporates several low-power modes of operation entered under program control and exited by several external
trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply
voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt
condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the
chip falls below the standby battery voltage.
1.2.8
FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN
protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh
EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers.
MCF52259 ColdFire Microcontroller, Rev. 2
10
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
1.2.9
Mini-FlexBus
A multi-function external bus interface called the Mini-FlexBus is provided on the device with basic functionality of interfacing
to slave-only devices with a maximum slave bus frequency up to 40 MHz in 1:2 mode and 80 MHz in 1:1 mode. It can be
directly connected to the following asynchronous or synchronous devices with little or no additional circuitry:
•
•
•
•
External ROMs
Flash memories
Gate-array logic
Other simple target (slave) devices
The Mini-FlexBus is a subset of the FlexBus module found on higher-end ColdFire microprocessors. The Mini-FlexBus
minimizes package pin-outs while maintaining a high level of configurability and functionality.
1.2.10
USB On-The-Go Controller
The device includes a Universal Serial Bus On-The-Go (USB OTG) dual-mode controller. USB is a popular standard for
connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host PCs.
The OTG supplement to the USB specification extends USB to peer-to-peer application, enabling devices to connect directly
to each other without the need for a PC. The dual-mode controller on the device can act as a USB OTG host and as a USB
device. It also supports full-speed and low-speed modes.
1.2.11
Fast Ethernet Controller (FEC)
The Ethernet media access controller (MAC) supports 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver
interface and transceiver function are required to complete the interface to the media. The FEC supports three different standard
MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FECs supports the 10/100 Mbps MII,
and the 10 Mbps-only 7-wire interface.
1.2.12
UARTs
The device has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock,
eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O
functions.
1.2.13
I2C Bus
The processor includes two I2C modules. The I2C bus is an industry-standard, two-wire, bidirectional serial bus that provides
a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for
applications requiring occasional communications over a short distance between many devices.
1.2.14
QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability.
It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.
1.2.15
Fast ADC
The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding
separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing. Signals on the
SYNCA and SYNCB pins initiate an ADC conversion.
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
11
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly
until manually stopped.
The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight
channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a
scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This
configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low
threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.
1.2.16
DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the device. Each
module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to
operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected,
it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual
timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode.
Timer events may optionally cause interrupt requests or DMA transfers.
1.2.17
General Purpose Timer (GPT)
The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a
seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare.
Additionally, channel three, can be configured as a pulse accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
The input capture and output compare functions allow simultaneous input waveform measurements and output waveform
generation. The input capture function can capture the time of a selected transition edge. The output compare function can
generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a
gated time accumulator.
1.2.18
Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal
processor intervention. Each timer can count down from the value written in its PIT modulus register or it can be a free-running
down-counter.
1.2.19
Real-Time Clock (RTC)
The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm, and interrupt
functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions
along with an alarm interrupt.
1.2.20
Pulse-Width Modulation (PWM) Timers
The device has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated
counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to
100%. The timer supports PCM mode, which results in superior signal quality when compared to that of a conventional PWM.
The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. For
MCF52259 ColdFire Microcontroller, Rev. 2
12
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to
form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.
1.2.21
Software Watchdog Timer
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running
down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
1.2.22
Backup Watchdog Timer
The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from
runaway code. This timer is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown. The backup watchdog timer can be clocked by either the relaxation oscillator or the system
clock.
1.2.23
Phase-Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced
frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL,
crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are
powered by the normal supply pins, VDD and VSS.
1.2.24
Interrupt Controllers (INTCn)
The device has two interrupt controllers that supports up to 128 interrupt sources. There are 56 programmable sources, 49 of
which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for
software interrupt requests.
1.2.25
DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor
intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered
by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.
1.2.26
Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what
caused the last reset. There are seven sources of reset:
•
•
•
•
•
•
•
External reset input
Power-on reset (POR)
Watchdog timer
Phase locked-loop (PLL) loss of lock / loss of clock
Software
Low-voltage detector (LVD)
JTAG
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags
indicating the last source of reset and a control bit for software assertion of the RSTO pin.
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
13
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
1.2.27
GPIO
Nearly all pins on the device have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all
eight bits. Each port has registers that configure, monitor, and control the port pin.
1.2.28
Part Numbers and Packaging
This product is RoHS-compliant. Refer to the product page at freescale.com or contact your sales office for up-to-date RoHS
information.
Table 2. Orderable Part Number Summary
Freescale Part
Number
MCF52252AF80
FlexCAN
Encryption
Speed
(MHz)
—
—
80
MCF52252CAF66
•
—
66
MCF52254AF80
—
—
80
•
—
66
MCF52255CAF80
•
•
80
MCF52256AG80
—
—
80
MCF52256CVN66
•
•
SRAM
(Kbytes)
Package
256
32
100 LQFP
Temp range
(°C)
0 to +70
-40 to +85
0 to +70
512
MCF52254CAF66
MCF52256CAG66
Flash
(Kbytes)
64
100 LQFP
-40 to +85
512
64
100 LQFP
32
-40 to +85
0 to +70
144 LQFP
—
66
64
-40 to +85
256
—
66
64
-40 to +85
144 MAPBGA
MCF52256VN80
—
—
80
MCF52258AG80
—
—
80
MCF52258CAG66
MCF52258CVN66
•
•
32
0 to +70
0 to +70
144 LQFP
—
66
-40 to +85
512
—
64
66
-40 to +85
144 MAPBGA
MCF52258VN80
—
—
MCF52259CAG80
•
•
MCF52259CVN80
•
•
MCF52268AG80
—
—
80
80
80
MCF52268VN80
—
0 to +70
512
512
144 LQFP
-40 to +85
144 MAPBGA
-40 to +85
144 LQFP
0 to +70
144 MAPBGA
0 to +70
64
64
—
MCF52259 ColdFire Microcontroller, Rev. 2
14
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TRST
TDI
TDO
ALLPST
TCLK
JTAG_EN
FB_RW
FB_D3
FB_D2
VDD
VSS
FB_D1
FB_D0
FB_CS0
FB_A4
FB_A3
FB_A2
FB_A1
FB_A0
ICOC3
VDD
VSS
UCTS1
UTXD1
URXD1
URTS1
TIN2
AN0
AN1
AN2
AN3
VSSA
VRL
VRH
CLKMOD1
CLKMOD0
RSTOUT
RSTIN
FB_D5
FB_D6
FB_D7
FB_OE
FB_A15
VDD
VSS
FB_A16
FB_A17
FB_A18
FB_A19
IRQ3
IRQ5
FEC_RXD3
FEC_RXD2
VDD
VSS
FEC_RXD1
FEC_RXD0
FEC_RXDV
FEC_RXCLK
FEC_RXER
FEC_TXER
FEC_TXCLK
FEC_TXEN
VDD
VSS
FEC_TXD0
FEC_TXD1
FEC_TXD2
FEC_TXD3
FEC_COL
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
Figure 2 shows the pinout configuration for the 144 LQFP.
FB_D4
1
108
FEC_CRS
FB_A14
2
107
VDDPLL
FB_A13
3
106
EXTAL
FB_A12
4
105
XTAL
FB_A11
5
104
VSSPLL
FB_A10
6
103
IRQ1
VDD
7
102
URXD2
VSS
8
101
UTXD2
TEST
9
100
VDD
RCON
10
99
VSS
TIN0
11
98
URTS2
TIN1
RTC_EXTAL
12
97
UCTS2
13
96
IRQ7
RTC_XTAL
14
95
ICOC2
UCTS0
15
94
ICOC1
UTXD0
16
93
ICOC0
URXD0
17
92
VDD
URTS0
18
91
VSS
TIN3
19
90
PST0
VDD
20
89
PST1
VSS
21
88
PST2
PCS3
22
87
PST3
PCS2
23
86
DDATA3
QSDI
24
85
DDATA2
QSD0
25
84
DDATA1
SCK
26
83
DDATA0
PCS0
27
82
VSSUSB
SCL
28
81
USB_DP
USB_DM
SDA
29
80
VDD
30
79
VDDUSB
VSS
31
78
VSTBY
FB_A9
32
77
AN4
FB_A8
33
76
AN5
FB_A7
34
75
AN6
FB_A6
35
74
AN7
FB_A5
36
73
VDDA
Figure 2. 144 LQFP Pin Assignment
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
15
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
37
TMS
•
FB_ALE
Family Configurations
VDD
VSS
TEST
RCON
TIN0
TIN1
RTC_EXTAL
RTC_XTAL
UCTS0
UTXD0
URXD0
URTS0
TIN3
VDD
VSS
PCS3
PCS2
QSDI
QSDO
SCK
PCS0
SCL
SDA
VDD
VSS
16
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CLKMOD1
CLKMOD0
RSTOUT
RSTIN
IRQ3
IRQ5
FEC_RXD3
FEC_RXD2
VDD
VSS
FEC_RXD1
FEC_RXD0
FEC_RXDV
FEC_RXCLK
FEC_RXER
FEC_TXER
FEC_TXCLK
FEC_TXEN
VDD
VSS
FEC_TXD0
FEC_TXD1
FEC_TXD2
FEC_TXD3
FEC_COL
Figure 3 shows the pinout configuration for the 100 LQFP.
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
FEC_CRS
VDDPLL
EXTAL
XTAL
VSSPLL
IRQ1
URXD2
UTXD2
VDD
VSS
URTS2
UCTS2
IRQ7
ICOC2
ICOC1
ICOC0
VSSUSB
USB_DP
USB_DM
VDDUSB
VSTBY
AN4
AN5
AN6
AN7
Figure 3. 100 LQFP Pin Assignments
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
TMS
TRST
TDI
TDO
ALLPST
TCLK
JTAG_EN
VDD
VSS
ICOC3
VDD
VSS
UCTS1
UTXD1
URXD1
URTS1
TIN2
AN0
AN1
AN2
AN3
VSSA
VRL
VRH
VDDA
Family Configurations
Figure 4 shows the pinout configuration for the 144 MAPBGA.
1
2
3
4
5
6
7
8
9
10
11
12
A
VSS
RSTOUT
RSTIN
FB_D6
FB_D7
IRQ3
IRQ5
FEC_
RXD0
FEC_
RXER
FEC_
TXEN
FEC_
TXD3
VSS
B
TEST
FB_A14
FB_D4
FB_D5
FB_OE
FB_A19
FEC_
RXD1
FEC_
RXCLK
FEC_
TXCLK
FEC_
TXD2
C
TIN1
FB_A12
FB_A13
FB_A15
FB_A16
FB_A18
FEC_
RXD2
FEC_
RXDV
FEC_
TXD1
URXD2
VDDPLL
EXTAL
C
D
RTC_
EXTAL
TIN0
FB_A11
FB_A17
FEC_
RXD3
FEC_
TXER
FEC_
TXD0
UTXD2
VSSPLL
XTAL
D
E
RTC_
XTAL
UCTS0
FB_A10
RCON
VDD
VDD
VDD
VDD
IRQ1
URTS2
UCTS2
IRQ7
E
F
UTXD0
URXD0
URTS0
TIN3
VDD
VSS
VSS
VSS
PST3
DDATA0
DDATA1
ICOC0
F
G
QSDO
QSDI
PCS2
PCS3
VDD
VSS
VSS
VSS
DDATA3
PST2
PST1
PST0
G
H
SCL
SDA
SCK
PCS0
VDD
VDD
VDD
VSS
VSSUSB
DDATA2
USB_DM
USB_DP
H
J
FB_A6
FB_A7
FB_A9
FB_A8
FB_D0
FB_A3
VDD
TIN2
VDDUSB
ICOC2
ICOC1
VSTBY
J
K
TMS
TRST
FB_ALE
FB_A5
FB_D2
FB_A4
UCTS1
UTXD1
AN3
AN6
AN4
AN5
K
L
TDI
TDO
ALLPST
FB_D3
FB_D1
FB_A1
FB_A0
URXD1
AN2
VRH
VDDA
AN7
L
M
VSS
JTAG_
EN
TCLK
FB_RW
FB_CS0
FB_A2
ICOC3
URTS1
AN0
AN1
VRL
VSSA
M
1
2
3
4
5
6
7
8
9
10
11
12
CLKMOD1 CLKMOD0
A
FEC_COL FEC_CRS B
Figure 4. Pinout Top View (144 MAPBGA)
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
17
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Family Configurations
Table 3. Pin Functions by Primary and Alternate Purpose
Secondary Tertiary Quaternary
Function Function Function
(Alt 2)
(GPIO)
(Alt 1)
Drive
Pull-up/
Pin on
Strength/Co
Pull-down2 144 MAPBGA
1
ntrol
MCF52259 ColdFire Microcontroller, Rev. 2
Pin on
144 LQFP
Pin on
100 LQFP
L12, K10, K12,
K11, K9, L9,
M10, M9
74–77; 69,
68, 67 ,66
51–54, 46,
45, 44, 43
—
L11
73
50
N/A
—
M12
70
47
N/A
N/A
—
L10
72
49
—
N/A
N/A
—
M11
71
48
—
—
N/A
N/A
—
C12
106
73
—
—
—
N/A
N/A
—
D12
105
72
VDDPLL
—
—
—
N/A
N/A
—
C11
107
74
VSSPLL
—
—
—
N/A
N/A
—
D11
104
71
RTC_EXTAL
—
—
—
N/A
N/A
—
D1
13
7
RTC_XTAL
—
—
—
N/A
N/A
—
E1
14
8
ALLPST
—
—
—
Low
High
—
L3
42
30
DDATA[3:0]
—
—
PDD[7:4]
Low
High
—
G9, H10, F11,
F10
86, 85, 84,
83
—
PST[3:0]
—
—
PDD[3:0]
Low
High
—
F9, G10, G11,
G12
87–90
—
Pin Group
Primary
Function
ADC
AN[7:0]
—
—
PAN[7:0]
Low
Low
—
VDDA
—
—
—
N/A
N/A
VSSA
—
—
—
N/A
VRH
—
—
—
VRL
—
—
EXTAL
—
XTAL
Clock
Generation
RTC
Debug
Data
Slew
Rate
Family Configurations
18
Table 3 shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Freescale Semiconductor
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Secondary Tertiary Quaternary
Function Function Function
(Alt 1)
(Alt 2)
(GPIO)
Drive
Pull-up/
Pin on
Strength/Co
2
Pull-down
144
MAPBGA
ntrol1
MCF52259 ColdFire Microcontroller, Rev. 2
Pin on
144 LQFP
Pin on
100 LQFP
B11
109
76
—
B12
108
75
PDSRH[2]
—
B8
120
87
PSRRH[6:3]
PDSRH[6:3]
—
D7, C7, B7, A8
127, 126,
123, 122
94, 93, 90,
89
PTI7
PSRRH[7]
PDSRH[7]
—
C8
121
88
—
PTJ0
PSRRH[8]
PDSRH[8]
—
A9
119
86
—
—
PTJ1
PSRRH[9]
PDSRH[9]
—
B9
117
84
FEC_TXD[3:0]
—
—
PTJ[2:5]
—
A11, B10, C9,
D9
110–113
77, 78, 79,
80
FEC_TXEN
—
—
PTJ6
PSRRH[14]
PDSRH[14]
—
A10
116
83
FEC_TXER
—
—
PTJ7
PSRRH[15]
PDSRH[15]
—
D8
118
85
H1
28
22
Pin Group
Primary
Function
FEC
FEC_COL
—
—
PTI0
PSRRH[0]
PDSRH[0]
—
FEC_CRS
—
—
PTI1
PSRRH[1]
PDSRH[1]
FEC_RXCLK
—
—
PTI2
PSRRH[2]
FEC_RXD[3:0]
—
—
PTI[3:6]
FEC_RXDV
—
—
FEC_RXER
—
FEC_TXCLK
FEC
I
2C03
Interrupts
PSRRH[13:10] PDSRH[13:1
0]
I2C_SCL0
—
UTXD2
PAS0
PSRR[0]
PDSR[0]
Pull-Up4
I2C_SDA0
—
URXD2
PAS1
PSRR[0]
PDSR[0]
Pull-Up4
H2
29
23
IRQ7
—
—
PNQ7
Low
Low
Pull-Up4
E12
96
63
Low
4
A7
128
95
4
IRQ5
JTAG/BDM
Slew
Rate
FEC_MDC
—
PNQ5
Low
Pull-Up
FEC_MDIO
—
PNQ3
Low
Low
Pull-Up
A6
129
96
IRQ1
—
USB_ALT
CLK
PNQ1
Low
High
Pull-Up4
E9
103
70
JTAG_EN
—
—
—
N/A
N/A
Pull-Down
M2
44
32
TCLK/
PSTCLK/
CLKOUT
—
FB_CLK
—
Low
Low
Pull-Up5
M3
43
31
TDI/DSI
—
—
—
N/A
N/A
Pull-Up5
L1
40
28
TDO/DSO
—
—
—
Low
Low
—
TMS/BKPT
TRST/DSCLK
—
—
—
—
—
—
N/A
N/A
N/A
N/A
L2
41
29
5
K1
38
26
5
K2
39
27
Pull-Up
Pull-Up
19
Family Configurations
IRQ3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Pin Group
Primary
Function
Secondary Tertiary Quaternary
Function Function Function
(Alt 1)
(Alt 2)
(GPIO)
Slew
Rate
Drive
Pull-up/
Pin on
Strength/Co
2
Pull-down
144
MAPBGA
ntrol1
Pin on
144 LQFP
Pin on
100 LQFP
MCF52259 ColdFire Microcontroller, Rev. 2
Mode
Selection
RCON/EZPCS
—
—
—
N/A
N/A
Pull-Up
E4
10
4
CLKMOD[1:0]
—
—
—
N/A
N/A
Pull-Down
D4, D5
144, 143
100, 99
QSPI
QSPI_CS3
SYNCA
USB_DP_
PDOWN
PQS6
PSRR[7]
PDSR[7]
—
G4
22
16
QSPI_CS2
SYNCB
USB_DM
_
PDOWN
PQS5
PSRR[6]
PDSR[6]
—
G3
23
17
QSPI_CS0
I2C_SDA0
UCTS1
PQS3
PSRR[4]
PDSR[4]
Pull-Up6
H4
27
21
QSPI_CLK/
EZPCK
I2C_SCL0
URTS1
PQS2
PSRR[3]
PDSR[3]
Pull-Up6
H3
26
20
QSPI_DIN/
EZPD
I2C_SDA1
URXD1
PQS1
PSRR[2]
PDSR[2]
Pull-Up6
G2
24
18
QSPI_DOUT/E I2C_SCL1
ZPQ
UTXD1
PQS0
PSRR[1]
PDSR[1]
Pull-Up6
G1
25
19
QSPI
Reset7
Freescale Semiconductor
RSTI
—
—
—
N/A
N/A
Pull-Up7
A3
141
97
RSTO
—
—
—
Low
High
—
A2
142
98
Test
TEST
—
—
—
N/A
N/A
Pull-Down
B1
9
3
Timer 3,
16-bit
GPT3
—
PWM7
PTA3
PSRR[23]
PDSR[23]
Pull-Up8
M7
58
35
Timer 2,
16-bit
GPT2
—
PWM5
PTA2
PSRR[22]
PDSR[22]
Pull-Up8
J10
95
62
Timer 1,
16-bit
GPT1
—
PWM3
PTA1
PSRR[21]
PDSR[21]
Pull-Up8
J11
94
61
Timer 0,
16-bit
GPT0
—
PWM1
PTA0
PSRR[20]
PDSR[20]
Pull-Up8
F12
93
60
Timer 3,
32-bit
DTIN3
DTOUT3
PWM6
PTC3
PSRR[19]
PDSR[19]
—
F4
19
13
Timer 2,
32-bit
DTIN2
DTOUT2
PWM4
PTC2
PSRR[18]
PDSR[18]
—
J8
65
42
Family Configurations
20
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Freescale Semiconductor
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group
Primary
Function
Secondary Tertiary Quaternary
Function Function Function
(Alt 1)
(Alt 2)
(GPIO)
Slew
Rate
Drive
Pull-up/
Pin on
Strength/Co
2
Pull-down
144
MAPBGA
ntrol1
Pin on
144 LQFP
Pin on
100 LQFP
MCF52259 ColdFire Microcontroller, Rev. 2
Timer 1,
32-bit
DTIN1
DTOUT1
PWM2
PTC1
PSRR[17]
PDSR[17]
—
C1
12
6
Timer 0,
32-bit
DTIN0
DTOUT0
PWM0
PTC0
PSRR[16]
PDSR[16]
—
D2
11
5
UART 0
UCTS0
—
USB_VBU
SE
PUA3
PSRR[11]
PDSR[11]
—
E2
15
9
URTS0
—
USB_VBU
SD
PUA2
PSRR[10]
PDSR[10]
—
F3
18
12
URXD0
—
—
PUA1
PSRR[9]
PDSR[9]
—
F2
17
11
UTXD0
—
—
PUA0
PSRR[8]
PDSR[8]
—
F1
16
10
UCTS1
SYNCA
URXD2
PUB3
PSRR[15]
PDSR[15]
—
K7
61
38
URTS1
SYNCB
UTXD2
PUB2
PSRR[14]
PDSR[14]
—
M8
64
41
L8
63
40
UART 1
UART 2
USB OTG
I2C_SDA1
—
PUB1
PSRR[13]
PDSR[13]
UTXD1
I2C_SCL1
—
PUB0
PSRR[12]
PDSR[12]
Pull-Up6
K8
62
39
UCTS2
I2C_SCL1
USB_
VBUSCH
G
PUC3
PSRR[27]
PDSR[27]
Pull-Up6
E11
97
64
URTS2
I2C_SDA1
USB_
VBUSDIS
PUC2
PSRR[26]
PDSR[26]
Pull-Up6
E10
98
65
URXD2
CANRX
—
PUC1
PSRR[25]
PDSR[25]
—
C10
102
69
UTXD2
CANTX
—
PUC0
PSRR[24]
PDSR[24]
—
D10
101
68
USB_DM
—
—
—
N/A
N/A
—
H11
80
57
USB_DP
—
—
—
N/A
N/A
—
H12
81
58
USB_VDD
—
—
—
N/A
N/A
—
J9
79
56
USB_VSS
—
—
—
N/A
N/A
—
H9
82
59
21
Family Configurations
URXD1
Pull-Up6
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Pin Group
MiniFlexBus9
Primary
Function
Secondary Tertiary Quaternary
Function Function Function
(Alt 1)
(Alt 2)
(GPIO)
Slew
Rate
Drive
Pull-up/
Pin on
Strength/Co
2
Pull-down
144
MAPBGA
ntrol1
Pin on
144 LQFP
Pin on
100 LQFP
FB_CS1
—
PAS2
PSRRL[20]
PDSRL[20]
—
K3
37
—
FB_AD[7:0]
—
—
PTE[7:0]
PSRRL[7:0]
PDSRL[7:0]
—
J2, J1, K4, K6,
J6, M6, L6, L7
34–36;
53–57
—
FB_AD[15:8]
—
—
PTF[7:0]
PSRRL[15:8]
PDSRL[15:8]
—
C4, B2, C3,
C2, D3, E3, J3,
J4
136, 2–6,
32–33
—
FB_AD[19:16]
—
—
PTG[3:0]
PSRRL[19:16] PDSRL[19:16
]
—
B6, C6, D6, C5
130–133
—
FB_CS0
—
—
PTG5
PSRRL[21]
PDSRL[21]
—
M5
52
—
FB_R/W
—
—
PTG7
PSRRL[31]
PDSRL[31]
—
M4
45
—
FB_OE
—
—
PTG6
PSRRL[30]
PDSRL[30]
—
B5
137
—
FB_D7
CANRX
—
PTH5
PSRRL[29]
PDSRL[29]
—
A5
138
—
FB_D6
CANTX
—
PTH4
PSRRL[28]
PDSRL[28]
—
A4
139
—
FB_D5
I2C_SCL1
—
PTH3
PSRRL[27]
PDSRL[27]
Pull-Up6
B4
140
—
FB_D4
I2C_SDA1
—
PTH2
PSRRL[26]
PDSRL[26]
Pull-Up6
B3
1
—
FB_D3
USB_
VBUSD
—
PTH1
PSRRL[25]
PDSRL[25]
—
L4
46
—
FB_D2
USB_
VBUSE
—
PTH0
PSRRL[24]
PDSRL[24]
—
K5
47
—
FB_D1
SYNCA
—
PTH7
PSRRL[23]
PDSRL[23]
—
L5
50
—
FB_D0
SYNCB
—
PTH6
PSRRL[22]
PDSRL[22]
—
J5
51
—
Standby
Voltage
VSTBY
—
—
—
N/A
N/A
—
J12
78
55
VDD10
VDD
—
—
—
N/A
N/A
—
E5–E8; F5;
G5; H5–7; J7
7; 20; 30;
48; 59; 92;
100; 115;
125; 135
1; 14; 24;
33; 36; 67;
82; 92
MCF52259 ColdFire Microcontroller, Rev. 2
FB_ALE
Family Configurations
22
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Freescale Semiconductor
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group
Primary
Function
VSS
VSS
Secondary Tertiary Quaternary
Function Function Function
(Alt 1)
(Alt 2)
(GPIO)
—
—
—
Slew
Rate
N/A
Drive
Pull-up/
Pin on
Strength/Co
2
Pull-down
144
MAPBGA
ntrol1
N/A
—
A1; A12; F6–8;
G6–8; H8; M1;
M2
Pin on
144 LQFP
Pin on
100 LQFP
8; 21; 31;
49; 60; 91;
99; 114;
124; 134
2; 15; 25;
34; 37; 66;
81; 91
1
The PDSR and PSSR registers are part of the GPIO module. All programmable signals default to 2mA drive in normal (single-chip) mode.
All signals have a pull-up in GPIO mode.
3 I2C1 is multiplexed with specific pins of the QSPI, UART1, UART2, and Mini-FlexBus pin groups.
4 For primary and GPIO functions only.
5 Only when JTAG mode is enabled.
6 For secondary and GPIO functions only.
7 RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended.
8 For GPIO functions, the Primary Function has pull-up control within the GPT module.
9 Available on 144-pin packages only.
10 This list for power and ground does not include those dedicated power/ground pins included elsewhere, such as in the ADC, USB, and PLL.
2
MCF52259 ColdFire Microcontroller, Rev. 2
Family Configurations
23
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
2
Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the microcontroller unit, including
detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
2.1
Maximum Ratings
Table 4. Absolute Maximum Ratings1, 2
Rating
Symbol
Value
Unit
VDD
–0.3 to +4.0
V
Clock synthesizer supply voltage
VDDPLL
–0.3 to +4.0
V
RAM standby supply voltage
VSTBY
+1.8 to 3.5
V
USB standby supply voltage
VDDUSB
–0.3 to +4.0
V
VIN
–0.3 to +4.0
V
EXTAL pin voltage
VEXTAL
0 to 3.3
V
XTAL pin voltage
VXTAL
0 to 3.3
V
IDD
25
mA
TA
(TL - TH)
–40 to 85 or
0 to 706
°C
Tstg
–65 to 150
°C
Supply voltage
Digital input voltage 3
Instantaneous maximum current
Single pin limit (applies to all pins)4, 5
Operating temperature range (packaged)
Storage temperature range
1
2
3
4
5
6
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings
are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond
those listed may affect device reliability or cause permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher
than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic voltage level (VSS or VDD).
Input must be current limited to the IDD value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then
use the larger of the two values.
All functional non-supply pins are internally clamped to VSS and VDD.
The power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the
injection current may flow out of VDD and could result in the external power supply going out of
regulation. Ensure that the external VDD load shunts current greater than maximum injection current.
This is the greatest risk when the MCU is not consuming power (e.g., no clock).
Depending on the packaging; see the orderable part number summary.
MCF52259 ColdFire Microcontroller, Rev. 2
24
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Electrical Characteristics
2.2
Current Consumption
Table 5. Typical Active Current Consumption Specifications
Symbol
Typical1
Active
(SRAM)
Typical1
Active
(Flash)
Peak2
(Flash)
Unit
IDD
22
30
36
mA
PLL @ 16 MHz
31
45
60
PLL @ 64 MHz
84
100
155
PLL @ 80 MHz
102
118
185
Characteristic
PLL @ 8 MHz
RAM standby supply current
• Normal operation: VDD > VSTBY - 0.3 V
• Standby operation: VDD < VSS + 0.5 V
Analog supply current
• Normal operation
USB supply current
PLL supply current
ISTBY
—
—
5
20
μA
μA
IDDA
23
15
mA
IDDUSB
—
2
mA
IDDPLL
—
6
4
mA
1
Tested at room temperature with CPU polling a status register. All clocks were off except the UART and CFM (when
running from flash memory).
2 Peak current measured with all modules active, CPU polling a status register, and default drive strength with matching
load.
3 Tested using Auto Power Down (APD), which powers down the ADC between conversions; ADC running at 4 MHz in
Once Parallel mode with a sample rate of 3 kHz.
4 Tested with the PLL MFD set to 7 (max value). Setting the MFD to a lower value results in lower current consumption.
Table 6. Current Consumption in Low-Power Mode, Code From Flash Memory1,2,3
Mode
8 MHz (Typ)
16 MHz (Typ)
Stop mode 3 (Stop 11)4
Stop mode 2 (Stop
80 MHz (Typ)
10
15
17
9
10
15
17
Wait / Doze
21
32
56
65
Run
23
36
70
81
Stop mode 0 (Stop
Symbol
mA
IDD
7.0
9
00)5
Unit
0.150
10)4
Stop mode 1 (Stop 01)4,5
64 MHz (Typ)
1
All values are measured with a 3.30V power supply. Tests performed at room temperature.
Refer to the Power Management chapter in the MCF52259 Reference Manual for more information on low-power
modes.
3
CLKOUT, PST/DDATA signals, and all peripheral clocks except UART0 and CFM off before entering low-power
mode. CLKOUT is disabled.
4 See the description of the Low-Power Control Register (LPCR) in the MCF52259 Reference Manual for more
information on stop modes 0–3.
5
Results are identical to STOP 00 for typical values because they only differ by CLKOUT power consumption.
CLKOUT is already disabled in this instance prior to entering low-power mode.
2
MCF52259 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
25
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Electrical Characteristics
Table 7. Current Consumption in Low-Power Mode, Code From SRAM1,2,3
Mode
Stop mode 3 (Stop 11)
8 MHz (Typ)
16 MHz (Typ)
4
64 MHz (Typ)
80 MHz (Typ)
Unit
Symbol
mA
IDD
0.090
Stop mode 2 (Stop 10)4
7
Stop mode 1 (Stop 01)
4,5
9
10
15
17
Stop mode 0 (Stop 00)
5
9
10
15
17
Wait / Doze
13
18
42
50
Run
16
21
55
65
1
All values are measured with a 3.30V power supply. Tests performed at room temperature.
Refer to the Power Management chapter in the MCF52259 Reference Manual for more information on low-power
modes.
3
CLKOUT, PST/DDATA signals, and all peripheral clocks except UART0 off before entering low-power mode.
CLKOUT is disabled. Code executed from SRAM with flash memory shut off by writing 0x0 to the FLASHBAR
register.
4
See the description of the Low-Power Control Register (LPCR) in the MCF52259 Reference Manual for more
information on stop modes 0–3.
5 Results are identical to STOP 00 for typical values because they only differ by CLKOUT power consumption.
CLKOUT is already disabled in this instance prior to entering low-power mode.
2
2.3
Thermal Characteristics
Table 8 lists thermal resistance values.
Table 8. Thermal Characteristics
Characteristic
144 MAPBGA Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to ambient, (@200 ft/min)
Junction to ambient, (@200 ft/min)
Value
Unit
Single layer board (1s)
θJA
531,2
°C/W
Four layer board (2s2p)
θJA
301,3
°C/W
Single layer board (1s)
θJMA
431,3
°C/W
Four layer board (2s2p)
θJMA
261,3
°C/W
°C/W
Junction to board
—
θJB
164
Junction to case
—
θJC
95
°C/W
Ψjt
26
°C/W
Tj
105
oC
Junction to top of package
Maximum operating junction temperature
144 LQFP
Symbol
Natural convection
—
Junction to ambient, natural convection
Single layer board (1s)
θJA
447,8
°C/W
Junction to ambient, natural convection
Four layer board (2s2p)
θJA
351,9
°C/W
Single layer board (1s)
θJMA
351,3
°C/W
Four layer board (2s2p)
θJMA
1,3
29
°C/W
°C/W
Junction to ambient, (@200 ft/min)
Junction to ambient, (@200 ft/min)
Junction to board
—
θJB
2310
Junction to case
—
θJC
711
°C/W
Ψjt
12
2
°C/W
Tj
105
Junction to top of package
Maximum operating junction temperature
Natural convection
—
oC
MCF52259 ColdFire Microcontroller, Rev. 2
26
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available
from Freescale for import or sale in the United States prior to September 2010: MCF52256, MCF52258, MCF52259, and MCF52268 products in 144 MAPBGA packages
Electrical Characteristics
Table 8. Thermal Characteristics (continued)
Characteristic
100 LQFP
Symbol
Value
Unit
Single layer board (1s)
θJA
5313,14
°C/W
Four layer board (2s2p)
θJA
391,15
°C/W
Junction to ambient, (@200 ft/min)
Single layer board (1s)
θJMA
1,3
42
°C/W
Junction to ambient, (@200 ft/min)
Four layer board (2s2p)
θJMA
331,3
°C/W
16
°C/W
Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to board
Junction to case
Junction to top of package
Maximum operating junction temperature
—
θJB
—
θJC
Natural convection
—
25
17
°C/W
18
°C/W
9
Ψjt
2
Tj
105
o
C
θJA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
2 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
3 Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
4 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
7 θ
JA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
8 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
9
Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
10 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
11 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
12 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
13
θJA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
14 Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
15
Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
1
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Electrical Characteristics
16
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
17
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
18
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
The average chip-junction temperature (TJ) in °C can be obtained from:
T J = T A + ( P D × Θ JMA ) (1)
Where:
TA
= ambient temperature, °C
ΘJA
= package thermal resistance, junction-to-ambient, °C/W
PD
= PINT + PI/O
PINT
= chip internal power, IDD × VDD, watts
PI/O
= power dissipation on input and output pins — user determined, watts
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
P D = K ÷ ( T J + 273°C )
(2)
Solving equations 1 and 2 for K gives:
K = PD × (TA + 273 °C) + ΘJMA × PD 2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for
any value of TA.
2.4
Flash Memory Characteristics
The flash memory characteristics are shown in Table 9 and Table 10.
Table 9. SGFM Flash Program and Erase Characteristics
(VDD = 3.0 to 3.6 V)
Parameter
System clock (read only)
System clock (program/erase)
1
2
2
Symbol
Min
Typ
Max
fsys(R)
0
—
66.67 or 801
MHz
—
801
MHz
fsys(P/E)
0.15
66.67 or
Unit
Depending on packaging; see the orderable part number summary.
Refer to the flash memory section for more information
Table 10. SGFM Flash Module Life Characteristics
(VDD = 3.0 to 3.6 V)
Parameter
Maximum number of guaranteed program/erase cycles1 before failure
Data retention at average operating temperature of 85°C
1
Symbol
Value
Unit
P/E
10,0002
Cycles
Retention
10
Years
A program/erase cycle is defined as switching the bits from 1 → 0 → 1.
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Electrical Characteristics
2
Reprogramming of a flash memory array block prior to erase is not required.
2.5
EzPort Electrical Specifications
Table 11. EzPort Electrical Specifications
Name
2.6
Characteristic
Min
Max
Unit
EP1
EPCK frequency of operation (all commands except READ)
—
fsys / 2
MHz
EP1a
EPCK frequency of operation (READ command)
—
fsys / 8
MHz
EP2
EPCS_b negation to next EPCS_b assertion
2 × Tcyc
—
ns
EP3
EPCS_B input valid to EPCK high (setup)
—
5
ns
EP4
EPCK high to EPCS_B input invalid (hold)
5
—
ns
EP5
EPD input valid to EPCK high (setup)
—
2
ns
EP6
EPCK high to EPD input invalid (hold)
5
—
ns
EP7
EPCK low to EPQ output valid (out setup)
—
12
ns
EP8
EPCK low to EPQ output invalid (out hold)
0
—
ns
EP9
EPCS_B negation to EPQ tri-state
—
12
ns
ESD Protection
Table 12. ESD Protection Characteristics1, 2
Characteristics
Symbol
Value
Units
ESD target for Human Body Model
HBM
2000
V
ESD target for Machine Model
MM
200
V
Rseries
1500
Ω
C
100
pF
Rseries
0
Ω
C
200
pF
Number of pulses per pin (HBM)
• Positive pulses
• Negative pulses
—
—
1
1
Number of pulses per pin (MM)
• Positive pulses
• Negative pulses
—
—
3
3
Interval of pulses
—
1
HBM circuit description
MM circuit description
—
—
sec
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
2 A device is defined as a failure if after exposure to ESD pulses the device no longer
meets the device specification requirements. Complete DC parametric and functional
testing is performed per applicable device specification at room temperature followed by
hot temperature, unless specified otherwise in the device specification.
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Electrical Characteristics
2.7
DC Electrical Specifications
Table 13. DC Electrical Specifications 1
Characteristic
Symbol
Min
Max
Unit
Supply voltage
VDD
3.0
3.6
V
Standby voltage
VSTBY
1.8
3.5
V
Input high voltage
VIH
0.7 × VDD
4.0
V
Input low voltage
VIL
VSS – 0.3
0.35 × VDD
V
Input hysteresis
VHYS
0.06 × VDD
—
mV
Low-voltage detect trip voltage (VDD falling)
VLVD
2.15
2.3
V
Low-voltage detect hysteresis (VDD rising)
VLVDHYS
60
120
mV
Iin
–1.0
1.0
μA
Output high voltage (all input/output and all output pins)
IOH = –2.0 mA
VOH
VDD – 0.5
—
V
Output low voltage (all input/output and all output pins)
IOL = 2.0mA
VOL
—
0.5
V
Output high voltage (high drive)
IOH = -5 mA
VOH
VDD – 0.5
—
V
Output low voltage (high drive)
IOL = 5 mA
VOL
—
0.5
V
Output high voltage (low drive)
IOH = -2 mA
VOH
VDD - 0.5
—
V
Output low voltage (low drive)
IOL = 2 mA
VOL
—
0.5
V
Weak internal pull Up device current, tested at VIL Max.2
IAPU
–10
–130
μA
Input Capacitance 3
• All input-only pins
• All input/output (three-state) pins
Cin
—
—
7
7
Input leakage current
Vin = VDD or VSS, digital pins
pF
1
Refer to Table 14 for additional PLL specifications.
Refer to Table 3 for pins having internal pull-up devices.
3 This parameter is characterized before qualification rather than 100% tested.
2
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Electrical Characteristics
2.8
Clock Source Electrical Specifications
Table 14. Oscillator and PLL Specifications
(VDD and VDDPLL = 3.0 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
Symbol
Min
Max
Clock Source Frequency Range of EXTAL Frequency Range
• Crystal
• External1
fcrystal
fext
0.5
0
48.0
50.0 or 60.0
PLL reference frequency range
fref_pll
2
10.0
0
fref / 32
66.67 or 803
66.67 or 803
Unit
MHz
MHz
System frequency 2
• External clock mode
• On-chip PLL frequency
fsys
Loss of reference frequency 4, 6
fLOR
100
1000
kHz
Self clocked mode frequency 5
fSCM
1
5
MHz
tcst
—
0.1
ms
2.0
VDD
VSS
0.8
Crystal start-up time
6, 7
EXTAL input high voltage
• External reference
VIHEXT
EXTAL input low voltage
• External reference
VILEXT
MHz
V
V
PLL lock time4,8
tlpll
—
500
μs
Duty cycle of reference 4
tdc
40
60
% fref
Frequency un-LOCK range
fUL
–1.5
1.5
% fref
Frequency LOCK range
fLCK
–0.75
0.75
% fref
CLKOUT period jitter 4, 5, 9 ,10, measured at fSYS Max
• Peak-to-peak (clock edge to clock edge)
• Long term (averaged over 2 ms interval)
Cjitter
—
—
10
.01
% fsys
7.84
8.16
MHz
On-chip oscillator frequency
foco
1
In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL.
All internal registers retain data at 0 Hz.
3
Depending on packaging; see the orderable part number summary.
4
Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode.
5 Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below f
LOR with
default MFD/RFD settings.
6 This parameter is characterized before qualification rather than 100% tested.
7 Proper PC board layout procedures must be followed to achieve specifications.
8 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
9
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage
for a given interval.
10 Based on slow system clock of 40 MHz measured at f
sys max.
2
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Electrical Characteristics
2.9
USB Operation
Table 15. USB Operation Specifications
Characteristic
Minimum core speed for USB operation
2.10
Symbol
Value
Unit
fsys_USB_min
16
MHz
Mini-FlexBus External Interface Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only
devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such
as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional
circuitry. For asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output
clock (MB_CLK). All other timing relationships can be derived from these values.
Table 16. Mini-FlexBus AC Timing Specifications
Num
Characteristic
Frequency of Operation
1
2
Min
Max
Unit
—
80
MHz
Notes
MB1
Clock Period
12.5
—
ns
MB2
Output Valid
—
8
ns
1
MB3
Output Hold
2
—
ns
1
MB4
Input Setup
6
—
ns
2
MB5
Input Hold
0
—
ns
2
Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
Specification is valid for all MB_D[7:0].
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Electrical Characteristics
MB_CLK
MB1
MB3
MB_A[19:X]
A[19:X]
MB2
MB_D[7:0] /
MB_A[15:0]
MB5
D[Y:0]
ADDRESS
MB4
MB_R/W
MB3
MB2
MB_ALE
MB_CSn
MB3
MB2
MB_OE
Figure 5. Mini-FlexBus Read Timing
MB_CLK
MB1
MB3
A[19:X]
MB_A[19:X]
MB2
MB_D[7:0] /
MB_A[15:0]
DATA[Y:0]
ADDRESS
MB_R/W
MB3
MB2
MB_ALE
MB_CSn
MB2
MB3
MB_OE
Figure 6. Mini-FlexBus Write Timing
2.11
Fast Ethernet Timing Specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
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Electrical Characteristics
2.11.1
Receive Signal Timing Specifications
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices.
Table 17. Receive Signal Timing
MII Mode
Num
Characteristic
—
1
Unit
Min
Max
—
25
MHz
5
—
ns
5
—
ns
RXCLK frequency
setup1
E1
RXD[n:0], RXDV, RXER to RXCLK
E2
RXCLK to RXD[n:0], RXDV, RXER hold1
E3
RXCLK pulse width high
35%
65%
RXCLK period
E4
RXCLK pulse width low
35%
65%
RXCLK period
In MII mode, n = 3
E4
RXCLK (Input)
E3
E1
RXD[n:0]
RXDV,
RXER
E2
Valid Data
Figure 7. MII Receive Signal Timing Diagram
2.11.2
Transmit Signal Timing Specifications
Table 18. Transmit Signal Timing
MII Mode
Num
—
1
Characteristic
Unit
TXCLK frequency
Min
Max
—
25
MHz
1
E5
TXCLK to TXD[n:0], TXEN, TXER invalid
5
—
ns
E6
TXCLK to TXD[n:0], TXEN, TXER valid1
—
25
ns
E7
TXCLK pulse width high
35%
65%
tTXCLK
E8
TXCLK pulse width low
35%
65%
tTXCLK
In MII mode, n = 3
E8
TXCLK (Input)
E7
E6
TXD[n:0]
TXEN,
TXER
E5
Valid Data
Figure 8. MII Transmit Signal Timing Diagram
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Electrical Characteristics
2.11.3
Asynchronous Input Signal Timing Specifications
Table 19. MII Transmit Signal Timing
Num
Characteristic
E9
Min
Max
Unit
1.5
—
TXCLK period
CRS, COL minimum pulse width
CRS, COL
E9
Figure 9. MII Async Inputs Timing Diagram
2.11.4
MII Serial Management Timing Specifications
Table 20. MII Serial Management Channel Signal Timing
Num
Characteristic
Symbol
Min
Max
Unit
tMDC
400
—
ns
E10
MDC cycle time
E11
MDC pulse width
40
60
% tMDC
E12
MDC to MDIO output valid
—
375
ns
E13
MDC to MDIO output invalid
25
—
ns
E14
MDIO input to MDC setup
10
—
ns
E15
MDIO input to MDC hold
0
—
ns
E10
E11
MDC (Output)
E11
E13
E12
Valid Data
MDIO (Output)
E14
MDIO (Input)
E15
Valid Data
Figure 10. MII Serial Management Channel TIming Diagram
2.12
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, timer, UART, Interrupt and USB interfaces. When in GPIO
mode, the timing specification for these pins is given in Table 21 and Figure 11.
The GPIO timing is met under the following load test conditions:
•
50 pF / 50 Ω for high drive
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Electrical Characteristics
25 pF / 25 Ω for low drive
•
Table 21. GPIO Timing
NUM
Characteristic
Symbol
Min
Max
Unit
G1
CLKOUT High to GPIO Output Valid
tCHPOV
—
10
ns
G2
CLKOUT High to GPIO Output Invalid
tCHPOI
1.5
—
ns
G3
GPIO Input Valid to CLKOUT High
tPVCH
9
—
ns
G4
CLKOUT High to GPIO Input Invalid
tCHPI
1.5
—
ns
CLKOUT
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 11. GPIO Timing
2.13
Reset Timing
Table 22. Reset and Configuration Override Timing
(VDD = 3.0 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM
1
2
Characteristic
Symbol
Min
Max
Unit
R1
RSTI input valid to CLKOUT High
tRVCH
9
—
ns
R2
CLKOUT High to RSTI Input invalid
tCHRI
1.5
—
ns
tRIVT
5
—
tCYC
tCHROV
—
10
ns
2
R3
RSTI input valid time
R4
CLKOUT High to RSTO Valid
All AC timing is shown with respect to 50% VDD levels unless otherwise noted.
During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the
system. Thus, RSTI must be held a minimum of 100 ns.
CLKOUT
1R1
RSTI
R2
R3
R4
R4
RSTO
Figure 12. RSTI and Configuration Override Timing
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Electrical Characteristics
2.14
I2C Input/Output Timing Specifications
Table 23 lists specifications for the I2C input timing parameters shown in Figure 13.
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
11
Start condition hold time
2 × tCYC
—
ns
I2
Clock low period
8 × tCYC
—
ns
I3
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
ms
I4
Data hold time
0
—
ns
I5
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
ms
I6
Clock high time
4 × tCYC
—
ns
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2 × tCYC
—
ns
I9
Stop condition setup time
2 × tCYC
—
ns
Table 24 lists specifications for the I2C output timing parameters shown in Figure 13.
Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
111
Start condition hold time
6 × tCYC
—
ns
I21
Clock low period
10 × tCYC
—
ns
I32
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
—
—
μs
I41
Data hold time
7 × tCYC
—
ns
—
3
ns
I5
3
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
I61
Clock high time
10 × tCYC
—
ns
1
Data setup time
2 × tCYC
—
ns
I81
Start condition setup time (for repeated start
condition only)
20 × tCYC
—
ns
I91
Stop condition setup time
10 × tCYC
—
ns
I7
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 24. The I2C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table 24 are minimum values.
2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
3 Specified at a nominal 50-pF load.
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Electrical Characteristics
Figure 13 shows timing for the values in Table 23 and Table 24.
I2
SCL
I1
I6
I4
I5
I3
I8
I7
I9
SDA
Figure 13. I2C Input/Output Timings
2.15
Analog-to-Digital Converter (ADC) Parameters
Table 25 lists specifications for the analog-to-digital converter.
Table 25. ADC Parameters1
Name
Characteristic
Min
Typical
Max
Unit
VREFL
Low reference voltage
VSSA
—
VSSA
+ 50 mV
V
VREFH
High reference voltage
VDDA
- 50 mV
—
VDDA
V
VDDA
ADC analog supply voltage
3.1
3.3
3.6
V
VADIN
Input voltages
VREFL
—
VREFH
V
RES
Resolution
12
—
12
Bits
INL
Integral non-linearity (full input signal range)2
—
±2.5
±3
LSB3
INL
Integral non-linearity (10% to 90% input signal range)4
—
±2.5
±3
LSB
DNL
Differential non-linearity
—
–1 < DNL < +1
<+1
LSB
Monotonicity
fADIC
ADC internal clock
RAD
Conversion range
0.1
—
5.0
MHz
VREFL
—
VREFH
V
tADPU
ADC power-up time
—
6
13
tAIC cycles6
tREC
Recovery from auto standby
—
0
1
tAIC cycles
tADC
Conversion time
—
6
—
tAIC cycles
tADS
Sample time
—
1
—
tAIC cycles
CADI
Input capacitance
—
See Figure 14
—
pF
XIN
Input impedance
—
See Figure 14
—
W
IADI
Input injection current7, per pin
—
—
3
mA
VREFH current
—
0
—
mA
Offset voltage internal reference
—
±8
±15
mV
Gain error (transfer path)
.99
1
1.01
—
Offset voltage external reference
—
±3
9
mV
IVREFH
VOFFSET
EGAIN
VOFFSET
5
GUARANTEED
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Electrical Characteristics
Table 25. ADC Parameters1 (continued)
Name
1
2
3
4
5
6
7
Characteristic
Min
Typical
Max
Unit
SNR
Signal-to-noise ratio
—
62 to 66
—
dB
THD
Total harmonic distortion
—
−75
—
dB
SFDR
Spurious free dynamic range
—
67 to 70.3
—
dB
SINAD
Signal-to-noise plus distortion
—
61 to 63.9
—
dB
ENOB
Effective number of bits
9.1
10.6
—
Bits
All measurements are preliminary pending full characterization, and made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground
INL measured from VIN = VREFL to VIN = VREFH
LSB = Least Significant Bit
INL measured from VIN = 0.1VREFH to VIN = 0.9VREFH
Includes power-up of ADC and VREF
ADC clock cycles
Current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
2.16
Equivalent Circuit for ADC Inputs
Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3
is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2, while
the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional
capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function
of the analog input voltage, VREF and the ADC clock frequency.
125W ESD Resistor
8pF noise damping capacitor
3
Analog Input
4
S1
C1
S/H
S3
1
1.
2.
3.
4.
5.
2
(VREFH- VREFL)/ 2
S2
C2
C1 = C2 = 1pF
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
Equivalent resistance for the channel select mux; 100 Ωs
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
1
Equivalent input impedance, when the input is selected =
(ADC Clock Rate) × (1.4×10-12)
Figure 14. Equivalent Circuit for A/D Loading
MCF52259 ColdFire Microcontroller, Rev. 2
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Electrical Characteristics
2.17
DMA Timers Timing Specifications
Table 26 lists timer module AC timings.
Table 26. Timer Module AC Timing Specifications
Characteristic1
Name
1
Min
Max
Unit
T1
DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time
3 × tCYC
—
ns
T2
DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width
1 × tCYC
—
ns
All timing references to CLKOUT are given to its rising edge.
2.18
QSPI Electrical Specifications
Table 27 lists QSPI timings.
Table 27. QSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
QS1
QSPI_CS[3:0] to QSPI_CLK
1
510
tCYC
QS2
QSPI_CLK high to QSPI_DOUT valid
—
10
ns
QS3
QSPI_CLK high to QSPI_DOUT invalid (Output hold)
2
—
ns
QS4
QSPI_DIN to QSPI_CLK (Input setup)
9
—
ns
QS5
QSPI_DIN to QSPI_CLK (Input hold)
9
—
ns
The values in Table 27 correspond to Figure 15.
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 15. QSPI Timing
2.19
JTAG and Boundary Scan Timing
MCF52259 ColdFire Microcontroller, Rev. 2
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Electrical Characteristics
Table 28. JTAG and Boundary Scan Timing
Characteristics1
Num
1
Symbol
Min
Max
Unit
J1
TCLK frequency of operation
fJCYC
DC
1/4
fsys/2
J2
TCLK cycle period
tJCYC
4 × tCYC
—
ns
J3
TCLK clock pulse width
tJCW
26
—
ns
J4
TCLK rise and fall times
tJCRF
0
3
ns
J5
Boundary scan input data setup time to TCLK rise
tBSDST
4
—
ns
J6
Boundary scan input data hold time after TCLK rise
tBSDHT
26
—
ns
J7
TCLK low to boundary scan output data valid
tBSDV
0
33
ns
J8
TCLK low to boundary scan output high Z
tBSDZ
0
33
ns
J9
TMS, TDI input data setup time to TCLK rise
tTAPBST
4
—
ns
J10
TMS, TDI Input data hold time after TCLK rise
tTAPBHT
10
—
ns
J11
TCLK low to TDO data valid
tTDODV
0
26
ns
J12
TCLK low to TDO high Z
tTDODZ
0
8
ns
J13
TRST assert time
tTRSTAT
100
—
ns
J14
TRST setup time (negation) to TCLK high
tTRSTST
10
—
ns
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
J2
J3
J3
VIH
TCLK
(input)
J4
VIL
J4
Figure 16. Test Clock Input Timing
MCF52259 ColdFire Microcontroller, Rev. 2
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Electrical Characteristics
TCLK
VIL
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Electrical Characteristics
VIH
J5
Data Inputs
J6
Input Data Valid
J7
Data Outputs
Output Data Valid
J8
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 17. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
TDI
TMS
J10
Input Data Valid
J11
TDO
Output Data Valid
J12
TDO
J11
TDO
Output Data Valid
Figure 18. Test Access Port Timing
TCLK
14
TRST
13
Figure 19. TRST Timing
MCF52259 ColdFire Microcontroller, Rev. 2
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2.20
Debug AC Timing Specifications
Table 29 lists specifications for the debug AC timing parameters shown in Figure 21.
Table 29. Debug AC Timing Specification
66/80 MHz
Num
1
Characteristic
Units
Min
Max
D1
PST, DDATA to CLKOUT setup
4
—
ns
D2
CLKOUT to PST, DDATA hold
1.5
—
ns
D3
DSI-to-DSCLK setup
1 × tCYC
—
ns
D41
DSCLK-to-DSO hold
4 × tCYC
—
ns
D5
DSCLK cycle time
5 × tCYC
—
ns
D6
BKPT input data setup time to CLKOUT rise
4
—
ns
D7
BKPT input data hold time to CLKOUT rise
1.5
—
ns
D8
CLKOUT high to BKPT high Z
0.0
10.0
ns
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to
the rising edge of CLKOUT.
Figure 20 shows real-time trace timing for the values in Table 29.
CLKOUT
D1
D2
PST[3:0]
DDATA[3:0]
Figure 20. Real-Time Trace AC Timing
MCF52259 ColdFire Microcontroller, Rev. 2
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Electrical Characteristics
Figure 21 shows BDM serial port AC timing for the values in Table 29.
CLKOUT
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Current
Figure 21. BDM Serial Port AC Timing
3
Package Information
The latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire.
Table 30 lists the case outline numbers per device. Use these numbers in the web page’s keyword search engine to find the latest
package outline drawings.
Table 30. Package Information
Device
Package Type
Case Outline Numbers
100 LQFP
98ASS23308W
144 LQFP
or
144 MAPBGA
98ASS23177W
MCF52252
MCF52254
MCF52255
MCF52256
MCF52258
MCF52259
98ASH70694A
MCF52259 ColdFire Microcontroller, Rev. 2
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Package Information
4
Revision History
Table 31. Revision History
Revision
Description
0
Initial public release.
1
• Added package dimensions to package diagrams
• Added listing of devices for MCF52259 family
• Changed “Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse
width modulation (PWM), and pulse accumulation” to “Four-channel general-purpose timer (GPT)
capable of input capture/output compare, pulse width modulation (PWM), pulse-code modulation
(PCM), and pulse accumulation”
• Updated the figure Pinout Top View (144 MAPBGA)
• Removed an extraneous instance of the table Pin Functions by Primary and Alternate Purpose
• In the table Pin Functions by Primary and Alternate Purpose, changed a footnote from “This list for
power and ground does not include those dedicated power/ground pins included elsewhere, such as in
the ADC” to “This list for power and ground does not include those dedicated power/ground pins
included elsewhere, such as in the ADC, USB, and PLL”
• In the table SGFM Flash Program and Erase Characteristics, changed “(VDDF = 2.7 to 3.6 V)“ to
“(VDD = 3.0 to 3.6 V)“
• In the table SGFM Flash Module Life Characteristics, changed “(VDDF = 2.7 to 3.6 V)“ to “(VDD = 3.0
to 3.6 V)“
• In the table Oscillator and PLL Specifications, changed “VDD and VDDPLL = 2.7 to 3.6 V“ to “VDD and
VDDPLL = 3.0 to 3.6 V“
• In the table Reset and Configuration Override Timing, changed “VDD = 2.7 to 3.6 V“ to “VDD = 3.0 to
3.6 V“
2
• Added EzPort Electrical Specifications.
• Updated Table 2 for part numbers.
• In Table 3, added slew rate column, updated derive strength, pull-up/pull-down values,JTAG pin
alternate functions, removed Wired/OR control column, and reordered AN[7:0] list of pin numbers for
144 LQFP and 100 LQFP.
• Updated Table 14.
• Updated Table 13, to change MIN voltage spec for Standby Voltage (VSTBY) to 1.8V (from 3.0V).
• Updated Figure 2 for RTC_EXTAL and RTC_XTAL pin positions.
MCF52259 ColdFire Microcontroller, Rev. 2
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Revision History
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Document Number: MCF52259
Rev. 2
8/2009
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