ON MC10E431FNR2 5v ecl 3-bit differential flip-flop Datasheet

MC10E431, MC100E431
5VECL 3-Bit Differential
Flip-Flop
Description
The MC10E/100E431 is a 3-bit flip-flop with differential clock,
data input and data output.
The asynchronous Set and Reset controls are edge-triggered rather
than level controlled. This allows the user to rapidly set or reset the
flip-flop and then continue clocking at the next clock edge, without the
necessity of de-asserting the set/reset signal (as would be the case with
a level controlled set/reset).
The E431 is also designed with larger internal swings, an approach
intended to minimize the time spent crossing the threshold region and
thus reduce the metastability susceptibility window.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of
the inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the
input clamps only operate when both inputs fall to 2.5 V below VCC.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
•
•
•
•
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MCxxxE431FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Features
•
•
•
•
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Edge-Triggered Asynchronous Set and Reset
Differential D, CLK and Q; VBB Reference Available
1100 MHz Min. Toggle Frequency
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Charged Device Model; > 2 kV
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
•
•
•
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 348 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 10
1
Publication Order Number:
MC10E431/D
MC10E431, MC100E431
VBB
CLK2 CLK2
25
24
23
D2
D2
R2
S2
22
21
20
19
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK1
26
18
Q2
D[0:2], D[0:2]
ECL Differential Data Inputs
CLK1
27
17
Q2
CLK[0:2], CLK[0:2]
ECL Differential Clock
R1
28
16
VCC
S[0:2]
ECL Edge Triggered Set Inputs
R[0:2]
ECL Edge Triggered Reset Input
1
15
Q1
Q[0:2], Q[0:2]
ECL Differential Data Outputs
VBB
Reference Voltage Output
VCC, VCCO
Positive Supply
VEE
Negative Supply
VEE
MC10E431/MC100E431
S1
2
14
Q1
D1
3
13
Q0
D1
4
12
Q0
5
6
7
CLK0 CLK0 D0
8
9
10
D0
R0
S0
11
VCCO
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28 (Top View)
S0
D0
D0
D
CLK0
CLK0
R0
S1
D1
D1
S
R
D
CLK1
CLK1
S
R
Q
Q0
Q
Q0
Q
Q1
Q
Q1
Q
Q2
Q
Q2
Table 2. FUNCTION TABLE
Dn
CLKn
Rn
Sn
L
Z
L
L
L
H
Z
L
L
H
X
X
Z
L
L
X
X
L
Z
H
Z = Low to high transition
X = Don’t Care
R1
S2
D2
D2
CLK2
CLK2
D
S
R
R2
VBB
Figure 2. Logic Diagram
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2
Qn
MC10E431, MC100E431
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
PECL Mode Power Supply
VEE = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
Tsol
Wave Solder
Pb
Pb−Free
Condition 2
VI v VCC
VI w VEE
Rating
Unit
8
V
6
−6
V
V
50
100
mA
mA
± 0.5
mA
0 to +85
°C
−65 to +150
°C
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
PLCC−28
22 to 26
°C/W
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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MC10E431, MC100E431
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
110
132
Min
85°C
Typ
Max
110
132
Min
Typ
Max
Unit
110
132
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage (Single−Ended)
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage (Single−Ended)
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
VBB
Output Voltage Reference
3.62
3.74
3.65
3.75
3.69
3.81
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
2.7
5.0
2.7
5.0
2.7
5.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 4)
0°C
Symbol
Characteristic
Typ
Max
110
132
−1020
−930
−840
Output LOW Voltage (Note 5)
−1950
−1790
VIH
Input HIGH Voltage (Single−Ended)
−1170
VIL
Input LOW Voltage (Single−Ended)
−1950
VBB
Output Voltage Reference
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
IIH
Input HIGH Current
IIL
Input LOW Current
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
VOL
Min
25°C
Min
85°C
Typ
Max
110
132
−980
−895
−810
−1630
−1950
−1790
−1005
−840
−1130
−1715
−1480
−1950
−1.38
−1.27
−2.3
0.0
Typ
Max
Unit
110
132
mA
−910
−815
−720
mV
−1630
−1950
−1773
−1595
mV
−970
−810
−1060
−890
−720
mV
−1715
−1480
−1950
−1698
−1445
mV
−1.35
−1.25
−1.31
−1.19
V
−2.3
0.0
−2.3
0.0
V
150
mA
150
0.5
0.3
Min
150
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E431, MC100E431
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 7)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
110
132
Min
85°C
Typ
Max
110
132
Min
Typ
Max
Unit
127
152
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 8)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage (Single−Ended)
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
VBB
Output Voltage Reference
3.62
3.74
3.62
3.74
3.62
3.74
V
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
2.7
5.0
2.7
5.0
2.7
5.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 10)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
110
132
Min
85°C
Typ
Max
110
132
Min
Typ
Max
Unit
127
152
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 11)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 11)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 12)
−2.3
0.0
−2.3
0.0
−2.3
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E431, MC100E431
Table 8. AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= −5.0 V (Note 13)
−40°C
Symbol
Min
Characteristic
Typ
fMAX
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
tS
Setup Time
tH
Hold Time
tPW
Minimum Pulse Width
tskew
Within-Device Skew (Note 15)
50
tJITTER
Random Clock Jitter (RMS)
<1
VPP
Input Voltage Swing
(Differential Configuration)
150
tr/tf
Rise/Fall Times
(20−80%)
250
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
1.1
CLK
R
S
550
500
500
700
725
725
D
R (Note 14)
S (Note 14)
250
1100
1100
D
250
CLK
400
850
975
975
550
550
550
700
725
725
0
700
700
200
1000
1000
0
200
850
925
925
550
550
550
700
725
725
0
700
700
200
1000
1000
0
700
700
ps
0
200
0
ps
400
450
700
150
850
925
925
400
<1
1000
Unit
GHz
1000
ps
50
ps
<1
ps
150
275
ps
450
1000
mV
650
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
13. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
14. These setup times define the minimum time the CLK or SET/RESET input must wait after the assertion of the RESET/SET input to assure
the proper operation of the flip-flop.
15. Within-device skew is defined as identical transitions on similar paths through a device.
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MC10E431, MC100E431
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E431FN
PLCC−28
37 Units / Rail
MC10E431FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E431FNR2
PLCC−28
500 / Tape & Reel
MC10E431FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E431FN
PLCC−28
37 Units / Rail
MC100E431FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E431FNR2
PLCC−28
500 / Tape & Reel
MC100E431FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC10E431, MC100E431
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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8
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E431, MC100E431
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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MC10E431/D
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